Manual 05.92 2075 Revision History: 05.92 Page Sub

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ISDN D-Channel Exchange Controller (IDEC®) 2075
Manual 05.92
2075 Revision History:
05.92
Page
Subjects (changes since last revision)
Data Classification Maximum Ratings Maximum ratings absolute ratings; exceeding only these values cause irreversible damage integrated circuit. Characteristics listed characteristics ensured over operating range integrated circuit. Typical characteristics specify mean values expected over production spread. otherwise specified, typical characteristics apply given supply voltage. Operating Range operating range functions given circuit description fulfilled. detailed technical information about "Processing Guidelines" "Quality Assurance" ICs, "Product Overview".
Edition 05.92 This edition realized using softwaresystem FrameMaker Published Siemens Bereich Halbleiter, Marketing-Kommunikation, D-8000
Siemens 1992. Rights Reserved.
patents other rights third parties concerned, liability only assumed components applications, processes circuits implemented within components assemblies. information describes type component shall considered assured characteristics. Terms delivery rights change design reserved. questions technology, delivery, prices please contact Offices Semiconductor Group Germany Siemens Companies Representatives worldwide (see address list). technical requirements components contain dangerous substances. information type question please contact your nearest Siemens Office, Semiconductor Group. Siemens approved CECC manufacturer.
Siemens Aktiengesellschaft
2075
Table Contents 2.4.1 2.4.2 2.4.3 2.4.4
Page
Features. Configuration Definitions Functions System Integration Functional Description. General Functions Device Architecture Operating Modes Interfaces Individual Functions Channel Access HDLC Communication Functions Collision Control Switching Functions Test Functions Preprocessed Channels Operational Description. Microprocessor Interface Operation Reset Initialization Interrupt Structure Processing Detailed Register Description Register Address Layout Register Description Electrical Characteristics. Appendix Package Outlines
Semiconductor Group
05.92
ISDN D-Channel Exchange Controller (IDEC®)
2075
CMOS Features
Four independent HDLC channels 64-byte FIFO storage channel direction Handling basic HDLC functions
flag detection/generation zero deletion/insertion checking/generation check abort Address recognition channel handler Single connection quad connection modes IOM® interface interface Programmable time slots channel data rates Mbit/s) Different methods contention resolution Standard interface, multiplexed non-multiplexed address data buses Vectored interrupt Advanced CMOS technology Power consumption less than during operation.
P-LCC-44
P-DIP-28
Type 2075-N 2075-P
Version Ordering Code Package V.1.3 V.1.3 Q67100-H6189 Q67100-H6188 P-LCC-44 (SMD) P-DIP-28
ISDN Digital Exchange Controller 2075 (IDEC) serial HDLC data communication circuit with four independent channels. telecommunication specific features make especially suited variable data rate systems. addition, device contains sophisticated switching functions implements automatic contention resolution between packet data from different sources. applications include: communication multiplexers, peripheral ISDN line cards, packet handlers X.25 packet switching devices. IDEC fundamental building block networks with either centralized, de-centralized mixed signaling/packet data handling architectures.
Semiconductor Group
05.92
Features
Configuration (top view)
N.C. N.C.
N.C. SD3R N.C. SD3X SD2R SD2X SD0R
RD/DS WR/R/W
2075
IDEC IDEC® 2075
IDEC® 2075
IDEC 2075
ITP00727
SD3R SD3X SD2R SD2X SD0R SD0X SD1R SD1X
N.C. N.C. N.C. SD1X SD1R SD0X N.C. N.C.
ITP03527
P-LCC-44
P-DIP-28
Semiconductor Group
Features
Definitions Functions
Definitions Functions P-LCC-44 P-DIP-28 Symbol Input Output Open Drain (OD) Function
Address Data Bus. multiplexed address/data interface mode selected these lines transfer data commands between IDEC.
demultiplexed mode used, these lines interface with system data bus. Address Bus. These inputs interface address select internal register read write access. Only provided P-LCC package only active demultiplexed interface selected. Chip Select. this line selects IDEC read/write operation. Write. This signal indicates write operation, active (Siemens/Intel mode). Read/Write. "high", identifies valid access read operation. "low", identifies access write operation (Motorola mode). Only provided P-LCC package. Read. This signal indicates read operation, active (Siemens/Intel mode). Data Strobe. rising edge marks valid read write operation (Motorola mode). Only provided P-LCC package.
Semiconductor Group
Features
Definitions Functions (cont'd) P-LCC-44 P-DIP-28 Symbol Input Output Open Drain (OD) Function
Address Latch Enable. Siemens/ Intel type multiplexed interface mode "high" this line indicates address internal register external address/data bus. Siemens/Intel type demultiplexed interface mode this line should connected demultiplexed Motorola type interface mode should connected Interrupt Request. This signal activated when IDEC requests interrupt. Reset. "high" this interrupt brings IDEC into reset state. Serial data receive.
SD0R SD1R SD2R SD3R SD0X SD1X SD2X SD3X
Serial data transmit. Serial data transmit. Serial data transmit. Serial data transmit.
Serial data transmit. Serial data transmit. Collision output.
Data Clock; supplies clock signal either equal twice data rate. Frame synchronization data strobe signal. Time-Slot Control. Supplies control signal external driver. Collision data receive. Ground. Positive power supply.
Semiconductor Group
Features
Timing
Collision Data Receive
Tristate Control
SD0R PCM/ SD0X SD1R
IDEC 2075
SD1X SD2R SD2X SD3R SD3X
(DS) (R/W)
ITL00726
System
Logic Symbol
Semiconductor Group
Features
SD0X
SD0R
SD1X
SD1R
SD2X
SD2R
SD3X
SD3R
Serial Interface Logic
Timing Switching Collision Control
Timing Switching Collision Control
Timing Switching Collision Control
Timing Switching Collision Control
HDLC Receiver Transmitter
HDLC Receiver Transmitter
HDLC Receiver Transmitter
HDLC Receiver Transmitter
RFIFO XFIFO
RFIFO XFIFO
RFIFO XFIFO
RFIFO XFIFO
Microcontroller Interface
ITB00728
AD0-AD7
Block Diagram
Semiconductor Group
Features
System Integration
Communication Multiplexers four independent serial HDLC communication channels implemented IDEC make circuit suitable communication multiplexers. collision detection/resolution capability circuit allows statistical multiplexing packets several physical data communication channels, example (mode applications. Centralized Signaling Data Packet Handlers IDEC used central packet handlers ISDN networks process signaling packet data four ISDN subscribers. this application, used with without Extended Interface Controller (EPlC®) 2055. IDEC connected interface EPIC, which itself connected system highway. EPIC implements concentration time slot assignment functions. alternative, IDEC directly connected highways (figure size (from bits) position time slot associated with each HDLC controller software programmable. addition receive transmit data highways, IDEC accepts third input connection collision detection purposes. mode collision detection programmable. "collision highway" time slot) used remote collision control, "clear send" lead, local contention resolution among several IDECs.
Semiconductor Group
Features
Highway
Highway
Line Transmit Receive Cards
Line Transmit Receive Cards
Transmit Receive EPIC
Transmit Receive
IDEC
IDEC
IDEC
IDEC
ITS00729
Highway
Highway
Line Transmit Receive Collision Detect Cards
Line Transmit Receive Collision Detect Cards
Transmit Receive Collision Detect IDEC
Transmit EPIC
Receive Collision Detect IDEC
IDEC
IDEC
ITS00730
Figure IDEC® Central Signaling Data Packet Handlers
Semiconductor Group
Features
Line Cards De-Centralized Mixed Signaling Data Packet Handling Architectures IDEC used peripheral line cards process D-channel packets ISDN subscribers. Controller 2055 layer-1 controlling capacity B-channel switching capacity total subscribers. channels control information eight subscribers carried interface. Thus line card dimensioned 32-ISDN subscribers employ eight IDECs, each connection (figure High Level Serial Communication Controller (HSCX) 82525 with HDLC channels, another IDEC used transmit receive signaling system highway common channel. Again, such common channel shared among several line cards, statistical multiplexing capability these controllers. completely de-centralized D-channel processing architectures, processing capacity line card usually dimensioned avoid blocking situations even under maximum conceivable D-channel traffic conditions. sometimes more advantageous perform p-packet handling centralized manner while keeping s-packet handling line cards. statistical increase p-packet traffic then effect line card, easily dealt with modular architectures central packet handler shown previous section. more effective sharing total p-packet handling capacity result, especially situation where p-packet traffic patterns vary widely from subscriber group another. IDEC mixed D-channel processing architecture illustrated figure additional "transparent data" connections supported IDEC enable merging packets into channel. Possible collision situations dealt with IDEC which uses either additional collision detect line (figure time slot system highway (figure from line card central packet handler.
Semiconductor Group
Features
Line Transceivers
c.c.s c.c.p C/I, MONITOR EPIC
System Highways
IDEC
IDEC
HSCX IDEC
Legend: c.c.s/p Common channel signaling packed data, respectively C/I, Control/Indication MONITOR channels interface
ITS00731
Figure Line Card De-Centralized D-Channel Handling Architecture
Semiconductor Group
Features
Line Transceivers
System Highway Coll
EPIC
IDEC
p(s)*
ITS00732
Line Transceivers
p(s)* Coll System Highway
IDEC
Coll
EPIC
Packets will discarded receiver Legend: Time-Slot packets Time-Slot packets Coll Time-Slot containing information about collision between packets packets
ITS00733
Figure IDEC® Line Card Mixed D-Channel Processing Architecture
Semiconductor Group
Functional Description
Functional Description General Functions Device Architecture
IDEC HDLC controller which handles four HDLC communication channels, each channel fully independent programmable register set. circuit performs following functions: Extraction (reception) insertion (transmission) HDLC data packets time division multiplex stream. Implementation basic HDLC functions layer-2 protocol, including address recognition. Interfacing data packets microprocessor bus. temporary storage data packets internal FlFOs used. Switching data between serial interfaces. Implementation different types collision resolution. Test functions. Operating Modes
Each HDLC controller IDEC assigned time channel determined either time slot assignment external strobe signal. basic configurations distinguished (figure quad connection configuration four HDLC controllers connected individual time multiplexed communication lines; single connection configuration four HDLC channels connected time multiplexed communication line.
QuadConnection
Main Connection
Single Connection
Auxiliary Connections
ITD00734
Figure
Semiconductor Group
Functional Description
quad connection configuration modes distinguished follows: Each connection time slotted highway, lengths positions time slots programmable (quad connection time slot mode); Each connection communication line, time channels marked external strobe signal (quad connection common control mode). modes distinguished turn single connection configuration follows: connection standard interface with predefined channel positions (single connection mode); connection time slotted highway (single connection time slot mode). simplicity, time slotted highway will usually referred "PCM highway", short.
Table Four Basic Operation Modes IDEC MDS1 MDS0 Mode Description Single connection time slot mode Quad connection common control mode Single connection mode Quad connection time slot mode
program single connection mode (CCR:MDS1, MDS0 with slave mode (MODE3-0:CMS1, CMS0 with multi master mode (MODE3-0:CMS1, CMS0 with uncond. trans. mode (MODE3-0:CMS1, CMS0 this additional programming made: MODE0:CCS1, CCS0 MODE1:CCS1, CCS0 MODE2:CCS1, CCS0 MODE3:CCS1, CCS0 TSR0 TSR1 TSR2 TSR3 four modes operation illustrated figure channel-by-channel programming, number collision detection modes selected each basic modes operation. future reference, they also depicted figure
Semiconductor Group
Functional Description
Quad Connection Mode
Programmable Time-Slots Receive Transmit Receive Transmit Receive Transmit Receive Transmit
Collision Data Slave/Multi-Master Collision Mode
ITC00735
Quad Connection Common Control Mode
Strobe
Receive Transmit Receive Transmit Receive Transmit Receive Transmit
Collision Data Slave/Multi-Master Collision Mode
ITC00736
Figure Operating Modes IDEC
Semiconductor Group
Functional Description
Single Connection Mode
Programmable Time-Slots Receive Transmit
Collision Data Slave/Multi-Master Collision Mode
ITC00737
Single Connection IOM® Mode
Receive Transmit
Collision Data Slave/Multi-Master Collision Mode
ITC00738
Figure Operating Modes IDEC
Semiconductor Group
Functional Description
Single Connection Mode
Programmable Time-Slots Receive Transmit
Programmable Time-Slots Transmit Receive Collision Data
Master Collision Mode
ITC00739
Single Connection IOM® Mode
Receive Transmit
Programmable Time-Slots Transmit Receive Collision Data
Master Collision Mode
ITC00740
Figure Operating Modes IDEC
Semiconductor Group
Functional Description
Interfaces
Microcontroller Interface IDEC programmable over 8-bit parallel microcontroller interface. Easy fast microprocessor access provided 8-bit address decoding chip. interface consists (19) lines directly compatible with processors multiplexed demultiplexed address/ data types (Siemens/Intel Motorola processor families). microprocessor interface signals summarized table
Table Microcontroller Interface Signals IDEC Symbol Input Output Open Drain (OD) Function
Address Data Bus. multiplexed address/data interface mode selected these lines transfer data commands between IDEC.
demultiplexed mode used, these lines interface with system data bus. Address Bus. These inputs interface address select internal register read write access. Only provided P-LCC package only active demultiplexed interface selected. Chip Select. this line selects IDEC read/write operation. Write. This signal indicates write operation, active (Siemens/Intel mode). Read/Write. "high", identifies valid access read operation. "low", identifies access write operation (Motorola mode). Only provided P-LCC package. Read. This signal indicates read operation, active (Siemens/Intel mode). Data Strobe. rising edge marks valid read write operation (Motorola mode). Only provided P-LCC package.
Semiconductor Group
Functional Description
Table (cont'd) Microcontroller Interface Signals IDEC Symbol Input Output Open Drain (OD) Function
Address Latch Enable. Siemens/Intel type multiplexed interface mode "high" this line indicates address internal register external address/data bus. Siemens/Intel type demultiplexed interface mode this line should connected demultiplexed Motorola type interface mode should connected Interrupt Request. signal activated when IDEC requests interrupt. Reset. "high" this input brings IDEC into reset state.
addition 8-bit processors, IDEC supports direct connection 16-bit processors. Thus, through internal address transformation, possible access IDEC registers using either even microprocessor addresses only microprocessor addresses only. Serial Interfaces Depending selected mode, IDEC supports four physically separate, full duplex serial interfaces, full duplex serial interface. addition data input data output lines, serial interface requires common data clock (input DCL) frame synchronization signal (input FSC). Input data latched falling edge output data clocked rising edge DCL. IDEC programmed that data clock rate either equal data rate, twice data rate.
Semiconductor Group
Functional Description
Individual Functions
2.4.1 Channel Access four HDLC controllers IDEC connected serial interfaces shown table table indicates selection data channel, selectable time slot widths, output driver type, function active-low Tri-State Control (TSC) output each operating modes. data output high impedance state outside time channel where data transmitted. Open-drain driver, Push-pull driver. output driver type refers SD0X SD0X, SD2X SD3X) outputs. push-pull signal. Quad Connection Time-Slot Mode Channel selection performed Time-Slot Select Registers (TSR). each HDLC channel, register gives position time slot with two-bit resolution. length time slot, either bits, selected using MODE register (CCS1, These parameters common receive transmit channel. case where number bits frame 512, frame synchronization signal need provided every frame beginning, since counters automatically reset frame end. When frame length equal either bits, frame synchronization signal provided beginning every frame.
Semiconductor Group
Functional Description
Table HDLC Controller Channel Selection Characteristics Mode MDS1 Channel MDS0 Input Channel Output Description
SD0R SD0R SD0R SD0R SD0X SD0X SD0X SD0X Single connection mode SD0R SD1R SD2R SD3R SD0X SD1X SD2X SD3X Quad connection common control mode SD0R SD0R SD0R SD0R SD0X SD0X SD0X SD0X Single connection mode SD0R SD1R SD2R SD3R SD0X SD1X SD2X SD3X Quad connection mode
Mode MDS1
Channel Characteristics MDS0 Channel Select registers strobe Fixed two-bit registers Channel Width Arbitrary
Tri-State Control (TSC) Signal Defined inverted Fixed two-bit
Output Driver
Open-drain driver, Push-pull driver. output driver type refers SD0X SD0X, SD1X, SD2X SD3X) outputs. push-pull signal.
Semiconductor Group
Functional Description
tristate control output line marks time slot when data transmitted/received HDLC controller position time slot with respect FSC, function register contents, shown figure
1-Bit Time-Slot
2-Bit Time-Slot
Bits
7-Bit Time-Slot Bits
8-Bit Time-Slot Bits
ITD02723
Figure Position Time Slot Different Channel Widths Function Register Contents
Semiconductor Group
Functional Description
Quad Connection Common Control Mode Channel selection performed active high strobe signal provided through input. strobe signal common four HDLC channels. output active when strobe active. Single ConnectionTS Mode time slots selected registers pertain same highway. programming channel otherwise proceeds exactly explained above. tristate control output line marks time slots when data transmitted/received four controllers. Single Connection Mode interface where frame composed channels figure Each channel unique structure. consists eight-bit bytes, corresponding ISDN channels, MONITOR byte, control byte which first bits allocated ISDN channel. single connection mode serial interface frame structure four HDLC channels assigned bits four consecutive channels. choice whether four HDLC controllers assigned channels governed microcontroller (Common Configuration Register). figure
Semiconductor Group
Functional Description
Multiplexed Frame Structure IOM® Interface
Data
Data
Byte
Byte
MONITOR Byte
Byte
ITD03562
Assignment HDLC Channels IOM® Mode
HDLC Channels
ITD03534
Figure
Semiconductor Group
Functional Description
2.4.2 HDLC Communication Functions Basic HDLC Functions Each four controller channels handles following basic HDLC functions. Receive direction Flag detection zero followed consecutive ones another zero recognized flag. Zero delete zero after five consecutive ones within HDLC frame deleted. Address recognition frame accepted rejected basis comparison most significant address byte (Service Access Point Identifier SAPI Link Access Procedure Dchannel LAPD) with three fixed SAPI values. checking field HDLC frame checked according generator polynomial Check abort Seven more consecutive ones interpreted abort sequence. Check idle Fifteen more consecutive ones interpreted "idle", reported processor status bit. Minimum length checking Reception frames with less than three bytes between opening closing flag reported microcontroller. Transmit direction Flag generation flag generated beginning every frame. Zero insert zero inserted after five consecutive ones within HDLC frame. generation field transmitted frame generated according generator polynomial Abort sequence generation HDLC frame terminated with abort sequence under software control FIFO underrun condition. Inter-frame time fill inter-frame time fill either flags idle (continuous ones) transmitted.
Semiconductor Group
Functional Description
Reception Transmission Functions FIFO Structure Each HDLC controller uses 64-byte FIFO direction intermediate storage data packets. data bytes between opening flag field HDLC frame passed through FIFO.
Flag
Flag
ITD03535
Generated HDLC Controller Bytes passed through FIFO
Figure HDLC Frame Structure receive transmit FlFOs both divided, blocks bytes each: accessible microcontroller inaccessible microcontroller. While microcontroller reading (receive FIFO) writing (transmit FIFO) data 32-byte block, other block filled (receive FIFO) emptied (transmit FIFO) IDEC. Thus length received transmitted frame limited FIFO size.
Semiconductor Group
Functional Description
Reception Frames Address Compare Before receive frame stored, address (the first byte following opening flag) optionally compared against three fixed values. SAPG SAPS SAPP "Group SAPI" "Signaling SAPI" "Packet SAPI"
Each address compare individually enabled disabled each HDLC channel bits AC0, (ACR register). effect match programmable shown table table assumed that address compare enable (AC) channel question. valid receive frames that channel accepted.
Table Address Compare Logic Effect Accept frames Reject frames with SAPP (16D) SAPS (0D) SAPS (0D) SAPP (16D) SAPG (63D) SAPG (63D) SAPP (16D) SAPG (63D) SAPS (0D) SAPG (63D), SAPS (0D) SAPP (16D)
Reject frames Accept frames with SAPP (16D) SAPS (0D) SAPS (0D) SAPP (16D) SAPG (63D) SAPG (63D) SAPP (16D) SAPG (63D) SAPS (0D) SAPG (63D), SAPS (0D) SAPP (16D)
Semiconductor Group
Functional Description
Frame Storage When frame accepted, stored receive FIFO. case frame length less than bytes, whole frame stored receive FIFO. After first bytes have been received, device prompts microcontroller read data from FIFO (Receive Pool Full interrupt status). Having done this, microcontroller releases FIFO. This done (Receive Message Complete) software command, after which rest frame, when ready, made available microcontroller (figure When whole frame shorter than bytes, final part frame longer than that becomes available, condition indicated (Receive Message End) interrupt status, instead RPF.
Prior Acknowledgement
After Acknowledgement
Bytes Inaccessible
Block
Free
Bytes Accessible
Block
Block
ITD03536
Figure Receive FIFO Case Frame Longer than Bytes. case frames least bytes long, microcontroller will repeatedly prompted interrupt read FIFO blocks bytes (except possibly final block). Again, after reading block, microcontroller acknowledges data software command thus releases FIFO. this done before additional 32-data bytes received, next data byte will lead "data overflow" condition. case several shorter frames seventeen stored inside HDLC controller. After interrupt (RME), frame available FIFO microcontroller read. sixteen other frames stored meanwhile upper half FIFO (figure 10). When microcontroller releases current data block from FIFO software command, next frame becomes available corresponding space freed upper half subsequent frame(s) (figure 10).
Semiconductor Group
Functional Description
Prior Acknowledgement Frame Bytes Inaccessible Frame
After Acknowledgement
Frame Frame
Bytes Accessible
Last Part Frame Frame
ITD03537
Figure Receive FIFO Case Short Frames interrupts accumulating process incorporated into queue transferred microcontroller well additional information about frame. particular, frame length stored register. Information such "frame aborted yes/no" "CRC error yes/no" "data overflow yes/no", included extra byte stored FIFO after last byte corresponding frame. Every interrupt acknowledged microcontroller. full FIFO beginning frame will lead frame overflow condition. microcontroller does wish preserve incoming frame, possibility exists ignore When corresponding command (RMD) issued, part frame stored deleted rest entire frame will ignored.
Semiconductor Group
Functional Description
Transmission Frames bytes intermediate storage provided HDLC controller transmit direction. After bytes have been written FIFO, transmission started software command (XHF). previous transmission still underway when transmission command issued, microcontroller access FIFO will blocked until first transmission completed (figure 11). This means that most complete frame written FIFO before transmission initiated. transmission request does include "frame end" indicator (XME), HDLC controller will request next data block interrupt FIFO contains more than bytes. This procedure will repeated until microcontroller indicates that frame closed. case when this indication given there more data ready transmission, frame terminated with abort sequence microcontroller notified transmit data underrun (XDU) interrupt. frame also aborted software command. completed transmission HDLC frame reported (Transmit Pool Ready) interrupt status.
Prior Transmission Command Frame
After Transmission Command Frame
After Interrupt "Transmit Pool Ready"
Inaccessible
Frame
Transmission
Inaccessible
Frame
Transmission
Inaccessible
Frame
Transmission
Accessible
Frame
Inaccessible
Frame
Accessible
ITD03538
Figure Transmit FIFO
Semiconductor Group
Functional Description
2.4.3 Collision Control Switching Functions IDEC possesses flexible collision control capabilities which totally transparent microcontroller. collision control modes enable circuit statistical multiplexing applications centralized de-centralized packet switches. Each four HDLC controllers individually programmed four modes register bits CMS1-0 (Collision Mode Select). Table lists four collision modes that selected, along with auxiliary lines used each case. outputs SD2X selected open-drain pushpull type.
Table Collision Modes IDEC CMS1 CMS0 Description Unconditional transmission Slave mode Multi-master mode Master mode SD1X SD2X Auxiliary Data
Data
Coll.
Coll.
Semiconductor Group
Functional Description
Unconditional Transmission Mode HDLC controller transmits frames without collision detection transmit line (time channel). Slave Mode input (Collision Data Receive) used control transmission frames. This input common HDLC controllers which programmed slave mode. Transmission inhibited "low" input. becomes "low" during transmission frame, frame aborted HDLC controller, data output high impedance. Refer figure
Single Connection Mode: SDOX Quad Connection Mode: SDiX,
ITD03539
Opening Flag
Figure Transmission Control Slave Mode (example) Note: evaluated falling edge DCL, rate equal data rate; falling edge immediately preceding rising edge used transmission, rate twice data rate. state evaluated HDLC controller only time channel used transmission that controller. (Figure simplified that grouping bits into time slots SD0X SD3X depicted, bits outside transmit time channel shown.) When switched high, inter-frame time fill marked transmit time channel transmission request pending, otherwise transmission starts first available instant. Transmission previously aborted frame automatically re-started HDLC controller beginning frame still available transmit FIFO. Otherwise interrupt (XDU) microcontroller indicates that transmission failed.
Semiconductor Group
Functional Description
slave mode applicable basic operation modes, both single connection quad connection applications. However, there only line. This should especially noted IDEC configured quad connection common control mode more than HDLC controller operated slave mode; when same time slot used more than HDLC controller slave mode. both cases more than controller evaluating line during same time interval, when goes "low" they stop transmitting. Multi-Master Mode multi-master mode controllers perform access procedure collision detection their assigned time channel(s). result, number IDECs assigned physical channel, where they perform statistical multiplexing. Collisions detected automatic comparison each transmitted with received input. this purpose logical "and" bits transmitted parallel controllers formed connected input CDR. This implemented most simply defining output line driver open drain type (ODS Consequently logical "and" outputs formed simply tying them together ("wired or"). result returned input parallel circuits. multi-master mode applicable operating modes, both single connection quad connection applications. quad connection mode, those output lines (SD0X SD3X) which this collision mode selected connected CDR. four HDLC controllers either programmed transmit separate time channels same time channel. prerequisite multi-master mode that inter-frame time fill used "idle". multi-master operation follows (refer figure 13). When mismatch between transmitted detected, HDLC controller stops sending further data output high impedance. soon detects transmit "idle" again, controller automatically attempts retransmit frame. definition, assumed idle when consecutive ones detected transmit channel. Normally equal
Semiconductor Group
Functional Description
Time Interval Transmission
Single Connection Mode: SDOX Quad Connection Mode: SDiX,
(See Note Figure
ITD03450
Figure Collision Detection Multi-Master Mode (example) automatic priority adjustment implemented multimaster mode. Thus, when complete frame successfully transmitted, increased ten, value restored eight when ten1's detected (CDR). Furthermore, transmission frame started HDLC controller after tenth This multi-master, deterministic priority management ensures equal right access every HDLC controller transmission medium, thereby avoiding blocking situations. Master Mode master mode requires three auxiliary connections: data input CDR, data output SD1X collision data SD2X. This mode applicable only single connection operation. master mode, controller performs functions: Switching data packets between main connection SD0X, SD0R auxiliary input output (CDR, SD1X) Resolution collisions between data from auxiliary connection HDLC frames from local microcontroller. Refer figure14.
Semiconductor Group
Functional Description
Controller
Collision Control Mode Programmable Time-Slots (TSR) HDLC Controller Controller Programmable Time-Slots (TSR) SDIX Data Data Controller SD2X Collision
Mode Fixed Time-Slots SD0X SD0R
Controller
ITS02721
Figure Connections Master Mode
Semiconductor Group
Functional Description
mode time slot programmed Time-Slot Select Register applies simultaneously SD0X/SD0R auxiliary lines CDR, SD1X SD2X. mode register selects time channel auxiliary connections CDR, SD1X SD2X only (however, channel width selected should bits, interface, ensure correct data throughput). switching data from SD0R SD1X transparent. switching data from SD0X depends state HDLC controller (transmit/no transmit) selected priorities, follows. When transmission command issued HDLC controller, data transparently switched through from SD0X. When transmit request issued Force HDLC Frame (FHF) data currently being received any) given priority. HDLC controller starts transmitting frame SD0X only after detected idle, other words, when eight ones observed CDR. Simultaneously, SD2X "low" indicate that data will accepted input data line. Figure shows time relation between (data SD2X (collision out) well logical relation between SD2X SD0X (data out). figures simplified that grouping bits into time slots SD0X, SD2X/CDR depicted. When transmit command issued Force HDLC Frame (FHF) frame currently being received aborted. Seven ones appended last aborted frame SD0X, after which HDLC controller starts transmitting frame (figure 15b). both cases, SD2X "high" again after delay eight bit-times following last closing flag, indicate that data accepted input data line. However, transmit command issued before that time, SD2X remains "low" transmission frame starts immediately after eighth
Semiconductor Group
Figure
Closing Flag Eight
with
SD2X Collision
Collision Resolution Master Mode with Programmable Priority (FHF)
SD2X Collision Abort Sequence Seven Frame from Frame from HDLC Controller Opening Flag Frame Closing Flag
SD0X Data
Functional Description
Command with
Semiconductor Group
Eight Bits Frame Frame from Frame from HDLC Controller Closing Flag Seven Frame Opening Flag Closing Flag Eight Bits
Data
Frame
SD0X Data
Command with
with
Data
Frame
ITD02722
Functional Description
Note Data Delay Master Mode data bits switched from SD0R SD1X from SD0X with minimum delay shown figure different cases distinguished: mode. this case time slots SD0R/SD0X CDR/SD1X identical. data delay from SD0X bit, whereas delay from SD0R times. mode with identical channel (time slot) SD0R/SD0X CDR/SD1X. This case identical previous one. mode with time slot CDR/SD1X which does coincide with channel bits SD0R/SD0X. this case, data bits undergo addition inherent delay different positions) delay time from SD0X, whereas additional delay introduced when going from SDOR SD1X.
Semiconductor Group
Functional Description
delay coinciding channel/time slot position SD0R/SD0X CDR/SD1X.
SD0R SD0X
SD1X
ITD03530
Figure Delay from SD0R/CDR SD1X/SD0X delay non-identical channel/time slot position SD0R/SD0X CDR/SD1X (possible only when SD0R/SD0X interface).
SD0R SD0X
SD1X
ITD03531
Figure Transmit Delay from SD0R/CDR SD1X/SD0X
Semiconductor Group
Functional Description
2.4.4 Test Functions test loop provided each four HDLC controllers IDEC. When test loop activated, input output HDLC channel connected together. test loop control independent each HDLC channel (bit TLP). test loop either transparent (forward data outputted line) non-transparent (forward data outputted line), depending selected mode. quad connection common control mode single connection mode loops transparent. other cases they non-transparent. During non-transparent loop, data output high impedance inside assigned time channel. Preprocessed Channels
IDEC supports
Command/lndicate channel IOM-2 interface.
handler takes care channels. Channel Handler activate handler, CCR:CDEN "1". handler used following switching modes: single connection mode single connection time-slot mode following access modes: unconditional transmission master multi master (only transmitter allowed subscriber). upstream direction signaling handler MONITORS received channels. Upon change interrupt generated (ISTAn:CD) actual value stored registers CIR3 CIR0. Only single last look carried out. channel sampled each frame. change detection only operates 4-bit channel. ISTAn:CD interrupt cleared when ISTAn read. downstream direction value written CIX3 CIX0 will sent channels each frame.
Semiconductor Group
Operational Description
Operational Description Microprocessor Interface Operation
IDEC microcontroller interface selected either Motorola type with control signals R/W, address data Siemens/lntel non-multiplexed type with control signals Address data Siemens/lntel multiplexed address/data type with control signals ALE; address/data non-multiplexed including Motorola type interface P-LCC-44 package IDEC needs used, since only this package provides additional pins separate 7-line address bus. input used control interface type follows tied tied Edge
occurrence edge ALE, either positive negative, time during operation immediately selects interface type (3). return other interface types possible only hardware reset issued.
Table Microcontroller Interface Summary Interface Type Address Data Control Pins P-DIP-28 P-LCC-44
Tied Tied Switching
Motorola Siemens/ Intel Siemens/ Intel
nonmultiplexed nonmultiplexed multiplexed
Reset
After hardware reset (pin RES), configuration/command register bits zeroed. interrupts active outputs high impedance state. Table sums state IDEC immediately after hardware reset been applied.
Semiconductor Group
Operational Description
Table State IDEC After Hardware Reset Register Name Value after Hardware Reset (hex) Meaning
Common registers Address comparison disabled. Single connection mode. Interrupt vector read bits Bits frame: 512. rate equal clock rate. Output drivers push-pull type. interrupt from IDEC channel. channel interrupts enabled.
VISR VISM Individual registers ISTA STAR
interrupts from channel channel interrupts enabled. Transmit FIFO ready written Receive line idle. commands. Test loop active. collisions will detected (unconditional transmission). Inter-frame time fill idle. Receiver de-activated. Channel disabled (high impedance output). Channel capacity bits/time slot. Zero bytes received. Time slot selected.
CMDR MODE
RFBC
Semiconductor Group
Operational Description
Initialization
purpose initialization IDEC into state where able correctly transfer HDLC frames manage collisions according requirements application. initialization process divided into phases. First, common settings determined registers VISM. These registers determine number HDLC channels used, serial interface configuration common characteristics serial input/output connections (table
Table Initialization IDEC(common bits) Function Configuration Serial interface characteristics Register Bits MDS1-0 Effect Basic configuration timing mode Output driver type open-drain push pull
Interrupt configuration VISM HDLC address recognition features MIC3-0
Clock rate data rate Number bits frame Mask HDLC channel(s) VISR read bits Address compare mode: accept/reject
SCG, SCS, AC0-3
Selection compare addresses
Address compare on/off HDLC channel
Semiconductor Group
Operational Description
Secondly, each HDLC channels initialized register shown table optional address comparison mode each HDLC channel selected programming register, located common address space (table Table Initialization HDLC Channels (channel-per-channel) Function Serial interface Register Bits MODE CMS1-0 CCS1-0 TSR7-0 Effect Collision mode Channel capacity Time slot Inter-frame time fill pattern Test loop Active channel (enable receiver transmitter, enable data outputs) Activate HDLC receiver
HDLC Controller MODE
Interrupt Structure
Special events reported processor interrupt logic IDEC. This logic allows connection more than IDEC interrupt input microcontroller. interrupt structure IDEC depicted figure Each HDLC channel circuit Interrupt Status Register (ISTA) where five possible interrupt causes read directly. When interrupt occurs HDLC channels, corresponding ISTA register interrupt line (INT) activated. Simultaneously, Vectored Interrupt Status Register (VISR) which indicates which four HDLC channels initiated interrupt. Thus, determine cause interrupt, microcontroller performs successively read VISR register (address 36/3F) read that ISTA register which indicated contents VISR.
Semiconductor Group
Operational Description
Mask VISM.VISR
Vector Bits)
Mask ISM.ISTA
Int. Status
Int. Status
Int. Status
Int. Status
ITD03532
Figure Interrupt Structure IDEC read ISTA clears register deactivates line. position which four bits Vectored Interrupt Status Register occupy AD7-0 when register read, programmable Vectored Interrupt Selection (CCR register). Thus, when VISR bits read positions 0-3, when VISR bits read positions 4-7. Unoccupied positions remain high impedance state. bits VISR selectively masked setting corresponding bits Vectored Interrupt Status Mask (VISM) register prevent several controllers from generating interrupt. that case, interrupts remain internally stored (pending) displayed VISR ISTA registers. Further, ISTA interrupts pertaining particular channel selectively masked Interrupt Status Mask register that channel. Pending interrupts will cause line activated will reported ISTA (and VISR) only when mask bits (and VISM) have been reset.
Semiconductor Group
Operational Description
Processing
After being initialized configuration/mode registers listed tables IDEC operational. control data transfer performed commands from microcontroller written Command Register (CMDR). Events pertaining data transfer reported Interrupt Status Register (ISTA) pointed Vectored Interrupt Status Register (VISR). Other events which lead interrupts monitored Status Register (STAR) information about receive frames found RFIFO Receive Frame Byte Counter (RFBC) register. powerful FIFO logic, which consists byte receive byte transmit FIFO channel, well intelligent FIFO controller, builds flexible interface upper protocol layers implemented microcontroller. Receive Frame Processing Reception HDLC frames with three more bytes between opening closing flags always reported microcontroller address comparison enabled address comparison enabled, reception frame dependent first byte received HDLC frame address field selected features address compare function (table bytes between opening flag field stored RFIFO. When frame (excluding field) longer than bytes, whole frame transferred block. reception frame reported Receive Message (RME) interrupt. length frame read from 8-bit register (RFBC). status byte appended data RFIFO after interrupt. includes information about frame, such frame aborted yes/no valid yes/no. frame status byte remain stored until microcontroller issues acknowledgment (Receive Message Complete: RMC). frame longer than bytes transferred microcontroller blocks bytes plus remainder block length bytes plus status byte. reception 32-byte block reported Receive Pool Full (RPF) interrupt data RFIFO remains valid until this interrupt acknowledged (RMC). This process repeated until reception remainder block reported (figure 18). Bits RFBC register represent number bytes stored RFIFO, including status byte. Bits indicate total number 32-byte blocks which were stored until reception remainder block. Bits overflow when counter status been reached indicate this case message length greater than bytes. contents RFBC register valid only after occurrence interrupt, remain valid until microprocessor issues acknowledgment (RMC). receive interrupts accumulated meantime stored (along with status bytes respective frame lengths) inside controller transferred microcontroller after each acknowledgment. frame could stored full FIFO, microcontroller informed this Receive Frame Overflow interrupt (RFO).
Semiconductor Group
Operational Description
(Reception Bytes) (Reception Bytes)
IDEC HDLC Receiver
System
(Reception Remainder)
ITD02720
Data Transfer Data Status Information (Status Byte, RFBC) Transfer
Figure Reception HDLC Frame Transmit Frame Processing After checking XFIFO status polling Transmit FIFO Write Enable (XFW) after Transmit Pool Ready (XPR) interrupt, bytes entered microcontroller XFIFO. Transmission HDLC frame started when Transmit HDLC Frame (XHF) command issued. HDLC controller will request another data block interrupt there more than bytes XFIFO frame close command (Transmit Message XME) been set. When set, remaining bytes XFIFO transmitted, field closing flag HDLC frame appended controller generates interrupt (figure19).
Semiconductor Group
Operational Description
(Transmission Flag plus Bytes)
IDEC HDLC Transmitter
(Transmission Bytes)
System
(Transmission Remainder plus plus Flag) Data Transfer
ITD02718
Figure Transmission HDLC Frame microcontroller does necessarily have transfer frame blocks bytes. matter fact, sub-blocks issued microcontroller separated command, between bytes long. XFIFO runs data command been set, frame will terminated with abort sequence (seven 1`s) followed inter-frame time fill, microcontroller will advised Transmit Data Underrun (XDU) interrupt. HDLC frame also aborted setting Transmit Reset (XRES) command bit. Table gives summary possible interrupts from HDLC controller appropriate reaction these interrupts.
Semiconductor Group
Operational Description
Table Possible Interrupt Causes Reactions Mnemonic Meaning Receive Pool Full Receive Message Reaction Read bytes from RFIFO acknowledge with RMC. Read "RFBC4-0" bytes from RFIFO acknowledge with RMC.
Receive Frame Overflow Error report statistical purposes (loss complete frame). Probable cause: deficiency software. Transmit Pool Ready Write data bytes XFIFO frame currently being transmitted finished frame transmitted, issue (and possible XME) command. Acknowledged read ISTA. Possible causes: Excessive software reaction times, transmit data collision.
Transmit Data Underrun
Semiconductor Group
Operational Description
Table lists most important commands which issued microcontroller setting several bits Command Register (CMDR).
Table List Commands Command Mnemonic 1000 0000 Meaning Receive Message Complete. Acknowledges block (RPF) frame (RME) stored RFIFO. Reset HDLC Receiver. RFIFO cleared receiver ready reception. Receiver Message Delete. part frame RFIFO deleted rest frame will ignored receiver. Transmit HDLC Frame. Enables transmission block entered last into XFIFO. frame complete. Transmit HDLC Frame close with flag. Same preceding, used master mode enforce transmission even case collision. Reset Transmitter. Clears XFIFO; frame currently being transmitted aborted.
RRES
0100
0000
0010
0000
0000
1000
XHFC F_XHF F_XHFC XRES
0000 0000 0000 0000
1010 1100 1110 0001
Semiconductor Group
Register Description
Detailed Register Description
following symbols used throughout chapter don't care used. logical write accesses switched IDEC either logical level read accesses. Register Address Layout
register consists configuration register common four channels (CCR) maskable vectored interrupt status register (VISR, VISM) register setting HDLC address recognition mode four channels (ACR) and, each four channels, individual registers. Multiplexed Address order support 16-bit microcontroller with multiplexed address bus, each register accessed with even address value (figure 20).
Semiconductor Group
Register Description
Read
Write
Channel-A Register Locations
VISR
VISM Channel-B Register Locations
Channel-C Register Locations
Channel-D Register Locations
ITD00741
Figure IDEC Register Multiplexed Address
Semiconductor Group
Register Description
address individual registers each channel shown table order obtain actual address register, "base" added address given table, follows: base channel channel channel channel
Table Address HDLC Channel Registers (multiplexed address bus) Address Even RFIFO ISTA STAR MODE RFBC XFIFO CMDR MODE Read Write
Semiconductor Group
Register Description
Non-Multiplexed Address address layout shown figure address individual registers each channel shown table order obtain actual address register, "base" added address given table, follows: base channel channel channel channel
Table Address HDLC Channel Registers Address Note: address values multiplexed non-multiplexed address cases related each other follows. AD0.7 multiplexed address bits A0.6 non-multiplexed address bits. Then: exor AD7. Read RFIFO ISTA STAR MODE RFBC Write XFIFO CMDR MODE
Semiconductor Group
Register Description
Read
Write
Channel-A Register Locations VISR VISM Channel-B Register Locations
Channel-C Register Locations
Channel-D Register Locations
ITD03533
Figure IDEC Register Non-Multiplexed Address
Semiconductor Group
Register Description
Register Description
Common Registers Common Configuration Register (CCR) Value after reset: 000n0000B MDS1 MDS0 CDEN Address: 37/3EH (1FH) Read/Write
MDS1,0 Mode Select
MDS1
MDS0
Description Single connection Quad connection Single connection Quad connection mode common control mode mode mode
Vectored Interrupt Selection channel (IOM mode), data bits VISR. channel (IOM mode), data bits VISR.
CDEN
Change Detection Enable.
Number Select. frame most bits long. frame between bits long.
Clock Rate Selection. clock rate equal data rate. clock rate equal twice data rate.
Output Driver Selection. Tristate. Open Drain.
Semiconductor Group
Register Description
selects driver type simultaneously data outputs (and control output SD2X master mode). However, single connection mode SD0X open-drain independent value ODS. Address Compare Register (ACR) Value after reset: Address: 34/3DH (1CH) Read/Write
AC0-3 Address Compare channel (0). first byte following opening flag receive frame will compared against reference values frame accepted rejected basis comparison. valid HDLC frames that channel stored. SAPI Compare Mode Accept HDLC frames which first address byte matches selected SAPI values. Reject HDLC frames which first address byte matches selected SAPI values. SAPI Compare Group first byte received HDLC frame compared with "Group SAPI" SAPG (63D). first byte received HDLC frame compared with SAPG. SAPI Compare Signaling first byte received HDLC frame compared with "Signaling SAPI" SAPS (0D). first byte received HDLC frame compared with SAPS. SAPI Compare Packet first byte received HDLC frame compared with "Packet SAPI" SAPP (16D). first byte received HDLC frame compared with SAPP.
Semiconductor Group
Register Description
HDLC address compare logic summarized table below.
Effect Accept frames Reject frames with SAPP (16D) SAPS (0D) SAPS (0D) SAPP (16D) SAPG (63D) SAPG (63D) SAPP (16D) SAPG (63D) SAPS (0D) SAPG (63D) SAPS (0D) SAPP (16D) SAPP (16D) SAPS (0D) SAPS (0D) SAPP (16D) SAPG (63D) SAPG (63D) SAPP (16D) SAPG (63D) SAPS (0D) SAPG (63D) SAPS (0D) SAPP (16D)
Reject frames Accept frames with
Semiconductor Group
Register Description
Vectored Interrupt Status Register (VISR) Value after reset: xxxx0000B
Address: 36/3FH (1EH)
Read
IC0-3 Interrupt from Channel When VISR read, these four bits placed data with offset determined (register CCR). Other positions remain high impedance. Mask Vectored Interrupt Status Register (VISM) Value after reset: nnnn0000B MIC3 MIC2 MIC1 MIC0 Address: 36/3FH Write
MIC0-3 Mask Interrupt from Channel A-D. mask bits active high. masked interrupt visible when VISR read. Instead, remains internally stored (pending). pending interrupt will generated corresponding IC0-3 will when mask reset zero. recommended bits during write accesses.
Semiconductor Group
Register Description
Individual Channel Registers FlFOs RFIFO (read), XFIFO (write) Address: Base (Base 0FH)
FlFO's have identical address range. addresses give access `current' FIFO location. Note RFIFO RFBC register bits indicate number bytes currently accessible microcontroller visible 32-byte RFIFO pool. more bytes read, data read after "RFBC" accesses "old" data loaded that part RFIFO previous current data. more than accesses, RFIFO will read cyclically (modulo 32). This will disturb next received frame. Note XFIFO more than bytes written XFIFO (without transmit command), XDOV interrupt generated. byte that entered first (first byte sent) will continuously overwritten extra write operations.
When closing flag receive frame detected, status byte appended data RFIFO. This byte following format:
RBC: Receive Byte Count length received frame (excluding flags Frame Check Sequence FCS) bits {1,2,3,.}). length multiple bits RDO: Receive Data Overflow part frame been lost because receive FIFO full. CRC: Check received bytes were correct RAB: Receive Abort implies that received frame aborted.
status byte equal indicates correctly received frame.
Semiconductor Group
Register Description
Status Command Registers Interrupt Status Register (ISTA) Value after reset: Address: Base 20/29H (Base 10H) Read
Receive Message End. complete frame length less than bytes, last part frame least bytes long stored receive FIFO, including status byte. number bytes stored given RFBC bits 0-4. Receive Pool Full. bytes frame have arrived receive FIFO. frame completely received. Receive Frame Overflow. least complete frame lost because storage space available RFIFO. Transmit Pool Ready. data block entered into XFIFO. Transmit Data Underrun. Transmitted frame terminated with abort sequence because either data available transmission XFIFO command issued, collision occurred after least block data been completely transmitted, thus automatic retransmission cannot attempted. Change detection interrupt. value been entered into register.
Note:
possible transmit frames when interrupt remains unacknowledged. Mask Interrupt Status Register (ISM) Value after reset: Address: Base 20/29H (Base 10H) Write
Each interrupt source ISTA register selectively masked setting corresponding ISM. Masked interrupts indicated when ISTA read. Instead, they remain internally stored pending. interrupt generated after mask reset zero.
Semiconductor Group
Register Description
Status Register (STAR) Value after reset: XDOV
Address: Base /28H (Base 11H)
Read
XDOV Transmit Data Overflow. More than bytes have been written into XFIFO. Transmit FIFO Write Enable. Data entered into XFIFO. Busy state receive line. this position indicates "idle" state input data line more consecutive ones). Receive line Active. Indicates whether flags/frames being received line (1). takes value after seven consecutive ones received line.
VN3-0 Version Number chip version version version
Semiconductor Group
Register Description
Command Register (CMDR) Value after reset: RRES
Address: Base 21/28H (Base 11H)
Write
XRES
Receive Message Complete. Reaction internupt. receive FIFO pool currently accessible microcontroller released subsequent frame 32-byte block data).
RRES Receiver Reset. HDLC receiver reset, receive FIFO cleared data. Receive Message Delete. Reaction interrupt. entire frame ignored receiver. part frame already stored discarded. Transmit HDLC Frame. Transmission HDLC frame block thereof) initiated. Force HDLC Frame. Used master collision mode (CMS1,0 11). When this Transmit HDLC Frame (XHF) command issued, controller aborts frame from any) sending seven SD0X then starts transmission. SD2X "low" indicate that data will accepted input data line. Transmit Message End. Indicates that current transmit frame closed with flag.
XRES Transmitter Reset. HDLC transmitter reset, XFIFO cleared data HDLC frame currently being transmitted any) aborted.
Semiconductor Group
Register Description
Mode Register (MODE) Value after reset: CMS1 CMS0
Address: Base 22/2BH (Base 12H)
Read/Write
CCS1 CCS0
Test Loop Input output HDLC channel connected together when test loop either transparent MDS1,0 MDS1,0 11).
CMS1,0 Collision Mode Select.
CMS1
CMS0
Description Unconditional transmission Slave mode Multi-master mode Master mode
Interframe Time Fill Idle (ITF flags (ITF used interframe time fill. Receiver Active. Receiver activated deactivated (0). Channel Active. channel completely disabled (receiver transmitter inactive, transmit line high impedance, output) long "0".
CCS1,0 Channel Capacity Select. These bits select number bits time slot where data received transmitted. They have significance only when MDS1,0 (Single connection mode Quad connection mode). rates given below assume channel repetition rate kHz.
CCS1
CCS0
Time Slot Width bits bits bits
Channel Data Rate kbit/s kbit/s kbit/s kbit/s
Semiconductor Group
Register Description
Command/lndicate Channel Receive Channel (CIR0 (read) Address: 23,2A offset (multiplexed), offset (demux)
Reset value: nnnn1111 bit7: bit6: bit5: bit4: CI3-0: used. used. used. used. Received code, will updated each frame. received first.
Command/lndicate Channel Receive Channel (CIX0 (write) Address: 23,2A offset (multiplexed), offset (demux)
Reset value: nnnn1111 bit7: bit6: bit5: bit4: CI3-0: used. used. used. used. Received code, will updated each frame. received first.
Semiconductor Group
Register Description
Recelve Frame Byte Counter (RFBC) Value after reset: RDC7 RDC6 RDC5 RDC4
Address: Base 25/2CH (Base 15H)
Read
RDC3 RDC2 RDC1 RDC0
RDC7-0 Receive Data Count Total number bytes received frame, including status byte. contents register valid after interrupt. RDC4-0 indicate length data block currently available receive FIFO. RDC7-5 count number full 32-byte blocks frame which have already been received. frame length exceeds bytes, RDC7-5 hold value "111", only RDC4-0 continue count modulo Time-Slot Register (TSR) Value after reset: TS7-0 Address: Base 25/2CH (Base 15H) Write
Time-Slot Select Determine particular time slot where HDLC controller receive transmit. This register significance only when MDS1,0 00,10 (single connection modes quad connection mode). register gives position time slot (either bits wide, CCS1,0) two-bit increments (two-bit resolution). position time slot relative frame sync signal that marks beginning frame.
Semiconductor Group
Electrical Characteristics
Electrical Characteristics
Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Voltage with respect ground Symbol Limit Values Unit
Characteristics Parameter L-input voltage H-input voltage L-output voltage H-output voltage H-output voltage Power supply current operational power down Symbol Limit Values Unit Test Condition min. max.
0.45
(SD0X.SD3X) (all other pins)
4096 Inputs output loads
Input leakage current Output leakage current
Capacitances Parameter Input capacitance capacitance Symbol Limit Values Unit min. max. Test Condition
Semiconductor Group
Electrical Characteristics
Characteristics
Inputs driven logical logical "0". Timing measurements made logical logical "0". testing input/output waveforms shown below.
Test Points 0.45 Device Under Test
Load
ITS00621
Figure Input/Output Waveforms Tests
Semiconductor Group
Electrical Characteristics
Microcontroller Interface TimingmP Read Cycle Siemens/Intel ModemP Read CyclemP Read CyclemP Read Cycle
Read Cycle
Data
ITT00712
Figure Write Cycle
-AD7 Data
ITT00713
Figure Multiplexed Address Timing
Address
ITT00714
Figure
Semiconductor Group
Electrical Characteristics
Multiplexed Address Timing
Address
ITT00715
Figure
Motorola Mode
Read Cycle
Data
ITT00716
Figure
Semiconductor Group
Electrical Characteristics
Write Cycle
Data
ITT00717
Figure
Address Timing
ITT00718
Figure
Semiconductor Group
Electrical Characteristics
Interface Timing
Parameter pulse width Address setup time Address hold time from Address latch setup time Address setup time Address hold time guard time Delay after setup pulse width Data output delay from Data float from control interval pulse width Data setup time Data hold time from control interval
Symbol
Limit Values min. max.
Unit
Semiconductor Group
Electrical Characteristics
Serial Interface Timing Characteristics
ITT00744
Figure Definition Period Width
Parameter period high
Symbol min.
Limit Values typ.
Unit
Test Condition single clock rate double clock rate single clock rate double clock rate
Semiconductor Group
Electrical Characteristics
Input/Output Characteristics Single Connection Modes Quad Connection Mode
Frame Frame
Data Rate equal Data Rate Data
Frame
Frame
Frame
Rate equal twice Data Rate
Data
Data
Frame
ITD00745
Figure Timing Characteristics
Semiconductor Group
Electrical Characteristics
Timing Characteristics Parameter set-up time setup time* hold time Output data delay from Input data set-up Input data hold Output data delay from FSC* *Note: This delay applicable cases when first time slot been programmed: When appears first time, e.g. system power-up. When number bits frame equal either 512. Symbol min. Limit Values max. Unit
Semiconductor Group
Electrical Characteristics
Quad Connection Common Control Mode
High Impedance Data
High Impedance
Data
ITD00746
Figure Characteristics (strobe)
Parameter set-up time hold time Output data from high impedance active Output data from active high impedance Output data delay from Input data Input data hold
Symbol min.
Limit Values max.
Unit
Semiconductor Group
Electrical Characteristics
Data
Data
ITD00747
Figure Data Characteristics Parameter Output data delay from Input data set-up Input data hold delay from Data OUT: Symbol min. Limit Values max. Unit
SD0X single connection modes SD0X, SD1X, SD2X, SD3X quad connection modes SD1X, SD2X master mode SD0R single connection mode SD0R, SD1X, SD2R, SD3R quad connection modes slave, multi-master master modes
Data
Characteristics Parameter high Symbol min. Limit Values max. Unit
Semiconductor Group
Appendix
Appendix
version number (STAR0-3:VN1, VN0) been incremented bin. IDEC version channel handler implemented. CCR:bit3 write accesses specified IDEC Technical Manual version upward compability ensured. When CCR:bit3 programmed channel handler active. support channel handler, these changes have been made: ISTA0-3:bit1 Change detection interrupt (maskable, reset when appropriate ISTA read).
Register
Address (Multiplexed busses) 23,2A 63,6A A3,AA E3,EA 23,2A 63,6A A3,AA E3,EA
Address (Separate busses)
Reset Value
Access
CIR0 CIR1 CIR2 CIR3 CIX0 CIX1 CIX2 CIX3
Please refer IDEC channel handling 2/90 details.
Semiconductor Group
Package Outlines
Package Outlines
Plastic Dual-in-Line Package, P-DIP-28
15.24 ±0.2
±0.3
0.25 +0.1 -0.3 +1.2 15.24
2.54
0.45
+0.1
35.9 -0.4
0.25
Index Marking
Plastic-Leaded Chip Carrier, P-LCC-44 (SMD)
Surface Mounted Device
Dimensions
Semiconductor Group

Manual 05.92 2075 Revision History: 05.92 Page Sub

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