High-Level Serial Communication Controller Extended (HSCX) 82525; 8252
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High-Level Serial Communication Controller Extended (HSCX) 82525; 82526 82525; 82526
User's Manual 10.94
82525; 82525; 82526; 82526 Revision History: 10.94 Previous Releases: Page 01.92
Subjects (changes since last revision) Update
Data Classification Maximum Ratings Maximum ratings absolute ratings; exceeding only these values cause irreversible damage integrated circuit. Characteristics listed characteristics ensured over operating range integrated circuit. Typical characteristics specify mean values expected over production spread. otherwise specified, typical characteristics apply given supply voltage. Operating Range operating range functions given circuit description fulfilled. detailed technical information about "Processing Guidelines" "Quality Assurance" ICs, "Product Overview".
Edition 10.94 This edition realized using software system FrameMaker®. Published Siemens Bereich Halbleiter, Marketing-Kommunikation, D-81541
Siemens 1994. Rights Reserved. patents other rights third parties concerned, liability only assumed components applications, processes circuits implemented within components assemblies. information describes type component shall considered assured characteristics. Terms delivery rights change design reserved. questions technology, delivery, prices please contact Offices Semiconductor Group Germany Siemens Companies Representatives worldwide (see address list). technical requirements components contain dangerous substances. information type question please contact your nearest Siemens Office, Semiconductor Group. Siemens approved CECC manufacturer. Packing Please recycling operators known you. also help touch with your nearest sales office. agreement will take packing material back, sorted. must bear costs transport. packing material that returned unsorted which obliged accept, shall have invoice costs incurred.
General Information
Table Contents Page Features Definitions Functions System Integration Functional Description Operating Modes Auto-Mode (MODE: MDS1, MDS0 Non-Auto Mode (MODE: MDS1, MDS0 Transparent Mode (MODE: MDS1, MDS0, 101) Transparent Mode (MODE: MDS1, MDS0, 100) Extended Transparent Modes (MODE: MDS1, MDS0 Receive Data Flow (Summary) Transmit Data Flow Procedural Support (Layer-2 Functions) Full-Duplex LAPB/LAPD Operation Half-Duplex SDLC-NRM Operation Error Handling Interface Register Data Transfer Modes Interrupt Interface Interface FIFO Structure Serial Interface (Layer-1 Functions) Clock Modes Clock Recovery (DPLL) Configuration Data Encoding Modem Control Functions (RTS/CTS, Special Functions Fully Transparent Transmission Reception Cyclic Transmission (Fully Transparent) Continuous Transmission (DMA Mode only) Receive Length Check Feature Insertion Data Inversion.
Semiconductor Group
General Information
Table Contents Page Test Mode Special Function Operational Description RESET Initialization Operational Phase Data Transmission Data Reception Detailed Register Description. Register Address Arrangement Register Definitions Electrical Characteristics Quartz Specifications Package Outlines
Semiconductor Group
General Information
82525 High-Level Serial Communication Controller compatible 82520 HSCC with extended features functionality (HSCX). 82526 software compatible 82525, realizing HDLC channel (channel HSCX been designed implement high-speed communication links using HDLC protocols reduce hardware software overhead needed serial synchronous communications. 8-bit demultiplexed adaptive interface fits perfectly into every Siemens/Intel Motorola 16-bit microcontroller microprocessor system. data through-put from/to system memory optimized transferring blocks data (usually bytes) means interrupt request. Together with storing capacity bytes on-chip FIFO's, serial interfaces effectively decoupled from system which drastically reduces dynamic load reaction time CPU. HSCX directly supports X.25 LAPB, ISDN LAPD, SDLC (normal response mode) protocols capable handling large layer-2 protocol functions independently from host processor. Furthermore, HSCX opens wide area applications which time division multiplex methods (e.g. time-slot oriented systems, systems designed packet switching, ISDN applications) programmable telecom-specific features. HSCX fabricated using Siemens advanced ACMOS technology available P-LCC-44 package. data link controller handles functions necessary establish maintain HDLC data link, such Flag insertion detection, stuffing, generation checking, Address field recognition. Associated with each serial channel independent command status registers (SP-REG) 64-byte deep FIFO's transmit receive direction. capability been added HSCX means 4-channel interface (SAB 82525) with request line each transmitter receiver both channels.
General Advanced CMOS technology power consumption: active standby
Semiconductor Group
High-Level Serial Communications Controller Extended (HSCX)
Preliminary Data Features
82525 82526 82525 82526
CMOS
Serial Interface independent full-duplex HDLC channels (SAB 82526: channel) chip clock generation external clock source chip DPLL clock recovery each channel independent baudrate generators (SAB 82526: baudrate generator) Independent time-slot assignment each channel with programmable time-slot length (1-256 bit) Different modes data encoding Modem control lines (RTS, CTS, Support configuration collision resolution Programmable inversion Transparent receive/transmit data bytes without HDLC framing Continuous transmission bytes possible Data rate Mbit/s
P-LCC-44-1
P-MQFP-44-2
Type 82525 82526 82525 82526 82525
Ordering Code Q67100-H6486 Q67100-H6512 Q67100-H6504 Q67100-H6511 Q67101-H6482
Package P-LCC-44-1 (SMD) P-LCC-44-1 (SMD) P-LCC-44-1 (SMD) P-LCC-44-1 (SMD) P-MQFP-44-2 (SMD)
Semiconductor Group
10.94
Features (cont'd)
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Protocol Support Various types protocol support depending operating mode Auto-mode Non-auto mode Transparent mode Handling oriented functions modes Support LAPB/LAPD/SDLC/HDLC protocol auto-mode S-frame handling) Modulo modulo operation Programmable time-out retry conditions Programmable maximum packet size checking Interface byte FIFO's channel direction Storage capacity short frames receive direction Efficient transfer data blocks from/to system memory interrupt request 8-bit demultiplexed multiplexed interface Intel Motorola type interface
Semiconductor Group
Configurations (top view)
RD/IC1 DRQTA
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P-LCC-44
WR/IC0 RxDA RTSA CTSA/CxDA TxDA TxDB CTSB/CxDB RTSB RxDB DRQRA DRQTB DRQRB TxCLKA RxCLKA AxCLKA RxCLKB TxCLKB AxCLKB DACKA DACKB
HSCX 82525 85525
ALE/IM0
ITP00944
WR/IC0 N.C. N.C. N.C. N.C. TxDB CTSB/CxDB RTSB RxDB
RD/IC1 N.C.
N.C. DRQTB DRQRB N.C. RxCLKA AxCLKA RxCLKB TxCLKB AxCLKB N.C. DACKB
P-LCC-44
HSCX1 82526 82526
ALE/IM0
ITP00945
Semiconductor Group
Configurations (top view)
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P-MQFP-44-2
DRQRA DRQTB DRQRB TxCLKA RxCLKA AxCLKA RxCLKB TxCLKB AxCLKB DACKA DACKB
DRQTA RD/IC
HSCX 82525
ALE/IM
WR/IC RxDA RTSA CTSA/CxDA TxDA TxDB CTSB/CxDB RTSB RxDB
ITP05885
Semiconductor Group
Definitions Functions
P-LCC P-MQFP
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Symbol
Input Output
Function
RD/IC1
Data data lines bidirectional threestate lines which interface with system's data bus. These lines carry data command/status from HSCX.
Read, Intel mode, connected This signal indicates read operation. When HSCX selected read signal enables drivers data from internal register addressed A0-A6 data bus. When HSCX selected transfers DACK, signal enables driver data from respective receive FIFO data bus. Inputs A0-A6 ignored. Input Control Motorola mode connected high. Motorola mode been selected this serves either Enable, active high (IM0 tied low) Data Strobe, active (IM0 tied high) input (depending selection IM0) control read/ write operations.
WR/IC0
Write, Intel mode This signal indicates write operation. When active HSCX loads internal register with data provided data bus. When DACK active transfers HSCX loads data from data respective transmit FIFO. Input Control Motorola mode Motorola mode, this serves input distinguish between read write operations.
Chip Select signal selects HSCX read/write operation.
Semiconductor Group
Definitions Functions (cont'd)
P-LCC P-MQFP
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Symbol
Input Output
Function
RXDA RXDB RTSA RTSB
Receive Data (channel A/channel Serial data received these pins standard CMOS levels.
Request Send (channel A/channel When mode register set, signal goes low. When reset, signal goes high transmitter finished there further request transmission. configuration, this programmed CCR2 during actual transmission frame shifted clock period, excluding collision bits during reception data frame stay always high (RTS disabled).
CTSA/ CXDA CTSB/ CXDB
Clear Send (channel A/channel inputs enables respective transmitter. Additionally, interrupt issued state transition occurs (programmable feature). "Clear Send" function required, inputs connected directly VSS. Collision Data (channel A/channel configuration, external serial must connected respective collision detection.
TXDA TXDB
Transmit Data (channel A/channel Transmit data shifted these pins standard CMOS levels. These pins programmed work either push-pull, open drain outputs supporting configurations.
RESET high signal this input forces HSCX into reset state. HSCX power-up mode during reset power-down mode after reset. minimum pulse width
Semiconductor Group
Definitions Functions (cont'd)
P-LCC P-MQFP
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Symbol
Input Function Output
Input Mode Connecting this either interface adapted either Siemens/Intel Motorola environment. LOW: HIGH: Intel mode Motorola mode
ALE/
Address Latch Enable (Intel mode) high this line indicates address external address/data bus, which will select HSCX's internal registers. address latched HSCX with falling edge ALE. This allows HSCX directly connected with multiplexed address/data compatible 82520 HSCC. address input pins A0-A6 must externally connected data pins (D0-D6 8-bit CPU's, D1D7 16-bit CPU's, i.e. multiply internal register addresses This should connected high de-multiplexed bus. Input Mode Motorola mode Motorola Mode, level this determines function (see description
Ground Address These inputs interface with seven bits system's address select internal registers read write. They usually connected A0-A6 8-bit systems A1-A7 16-bit systems.
Semiconductor Group
Definitions Functions (cont'd)
P-LCC P-MQFP
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Symbol
Input Function Output
Interrupt Request signal activated, when HSCX requests interrupt. determine particular source cause interrupt reading HSCX's interrupt status registers. (ISTA, EXIR). open drain output, thus interrupt requests outputs several HSCX's connected interrupt input "wired-or" combination. This must connected pull-up resistor.
DACKA DACKB
Acknowledge (channel A/channel When low, this input signal from controller notifies, HSCX, that requested cycle controlled DRQxx (pins 37-40) progress, i.e. controller achieved mastership from will start data transfer cycles (either read write). Together with been requested from receiver, with been requested from transmitter, this input works like enable data byte read from written receive transmit FIFO specified channel. DACKn active, input pins A0-A6 ignored FIFOs implicitly selected. DACKn signals used, these pins must connected VDD.
AxCLK AxCLK
Alternative Clock (channel A/channel These pins realize several input functions. Depending selected clock mode, they supply either Carrier Detect) modem control general purpose input. This programmed functions receiver enable "auto start" feature selected (CAS XBCH set). state this read from VSTR register, receive strobe signal (clock mode frame synchronization signal time-slot oriented operation mode (clock mode together with RxCLK, crystal connection internal oscillator (clock mode AxCLK only).
Semiconductor Group
Definitions Functions (cont'd)
P-LCC P-MQFP
82525 82526 82525 82526
Symbol
Input Function Output
TxCLK TxCLK
Transmit Clock (channel A/channel functions these pins depend programmed clock mode, provided that CCR2 register reset. Programmed inputs CCR2 reset), they supply either transmit clock respective channel (clock mode transmit strobe signal (clock mode Programmed outputs CCR2 set), TxCLK pins supply either transmit clock respective channel which generated either from baudrate generator (clock mode CCR2 set), from DPLL circuit (clock mode from crystal oscillator (clock mode tristate control signal indicating programmed transmit time-slot (clock mode
RxCLK RxCLK
Receive Clock (channel A/channel functions these pins also depend programmed clock mode. each channel, RxCLK supply either receive clock (clock mode receive transmit clock (clock mode clock baudrate generator (clock mode crystal connection internal oscillator (clock mode 4,6,7, RxCLK together with AxCLK
DRQRA DRQRB
Request Receiver (channel A/channel receiver HSCX requests data transfer activating this line. DRQRn remains high long receive FIFO requires data transfers, thus always blocks data (32, bytes) transferred. DRQRn deactivated immediately following falling edge last read cycle.
Semiconductor Group
Definitions Functions (cont'd)
P-LCC P-MQFP
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Symbol
Input Output
Function
DRQTA DRQTB
Request Transmitter (channel A/channel transmitter HSCX requests data transfer activating this line. DRQTn remains high long transmit FIFO requires data transfers. amount data bytes transferred from system memory HSCX byte count) must written first XBCH, XBCL registers. Always blocks data bytes REST, 1,.) transferred till byte count reached. DRQTn deactivated immediately following falling edge last cycle.
Power supply
Semiconductor Group
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A0-A6 SP-REG D0-D7 RD/IC1 WR/IC0 ALE/IMO Interface Transmit FIFO Receive FIFO
Channel Controller Decoder Collision Detection RxDA TxDA RTSA CTSA/ CxDA
Data Link Controller
DPLL RxCLKA Clock Controll AxCLKA TxCLKA
TxCLKB DRQTA DRQRA DACKA DRQTB DRQRB DACKB Channel
ITB00946
AxCLKB RxCLKB Interface CTSB/ CxDB RTSB TxDB RxDB
Figure Block Diagram 82525/SAB 82526 HSCX 82526 comprises (channel 82525 completely independent full-duplex HDLC channels (channel channel supporting various layer-1 functions means internal oscillator, Baud Rate Generator (BRG), Digital Phase Locked Loop (DPLL), Time-Slot Assignment (TSA) circuits. Furthermore, layer-2 functions performed on-chip (Link Access Procedure, e.g. LAPB LAPD) controller.
Semiconductor Group
System Integration General Aspects Figure gives general overview system integration HSCX.
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System DRQTA, DRQRA, DACKA Controller DRQTB, DRQRB, DACKB HSCX
DATA Serial Serial Channel Channel
ITS00947
Figure General System Integration HSCX HSCX interface consists 8-bit bidirectional data (D0-D7), seven address line inputs (A0-A6), three control inputs (RD/DS, WR/R/W, CS), interrupt request output (INT) 4-channel interface (DRQTA, DRQRA, DACKA, DRQTB, DRQRB, DACKB). Mode input pins (strapping options) allow interface configured either Siemens/ Intel Motorola environment. Generally, there types transfers occurring system bus: command/status transfers, which always controlled CPU. sets operation mode (initialization), controls function sequences gets status information writing reading HSCX's registers (via register address A0-A6). data transfers, which effectively performed without interaction using HSCX's interface (DMA mode). Optionally, interrupt controlled data transfer done (interrupt mode).
Semiconductor Group
Status
Memory
Command
Specific Applications HSCX with 8051 Microcontroller
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cost-sensitive applications, HSCX interfaced with small 8051 microcontroller system (without support) very easily shown figure
8051
INT0
DACKA DACKB 82525 HSCX
Channel
Channel
Latch
Common
A15,D0
Memory
ITS00948
Figure HSCX with 8051 Although HSCX provides demultiplexed interface, optionally connected directly local multiplexed 8051 because internal address latch function (via ALE, compatibility 82520 HSCC). address lines must wired externally data lines (direct connection) this case. Intel mode selected connecting VSS). Since data transfer controlled interrupt, acknowledge inputs (DACKA, DACKB) connected
Semiconductor Group
HSCX with 80188 Microprocessor
82525 82526 82525 82526
system with minimized additional hardware expense with 80188 microprocessor shown figure
INTn
PSCn DRQ0 DRQ1
DRQTA DRQRA DACKA DACKB
Serial Channel
80188
82525 HSCX
Serial Channel
Latches
Transceiver
System
A0-A6
D0-D7
System Memory
ITS00949
Figure HSCX with 80188 HSCX connected demultiplexed system bus. Data transfer serial channel done 2-channel on-chip controller 80188, other channel serviced interrupt. Since 80188 does provide acknowledge outputs, data transfer from/to HSCX controlled address information DACKA, DACKB inputs used. This solution supports applications with high speed data rate serial channel with minimum hardware expense making on-chip peripheral functions 80188 (chip select logic, interrupt controller, controller).
Semiconductor Group
HSCX with 80186 Microprocessor 82258 Advanced Controller (ADMA)
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applications, where high-speed channels required, 16-bit system with 80186 82258 ADMA suitable. This shown figure
INTn
PSCn DREQ0 DREQ1 DACK0 DACK1 DREQ2 DREQ3 DACK2 DACK3
HOLD
DRQTA DRQRA
Serial Channel
80186
HLDA
82258 ADMA
DACKA
82525
Serial Channel
DRQTB HSCX DRQRB
DACKB
AD15
AD15
Latches
Transceiver
Control
System
System Memory
ITS00950
Figure HSCX with 80186 CPU/SAB 82258 ADMA
Semiconductor Group
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four selector channels ADMA used serving four request sources HSCX, allowing very high data rates both system serial channels. Another advantage ADMA it's data chaining feature, providing optimized memory management receive transmit data. Recording HSCX, linked chain byte deep buffers which subsequently filled with contents HSCX's FIFOs during reception. used buffers saved linked another buffer chain reserved reception next frame. result, it's necessary reserve very large space system memory, determined maximum frame length every received frame. this example, ADMA works directly CPU's local shares same interface logic (address latches, transceivers, controller) with 80186. Since acknowledge line provided each request, DACK outputs must ANDed together input HSCX. HSCX's data lines connected lower half system data address lines thus (from CPU's point view) internal register addresses must multiplied (even register addresses only). e.g. CMDR register: HSCX address system address C2H.
Functional Description General HSCX distinguishes from other level HDLC devices advanced characteristics. most important are: Enlarged support link configurations. Beyond point-to-point configurations, HSCX directly enables point-to-multipoint multimaster configurations without additional hardware software expense. point-to-multipoint configurations, HSCX used master well slave station. Even when working slave station, HSCX initiate transmission data time. internal function block provides means idle collision detection collision resolution, which necessary several stations start transmitting simultaneously. These features were integrated support multimaster configurations.
Semiconductor Group
Point-to-Point Configuration
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HSCX
HSCX
Controller
Controller
ITC02705
Receive Data Transmit Data
Controller
Master
HSCX
Point-to-Multipoint Configuration
HSCX
HSCX
HSCX
HSCX
Slave
Controller
Slave
Controller
Slave
Controller
Slave
Controller
ITC02694
Receive Data Transmit Data
Collision Data
Multimaster Configuration
HSCX
HSCX
HSCX
HSCX
Master
Controller
Master
Controller
Master
Controller
Master
Controller
ITC02695
Receive Data Transmit Data
Collision Data
Figure Link Configuration Semiconductor Group
Support layer-2 functions HSCX
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Beside those bit-oriented functions usually supported with HDLC protocol, such stuffing, check, flag address recognition, HSCX provides high degree procedural support. special operating mode (auto-mode), HSCX processes information transfer procedure handshaking (I-, S-frames HDLC protocol) autonomously. only restriction that window size number outstanding unacknowledged frames) limited which will sufficient most applications. communication procedures mainly processed between communication controllers between processors. Thus dynamic load software expense largely reduced.
HSCX
HSCX
Frame Frame Frame
ITS05502
Figure Procedural Support Auto-Mode informed about status procedure manage receive transmit data mainly. order maintain cost effectiveness flexibility, such functions link setup/disconnection error recovery case protocol errors (U-frames HDLC protocols) implemented hardware must done user's software. Telecom specific features special operating mode, HSCX transmit receive data packets time-slots programmable width (clock mode Furthermore, HSCX transmit receive variable data portions within defined window more clock cycles, which selected external strobe signal (clock mode These features make HSCX especially suitable applications using time division multiplex methods, such time-slot oriented systems, systems designed packet switching, ISDN applications. FIFO buffers efficient transfer data packets. further speciality HSCX FIFO buffers used temporary storage data packets transferred between serial communications interface parallel system bus. Also because overlapping input/output operation (dual-port behaviour), maximum message length limited size buffer. Together with capability, dynamic load drastically reduced transferring data packets block block direct memory access. only initiate data transmission HSCX determine status case completely received frames, involved data transfers. Semiconductor Group
Operating Modes
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HDLC controller each channel programmed operate various modes, which different treatment HDLC frame receive direction. Thus, receive data flow address recognition features effected very flexible way, which satisfies most requirements. There different operating modes which MODE register. Auto-Mode (MODE: MDS1, MDS0 Characteristics: Window size arbitrary message length, address recognition. HSCX processes autonomously numbered frames (S-, I-frames) HDLC procedure. HDLC control field, data I-field frames additional status byte temporarily stored RFIFO. HDLC control field well additional information also read from special registers (RHCR, RSTA). According selected address mode, HSCX perform 2-byte 1-byte address recognition. 2-byte address field selected, high address byte compared with fixed value (group address) well with individually programmable values RAH1 RAH2 registers. According ISDN LAPD protocol, high byte address will interpreted COMMAND/RESPONSE (C/R), dependent setting RAH1, will excluded from address comparison. Similary, compare values programmed special registers (RAL1, RAL2) address byte. valid address will recognized case high byte address field correspond compare values. Thus, HSCX called (addressed) with different address combinations, however, only logical connection identified through address combination RAH1, RAL1 will processed auto-mode, others non-auto mode. HDLC frames with address fields that match with address combinations, ignored HSCX. case 1-byte address, RAL1 RAL2 will used compare registers. According X.25 LAPB protocol, value RAL1 will interpreted COMMAND value RAL2 RESPONSE. After receiving frame takes clock cycles generate response frame start transmission.
Non-Auto Mode (MODE: MDS1, MDS0 Characteristics: address recognition, arbitrary window size. frames with valid addresses (address recognition identical auto-mode) forwarded directly system memory. HDLC control field, data I-field additional status byte temporarily stored RFIFO. HDLC control field additional information also read from special registers (RHCR, RSTA). non-auto mode, frames treated similarly. Semiconductor Group
Transparent Mode (MODE: MDS1, MDS0, 101) Characteristics: address recognition high byte
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Only high byte 2-byte address field will compared. whole frame except first address byte will stored RFIFO. RAL1 contains second RHCR third byte following opening flag.
Transparent Mode (MODE: MDS1, MDS0, 100) Characteristics: address recognition address recognition performed each frame will stored RFIFO. RAL1 contains first RHCR second byte following opening flag.
Extended Transparent Modes (MODE: MDS1, MDS0 Characteristics: fully transparent extended transparent modes, fully transparent data transmission/reception without HDLC framing performed, i.e. without FLAG generation/recognition, generation/check, bitstuffing mechanism. This allows user specific protocol variations usage Character Oriented Protocols (such BISYNC). Data transmission always performed XFIFO. extended transparent mode (ADM data reception done RAL1 register, which always contains actual data byte assembled pin. extended transparent mode (ADM receive data additional shifted into RFIFO. Also refer chapter 6.2.
Semiconductor Group
Receive Data Flow (Summary)
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following figure gives overview management received HDLC frames affected different operating modes.
FLAG MDS1 MDS0 MODE
ADDR
CTRL
DATA RFIFO
STATUS
FLAG
ADDRESS CONTROL RAH1, RAL1,
Auto/16 RHCR RSTA
RAL1, Auto/8
RFIFO RHCR RSTA
RAH1, Auto/16
RAL1, RFIFO RHCR RSTA
RAL1, Auto/8
RFIFO RHCR RSTA
RAH1, RFIFO Transparent RAL1 RHCR RSTA
RFIFO Transparent RAL1 RHCR RSTA
Description Symbols: Compared with (register) Processed autonomously Stored (FIFO, register) Note: case Address, Control Field starts here!
ITD00228
Figure Receive Data Flow HSCX Semiconductor Group
Transmit Data Flow different types frames transmitted: I-frames transparent frames shown below.
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FLAG
ADDR ADDRESS
CTRL CONTROL XFIFO
DATA
CHECKRAM
FLAG
Transmit Transparent Frame (XTF)
Transmit I-Frame (XIF)
XAD1
XAD2
XFIFO
ITD00229
Optional checkram handling version upward
Figure Transmit Data Flow HSCX
I-frames (command CMDR register), address control fields generated autonomously HSCX data XFIFO entered into information field frame. This possible only, HSCX operated auto-mode. transparent frames (command CMDR register), address control fields have entered XFIFO well. This possible operating modes used also auto-mode sending U-frames.
Semiconductor Group
Procedural Support (Layer-2 Functions)
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When operating auto-mode, HSCX offers high degree procedural support. addition address recognition, HSCX autonomously processes (numbered) I-frames (prerequisite window size with either normal extended control field format (modulo modulo sequence numbers selectable RAH2 register). following functions will performed: updating transmit receive counter evaluation transmit receive counter processing commands flow control with RR/RNR generation responses recognition protocol errors transmitting commands, acknowledgement missing continuous status query opposite termination after been received programmable timer/repeater functions. addition, unnumbered frames forwarded directly processor. Additional logic connections operated parallel software. logic link initialized software time (RHR).
Full-Duplex LAPB/LAPD Operation Initially (i.e. after RESET), controllers serial channels configured function combined station, where they autonomously perform subset X.25 LAPB/ ISDN LAPD protocol. Reception Frames logic processing received S-frames performed HSCX without interrupting merely informed interrupt with respect status changes opposite station (receive ready/not receive ready) protocol errors (unacceptable N(R) S-frame with field). I-frames also processed autonomously checked protocol errors. I-frame will accepted case N(s) error interrupt forwarded µC), immediately confirmed response. sets HSCX into "receive ready" status, I-frame will accepted interrupt) response transmitted. U-frames always stored RFIFO forwarded directly logic sequence reception frame auto-mode illustrated figure Note: state variables N(S), N(R) evaluated within window size, i.e. HSCX checks only receive transmit counter regardless selected modulo count. Semiconductor Group
Transmission Frames
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HSCX autonomously transmits commands responses auto-mode. Either transparent I-frames transmitted user. software timer operated internal timer mode transmit I-frames. After frame been transmitted, timer self-started, XFIFO inhibited, HSCX waits arrival positive acknowledgement. This acknowledgement provided means I-frame. positive acknowledgement received during time HSCX transmits command which must followed response response omitted, process performed times before terminated. Upon arrival acknowledgement after completion this poll procedure XFIFO enabled interrupt forwarded Interrupts triggered following: message been acknowledged positive (XPR interrupt) message must repeated (XMR interrupt) response been received (TIN interrupt) Upon arrival frame, software timer started status opposite station polled periodically after expiration until status "receive ready" been detected. user informed accordingly interrupt. response received after times interrupt will generated (TIN interrupt). result, process will terminated illustrated figure Note: internal timer mode should only used auto-mode. Transparent frames transmitted operating modes. After transmission transparent frame XFIFO immediately enabled, which confirmed interrupt (XPR). this case, time monitoring performed with timer external timer mode.
Semiconductor Group
Rec. Activ
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REJ, SREJ
Frame
Frame
Error Abort Prot. Error
Error Abort Prot. Error
Aborted
Aborted
Error
CRCE
RESET RRNR
RRNR
Prot. Error
Error
Wait Acknowledge N(R) V(S)
Wait Acknowledge N(R) V(S) V(S) V(S) RESET Wait Acknowledge ALLS
CRCE
Response RESET Wait Acknowledge ALLS
V(S) V(S) RESET Wait Acknowledge ALLS
Data Overflow
Rec. Ready
Command with Rec. Ready Response Response
N(S) V(R) Data Overflow
V(R) V(R) Response
ITD00230
Figure Processing Received Frames Auto-Mode Semiconductor Group
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Proc. Inactiv
Rec.
CMDR RR/RNR Command
Frame wait Acknowledge
RRNR
Load
Load
Proc. Activ
Rec. Frame
Rec.
Rec.RNR
RRNR
Response with
Load
Load Wait Acknowledge Wait Acknowledge
Load
Rec. Ready Command,
N(R)
Command,
ITD00231
Figure Timer Procedure/Poll Cycle
Semiconductor Group
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Examples interaction between HSCX during transmission reception I-frames illustrated figure flow control with RR/RNR during reception I-frames figure during transmission I-frames figure Both sequence poll cycle protocol errors illustrated figure
ALLS
(0.0) Transmit Frame
(0.1) Reception Frame
ALLS
(1.1) (1.2) Transmit Frame Confirm with Frame
ITD00232
Figure Transmission/Reception I-Frames
(0.0) (0.0)
XRNR
ITD00234
Figure Flow Control/Reception Semiconductor Group
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RSC(RNR) ALLS (RR)
(0.0)
ITD00233
Figure Flow Control/Transmission
Poll Cycle ALLS Protocol Error (0.0)
ITD00235
ALLS
Figure Commands/Protocol Error
Semiconductor Group
Half-Duplex SDLC-NRM Operation
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controllers serial channels configured function half-duplex Normal Response Mode (NRM), where they will operate slave (secondary) station, setting XBCH register respective channel. contrast full-duplex LAPB/LAPD operation, where combined (primary secondary) station transmits both commands responses transmit data time, mode allows only responses transmitted secondary station transmit only when instructed master (primary) station. HSCX gets permission transmit frame from primary I-frame with poll set! mode profitably used point-to-multipoint configuration with fixed master-slave relationship avoids collisions common transmit line. It's responsibility master station poll slaves periodically process error recovery. Prerequisite operation auto-mode with 8-bit address field selected MODE: MDS0, MDS1, external timer mode MODE: same transmit receive addresses, since only responses transmitted, i.e. XAD1 XAD2 RAL1 RAL2
(address
secondary)
Note: broadcast address programmed RAL2 broadcasting required. Reception Frames reception frames functions equally LAPB/LAPD operation. Transmission Frames HSCX does transmit I-frames instructed primary station sending I-frame with poll set. HSCX prepared send I-frame issuing command (via CMDR) time. transmission frame, however, will initiated HSCX prior reception either I-frame with poll After frame been transmitted (with final set), XFIFO inhibited HSCX waits arrival positive acknowledgement.
Semiconductor Group
901.90
82525 82526 82525 82526
Since on-chip timer HSCX must operated external mode secondary poll primary acknowledgements), time supervisory must done primary station. Upon arrival acknowledgement XFIFO enabled interrupt forwarded CPU, either message been acknowledged positive (XPR interrupt), message must repeated (XMR interrupt). Additionally, timer used under control provide timer recovery secondary acknowledgements received all. Note: transmission transparent frames possible only permission send achieved S-frame I-frame.
Semiconductor Group
Examples
82525 82526 82525 82526
examples HSCX/CPU interaction case mode provided figure figure
HSCX Secondary
Primary
ITD00236
Figure Data Send
(0,0)
(0,1)
(1,1) ALLS
ITD00237
Figure Data Reception/Transmission Semiconductor Group
82525 82526 82525 82526
(0,0)
ALLS
ITD00238
Figure Data Transmission Error)
(0.0)
Read EXIR
ITD00239
Figure Data Transmission (Error)
Semiconductor Group
Error Handling Depending error type, erroneous frames handled according table Table Error Handling Frame Type Error Type error aborted unexpec. N(S) unexpec. N(R) error aborted unexpec. N(R) with I-field Generated Response S-frame Generated Interrupt
82525 82526 82525 82526
Rec. Status error abort
Note: station variables (V(S), V(R)) changed. Interface
Register communication between HSCX done directly accessible 8-bit registers. sets operating modes, controls function sequences, gets status information writing reading these registers (Command/Status transfer). Complete information concerning register functions provided detailed register description. most important functions programmable these registers are: setting operating clocking modes layer-2 functions data transfer modes (Interrupt, DMA) mode DPLL mode baudrate generator test loop Each serial channels HSCX controlled equal, totally independent register file (channel channel
Data Transfer Modes Data transfer between system memory HSCX both transmit receive direction controlled either interrupts (Interrupt Mode), independently from interaction using HSCX's 4-channel interface (DMA Mode). After RESET, HSCX operates Interrupt Mode, where data transfer must done CPU. user selects Mode setting XBCH register. Both channels independently operated either Interrupt Mode (e.g. Channel A-DMA, Channel B-Interrupt). Semiconductor Group
Interrupt Interface
82525 82526 82525 82526
Special events HSCX indicated means single interrupt output, which requests read status information from HSCX, Interrupt Mode selected, transfer data from/to HSCX. Since only request output provided, cause interrupt must determined reading HSCX's interrupt status registers (ISTA, EXIR). structure interrupt status registers shown figure
Figure HSCX Interrupt Status Registers
Semiconductor Group
82525 82526 82525 82526
Five interrupt indications read directly from ISTA register another interrupt indications from extended interrupt register (EXIR). After HSCX requested interrupt setting low, must first read interrupt status register channel (ISTA-B) associated interrupt service routine. three lowest order bits (bit 2-0) ISTA-B (ICA, EXA, EXB) point those registers which actual interrupt source indicated. possible that several interrupt sources indicated referring interrupt request (e.g. set, least interrupt indicated ISTA register channel interrupt source from channel implicitly indicated bits ISTA-B; therefore these bits must also always checked. HSCX remains active until interrupt sources cleared reading corresponding interrupt register. Therefore possible that still active when interrupt service routine finished. some interrupt controllers CPUs might necessary generate edge interrupt line recognize pending interrupts. This done masking interrupts interrupt service routine (writing into MASK register) write back mask MASK register. HSCX interrupt sources logically grouped into receive interrupts, transmit interrupts, special condition interrupts. Each interrupt indication ISTA registers selectively masked setting respective MASK register. following tables give complete overview individual interrupt indications cause their activation well specific restrictions (marked with ''*'').
Semiconductor Group
Table Receive Interrupts RECEIVE INTERRUPTS Receive Pool Full (ISTA)
82525 82526 82525 82526
*Only activated Interrupt Mode! Activated soon 32-bytes stored RFIFO message completed. Interrupt Mode: Activated either message bytes last part message with more than bytes stored RFIFO, i.e. after reception closing flag sequence. Mode: Activated after complete message been read controller.
Receive Message (ISTA)
Receive Frame Overflow (EXIR)
Activated complete frame could stored occupied RFIFO, i.e. RFIFO full HSCX detected start frame. *Only activated enabled setting CCR2 register. Activated after start valid frame been detected, i.e. after valid address check operation modes providing address recognition, otherwise after opening flag (transparent mode delayed bytes. After interrupt, contents RHCR RAL1 RSTA valid read CPU.
Receive Frame Start (EXIR)
Semiconductor Group
Table Transmit Interrupts TRANSMIT INTERRUPTS Transmit Pool Ready (ISTA)
82525 82526 82525 82526
Activated whenever 32-byte FIFO pool empty accessible CPU, i.e. following XRES command CMDR. Interrupt Mode: Repeatedly during frame transmission started command, message indication (XME command) been issued CPU, after end-of-message indication when frame transmission transparent frame completed (i.e. closing flag sequence shifted out), Auto-Mode: I-frame been positively acknowledged opposite station.
Transmit Message Repeat (EXIR)
Auto-Mode: Activated last transmitted I-frame repeated reception negative acknowledgement (S-, I-frame with unaccording receive sequence number) opposite station. Configuration: collision occurred after sending 32nd data byte message. Point-to-Point Configuration: been withdrawn after sending 32nd data byte.
Transmit Data Underrun (EXIR)
Activated XFIFO holds further data, i.e. data been shifted serial pin, Message (EOM) indication been detected HSCX. indication supplied either command from Interrupt Mode, checking pre-programmed transmit byte count (via XBCH, XBCL) against actual amount data bytes shifted Mode.
Semiconductor Group
Table Special Condition Interrupts SPECIAL CONDITION INTERRUPTS Layer 2-Specific Activated only "Auto" operating mode been selected MODE register) Receive Status Change
82525 82526 82525 82526
Activated after status change opposite stations receiver been detected (Receiver Ready/Receiver Ready) reception frame, receiver ready, frame, receiver ready. Activated protocol violation been detected reception I-frame with incorrect N(R), S-frame containing I-field.
Protocol Error
Internal Timer Timer Interrupt (ISTA) Activated internal timer repeat counter been expired (see description TIMR register chapter
External Status Change (EXIR) Only activated enabled setting CCR2 register.
Interface HSCX comprises 4-channel interface fast effective data transfers. both serial channels, separate Request Output Transmit (DRQT) receive direction (DRQR) well Acknowledgement (DACK) input provided. HSCX activates line long data transfers needed from/to specific FIFO (level triggered demand transfer mode controller). It's responsibility controller perform correct amount cycles. Either read cycles will performed transfer been requested from receiver, write cycles been requested from transmitter. controller provides acknowledge signal (input HSCX's DACK pin), each cycle implicitly selects specific FIFO neither address (via A0-A6) chip select need supplied (I/O Memory transfers). DACK signal supplied, normal read/write operations (providing addresses) must performed (memory memory transfers). HSCX deactivates line immediately after last read/write cycle data transfer started.
Semiconductor Group
82525 82526 82525 82526
HSCX supports target synchronous well source synchronous transfer. source synchronous transfer mode cycle started when active level occurs request line. This request controlled source (transfer peripheral device memory). First data read peripheral device. During second clock cycle written into memory according target address. there target synchronous transfer cycle started when there active level request line. request controlled target (transfer memory peripheral). First data read from memory. During second clock cycle written into peripheral request line continues being activated until reset write cycle peripheral device
CLOCKOUT (FIFO) (Memory)
CLRL DRHSYS
ITD02697
INVCL
DRHSYS CLRL INVCL CLCL CLRL INVCL CLKOUT CLCL CLRL INVCL DRHSYS
12.5 62.5 141.5
Semiconductor Group
CLOCKOUT (Memory) (FIFO)
ITD02698
82525 82526 82525 82526
CVCTV INVCL DRHSYS
DRHSYS CLKOUT
12.5
CVCTV
CLCL
62.5
INVCL CVCTV
INVCL
DRHSYS
16.5
write signal instead chip select signal order reset request gain some time. extra circuit just gate. first input gate connected request line peripheral second input connected chip select line. gate's output request signal 80(C)188.
80(C)188
DRQTx HSCX
ITS02699
Theoretically, request line 80(C)188, example, would still active when determination made cycles would performed permanently. Therefore decision request line delayed; already made clock cycles before write cycle. wait-states inserted decision made clock cycle. fact that write signal will valid beginning there only little time left resetting request line.
Semiconductor Group
82525 82526 82525 82526
CLOCKOUT DRQTx (Memory) (FIFO) (FIFO)
CHCSX CVCTV
ITD02700
CLCSV
DRHSYS
DRHSYS T4/2 CVCTV CHCSX CLKOUT CLCL CVCTV CHCSX
12.5 62.5
DRHSYS
261ns
circuit mentioned above results slower data transfer with HSCX. HSCX usually performs block transfers. block length bytes. request line remains active long more data needed. Having transmitted last byte request being reset. Using additional circuit request line will active least shortly before next cycle will started four (instead two) clock cycles later. Therefore maximum transmission rate reduced from 1.25 Mbyte/s 1.04 Mbyte/s (clock rate: 12.5 MHz). more information refer chapter (Data Transmission: Mode), chapter (Data Reception: mode), Appendix (Application Example HSCX with 80(C)188 using DMA).
Semiconductor Group
FIFO Structure
82525 82526 82525 82526
both transmit receive direction 64-byte deep FIFO's provided intermediate storage data between serial interface interface. FIFO's divided into halves 32-bytes, where only half accessible controller time. organization Receive FIFO (RFIFO) such, that case frame most bytes long, whole frame stored RFIFO. After first bytes have been received, HSCX prompts read 32-byte block means interrupt request (RPF interrupt activation DRQR line). This block remains RFIFO until confirmation given HSCX acknowledging transfer data block. This confirmation either (Receive Message Complete) command CMDR register Interrupt Mode, implicitly achieved mode after 32-bytes have been read from RFIFO. result, it's possible Interrupt Mode, read data block number times until command issued. configuration RFIFO prior after acknowledgement shown figure
Bytes Inaccessible
Block
Free
Bytes Accessible
Block Prior Acknowledgement
Block After Acknowledgement
ITD01582
Figure Configuration RFIFO (Long Frames)
Semiconductor Group
82525 82526 82525 82526
frames longer than bytes received, device will repeatedly prompt read 32byte data blocks interrupt DMA. case several shorter frames, stored HSCX. accessible half RFIFO contains frame last part frame short frames stored other half meanwhile, prior frame being fetched from RFIFO. This illustrated figure description transmit receive sequence both Interrupt Mode, please refer chapter 7.3.
Frame Bytes Inaccessible Frame
Frame
Frame
Bytes Accessible
Last Part Frame Prior Acknowledgement
Frame After Acknowledgement
ITD00486
Figure Configuration RFIFO (Short Frames) Note: number frames applies e.g. HSCX operating auto non-auto mode (address recognition), short frames only containing HDLC Address Control field received. Since address stored, control field always stored first RFIFO, additional status byte always appended each frame RFIFO, these frames will occupy bytes.
Semiconductor Group
Serial Interface (Layer-1 Functions)
82525 82526 82525 82526
serial interfaces HSCX provide fully independent communications channels, supporting layer-1 functions high degree various means clock generation clock recovery. Clock Modes HSCX includes internal Oscillator (OSC) well independent Baudrate Generator (BRG) Digital Phase Locked Loop (DPLL) circuitry each serial channel. transmit receive clock either generated externally, supplied and/or pins, internally, means and/or BRG, DPLL, recovering receive (and optionally transmit) clock from received data stream external crystal connected pins. Totally, there different clocking modes programmable CCR1 register, providing wide variety clock generation clock functions, shown table
Table Overview Clock Modes Clock Type Receive Clock Source Pins DPLL Pins Pins DPLL BRG/16 Generation Externally Mode
Internally Externally Internally
Transmit Clock
transmit clock pins also output clock control signal certain clock modes programmed outputs CCR2 register (TIO set). clocking source DPLL's always internal BRG; scaling factor (divider) programmed through CCR2 registers between 1,2,4,6. .2048. HSCX system clock always derived from transmit clock thus eliminating need additional clock sources. Clock Mode (External Clocks) Separate, externally generated receive transmit clocks forwarded HSCX their respective pins. Semiconductor Group
Clock Mode (Receive/Transmit Strobes)
82525 82526 82525 82526
Externally generated, identical receive transmit clocks forwarded pins. addition, receive strobe connected transmit strobe pins. operating mode applied time division multiplex applications adjusting disparate transmit receive data rates. Clock Mode (Receive Clock from DPLL) driven with external clock CLK) delivers reference clock DPLL which turn generate receive clock. Depending programming CCR2 register (TSS bit), transmit clock will either external clock signal CLK) clock delivered divided this case, transmit clock output (CCR2 Clock Mode (Receive Transmit Clock from DPLL) with externally generated clock supplies reference clock DPLL, which generates both receive transmit clock. This clock also output pin. Clock Mode (OSC-Direct) receive transmit clocks directly supplied OSC. addition this clock output CLK. Clock Mode (Time-Slots) This operating mode been designed application time-slot oriented systems. receive transmit clock identical each channel must supplied externally pins. HSCX receives transmits only during certain time-slots programmable width .256 bit, RCCR XCCR registers) location with respect frame synchronization signal, which must delivered HSCX pin. time-slots programmed independently receive transmit direction TSAR TSAX registers, additional clock shift bits TSAR, TSAX, CCR2 registers. Together with bits XCS0 RCS0 (LSB clock shift), located CCR2 register, there bits determine location time-slot. According value programmed those bits, receive/transmit window (time-slot) starts with delay (minimum delay) clock periods following frame synchronization signal active during number clock periods programmed RCCR, XCCR (number bits received/transmitted within time-slot) shown figure
Semiconductor Group
82525 82526 82525 82526
Register TSAR TSAX
TSNR TSNX Time Slot Number Bits) Bits
RCS2 RCS0 XCS1 Clock Shift Bits)
TIME SLOT DELAY SNx8 (1.512 Clocks)
WIDTH RCCR, XCCR (1.256 Clocks)
ITD00240
Figure Location Time-Slots transmit time-slot additionally indicated control signal CLK, which output during transmit window. Note: extended transparent mode width time-slots bit.
Semiconductor Group
Signal Clock Mode
82525 82526 82525 82526
When using signal clock mode considered, that signal deactivated after transmission second last (instead last) closing flag, that second last last time-slot "window". other words, inactive during transmission last bit, transmitted next time-slot window. figure
Time-Slot TxCLK (TS,- Ctrl)
Time-Slot
IDLE, interframe time-fill DDD.D Last frame Last closing flag Valid data bits
Status
ITD05965
Figure
Semiconductor Group
82525 82526 82525 82526
This must considered applications, where several transmitters sharing same time-slot open-drain bus, e.g. balanced bus, using collision detection resolution mechanism. such application slave stations point-to-multipoint configuration sharing same time-slot using auto-mode. Thus, timeslot marker TxCLK cannot simply gated generate driver control signal. Instead following recommendations apply: signal directly clock mode e.g. enable drivers balanced configuration. Instead, arrangement type shown figure
HSCX
Transmission Line
ITD05980
Figure
Semiconductor Group
delay rising edge (e.g. mode with balanced bus).
82525 82526 82525 82526
HSCX TxCLK
ITD05966
Figure Timing diagram recommendation
Time-Slot TxCLK (TS-Ctrl)
Time-Slot
IDLE, interframe time-fill DDD.D Last frame Last closing flag Valid data bits
ideal (rec. Status
ITD05981
Figure Semiconductor Group
Signal Clock Mode
82525 82526 82525 82526
clock mode signal evaluated only time-slot "window", also between time-slot "windows". data transmission must stopped, active, even between time-slot "windows", until transmission frame been completed. other words, deactivation stops transmitter immediately. Note: When several HDLC channels sharing same time-slot without using collision detection, strobe signals (AxCLKA/B) used select/ deselect particular time-slot "windows" individual HDLC channel.
Clock Mode (OSC Receive Clock from DPLL) This clock mode equals features Clock Mode with only exception that clock delivered must provided externally. Clock Mode (OSC Receive Transmit Clock from DPLL) Similar Clock Mode clock provided OSC.
Semiconductor Group
Summary features different clock modes summarized table Table Clock Modes HSCX
Channel Configuration Clock Mode CCR2 CCR1 CM2, CM1, Clock Sources Control Sources Output TxCLK BRG/16 DPLL TS-Control BRG/16 DPLL
82525 82526 82525 82526
Timer Source TxCLK RxCLK TxCLK DPLL DPLL RxCLK TxCLK BRG/16 BRG/16 DPLL DPLL
RxCLK RxCLK RxCLK
DPLL
RxCLK RxCLK DPLL DPLL DPLL RxCLK DPLL DPLL DPLL DPLL DPLL
TxCLK RxCLK TxCLK BRG/16 DPLL RxCLK TxCLK BRG/16 BRG/16 DPLL DPLL
AxCLK AxCLK AxCLK AxCLK TxCLK TxCLK TxCLK TxCLK
R-Strobe AxCLK (TSAR)
X-Strobe TxCLK (TSAX)
F-Sync AxCLK
Note: maximum data rate externally clocked operating mode Mbit/s. internally clocked operating mode with external reference clock, using OSC, maximum clock rate 19.2 scaling factor programmed maximum data rate will 1200 kbit/s. ratio between receive frequency (fr) transmit frequency (fx) channel must satisfy condition fr/fx less than clock modes there restrictions phase shift. Slower transmit data rates realized with receive transmit strobes (clock mode clock modes internal need external quartz crystal connected RxCLK A-AxCLK pins. necessary separate crystals serial channels, instead sufficient apply crystal channel provide reference clock channel externally connecting AxCLKA RxCLKB pins. 82526 also uses RxCLK A-AxCLK pins connect external quartz crystal.
Semiconductor Group
82525 82526 82525 82526
Normally capacitors used frequencies below capacitors used frequencies above MHz.
RxCLKA
AxCLKA
ITS01450
guarantee oscillation capacitances which specified crystal manufacturer.
Clock Recovery (DPLL) HSCX offers advantage recovering receive clock from receive data means internal DPLL circuitry, thus eliminating need transfer additional clock information serial link. this purpose, DPLL supplied with reference clock from which times data clock rate (clock mode Additionally, transmit clock obtained dividing output constant factor (clock mode CCR2 set) also directly from DPLL (clock mode
Interference Rejection DPLL
Rec. Data
ITT06028
Figure DPLL circuits implemented HSCX optimized with respect HDLC protocol. main task DPLL derive receive clock adjust phase incoming data stream order enable sampling middle bit-cell with falling edge receive clock. this purpose, edges receive data, indicating begin bitcell, necessary. When using NRZI encoding, zero insert/zero delete method ensures that sufficient number edges occur data stream during reception HDLC frame. Furthermore completely "one insertion" mechanism been implemented with HSCX, which also guarantees sufficient number edges when using encoding (especially configurations, chapter details). Semiconductor Group
82525 82526 82525 82526
following functions have been implemented facilitate high-speed reliable synchronization (see figures 28). Interference Rejection case where more edges appear data stream within time period reference clocks, these detected interference without performing additional adjustments.
Phase Adjustment DPLL
Rec. Data
ITT00241
Figure Phase Adjustment case where edge with phase angle degrees appears data stream within time window, phase will adjusted 1/16 data clock.
Receive Data Reference Clock Nominal Data Clock Rate DPLL
Receive Clock
Receiver
ITS06029
Figure
Semiconductor Group
Phase Shift
82525 82526 82525 82526
case DPLL detects edge data stream range DPLL count (Phase Shift) this only assumed cell period, then DPLL receive clock phase shifted certain DPLL count value.
Phase Shift DPLL Input Receive Data DPLL Count DPLL Phase Correction DPLL Output Receive Clock
Assumed Cell
Phase Adjust
Phase Shift
Phase Adjust
ITD05884
Figure Synchronization Data Clock DPLL Mode: Interference Rejection Phase Adjustment DPLL value corresponding phase shift degree listed below HSCX versions V2.1: HSCX Version V2.1 DPLL Count Phase Shift 180o 157,5o
Note: operating characteristics DPLL therefore allow phase jitter 18.75% frequency.
Semiconductor Group
Configuration
82525 82526 82525 82526
Beside point-to-point configuration, HSCX effectively supports point-to-multipoint (ptmpt, bus) configurations means internal idle collision detection/collision resolution methods. pt-mpt configuration, comprising central station (master) several peripheral stations (slaves), multimaster configuration (see figure data transmission initiated each station over common transmit line (bus). case more than station attempt transmit data simultaneously (collision), assigned station collisionresolution procedure implemented HSCX. assignment function based priority principle with both fixed rotating priorities that enables each station access predeterminable time. result, number transmitters connected serial bus. Prerequisites operation are: encoding connection data feedback information input) configuration selected CCR1 register.
Note: Central clock supply each station necessary both receive transmit clock recovered DPLL (clock mode this case, function DPLL also minimizes phase shift between transmit clocks individual transmitters that opening flag sequence will sufficient allow correct collision detection. mode operated independently clock mode, e.g. also during clock mode (receive transmission strobe) clock mode (programmable time-slots).
Semiconductor Group
Access Procedure
82525 82526 82525 82526
idle state identified eight more successive 1's. case transmit request HSCX, frame transmitted identified busy with first zero opening flag (start flag). After frame been transmitted, becomes available again transmitting 1's.
Note: occupied other transmitters and/or there transmit request HSCX, will continuously transmitted output.
Collisions During transmitting process, data transmitted from HSCX compared with data bus. case erroneous detected (log sent detected, vice versa) frame immediately aborted, idle (log transmitted. Transmission will initiated again HSCX soon possible. Since transmitted zero given priority over connection bus, since individually combined stations address field transmitted HDLC frame differ from another, fact that collision occurred will detected prior latest within address field. frame transmitter with highest temporary priority (address field) affected transmitted without interruptions. other transmitters terminate their operation immediately.
Note: wired connection been realized external pull-up resistor without decoupling, data output used open drain output connected directly input.
Priority Principle When HDLC frame been successfully transmitted HSCX, priority decremented. order transmit additional frame, successive must present bus. This fact used criterion ensure that higher priority transmitters contain transmit requests. possible transmit frame priority increased again successive 1's). This method offers priority allocation based selection particular address. also ensures that each subscriber access pre-determinable time. Timing Modes configuration been selected, HSCX provides timing modes, differing period between sending data evaluation transmitted data collision detection. timing mode (CCR1: SC1, Data output with rising edge transmit clock pins, evaluated clock period later with falling clock edge pins. timing mode (CCR1: SC1, Data output with falling clock edge evaluated with next falling clock edge. Thus complete clock period available during data output their evaluation.
Semiconductor Group
Functions Output
82525 82526 82525 82526
clock modes output programmed CCR2 (SOC bits) active when frame being transmitted. signal delayed clock period with respect data output marks data bits that could transmitted without collision. this configuration implemented which access resolved local basis (collision bus) where data sent clock period later separate transmission line. output used control external driver ANDed with order drive first correctly.
CxDA/B
Line
TxDA/B RTSA/B
ITS02701
Collision
ITT00242
Figure Request-to-Send Operation
Note: regular special functions refer chapter 6.6.
Semiconductor Group
Data Encoding
82525 82526 82525 82526
point-to-point configuration, HSCX supports both NRZI data encoding (selectable CCR1 register).
Encoding
NRZI Encoding
ITT00243
Figure Encoding/NRZI Encoding During NRZI encoding, level changes interpreted changes level Since more than successive appear HDLC frame, this type encoding especially suitable clock modes, where clock recovered from received data means DPLL circuits, because least transition appears within clock cycles. Thus, NRZI coding especially recommended clock modes Data output performed with rising, data input with falling clock edge. Modem Control Functions (RTS/CTS, RTS/CTS Handshaking HSCX provides pins (RTS, CTS) serial channel supporting standard RTS-CTS modem handshaking procedure control HDLC transmitters. Data output performed with rising clock edge, data input with falling clock edge. transmit request will indicated outputting request-to-send output (RTSA/ RTSB). also possible program outputs software. After having received permission transmit (CTSA/CTSB) HSCX transmits frame. case where permission transmit withdrawn during transmission process, frame aborted (idle). After permission transmit been received data still available HSCX, terminated frame will re-transmitted (self-recovery), without interrupting CPU. However, permission transmit withdrawn after 32nd byte information field, transmitter XFIFO reset, output deactivated interrupt generated Semiconductor Group
Signal Clock Mode
82525 82526 82525 82526
clock mode signal evaluated only time-slot "window", also between time-slot "windows". must disabled during transmission frame. Even between time-slot "windows" active until transmission frame been completed. Thus, cannot used select/deselect particular timeslot "windows" HSCX. Note: case where permission transmit required, CTSA/CTSB inputs connected directly VSS. Additionally, state transition input will generate interrupt indicated EXIR register, this function enabled setting CCR2 register.
Sampling
ITT00244
Figure RTS-CTS Handshaking
Carrier Detect (CD) Receiver Control Similar RTS/CTS control transmitter, HSCX supports carrier detect modem control function serial receivers, Carrier Detect Auto Start (CAS) function programmed setting XBCH register. This function always available clock modes pin, clock modes only been programmed input clearing CCR2 register. clock mode function supported (see table overview). function selected, respective HDLC receiver enabled data reception started when high level sampled input.
Semiconductor Group
Special Functions Fully Transparent Transmission Reception
82525 82526 82525 82526
When programmed extended transparent mode MODE register (MDS1, MDS0 11), each channel HSCX supports fully transparent data transmission reception without HDLC framing overhead, i.e. without FLAG insertion deletion generation checking Bit-stuffing mechanism. order enable fully transparent data transfer, MODE reset written XAD1, XAD2 RAH2. Data transmission always performed transmit FIFO directly shifting contents XFIFO serial transmit data Transmission initiated setting CMDR (08H); transmission indicated EXIR (40H). receive direction, character currently assembled receive data line available RAL1 register. Additionally, extended transparent mode (MODE: MDS1, MDS0, 111), received data shifted into RFIFO. This feature profitably used e.g. for: user specific protocol variations application character oriented protocols (e.g. BISYNC) test purposes, line intentionally violation HDLC protocol rules (e.g. wrong CRC) Character synchronization achieved either clock mode with external receive strobe input pin, clock mode with programmed time-slot frame synchronization signal input CLK. Using clock mode multiples bits received time-slot. Cyclic Transmission (Fully Transparent) extended transparent mode selected, HSCX supports continuous transmission transmit FIFO's contents. After having written bytes XFIFO, command XREP.XTF.XME CMDR register (bit "00101010" 2AH) forces HSCX repeatedly transmit data stored XFIFO pin. cyclic transmission continues until reset command (CMDR XRES) issued, after which continuous '1'-s transmitted. Note: DMA-mode command XREP, written CMDR. Semiconductor Group
Continuous Transmission (DMA Mode only)
82525 82526 82525 82526
data transfer from system memory HSCX done (DMA XBCH set), number bytes transmitted usually defined Transmit Byte Count registers (XBCH, XBCL bits XBC11. .XBC0). Setting "Transmit Continuously" (XC) XBCH, however, byte count value ignored interface HSCX will continuously request transmit data time bytes stored XFIFO. This feature used e.g. continuously transmit voice data onto highway (clock mode 5/extended transparent mode), transmit frames exceeding byte count programmable XBCH, XBCL (frames with more than 4095 bytes). Note: reset during continuous transmission, transmit byte count becomes valid again, HSCX will request amount transfers programmed XBC11. .XBC0. Otherwise continuous transmission stopped when data underrun condition occurs XFIFO, i.e. controller does transfer further data HSCX. this case continuous '1'-s (IDLE), without appending CRC, transmitted. Receive Length Check Feature HSCX offers possibility supervise maximum length received frames terminate data reception case this length exceeded. This feature controlled special Receive Length Check Register (RLCR). function enabled setting (Receive Check) RLCR programming maximum frame length bits RL6. .RL01). According value written RL6. .RL0, maximum receive length adjusted multiples 32-byte blocks follows: MAX. LENGTH frames exceeding this length treated they have been aborted from opposite station, i.e. informed interrupt, RSTA register set! distinguish between frames really aborted from opposite station, receive byte count (readable from RBCH, RBCL registers) exceeds maximum receive length (via RL6. .RL0) bytes this case. check includes data that copied into RFIFO. does include address byte address recognition selected. includes RSTA value operating modes.
frame length includes bytes which stored RFIFO.
Semiconductor Group
Insertion
82525 82526 82525 82526
Similar zero insertion (bit-stuffing) mechanism, defined HDLC protocol, HSCX offers completely feature inserting/deleting after seven consecutive zeros transmit/receive data stream, serial channel operating configuration. This method profitable clock recovery should performed DPLL. Since only data encoding supported configuration (see chapter 5.4), there possibly long sequences without edges receive data stream case successive "0"-s received, DPLL loose synchronization. Using insertion feature setting CCR1 register, however, guaranteed that least after consecutive "1"-s will appear (bit-stuffing), consecutive "0"-s will appear (one insertion) thus correct function DPLL ensured. Note: with bit-stuffing, this method fully transparent user, accordance with HDLC protocol, i.e. only applied private systems using HSCX circuits exclusively. Data Inversion When data encoding been selected, HSCX transmit receive data inverted, i.e.
Transmit Log. Data Receive
ITD00245
Phys. Level
"one" transmitted phys. zero "zero" phys. line. This feature selected setting CCR2 register. Please note that data cannot inverted mode unless invert signal before sent into
Semiconductor Group
Special Function
82525 82526 82525 82526
Beyond regular function, signifying transmission frame (Request Send), output programmed special function SOC1, SOC0 bits CCR2 register, provided serial channel operating configuration clock mode SOC1, SOC0 bits '11'; output active low) during reception frame. SOC1, SOC0 bits '10'; output function disabled remains always high.
Test Mode provide fast efficient testing, HSCX operated test mode setting MODE register. on-chip serial input output connected generating local loopback. input ignored. remain active. result, user perform self-test HDLC channels HSCX.
Semiconductor Group
Operational Description
82525 82526 82525 82526
RESET HSCX forced into reset state high signal input minimum period During RESET, HSCX temporarily power-up mode, subset registers initialized with defined values. After RESET, HSCX power down mode, following registers contain defined values: Table RESET Values Register CCR1 RESET Value Meaning power down mode serial port configuration; pt-pt, coding, transmit data pins open drain outputs clock mode normal function interrupts disabled data inversion auto-mode byte address field external timer mode receivers inactive output controlled HSCX, timer resolution: 32.768, testloop XFIFO write enable receive line inactive commands executing interrupts masked commands interrupt controlled data transfer (DMA disabled) full-duplex LAPB/LAPD operation controller carrier detect auto start receiver disabled 1-bit time-slot
CCR2 MODE
STAR
ISTA EXIR CMDR XBCH RBCH XCCR RCCR
Semiconductor Group
Initialization
82525 82526 82525 82526
After reset write minimum registers optionally dependent required features operating modes. First, configuration serial port clock mode defined CCR1 register. clock mode must before power-up, same step with power-up. switch HSCX between power-up power-down mode, which influence upon contents registers, i.e. internal state remains stored. power-down mode however, internal clocks oscillator circuitry disabled, interrupts forwarded CPU. This state used standby mode, when HSCX temporarily used, thus lessening power consumption high degree. individual operating mode must defined writing MODE register. need programming further registers depends selected features (clock mode, operating mode, address mode, user demands) according following tables: Clock Mode Register BGR, CCR2 CCR2, TSAR, TSAX, XCCR, RCCR
Table Register Setup Address Mode Operating Mode Byte Address Field (MODE: Byte Address Field (MODE: TIMR XAD1 XAD2 RAH1 RAH2 RAL1 RAL2 RAH1 RAH2 RAL1
Auto
RAH1 RAH2 RAL1 RAL2 RAH1 RAH2 RAL1 RAL2 RAH1 RAH2
Auto
Transparent Semiconductor Group
Table User Demand Registers User Demand CTS/RFS Interrupt Provided Selective Interrupts Should Masked Timer will used (external timer mode) Controlled Data Transfer Receive Length Check Feature Extended (module 128) Counting Operational Phase
82525 82526 82525 82526
Register CCR2 MASK TIMR XBCH RLCR RAH2
After having performed initialization, switches each individual channel HSCX into operational phase setting CCR1 register (power-up, already done during initialization). Initially, should bring transmitter receiver defined state issuing XRES (transmitter reset) (receiver reset) command CMDR register. data reception should performed, receiver must activated setting MODE "Clear send" function provided modem, HSCX must connected directly ground, order enable data transmission. HSCX ready transmit receive data. control data transfer phase mainly done commands from HSCX CMDR register, interrupt indications from HSCX CPU. Additional status information, which does trigger interrupt, available STAR register. Data Transmission Interrupt Mode transmit direction byte FIFO buffers (transmit pools) provided each channel. After checking XFIFO status polling Transmit FIFO Write Enable (XFW STAR register) after Transmit Pool Ready (XPR) interrupt, bytes entered XFIFO. transmission frame then started issuing command CMDR register. transmit command does include message indication (CMDR XME), HSCX will repeatedly request next data block means interrupt soon more than bytes stored XFIFO, i.e. 32-byte pool accessible CPU. This process will repeated until indicates message command, after which frame transmission finished correctly appending closing flag sequence. case more data available XFIFO prior arrival XME, transmission frame terminated with abort sequence notified interrupt (EXIR XDU). frame also aborted software (CMDR XRES). data transmission sequence, from CPU's point view, outlined figure Semiconductor Group
82525 82526 82525 82526
START
Transmit Pool Ready Write Data Bytes) XFIFO
Interrupt STAR Register
Command
Massage Command
ITD00246
Figure Interrupt Driven Data Transmission (Flow Diagram) activities both serial interface during frame transmission (supposed frame length bytes) shown figure
Serial Interface Transmit Frame Bytes)
HSCX Interface
Bytes
Bytes Command
Bytes
ITD00247
Figure Interrupt Driven Transmission Sequence Example Semiconductor Group
Back Back Frames
82525 82526 82525 82526
more frames should transmitted high speed sequence without interframe time fill, transmission sequence according figure used. This means that closing flag will immediately followed opening flag. HSCX receiver, however, capable receiving frames separated only (shared) flag.
START
Transmit Pool Ready
Interrupt STAR Register
XFIFO Data Bytes)
CMDR
FRAME
Transmit Pool Ready
Last Frame CMDR
CMDR
ITD05883
Figure Continuous Frames Transmission (Flow Diagram) Semiconductor Group
82525 82526 82525 82526
activities during frame transmission (supposed frames, bytes bytes) shown figure
Serial Interface
Frame Bytes
Frame Bytes Bytes
HSCX Interface
Bytes
Bytes
Bytes
ITD00249
Figure Continuous Frames Transmission Sequence Example
Mode Prior data transmission, length next frame transmitted must programmed Transmit Byte Count Registers (XBCH, XBCL). resulting byte count equals programmed value plus byte, i.e. since bits provided XBCH, XBCL (XBC11. .XBC0) frame length 4096 bytes Kbytes) selected. After this, data transmission initiated command (XTF XIF). HSCX will then autonomously request correct amount write cycles activating DRQT line. Depending programmed frame length, block data transfers
32-bytes remainder 1,.128) requested everytime 32-byte FIFO half (transmit pool) empty accessible controller.
Semiconductor Group
82525 82526 82525 82526
following figure gives example driven transmission sequence with supposed frame length bytes, i.e. programmed transmit byte count (XCNT) equal bytes.
Transmit Frame Bytes) Serial Interface
HSCX (69) CPU/DMA Interface DRQT(32) DRQT(32) DRQT(6)
XCNT
Write Cycles (70)
ITD00250
Figure Driven Transmission Sequence Example
Data Reception Interrupt Mode Also byte FIFO buffers (receive pools) provided each channel receive direction. There different interrupt indications concerned with reception data: (Receive Pool Full) interrupt, indicating that byte block data read from RFIFO received message complete. (Receive Message End) interrupt, indicating that reception message completed, i.e. either message with less than bytes, last part message with more than bytes stored RFIFO. After interrupt been processed, i.e. received data been read from RFIFO, this must explicitly acknowledged issuing (Receive Message Complete) command. handle interrupt before additional bytes received serial interface which would cause "Receive Data Overflow" condition. Semiconductor Group
82525 82526 82525 82526
addition message (RME) interrupt, following information about received frame stored HSCX special registers and/or RFIFO: Table Status Information after Interrupt Length message (bytes) Address combination and/or Address field Control field Type frame (COMMAND/RESPONSE) result (good/bad) Valid frame (yes/no) ABORT sequence recognized (yes/no) Data overflow RBCH, RBCL RSTA RAL1 RHCR RSTA RSTA RSTA RSTA RSTA register RFIFO: last byte RFIFO RFIFO RFIFO: last byte RFIFO: last byte RFIFO: last byte RFIFO: last byte RFIFO: last byte
Semiconductor Group
82525 82526 82525 82526
following figure gives example interrupt controlled reception sequence, supposed that long frame bytes) followed short frames bytes each) received.
Serial Interface
Receive Frame Bytes)
HSCX Interface
Bytes
Count
Bytes
Status Count
Status Count
Status
ITD00251
Figure Interrupt Driven Reception Sequence Example Mode RFIFO contains bytes, HSCX autonomously requests block data transfer activating DRQR line long start 32nd read cycle. This forces controller continuously perform cycles till bytes transferred from HSCX system memory. RFIFO contains less than bytes (one short frame last part long frame) HSCX requests block data transfer depending contents RFIFO according following table: RFIFO Contents (Bytes) Request (Bytes)
Note: available status informations after summarized table
Semiconductor Group
82525 82526 82525 82526
After controller been reception next frame, must issue command acknowledge completion receive frame processing. HSCX will initiate further cycles activating DRQR line prior reception RMC.
Note: It's also possible controller immediately after start frame been detected using HSCX's (Receive Frame Start) interrupt option (see chapter 4.3). following figure gives example controlled reception sequence, supposed that long frame bytes) followed short frames bytes each) received.
Serial Interface
Receive Frame Bytes)
HSCX CPU/DMA Interface DRQR(32) DRQR(32) DRQR(4) DRQR(8)
DRQR(8)
Count
Count
Count
ITD00252
Read Cycles (68)
Figure Driven Reception Sequence Example
Semiconductor Group
Detailed Register Description
82525 82526 82525 82526
Register Address Arrangement Table Layout Register Addresses ADDRESS Channel
REGISTER Read Write
Refer page:
RFIFO XFIFO Receive/Transmit FIFO ISTA STAR MASK Interrupt STAtus/Mask CMDR STAtus/CoManD MODE TIMer EXtended Interrupt/Transmit ADdress Receive Byte Count Low/Transmit ADdress Receive Address High Receive STAtus/Rec. Addr. High
EXIR RBCL RSTA RAL1
MODE TIMR XAD1 XAD2 RAH1 RAH2
RAL1 Receive Address Receive HDLC Control/Receive Addr. Transmit Byte Count Baudrate Generator Register Channel Configuration Register Receive/Transmit Byte Count High Version STatus/Receive Frame Length Check Channel Configuration Register Time-Slot Assignment Transmit Time-Slot Assignment Receive
RHCR RAL2 XBCL CCR2 RBCH XBCH VSTR RLCR
CCR1 TSAX TSAR
XCCR Transmit Channel Capacity RCCR Receive Channel Capacity
Note: Channel implemented 82526
Semiconductor Group
Register Definitions Receive FIFO (Read) RFIFO (00. .1F/40. .5F) Interrupt Controlled Data Transfer (Interrupt Mode) selected XBCH reset.
82525 82526 82525 82526
bytes receive data read from RFIFO following interrupt. Interrupt: Exactly bytes read. Interrupt: Number bytes determined reading RBCL, RBCH registers. Controlled Data Transfer (DMA Mode) selected XBCH RFIFO contains bytes, HSCX autonomously requests block data transfer activating DRQR line long start 32nd read cycle. This forces controller continuously perform cycles till bytes transferred from HSCX system memory, (level triggered, demand transfer mode controller). RFIFO contains less than bytes (one short frame last long frame) HSCX requests block data transfer depending contents RFIFO according following table: RFIFO Contents (Bytes) Request (Bytes)
Additionally interrupt issued after last byte been transferred. result, controller transfer more bytes actually valid current received frame. valid byte count must therefore determined reading RBCH, RBCL registers following interrupt.
Semiconductor Group
Transmit FIFO (WRITE) XFIFO (00. .1F/40. .5F) Interrupt Mode selected XBCH reset.
82525 82526 82525 82526
bytes transmit data written XFIFO following interrupt. Mode selected XBCH set. Prior data transfer, actual byte count frame transmitted must written XBCH, XBCL registers user. data transfer then initiated CMDR register (command XIF), HSCX autonomously requests correct amount block data transfers REST, Note: Addresses within address space FIFO's interpreted equally, i.e. actual data byte accessed with address within valid scope.
Semiconductor Group
Interrupt Status Register (READ) ISTA
82525 82526 82525 82526
(20/60)
Value after RESET: RME. .Receive Message message bytes last part message greater then bytes been received available RFIFO. message complete! actual message length determined reading RBCH, RBCL registers. Additional information available RSTA register. RPF. .Receive Pool Full block bytes message stored RFIFO. message completed! Note: This interrupt only generated Interrupt Mode! RSC. .Receive Status Change (significant auto-mode only!) status change (receiver ready/receiver ready) opposite station been detected auto-mode. (i.e. HSCX received RR/RNR supervisory frame according HDLC protocol.) current status read from STAR register (RRNR bit). XPR. .Transmit Pool Ready data block bytes written transmit FIFO. TIN. .Timer Interrupt internal timer repeat counter been expired. (See also description TIMR register!) Interrupt Channel (Channel only) Indicates, that interrupt caused channel interrupt source(s) (are) indicated ISTA register channel (i.e. least ISTA register channel set).
Semiconductor Group
Extended Interrupt Channel (Channel only)
82525 82526 82525 82526
interrupt caused channel source(s) (are) indicated EXIR register channel Note: ICA, EXA, present channel only point ISTA (CHA), EXIR (CHA), EXIR (CHB) registers. After HSCX requested interrupt turning low, must first read ISTA register channel check state these bits order determine which interrupt source(s) which channel(s) caused interrupt. More than interrupt source indicated single interrupt request.
After respective register been read, EXA, reset. other bits will reset after reading ISTA. prevent malfunctions, each individually monitored reset. generate edges necessary mask interrupts interrupt service routine write back mask mask register.
Mask Register (WRITE) MASK (20/60)
Value after RESET: (all interrupts enabled) Each interrupt source selectively masked setting respective MASK (bit positions corresponding ISTA register). Masked interrupts indicated when reading ISTA. Instead, they remain internally stored will indicated after respective MASK reset. Note: event extended interrupt, interrupt request will generated with masked EXA, bit, although this ISTA.
Semiconductor Group
Extended Interrupt Register (READ) Value after RESET: EXIR
82525 82526 82525 82526
(24/64)
Transmit Message Repeat transmission last message repeated because HSCX received negative acknowledgement auto-mode, collision occurred after sending 32nd data byte message configuration. (transmission enable) been withdrawn after sending 32nd data byte message point-to-point configuration. XDU/EXE Transmit Data Underrun/Extended Transmission actual frame been aborted with IDLE, because XFIFO holds further data, frame complete! extended transparent mode, this indicates transmission-end condition. Note: possible send transparent-, I-frames when interrupt indicated.
Semiconductor Group
Protocol Error (significant auto-mode only!) HSCX detected protocol error, i.e. received I-frame with incorrect S-frame containing I-field.
82525 82526 82525 82526
Receive Frame Overflow frame could stored occupied RFIFO (i.e. whole frame been lost). This interrupt used statistical purposes indicates, that does respond quickly enough incoming RPF, interrupt. Clear send Status Change Indicates, that state transition occurred pin. actual state read from STAR register (CTS bit). This interrupt must enabled setting CCR2. RFS. .Receive Frame Start This early receiver interrupt activated after start valid frame been detected, i.e. after valid address check operation modes providing address recognition, otherwise after opening flag (transparent mode delayed bytes. After interrupt, contents RHCR RAL1 RSTA valid read CPU. This interrupt must enabled setting CCR2.
Semiconductor Group
Status Register (READ) Value after RESET: STAR XDOV XRNR RRNR
82525 82526 82525 82526
(21/61)
XDOV Transmit Data Overflow More than bytes have been written XFIFO. Transmit FIFO Write Enable Data written XFIFO. Note: valid only! XRNR Transmit (significant auto-mode only!) Indicates status HSCX. receiver ready receiver ready RRNR Receive (significant auto-mode only!) Indicates status remote station. receiver ready receiver ready Receive Line Inactive Neither FLAGs interframe time fill frames received receive line. Note: Significant point-to-point configurations! Command Executing command currently executed, CMDR register written command (written previously CMDR) currently executed, further command temporarily written CMDR register. Note: will active most transmit clock periods. HSCX power down mode will stay active. Clear Send State CCR2 set, this indicates state pin. inactive (high signal CTS) active (low signal CTS) Waiting Acknowledgement (significant auto-mode only) Indicates 'Waiting Acknowledgement' status HSCX. Semiconductor Group
Command Register (WRITE) Value after RESET: CMDR XREP XRES
82525 82526 82525 82526
(21/61)
Note: maximum time between writing CMDR register execution command clock cycles. Therefore, operates with very high clock comparison with HSCX's clock, it's recommended that STAR register checked before writing CMDR register avoid loss commands.
Receive Message Complete Confirmation from HSCX, that actual frame data block been fetched following interrupt, thus occupied space RFIFO released. Note: mode, this command only issued once after interrupt. HSCX does generate further requests prior reception this command. Reset HDLC Receiver data RFIFO HDLC receiver deleted. auto-mode, additionally transmit receive sequence number counters reset.
RNR/XREP Receiver Ready/Transmission Repeat function this command depends selected operation mode (MDS1, MDS0, MODE): Auto-mode: status HSCX receiver set. Determines, whether received frame acknowledged supervisory frame auto-mode. Receiver Ready (RR) Receiver Ready (RNR) Extended transparent mode XREP Together with (write CMDR), HSCX repeatedly transmits contents XFIFO bytes) without HDLC framing fully transparent, i.e. without FLAG, insertion, stuffing. cyclic transmission stopped with XRES command!
Semiconductor Group
Start Timer internal timer started. Note: timer stopped rewriting TIMR register after start. Transmit Transparent Frame Interrupt mode
82525 82526 82525 82526
After having written bytes XFIFO, this command initiates transmission transparent frame. opening flag sequence automatically added data HSCX. mode After having written length frame transmitted XBCH, XBCL registers, this command initiates data transfer from system memory HSCX DMA. Serial data transmission starts soon bytes stored XFIFO. Transmit I-Frame (used auto-mode only!) Initiates transmission I-frame auto-mode. Additional opening flag sequence, address control field frame automatically added HSCX.
Transmit Message (used interrupt mode only!) Indicates, that data block written last transmit FIFO completes actual frame. HSCX terminate transmission operation properly appending closing flag sequence data. mode, frame determined transmit byte count XBCH, XBCL! This must mode. XRES Transmit Reset contents XFIFO deleted IDLE transmitted. This command used abort frame currently transmission. After setting XRES interrupt generated every case.
Semiconductor Group
Mode Register (READ/WRITE) Value after RESET: MODE MDS1 MDS0
82525 82526 82525 82526
(22/62)
MDS1, MDS0 Mode Select operating mode HDLC controller selected. auto-mode non-auto mode transparent mode extended transparent mode
Address Mode meaning this varies depending selected operating mode: Auto-mode, non-auto mode Defines length HDLC address field. 8-bit address field 16-bit address field transparent modes, this differentiates between sub-modes: Transparent mode transparent mode address recognition. transparent mode high byte address recognition. Extended transparent mode; without HDLC framing. extended transparent mode received data RAL1. extended transparent mode received data RFIFO RAL1. Note: extended transparent modes, must enable fully transparent reception!
Semiconductor Group
82525 82526 82525 82526
Timer Mode operation mode internal timer set. external mode timer controlled started time setting CMDR. internal mode timer used internally HSCX time-out retry conditions auto-mode. (refer description TIMR register) Receiver Active Switches receiver inoperational state. HDLC receiver inactive HDLC receiver active extended transparent modes this must reset enable fully transparent reception!
Request Send Defines state control pin. controlled HSCX autonomously. activated when frame transmission starts deactivated after transmission operation completed. controlled CPU. this set, activated immediately remains active till this reset (not valid configuration). Timer Resolution resolution internal timer (factor description TIMR register) selected 32.768 Test Loop disconnected from mechanical internally connected same channel. remains active.
Semiconductor Group
Timer Register (READ/WRITE) TIMR VALUE
82525 82526 82525 82526
(23/63)
VALUE Sets time period follows:
(VALUE
where timer resolution factor which either 32.768 512-clock cycles dependent programming MODE. clock period transmit data.
Interpreted differently dependent selected timer mode (bit MODE). Internal timer mode (MODE.TMD retry counter HDLC known indicates number S-commands (max. which transmitted autonomously HSCX after expiration time period case I-frame acknowledged opposite station. number S-commands unlimited. External timer mode (MODE,TMD plus VALUE indicates time period after which timer interrupt will generated. time period timer interrupt periodically generated after expiration
Semiconductor Group
Transmit Address Byte (WRITE) XAD1 2-byte address 1-byte address XAD1 (high byte) XAD1 (COMMAND)
82525 82526 82525 82526
(24/64)
XAD1 (and XAD2) programmed with individual address byte which appended automatically frame HSCX auto-mode. function depends selected address mode (bit MODE). 2-byte address field (MODE.ADM XAD1 forms high byte 2-byte address field. must According ISDN LAPD protocol, interpreted (COMMAND/RESPONSE) bit. This manipulated automatically HSCX dependent setting RAH1:
(C/R) Commands transmit Responses transmit
ISDN, high address byte known SAPI). accordance with HDLC protocol, should indicating extension address field bytes. 1-byte address field (MODE.ADM According with X.25 LAPB protocol, XAD1 indicates COMMAND.
Semiconductor Group
Transmit Address Byte (WRITE) XAD2 2-byte address 1-byte address XAD2 (low byte) XAD2 (RESPONSE)
82525 82526 82525 82526
(25/65)
Second individually programmable address byte. 2-byte address (MODE.ADM XAD2 builds byte 2-byte address field ISDN, address byte known TEI) 1-byte address (MODE.ADM According X.25 LAPB protocol, XAD2 indicates RESPONSE,
Note: XAD1, XAD2 registers used only HSCX operated auto-mode.
Receive Byte Count (READ) RBCL RBC7 RBC0 (25/65)
Together with RBCH (bits RBC11 RBC8), length actual received frame (1.4095 bytes) determined. These registers must read following interrupt.
Semiconductor Group
Receive Address Byte High Register (WRITE) RAH1 RAH1
82525 82526 82525 82526
(26/66)
operating modes that provide high byte address recognition, high byte received address compared with individual programmable values RAH1, RAH2.
RAH1 Value first individual high address byte Command/Response Interpretation (auto-mode non-auto mode only) setting affects meaning RSTA follows: meaning Commands received Responses received value
Important: byte address field selected auto-mode, RAH1 must 00H.
Receive Address Byte High Register (WRITE) RAH2 RAH2 (27/67)
RAH2 Value second individual programmable high address byte. Module Count Select; valid auto-mode only. adjusts control field format according HDLC (ISDN/LAPD). basic operation (modulo extended operation (modulo 128) Note: When modulo selected, auto-mode "RHCR" register contains compressed information extended control field (see RHCR, register description). RAH1, RAH2 registers used auto non-auto operating modes when 2-byte address field been selected (MODE.ADM transparent mode RAH2 initialized. Semiconductor Group
Receive Status Register (READ) RSTA
82525 82526 82525 82526
(27/67)
Valid Frame Determines whether valid frame been received. Valid Invalid invalid frame either frame which integer number bits bits) length (e.g. bit), frame which short depending selected operation mode MODE (MDS1, MDS0, ADM) follows: Auto-/non-auto mode (16-bit address): bytes Auto-/non-auto mode (8-bit address): bytes Transparent mode bytes. Transparent mode bytes. Note: Shorter frames reported. Receive Data Overflow data overflow occurred within actual frame. Caution: Data loss because serve interrupt time.
compare/check check failed; received frame contains errors. check o.k.; received frame error-free. Receive Message Aborted received frame aborted from transmitting station. According HDLC protocol, this frame must discarded CPU.
Semiconductor Group
82525 82526 82525 82526
HA1, High Byte Address Compare; significant only 2-byte address mode been selected. operating modes which provide high byte address recognition, HSCX compares high byte 2-bytes address with contents individual programmable registers (RAH1, RAH2) fixed values (group address). Dependent result this comparison, following combinations possible: RAH1 been recognized RAH2 been recognized group address been recognized Note: RAH1, RAH2 contain identical values, combination will omitted.
Command/Response; significant only, 2-byte address mode been selected. Value (bit high address byte) received frame. interpretation depends setting RAH1 register. Refer also description RAH1 register. Byte Address Compare; significant transparent extended transparent operating modes. byte address 2-byte address field, single address byte 1-byte address field compared with programmable registers (RAL1, RAL2) RAL2 been recognized RAL1 been recognized According X.25 LAPB protocol, RAL1 interpreted COMMAND RAL2 interpreted RESPONSE. Note: RSTA corresponds last received HDLC frame; duplicated into RFIFO every frame (last byte frame).
Semiconductor Group
Receive Address Byte Register (READ/WRITE) RAL1 RAL1
82525 82526 82525 82526
(28/68)
general function (READ/WRITE) meaning contents this register depends selected operating mode: Auto-/non-auto mode (16-bit address) WRITE only: RAL1 programmed with value first individual address byte. Auto-/non-auto mode (8-bit address) WRITE only: According X.25 LAPB protocol, address RAL1 recognized COMMAND address. Transparent mode (high byte address recognition) READ only: RAL1 contains byte following high byte address receive frame (i.e. second byte after opening flag). Transparent mode address recognition) READ only: RAL1 contains first byte after opening flag (first byte received frame). Extended transparent modes READ only: RAL1 contains actual data byte currently assembled pin, passing HDLC receiver (fully transparent reception without HDLC framing).
Receive Address Byte Register (WRITE) RAL2 RAL2 (29/69)
Value second individual programmable address byte. byte address field selected, RAL2 recognized RESPONSE according X.25 LAPB protocol.
Semiconductor Group
Receive HDLC Control Register (READ) RHCR RHCR
82525 82526 82525 82526
(29/69)
Value HDLC control field corresponds last received frame. Note: RHCR duplicated into RFIFO every frame. Contents RHCR Mode Auto-mode,1-byte address (U-frames) (Note Auto-mode, 2-byte address (U-frames) (Note Auto-mode, 1-byte address (I-frames) (Note Auto-mode, 2-byte address (I-frames) (Note Non-auto mode, 1-byte address Non-auto mode, 2-byte address Transparent mode Transparent mode Modulo (MCS Control field Control field Control field Control field byte after flag byte after flag byte after flag byte after flag Modulo (MCS Control field (Note Control field (Note Control field compressed form (Note Control field compressed form (Note
Note S-frames handled automatically transferred microprocessor. Note U-frames (bit RHCR control field modulo case. Note I-frames (bit RHCR compressed control field same format modulo case, only three LSB's receive transmit counters visible: N(R) N(S)
Semiconductor Group
Transmit Byte Count (WRITE) XBCL XBC7 XBC0
82525 82526 82525 82526
(2A/6A)
Together with XBCH (bits XBC11.XBC8) this register used mode only, program length (1.4095 bytes) next frame transmitted. This allows HSCX request correct amount cycles after command CMDR. Note: number transmitted bytes e.g. content exactly byte will transmitted.
Baudrate Generator Register (WRITE) (2B/6B)
BR0.Baudrate, Together with bits BR9, CCR2, division factor baudrate generator adjusted. Dependent programmed value 0.1023) division factor results follows:
Semiconductor Group
Channel Configuration Register (READ/WRITE) Value after RESET: meaning individual bits CCR2 depends selected clock mode follows: CCR2 clock mode clock mode clock mode clock mode clock mode SOC1 SOC0 XCS0 RCS0
82525 82526 82525 82526
(2C/6C)
SOC1 SOC0 SOC1 SOC0
SOC1, SOC0 Special Output Control configuration (selected CCR1) function defined output activated during transmission frame. output always high (RTS disabled). indicates reception data frame (active low). point-to-point configuration (selected CCR1) pins flipped data transmitted received (normal case) data transmitted received
BR9, Baudrate, (higher significant bits, refer description register). Baudrate Division Factor division factor baudrate generator (constant). division factor adjusted with bits CCR2 register. Transmit Clock Source Select transmit clock input CLKA/T CLKB pins. transmit clock derived from baudrate generators output divided Transmit Clock Input Output Switch CLKA, CLKB pins inputs CLKA, CLKB pins outputs
Semiconductor Group
Clear Send Interrupt Enable
82525 82526 82525 82526
state transition input cause interrupt which indicated EXIR register (CSC bit). actual state determined reading STAR register. disable enable Receive Frame Start Interrupt Enable When, interrupt (via EXIR) enabled! Data Inversion Only valid data encoding selected. Data transmitted received inverted. XCS0, RCS0 Transmit/Receive Clock Shift, Together with bits XCS2, XCS1 (RCS2, RCS1) TSAX (TSAR) clock shift relative frame synchronization signal transmit (receive) time-slot adjusted. clock shift bits programmable (clock mode only!).
Semiconductor Group
Transmit Byte Count High (WRITE) Value after RESET: 000xxxxx XBCH XBC11 XBC8
82525 82526 82525 82526
(2D/6D)
Mode Selects data transfer mode HSCX system memory. Interrupt controlled data transfer (interrupt mode) controlled data transfer (DMA Mode) Normal Response Mode Valid auto-mode only! auto-mode only; reset this auto-mode, transparent mode, extended transparent mode. Determines function controller: full-duplex LAPB/LAPD operation half-duplex operation Carrier Detect Auto Start When set, high CLK) enables respective receiver data reception started. Note: clock mode Transmit Continuously Only valid mode selected! set, HSCX continuously requests transmit data ignoring transmit byte count programmed XBCH, XBCL. XBC11 XBC8 Transmit Byte Count (most significant bits) Valid only mode selected! Together with XBC7 XBC0 length frame programmed.
Semiconductor Group
Received Byte Count High (READ) Value after RESET: 000xxxxx RBCH XBCH RBC11 RBC8
82525 82526 82525 82526
(2D/6D)
DMA, NRM, These bits represent read-back value programmed XBCH (see XBCH!) Counter Overflow More than 4095 bytes received! received frame exceeded byte count RBC11 RBC0.
RBC11 RBC8 Receive Byte Count (most significant bits) Together with RBCL (bits RBC7 RBC0) length received frame determined.
Version Status Register (READ) VSTR (2E/6E)
Carrier Detect This represents inverted state even when enabled. active (low) inactive (high)
Version Number Chip 0:000 Version 2:010 Version 4:100 Version 5:101 Version
Semiconductor Group
Receive Length Check Register (WRITE) RLCR
82525 82526 82525 82526
(2E/6E)
Receive Check (on/off) receive length check feature disabled receive length check feature enabled Note: bytes stored RFIFO relevant receive length check feature including receiver status byte. Receive Length maximum receive length after which data reception suspended programmed here. Depending value programmed RL0, receive length bytes! frame exceeding this length treated aborted opposite station (RME Interrupt, set). this case, Receive Byte Count (RBCH, RBCL) greater than programmed receive length.
Channel Configuration Register (READ/WRITE) Value after RESET: CCR1 (2F/6F)
Switches between Power Power Down mode power down (standby) power (active) SC1, SC0. .Serial Port Configuration data encoding NRZI data encoding configuration, timing mode configuration, timing mode Note: configuration selected, only coding supported.
Semiconductor Group
Output Driver Select Defines function transmit data pins pins open drain outputs pins push-pull outputs
82525 82526 82525 82526
Note: Since time-slot oriented systems tristated automatically programmed time-slot, should configured open drain time-slot oriented systems.
ITF/OIN Interframe Time Fill/One Insertion function this depends selected serial port configuration (bit SC0) Point-to-point configurations: Determines idle data send) state transmit data pins Continuous IDLE sequences output pins remain state) Continuous FLAG sequences output ("01111110" patterns) configurations: configurations, implicitly i.e. continuous "1"s transmitted, data encoding NRZ! When this set, "ONE" insertion (deletion) mechanism activated, inserting after seven consecutive "0"s transmit data stream deleting receive data stream. Similar HDLC's bit-stuffing mechanism (inserting after five consecutive "1"s), this method proves advantageous when receive clock recovered from receive data stream means DPLL, because guaranteed that least after seven bits transition occurs receive data case long sequences!
CM2, CM1, Clock Mode Selects different clock modes clock mode clock mode
Semiconductor Group
Time-Slot Assignment Register Transmit (WRITE) This registers only used clock mode TSAX TSNX XCS2 XCS1
82525 82526 82525 82526
(30/70)
TSNX Time-Slot Number Transmit Selects possible time-slots (00H 3FH) which data transmitted. number bits time-slot programmed XCCR. XCS2, XCS1 Transmit Clock Shift, Together with XCS0 CCR2, transmit clock shift adjusted.
Time-Slot Assignment Register Receive (WRITE) This register only used clock mode TSAR TSNR RCS2 RCS1 (31/71)
TSNR Time-Slot Number Receive Defines possible time-slots (00H 3FH) which data received. number bits time-slot programmed RCCR. RCS2, RCS1 Receive Clock Shift, Together with RCS0 CCR2, receive clock shift adjusted.
Semiconductor Group
Transmit Channel Capacity Register (WRITE) Value after RESET: This register only used clock mode XCCR XBC7
82525 82526 82525 82526
XBC0 (32/72)
XBC7 XBC0 Transmit Count, Defines number bits transmitted with time-slot: Number bits bits/time-slot)
Receive Channel Capacity Register (WRITE) Value after RESET: This register only used clock mode RCCR RBC7
RBC0 (33/73)
RBC7 RBC0 Receive Count, Defines number bits received within time-slot: Number bits bits/time-slot)
Semiconductor Group
Electrical Characteristics Absolute Maximum Ratings Parameter Ambient temperature under bias: Storage temperature Voltage with respect ground Maximum voltage Symbol Limit Values
82525 82526 82525 82526
Unit
Tstg Vmax
Note: Stresses above those listed here cause permanent damage device. Exposure absolute maximum ratings conditions extended periods affect device reliability. Characteristics SAB: SAF: Parameter L-input voltage H-input voltage L-output voltage H-output voltage H-output voltage Power supply current operational Symbol Limit Values min. max. 0.45 Unit Condition
(pins (all other) Inputs V/VDD,
output loads VOUT
power down
Input leakage current Output leakage current
Semiconductor Group
Capacitances MHz, unmeasured pins returned GND. Parameter Input capacitance Output capacitance Symbol typ. COUT CI/O Limit Values max.
82525 82526 82525 82526
Unit
Characteristics SAB: SAF: Inputs driven logical logical "0". Timing measurements made logical logical "0". testing input/output waveforms shown below.
Input/Output Waveform Tests
2.4/2.4 Test Points 0.45/0.4 Device Under Test
Load
ITS02702
Semiconductor Group
Microcontroller Interface Timing Intel Mode
82525 82526 82525 82526
Data
DRQR
ITT00953
Read Cycle
Data
DRQT
ITT00954
Write Cycle
ITT00955
Multiplexed Address Timing
Semiconductor Group
Microcontroller Interface Timing Intel Mode
82525 82526 82525 82526
DACK
ITT00956
Address Timing
Semiconductor Group
Motorola Mode
82525 82526 82525 82526
Data
DRQR
ITT00957
Read Cycle
Data
DRQT
ITT00958
Write Cycle
DACK
ITT00959
Address Timing Semiconductor Group
Interface Timing Parameter Symbol min. pulse width Address setup time Address hold time from Address latch setup time Address setup time Address hold time from request delay: pulse width Data output delay from Data float delay from control interval pulse width Data setup time CS/DS Data hold time from CS/DS control interval delay after Serial Interface Timing Receive data setup Receive data hold Collision data setup Collision data hold Transmit data delay, falling clock edge Transmit data delay, rising clock edge Request send delay Request send delay Clock period Clock period Clock period HIGH Semiconductor Group Limit Values max.
82525 82526 82525 82526
Unit
tALS tDRH tDSD
tRDS tRDH tCDS tCDH tXDD2 tXDD1 tRTD1 tRTD2 tCPL tCPH
Serial Interface Timing
82525 82526 82525 82526
Clock
RxDA/B
Clock
XDD1
TxDA/B
TxDA/B Timing Mode
CxDA/B CTSA/B
RTD1
RTSA/B
RTD1
RTSA/B Timing Mode Timing Mode
RTSA/B
RTD2
ITT00960
Semiconductor Group
Strobe Timing (Clock Mode1)
82525 82526 82525 82526
RxCLK
AxCLK
TxCLK
Timing Mode
ITT00961
Parameter Receive strobe delay Receive strobe setup Receive strobe hold Transmit strobe delay Transmit strobe setup Transmit strobe hold Transmit data delay Strobe data delay High impedance from clock High impedance from strobe
Symbol min.
Limit Values max. Unit
tRSD tRSS tRSH tXSD tXSS tXSH tXDD tSDD tXCZ tXSZ
Semiconductor Group
Clock Mode
82525 82526 82525 82526
RxCLK
AxCLK
TxCLK
TxCLK
Timing Mode
ITT00962
Synchronization Timing
Parameter Sync pulse delay Sync pulse setup Sync pulse width Time-slot control delay
Symbol min.
Limit Values max.
Unit
tTCD
Semiconductor Group
Clock Mode Internal Clocking Parameter Clock frequency Baudrate generator used Clock frequency Baudrate generator used Symbol min. Limit V
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