PM5948 DART-BOARD S/UNI DUAL AREFERENCE TRANSCEIVER BOARD PM
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PMC-960552 ISSUE
PM5948 DART-BOARD
S/UNI DUAL AREFERENCE TRANSCEIVER BOARD
PM5948 S/UNI
155-DUAL
DART BOARD S/UNI-DUAL AREFERENCE TRANSCEIVER BOARD
Issue
January, 1997
105-8555 Baxter Place Burnaby, Canada (604 )415-6000
PMC-960552 ISSUE
PM5948 DART-BOARD
S/UNI DUAL AREFERENCE TRANSCEIVER BOARD
105-8555 Baxter Place Burnaby, Canada (604 )415-6000
PMC-960552 ISSUE
PM5948 DART-BOARD
S/UNI DUAL AREFERENCE TRANSCEIVER BOARD
CONTENTS OVERVIEW.1 DART board IMPLEMENTATION.2 2.1. Important implementation principles 2.2. Block diagram.2 2.3. Power supply ground layers 2.4. Optical line side interface 2.5. ALOS+/- inputs 2.6. Interfacing TXD+/- outputs.6 2.7. RXD+/- inputs.7 2.8. REFCLK 19.44 inputs.8 2.9. Drop side FIFO bus.9 2.10. Drop side microcontroller interface 2.11. Decoupling Intrinsic Jitter DART board.11 DESIGN CONSIDERATIONS.11 3.1. When PECL/ECL instead TTL/CMOS? 3.2. What main concerns using PECL over ECL?.12 3.3. What PECL termination scheme best use?.12 3.4. convert S/UNI-DUAL CMOS outputs PECL levels? 3.5. What done minimize power supply transient voltages?.16 3.6. What values should decoupling capacitor be?.17 3.7. Where should decoupling capacitors placed?.18 3.8. What done minimize ground noise?.18 3.9. What with unused (CMOS) inputs? 3.10. necessary isolate analog from digital? 3.11. Should isolate transmit analog from receive analog?.19 3.12. isolate analog from digital transmit from receive? 3.13. does layout affect high speed return current?.20 3.14. When should ferrite beads used?.20 3.15. necessary de-couple every power S/UNI-DUAL?.21 3.16. Loop filter using ceramic capacitors.21
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3.17. Loop filter using polarized tantalum capacitors 3.18. drive REFCLK± inputs using oscillator?.24 3.19. accurate should board reference clock be?.30 3.20. CMOS terminology?.31 ACCESSING DART board 4.1. DART board DART Interface Card SCI-PHY Mother Board 4.2. Drop side loop-back PM5348 S/UNI-DUAL.33 S/UNI-DUAL register address
APPENDIX LAYOUT NOTES A.1. Background.1 A.2. Trace Impedance Control.1 A.3. Routing.3 APPENDIX DART board DROP SIDE CONNECTOR PINOUT.1 APPENDIX MECHANICAL DRAWINGS.1 APPENDIX DART board PARTS LIST.1 APPENDIX 4.7µF Ceramic Multilayer Capacitor Sources.1 APPENDIX SCHEMATICS.1 APPENDIX SCHEMATIC COMPONENT CROSS REFERENCE APPENDIX SCHEMATIC SIGNAL CROSS REFERENCE APPENDIX ARTWORK APPENDIX REFERENCES.1 CONTACTING PMC-SIERRA
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OVERVIEW DART board layer subassembly that contains PM5348 S/UNI-DUAL IC's, 19.44 crystal oscillator clock reference, power supply decoupling, fiber optic transceiver devices drop-side system connector. These devices typically used implement core Auser Network Interface. Each PM5348 contains logical Ainterfaces, therefore DART board total four such ASONET/SDH interfaces. board also contains optical serial fiber transceivers. normal operation, optical RX/TX fiber 140-pin edge connector local controller, drop side assembly/disassembly SAR) required. Fig. DART board overview controller Power input ASAR (DROP SIDE)
DUAL DART BOARD DUAL
SONET/SDH Fiber (LINE SIDE)
This layer contains S/UNI-DUAL PM5348 chips. line side, each S/UNI-DUAL processes two, full duplex Apacked, SONET/SDH Mbit/s STS-3c/STM-1, 51.8 Mbit/s (STS-2) data streams. This gives four logical Adevices, each operating Mbit/s both receive transmit directions board aggregate full duplex rate Mbit/s. line side requires stable 19.44 6.48 STS-2) reference clock both PM5348 ICs. Clock jitter must carefully controlled and, depending design, special attention must given buffers, propagation delays, clock skew, power supply decoupling, trace impedance termination. drop side provides Saturn Compliant Interface PHYsical layer (SCIPHY) 16-bit bus. clocked aggregate parallel transfer bandwidth megabits bits MHz) both receive transmit directions. Configuration, control status monitoring S/UNI-DUAL chips accomplished connector using 8-bit microcontroller external motherboard controller.
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DART board IMPLEMENTATION 2.1. Important implementation principles reduce digital analog power/ground noise DART board, multi-layer with three ground planes required. This simplifies design reduces time market. 19.44 reference (not PECL) oscillator buffered with 74FCT541. series transmission line termination method used reduce drive current system noise. Transmission line traces characteristic impedance implemented 19.44 reference clock. compromise between that traces wide enough repeatable manufacturing, also have high enough keep currents possible. connections used 155.52 Mbit/s PECL data, between DUAL PMD, wider traces. 2.2. Block diagram Fig. DART board block diagram
DART BOARD PM5948
Status
Loop Filter
Ctrl
S/UNI-DUAL
PM5348
four direct controls external Reference 19.44mHz external FIFO clock (50mhz) FIFO Ctrl 8-bit
Loop Filter
Tx/Rx [15:0] generic 8-bit micro external RESET +5VDC power, Ground ADATA Ctrl
Loop Filter
PM5348
Ctrl S/UNI-DUAL
Loop Filter
Optical
Optical
Status details see75 controlled PECL parallel terminations impedance trace Component side trace layer Ground Plane labeled 'TA' shematics Digital Ground Plane labeled schematics +5VDC Power Plane labeled 'Vcc' shematics Ground Plane labeled 'RA' schematics Layer Solder side trace layer discrete components)
three ground planes shorted connector
SONET/SDH OC-3
Optical
Optical
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2.3. Power supply ground layers power supply carefully distributed power ground planes. power plane supplies digital circuits directly ferrite series elements used generate other analog supplies. addition, there three separate ground planes that originate from main drop side connector: Digital ground (D), line side Transmit Analog Ground (TA) line side Receive Analog Ground (RA). optimize jitter tolerance, separate ground planes isolate noisy digital circuits (grounds) from more sensitive analog receive transmit blocks. Fig. Power ground distribution
Power Connector
100µF Bulk
10µF Bulk
Ferrite
(digital power) Layer Analog Power
Ferrite
.1µF plus 10nF caps
Analog Power
.01µF caps
Star Ground Distribution
.1µF plus 10µF 10nF Bulk caps
(Transmit Ground -Layer (Digital Ground Layer (Receive Ground -Layer
2.4. Optical line side interface serial line side utilizes four (Physical Media Device) Optical Transceiver modules. receive optics connect directly S/UNI-DUAL RXD+/- inputs. ensure that there clock absence optical input, signal detect (SD) output optics connected ALOS- input S/UNI-DUAL (the ALOS+ input grounded). normal operation (good incoming signal) S/UNI-DUAL device recovers clock from incoming data. loss signal condition, S/UNIDUAL will squelch data receive data (RXD+/-) pins phase lock loop will switch reference clock (19.44 MHz) keep recovered clock range. This technique guarantees that S/UNI-DUAL will generate SONET indication Optical Transceiver loses optical input.
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transmit line interface consists S/UNI-DUAL CMOS transmit outputs which AC-coupled, attenuated, terminated, level shifted into transmit optics. Optical transceivers having standard 9-pin duplex receptacle used. non-loop timed mode, 155.52 transmit clock source synthesized from local 19.44 oscillator 155.52 receive clock recovered from incoming data. 2.5. ALOS+/- inputs S/UNI-DUAL analog Loss Signal inputs designed accept inputs from either single ended PECL balanced differential PECL, single ended CMOS voltage source. These true differential inputs, they sense difference between inputs. Grounding ALOS+ input, causes ALOS- single ended threshold input. 3.7V bias derived internally from power ground. Since (Signal Detect output from Optical Transceiver) high speed signal, it's important, critical, that power ground common noise free with (Optics UTP-5 module). threshold level gates also added equivalent input structure looks like this: Fig. ALOS± block diagram
S/UNI-DUAL
Signal Detect (SD) from Optical UTP-5 121(80) ALOS119(82) ALOS+ 3.7Vdc Level input buffer
3.7Vdc
3.7Vdc threshold differential PECL RXVR
Level input buffer
These inputs would typically receive very slow changing signals. would expect (Signal Detect outputs from optical PMD) changing during normal operation. ALOS asserted, means there something drastically wrong with signal source, (e.g. fiber loop cut). ALOS function hence this signal must coupled. Also since source high speed, ALOS inputs require transmission line controlled impedance traces termination schemes. Also connected these input pins gates with their input thresholds traditional levels. That less than high greater than operate inputs single ended threshold inputs, ALOS+ input must grounded ALOS- must connected output. this case, gate detects logic ALOS+ selects input which comes from ALOS-.
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When operating with PECL, PECL signal always >2.0 VDC. Therefore, gate selects input '1', which comes from differential PECL RXVR. Interfacing single ended PECL output (most common) source single ended PECL voltage level, then ALOS+ must coupled (Receive Analog Ground, Layer 0.01 capacitor, connected ALOS- input, with appropriate PECL pulldown close PMD. Notice that PMD's analog signal detector output labeled (Signal Detect). DUAL's input labeled ALOS (Analog Loss Signal). These have inverse logic labels. However, logic high means that there sufficient signal level, logic low, means that input signal low. Fig. ALOS- driven from single ended PECL source PECL levels 0.01µF S/UNI-DUAL ALOSALOS+
(Receive Analog Ground)
Interfacing level output (OPTICS UTP-5 interface) device with single ended level output connected shown below. Fig. ALOS- driven from source S/UNI-DUAL ALOSALOS+ =RA=Receive Analog Ground
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Interfacing differential PECL outputs Notice that both pins internally self biased source impedance. PECL inputs high-Z CMOS differential structures. with traditional PECL outputs connected shown with pulldowns close bias PECL drivers. Fig. ALOS± driven from differential PECL± source PECL SD330 (Receive Analog Ground) 2.6. Interfacing TXD+/- outputs TXD+/- high speed data outputs running 155.52 Mbit/s worst case. data alternate ones zeros, 77.26 signal will result. fastest signals board proper attention must taken minimize jitter. Fig. TXD± driving with PECL inputs ALOS+ S/UNI-DUAL ALOS-
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resistors reduce Vp-p safe mVp-p PECL level. Ceramic 0.01µF capacitors used couple level shift these CMOS output proper PECL levels. transmission line effects addressed with trace terminating resistors. terminating resistors terminated into locally generated Vdc. 2.7. RXD+/- inputs RXD+/- high speed data inputs running 155.52 Mbit/s worst case. data alternate ones zeros, 77.26 signal will result. fastest signals board proper attention must taken minimize jitter. These inputs should driven with balanced PECL± source. S/UNI-DUAL differential RXD± inputs with common mode rejection. bias voltage these inputs internally Vdc, through impedance. These resistors tied power R1AVD1 ground R1AVS1 pins. Hence, noise these power pins alter switching bias point. Proper decoupling this supply important optimum jitter tolerance. Also, these PECL inputs have coupled else 3.7V bias will affected. Fig. RXD± block diagram
S/UNI-DUAL
3.7Vdc
RXD+
3.7Vdc
3.7Vdc threshold differential PECL RXVR
DART board incorporates optical with PECL level RXD± outputs. following points were observed: Bias PECL outputs with resistors ground Route signal DUAL along proper traces: controlled trace impedance, DART board vias sharp turns resistor termination between signals close DUAL. couple RXD+/- with 0.01uF ceramic high frequency capacitors. Decouple R1AVD1 R1AVS1 shown with series ferrite capacitors (two capacitors parallel, with 0.01 µF).
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Fig. Terminating RXD± PECL signal
Vcc=+5V
DART BOARD
0.01µF
Optical
Zo=50
Rt=2*Zo=100
Ferrite
RXD+ R1AVD1
DUAL
RXD-
Zo=50
0.01µF
R1AVS1
2.8. REFCLK 19.44 inputs DUAL reference clock inputs different than S/UNI-LITE PM5346. DUAL programmable inputs. drive these with either wire PECL single ended CMOS source. These inputs have same input structure DUAL ALOS+/- inputs. PECL wire signal connected between REFCLK+ REFCLK-. input mode selected grounding REFCLK+. input gate forces select output gate Fig. REFCLK± input block diagram
3.7Vdc
Level input buffer 3.7Vdc threshold differential PECL RXVR
REFCLK111 REFCLK+
S/UNI-DUAL
Level input buffer
DART board utilized (vs. PECL) 20ppm oscillator 74FCT541 high speed single ended buffer. Fast slew rate buffer required reduce clock jitter. source series termination used drive transmission line. REFCLK+ strapped ground enable single ended REFCLK- operation.
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Fig. REFCLK± implemented DART board
TAVS1 TAVS2 REFCLK+
Buffer 74FCT541 19.44Mhz Oscillator Rs=27 Zo=75
DUAL
REFCLK-
Rs=27
Zo=75
REFCLKREFCLK+ TAVS2 TAVS1 DUAL
Transmit Analog Ground
2.9. Drop side FIFO drop side refers parallel FIFO Receive Transmit data associated handshake control signals shown below: FIFO RFCLK TFCLK clock present careful timing termination design ensure error free operation. Please refer data sheet detail timing information. Please note output electrical specs that driving termination load even possible. Series source terminations about could used timing permits (ie. clock speeds slower than MHz), driver could used driving off-board. Fig. Drop side Interface block diagram
DART BOARD
16-bit FIFO 16-bit FIFO DUAL
control (RCA, TCA, RSOC,TSOC, RRDENB, RFCLK,TFCLK) DUAL
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associated drop side timing illustrated below. complete detailed timing information, please refer S/UNI-DUAL, PM5348 Data Book, PMC950919. Fig. Multi-PHY mode timing 16-bit, FIFO near empty option
TFCLK TWRENBn TCAn TSOC1 TDAT[15:0] TXPRTY[1:0]
W(n-4)
W(n-3)
W(n-2)
W(n-1)
W(n)
Fig. Multi-PHY Mode Timing, 16-bit, receive FIFO empty Tristate options
RFCLK RRDENB1 RRDENB2 RCA1 RCA2 RSOC1 RDAT[15:0] RXPRTY[1:0]
W(n-1) W(n)
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2.10. Drop side microcontroller interface S/UNI-DUAL powers 'basic' default state ready receive transmit Acells. microprocessor required requires ability read write internal status control registers. Please refer PM5348 data sheet interface specifications. Relative RXD+/-, drop side FIFO interface, this slow normal digital design rules should followed. Fig. DART board interface
DART BOARD
8-bit data
control (RD, A[8:0], RST, INTB, RSTB) Decode
DUAL
DUAL
2.11. Decoupling Intrinsic Jitter DART
board
optimize intrinsic jitter this reference design, beneficial decouple power pins, TAVD1 TAVD2 shown enclosed schematics. series ferrite required with 1.0µF Tantalum parallel with 0.01µF ceramic decoupled their respective analog ground pins, RAVD1 RAVD2. DESIGN CONSIDERATIONS
3.1. When PECL/ECL instead TTL/CMOS? faster digital signal, faster technology must (implies fast slew rates also) maintain data integrity. Also, longer traces, more reliable transmission technology required. S/UNI-DUAL mixed mode CMOS semiconductor with high speed analog digital circuits. Since PECL/ECL more complex expensive use, should used only where necessary. normal short distance layouts 19.44 REFCLK single ended CMOS type long transmission line design rules adhered Controlled impedance traces with proper termination recommended. RXD± TXD± signals must PECL speed jitter integrity.
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3.2.
What main concerns using PECL over ECL?
uses upper rail supply reference internal switching, negative supply with ground being reference natural choice, easier keep ground plane quieter than power rail. Since requires negative power supply most designers mixing TTL/CMOS with only want single supply, PECL (positive ECL) became common choice. PECL operates same noisier Volt rail reference. PECL devices differential; noise inputs will common mode noise will affect differential input, will affect internal reference, especially power supplying transmitting device common with receiver. S/UNI-DUAL RXD± REFCLK± differential inputs with common mode rejection. These inputs will decode voltage difference between input, with respect ground. However bias voltage internally through impedance. These resistors tied power R1AVD1 ground R1AVS1 pins. Hence, noise these power pins alter switching bias point. Proper decoupling this supply important optimize jitter tolerance. Also, these PECL inputs have coupled, otherwise 3.7V bias will affected.
3.3. What
PECL termination scheme best use?
"Termination" applies terminating signal propagating down transmission line characteristic impedance line. line terminated characteristic impedance, there will reflection back down line. amount reflection load (receiver) given load reflection coefficient: Zo)/(RT where load impedance characteristic impedance line. amount reflection source (transmitter) given source reflection coefficient: Zo)/(R where source impedance characteristic impedance line. reflected signal propagates back forth until "ringing" dies out. There basic types terminations used PECL ECL): Open line termination, series termination, parallel termination, parallel termination. Since PECL ECL) signals only drive high, external biasing need pull PECL signal low. This biasing incorporated into termination scheme.
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Unterminated lines (open line) should only used very short line lengths (less than inch), frequency signals. unterminated line shown below with resistor used pull PECL signal low: Fig. Unterminated transmission line
maximum unterminated line length given following equation CO)2 TPD)2 where line length, rise time, propagation delay unit length, capacitance unit length, distributed capacitance. above equation assures that undershoot will limited full logic swing. Series terminated lines used when interconnect distances long there discontinuities characteristic impedance lines. series resistor output driver reduces voltage swing logic signal half. amplitude signal propagates down transmission line. characteristic impedance line, voltage doubles since reflection coefficient unity unterminated line. half amplitude swing along transmission line reduces crosstalk, distance between transmission line receiver input kept short Lmax above, reflection added signal propagates back transmitter. series terminated line shown below where Zint//Re must equal Fig. Series terminated transmission line
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Parallel terminated lines offer best terminations speed power consumption. receiver transmission line terminates biases signal. terminating resistor same value characteristic impedance transmission line. Unfortunately this requires another voltage supply terminating voltage (VT) Volts. parallel terminated line shown below where equals Fig. Parallel terminated transmission line
terminated lines terminate lines characteristic impedance sets terminating (VT) voltage. equivalent parallel termination shown below: Fig. Parallel terminated transmission line
resistors parallel must equal voltage input must pull output transmitting gate Volts. Working equations PECL Volt supply gives: R2*2/3
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Note that above examples show only differential inputs. With termination care must taken that grounds differential signals taken close proximity each other noise ground will common with each other. Since S/UNI-DUAL's PECL (pseudo ECL) inputs internally self-biased, hybrid parallel termination used which minimum current draw terminating voltage (VT) required. AC-coupling into S/UNI-DUAL, S/UNI-DUAL sets internal switching threshold. resistor placed between differential outputs terminating shown below terminate line: Fig. S/UNI-DUAL RXD± driven PECL
0.01 PECL Transmiter
2*Zo
S/UNI-DUAL
0.01
resistors placed close drivers required properly bias PECL output structures since PECL drives high only. 3.4. convert S/UNI-DUAL CMOS outputs PECL levels? S/UNI-DUAL high speed CMOS outputs have AC-coupled, attenuated, level shifted terminated into PECL optical transmitter input. This done with CMOS PECL converter like Motorola MC10H352, however more cost effective shown below:
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Fig. DUAL's TXD± driving PECL input
0.01 TXD+ 5Vp-p S/UNI-DUAL 0.01µF TXVD_AC 0.01µF TXD0.01 Optical Transmiter
TXVS_AC
Ferrite
0.1µF
800mVp-p differential
5Vp-p
TxD+/- outputs AC-coupled then series resistor used attenuate CMOS levels PECL levels. input (voltage requirement PECL input) swing given equation below with Rout (approximately ohms) being output impedance S/UNI-DUAL drivers. mVolts swing, approximately ohms. (Zo/((Rs Rout) Zo)*Vcc voltage (3.7 volts PECL) generated voltage divider network which switching threshold optical transmitter: Vcc* R2/(R2 3.5. What done minimize power supply transient voltages? High current draw during switching causes power supply transients inductance power lines. Large voltages appear power rails transient current flowing through these power line inductances. magnitude noise voltage reduced minimizing inductance power lines decreasing magnitude transient currents. power line inductance minimized using power plane. transient currents power rails minimized supplying power from alternate source such decoupling capacitor near circuit that drawing current.
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decoupling capacitance inductance wiring between capacitor power determines noise voltage power pin. Bulk decoupling capacitors used supply bulk current, high frequency decoupling capacitors used supply transient current that required when circuit switching. 3.6. What values should decoupling capacitor bulk decoupling value should times value decoupling capacitance combined should located where power comes Capacitors with internal inductance should used such tantalum electrolytic. Stay away from aluminum electrolytic their inductances order magnitude larger than tantalum capacitor. ferrite bead inductor) used before bulk capacitor keep power supply transient noise from entering circuit. power decoupling capacitor must able supply switching current. minimum capacitance calculated transient voltage drop supply voltage caused transient current occurring over time Using decoupling capacitors that large should avoided. Since capacitors have some inductance series with capacitance there will self-resonance certain frequency. Above this frequency, inductor's impedance will increase, effective impedance capacitor will increase thus high frequency decoupling will suffer. selfresonant frequency given equation: decoupling particular frequency, lower capacitor's impedance (Xc) resonance, better. capacitor's self inductance (XL), effective impedance capacitor (XCeff) XCeff 0.1µF resonance Frequency Note that larger capacitance (for same inductance) lower resonant frequency. capacitor large, self-resonance will effective bypass capacitor large enough, there will insufficient current supply transient current during switching. smallest value capacitor satisfy above equations should used. rarely necessary that capacitor larger than 0.01 used.
0.01µF
XCeff
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3.7. Where should decoupling capacitors placed? decoupling capacitor should placed close power possible reduce wiring inductance. there capacitors like 1.0uF 0.01uF, place 0.01uF closest pins. Ideal placement device component side pins, where trace length even vias eliminated. There sources inductance: inductance capacitor, inductance wiring between capacitor power pin, power lead inductance inside ground lead inductance inside ground inductance between ground. capacitor inductance negligible correct capacitor used. There control over lead frame inductance. keep inductance low, both power lead ground lead should keep short possible (less than inches). inductance trace given 0.005 In(2 h/w) H/inch where inverse log, height between power ground lead ground plane width power ground lead. Note that doubling width trace reducing will only decrease approximately decreasing length will decrease inductance 50%. typical board about inductance inch. 3.8. What done minimize ground noise? Return currents power supply transients during high current consumption produce most ground noise. Since ground noise cannot controlled decoupling capacitors, only minimizing effect ground noise minimize ground impedance design circuits minimize currents. best minimize ground impedance ground plane. advisable ferrite beads ground path this will inhibit return currents from leaving raise ground noise level. This problem since CMOS logic referenced ground. 3.9. What with unused (CMOS) inputs? unused inputs should connected their inactive state prevent unintentional switching which produces noise generation power consumption. CMOS inputs inactive state connected ground inactive high state connected power rail (Vcc) through series resistor (4.7k).
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3.10. necessary isolate analog from digital? Yes. digital CMOS circuits have high immunity external noise (approximately Vcc) whereas small amount external noise coupled into analog circuits devastating. analog circuits operate voltage swings (600 mVolts S/UNI-DUAL PECL inputs) compared large Volt) CMOS inputs. CMOS circuits also generate switching noise, especially when large number circuits running synchronously timed same system clock. analog power grounds isolated from each other unlikely that device will able clock data recovery without errors. 3.11. Should isolate transmit analog from receive analog?
Yes. noise S/UNI-DUAL receive analog power ground inputs PECL inputs will impact internal PLL's ability recover clock from incoming data. Added noise will degrade jitter tolerance jitter recovered clock. also important keep analog optical receiver common with receiver portion S/UNI-DUAL, especially grounds. S/UNIDUAL PECL inputs differential will reject common mode noise. However, they internally self-biased between ground (about Vdc) therefore must AC-coupled. This 3.7V reference must stable with reference incoming signal that switching threshold does move thus cause data jitter. especially important keep ground plane between optical receiver common with RAVS1 RAVS2 inputs S/UNI-DUAL. Ideally, transmission trace should routed directly over it's respective ground plane. transmit side S/UNI-DUAL, 155.52 clock synthesized from 19.44 reference clock. added noise power ground inputs impacts resulting 155.52 clock. added noise will increase intrinsic jitter transmitter. power ground optical transmitter common with analog transmit power ground S/UNI-DUAL. 3.12. isolate analog from digital transmit from receive? DART board three separate grounds, digital, analog 155.52 Mbit/s transmit high speed analog receive. three grounds shorted together main connector. Digital power used directly with some local decoupling. other analog power supplies derived with series ferrites local decoupling appropriate Transmit (TA)or Receive (RA) analog grounds. very important keep optics same ground DUAL. same goes ground plane since DUAL RXD± internal 3.7V reference derived from power ground.
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previous reference designs used cuts (channels power/ground planes isolate currents. This more difficult control predict final results. Using this method, several revisions required achieve optimum result. 3.13. does layout affect high speed return current? speeds return current follows path least resistance back driver. high speeds, however, return current follows path least inductance which lies plane directly under signal trace, total loop area between outgoing returning paths minimized. other words, highspeed return current follows path that almost "mirror image" signal trace plane underneath trace. This tight coupling provides good flux cancellation that common-mode current reduced. Therefore, high speed traces should cross cuts heavily perforated areas (where tight spacing through-hole components reside) power ground planes, cuts these planes interrupt return currents, causing them seek alternative paths back driver. different routes taken outgoing return currents will both induce common-mode noise other nearby signal traces. addition, routing high speed signals over continuous power planes, return current paths these signals known other signals will cross over these return currents, reducing possibility noise coupling. Detailed discussions high-speed design provided references. 3.14. When should ferrite beads used? Ferrite beads mainly used power rails pass current attenuated higher frequency noise that riding rail. impedance ferrite beads increases with frequency. ferrite bead like short, higher frequencies, impedance ferrite bead increase over ohms (depending bead frequency). Ferrite beads attenuate high frequency noise from power supply from getting into circuit, they also stop high frequency noise from leaving circuit. important, therefore, proper bypass decoupling when using ferrite beads. Ferrite beads should avoided CMOS power pins high current switching CMOS circuits causes noise introduced into power rail. Ferrite beads should also avoided ground this inhibits return currents. Ferrite beads used S/UNI-DUAL analog power pins they draw very little current. ferrite beads isolate receive inputs from each other. noise frequencies levels different every design, hard decide beads necessary what frequency should they effective. However, harder insert ferrite bead after board built than short bead needed.
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S/UNI-DUAL analog power RAVD2 generates oscillation. there ferrite bead this input, signal into other analog power pins performance affected. Ferrite beads used optical receiver receiver portion draws very little current. Ferrite beads also used optical transmitter power rails transmitter drives differential PECL pair which draws constant current. Most optical module vendors recommend using ferrite beads both receive transmit power rails. PECL (ECL) circuits draw constant current regardless frequency operation opposed CMOS, which only draws current during switching. DUAL does have true PECL drivers, they CMOS matched complimentary drivers. There will always drivers turned there will constant current drawn through power pins. 3.15. necessary de-couple every power S/UNI-DUAL? S/UNI-DUAL generate simultaneous synchronous asynchronous switching noise. Especially drop side clock frequencies transmit receive synchronous both logical devices operational. important decouple every power reduce self generated noise also prevent this noise from coupling onto other planes power pins.
3.16. Loop filter using ceramic capacitors internal op-amp S/UNI-DUAL's clock recovery unit (CRU) regenerates 155.52 clock from incoming SONET data. NOTE: component values below provisional. capacitors (C1, determine amount "peaking" jitter transfer curve. capacitor should non-polarized because when S/UNI-DUAL held reset, reverse-biased approximately VDC. Also, some process extremes, capacitors operate with reverse-bias VDC. addition, under normal operating conditions, when locked, will about +1.0 average. Since S/UNI-DUAL terminating device, loop filter values were chosen achieve maximum jitter tolerance performance application. should temperature stable Ceramic (X=55°C, 5=+85°C, 7=+125°C, ±15% capacitance variation over this temperature). devices available initial tolerance ±20%, ±15%, ±10% available 6.3V, 10V, 16V, 50V. should avoided these ceramics exhibit poor temperature tolerance this application.
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Fig. Clock recovery loop filter using ceramic capacitors
RAVD2
RXD+/RRCLK+/-
Phase/Freq Detector
Prefilter
OpAmp
recovered clock
LFRAVD2 RAVS2
on-chip off-chip
RAVS2
2N3904
Line Rate (Mbit/s) 155.52
(±1%) 68.1
(±1%)
(X5R, 20%)
(±1%)
Table
Recommended Component Values
Please Appendix capacitor vendor details. suggested manufacturers ceramic capacitors are: Manufacturer Taiyo Yuden LMK316BJ475ML Taiyo Yuden EMK325BJ475MN CC1206JX5R475K PHILIPS 2220RR475K8AB0C SM015C475KAJ240 Prestidio 3736X7R475K1NT91A Vitramon VJ2225Y475KXXAT
Type
6.3V
Footprint 1206 (0.12" .10") 1210 (0.12" .10") 1206 (0.12" .06") 2220 (0.22" .20") 3230 (0.32" .30") 3736 (0.37" .36") 2225 (0.22" .25")
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3.17. Loop filter using polarized tantalum capacitors footprint requirements, sourcing constraints, polarized Tantalum capacitors connected series more desirable option. Either back back (-'ve -'ve) anode anode (+'ve +'ve) used form non-polar capacitor. Since effective capacitance will halved, capacitors must used form (actually 16.5 non-polar capacitor. Since will always have positive bias (about when lock), single polarized capacitor with positive terminal connected pin. However, made series combination shown schematic below. corporation publishes several articles back back tantalums. capacitor should non-polarized because when S/UNI-DUAL held reset, capacitor could reverse-biased approximately 2.0V. Also, some process extremes, this capacitor operate with reverse-bias Vdc. Fig. Clock recovery loop filter with tantalum polarized capacitors
RAVD2
RXD+/RRCLK+/-
Phase/Freq Detector
Prefilter
OpAmp
recovered clock
LFR1 RAVD2
on-chip off-chip
RAVS2
2N3904
RAVS2
Line Rate (Mbit/s) 51.84
(±1%) 68.1
(±1%)
(Tantalum, 20%,
(Tantalum, 20%,
(±1%)
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3.18. drive REFCLK± inputs using oscillator? REFCLK± 19.44 clock input block diagram show below. These inputs driven with balanced coupled PECL source. ground REFCLK+, drive REFCLK- with single ended gate. this case clock must less than 0.4V more logic high. Fig. Block diagram DUAL's REFCLK inputs
3.7Vdc
Level input buffer 3.7Vdc threshold differential PECL RXVR
REFCLK111 REFCLK+
S/UNI-DUAL
Level input buffer
most applications it's more cost effective technically desirable supply single ended 19.44 reference clock. Generally, PECL clocks very expensive don't have route clock source great distance TTL/CMOS device more than adequate, provided design with care. Fig. Ideal reference clock
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Fig. Reference clock potential problems
Noise Overshoot Transmission Line Reflection Thresholds Slow dv/dt Undershoot
Ideal intrinsic jitter required 'non-loop time' mode clocking. However, even loop-time mode, fall-back reference clock clocking lost loss clock. non-loop time, whatever method decide use, please ensure that there minimum jitter generated 155.52 clock. shown diagram above, ensure that provide noise, free jitter, properly terminated, minimum over/undershoot reference. it's single ended clock, then attention must paid routing, termination, supply noise, grounding. Since multiplies reference clock derive 155.52 also multiplies jitter input. jitter input only 19.44 reference. However output 155.52 clock will have same jitter it's ns/6.4 jitter. shown below, system designer several choices clock generation distribution. cases, optimize intrinsic jitter, power supply decoupling required. Note larger caps TAVD1 TAVD2. Please mount capacitors, especially 0.01 right pins. Fig. Decoupling REFCLK power pins
Ferrite
Ferrite
Ferrite .01uF
TAVD1
TAVS1
.1uF
TTL/CMOS OSCILLATOR
.1uF
buffer required
Ferrite
SUNIDUAL
REFCLK-
transmission line coupling components
.01uF
.01uF
.01uF
TAVD1
TAVS2 REFCLK+
Transmit Analog Ground Plane
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Series source termination series termination most desirable offers lowest current consumption drivers, virtually zero current signal trace, zero ground return currents. Therefore, least amount board noise interfere with analog circuitry. chose trace because trace widths easily manufacturable, large enough swamped buffer source DART board incorporates FCT541 circuit below. FCT541 chosen faster rise time compared 74ACT541 74F541. Fig. REFCLK using series termination with loads
buffer with about source FCT541 CMOS OSCILLATOR
Zo=75
REFCLK+
SUNI-DUAL PECL INPUTS
REFCLK-
very short traces
another S/UNI-DUAL
Fig. REFCLK using series source termination load
REFCLK+ CMOS OSCILLATOR
Zo=75 SUNI-DUAL PECL INPUTS
REFCLK-
REFCLK+ signal must connected (Transmit Analog Ground) signal source must properly terminated. Also, very carefully decouple TAVD1 TAVS1 TAVD2 TAVS2 schematic. substitute/remove ferrites capacitors.
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Grounding REFCLK+, internally turns PECL threshold inputs, enables level threshold (low less than high more than 2.0V) gates. oscillator should placed close buffer possible unterminated. reason using oscillator match 74FCT541's input level. CMOS oscillator connected these inputs will cause duty cycle distortion output clock CMOS signals switch different thresholds. input thresholds, edges must sharp free noise, etc. When different oscillator buffer pair used, important match output level oscillator input level buffer order avoid duty cycle distortion. Notice FCT541 input thresholds (0.4V CMOS level outputs. DART board, series terminations best choice since offers lowest power consumption, least amount noise generated into circuit. buffer(s) driving into high impedance load hence current will almost zero except current required stray capacitance (gate input capacitance). source impedance must match trace. This source impedance both driver gate impedance external resistor. case chose with trace Careful check destination with scope will assure proper selected. Make sure inputs don't jitter steps especially input gate thresholds. only have DUAL your PCB, then buffer chip like FCT541 required oscillator drive (source series resistor) directly. have multiple destinations it's good idea multiple drivers with their Multi drop recommended with same driver reflections will serious problem, depending trace length. have only Analog ground plane multiple isolation cuts SORD (S/UNI-LITE) reference design, then more careful attention must placed routing ground returns. Parallel termination load using thresholds DUAL ground REFCLK+ pin, REFCLK- becomes threshold single ended input. Parallel termination used. However, driver must able drive necessary current into termination. must thus current 5V/50= This will generate noise driver switching, trace ground return currents recommended. halve drive current, could with traces =100. practice, these thin (0.008" wide) traces difficult manufacture reliably. Driving multiple loads recommended high current demands this type design.
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Fig. Driving parallel termination load
V=2.4 5Vp-p
CMOS OSC. Zo=50
S/UNI DUAL
REFCLKREFCLK+
current
Parallel termination with DUAL's PECL input thresholds reduce drive current, thus lower power noise, better utilize PECL thresholds REFCLK inputs. Care must taken over load DUAL inputs past power rails. Simply decouple REFCLK+ (Transmit analog Ground) with 0.01 drive REFCLK- with coupled clock. Here current method above. Fig. Parallel termination using DUAL's PECL inputs
CMOS OSC.
800mVVp-p rren 5Vp-p ents
Rs=100 Zo=50 0.01µF
S/UNI DUAL REFCLK-
current
REFCLK+
min)
Rt[Vo( min) min)]
this case, transmission trace, Vi(min), Vo(min)= 2.4V, maximum current Vo(max)=5V, would only about 5V/150 signal DUAL would about 50/150 1.67 Vp-p max. output only Vp-p worst case spec), then current input would mVp-p. then
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Multidrop parallel termination with PECL load tempted connect clock trace different devices terminate end. concern that transmit receive grounds could isolated channels into ground plane. Potential difference between grounds will affect reference clock inputs. example, reference clock terminated ground device, other device will less than ideal signal. second problem arise clock signal trace crosses cuts ground plane (i.e. from transmit ground island receive ground island). that case, ground return current from receive side cannot follow signal trace back driver. Instead, will seek alternative path least inductance. Consequently, this ground current will induce common-mode noise signals nearby. solution clock trace vicinity inputs then split into traces. There will discontinuity junction traces. traces will look like trace since they parallel. following diagram illustrates this solution: Fig. Multidrop parallel termination REFCLK
REFCLK+ REFCLKS/UNI DUAL REFCLK+ S/UNI DUAL REFCLK-
CMOS
Transmit Analog Ground
drawback above solution that, based layer setup described Appendix width trace less than mil. This width difficult board manufacturer fabricate accurately. Inaccuracy trace impedance will cause signals improperly terminated. PECL oscillator This most expensive method least risky terms layout possible noise. shown above, we've used single ended most reference designs with adverse effects long careful attention placed design layout stages. PECL drivers PECL Oscillator) long traces required, especially, clock different board your system.
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Fig. PECL oscillator driving long traces into REFCLK±
PECL Transmit Analog Ground REFCLKS/UNI DUAL REFCLK+
2*Zo
PECL oscillator driving PECL single ended loads Another alternative uses single PECL source clock drive different PECL inputs. PECL driver outputs +'ve -'ve. PECL oscillator 'out+' drive DUAL's REFCLK- while REFCLK+ decoupled ground with 0.01µF capacitor. PECL oscillator 'out-' connected other DUAL's REFCLK-. Appropriate terminations required each case. PECL oscillators tend more expensive than combined costs oscillator buffer. required. However, traces long, off-board, good choice would PECL oscillator PECL buffers there multiple loads. 3.19. accurate should board reference clock board reference clock required provide alternative timing reference event that primary timing reference becomes unavailable. example, network equipment (NE) configured line timing mode which transmitted signals timed from clock derived from received signal, alternative timing reference allows provide capability switch secondary clock incoming signal becomes unsuitable derive clock from. interfacing between equipment, between private public Aequipment, Bellcore specification GR-CORE-253, Issue Dec. 2,1995, Section 5.4.1 requires accuracy board reference clock better. interface between private Auser devices private Anetwork equipment, AForum specification "APHYsical Medium Interface Specification Mbit/s over Twisted Pair Cable", version Ballot Draft, 1994, requires transmitter Auser device have free-running transmit reference clock 155.52 Mbit/s with accuracy better. DART board design, 19.44 oscillator used reference from which 155.52 Mb/s generated without loss clock accuracy. Some vendors that provide these 19.44 oscillators listed below:
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Vendor
Motron Industries 605-665-9321 Connor Winfield 708-851-4722 Oscillatek Champion 708-451-1000 Frequency Control Group 717-486-3411 Ecliptek 714-433-1200 Table 19.44 3.20. CMOS terminology?
+/-20ppm better
+/-100ppm
Oscillator Vendors
CMOS terminology little confusing evolution naming convention. Even though these refer semiconductor family types, it's voltage levels logic highs lows that important. Their speed application also relevant. letter device prefix usually means that IC's input thresholds traditional levels. That zero will decoded voltage lower than volts. logic high will decoded input detects volts more. letter prefix means that device outputs will switch from power rails (typically zero volts depending loading). guaranteed drive past 2.4V pull required interfacing other types logic like PECL CMOS. Relative Speed Slew Rate 74C541 74LS541 74S541 74HC541 74F541 74FCT541 slowest slower slow faster fast fastest DEVICE EXAMPLES Level CMOS CMOS Outputs Level Outputs Hi>2.4V High Inputs Low<0.8V Level Inputs 2.0V <0.4V
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chose 74FCT541 since fastest output slew rate, power, inputs drives rails. ACCESSING DART board 4.1. DART board DART Interface Card SCI-PHY Mother Board arrangement below used test functionality DART board. SCI-PHY motherboard standard PMC-Sierra controller that allows access DART board's DUAL registers and. This motherboard also incorporates functionality which provides means transmitting receiving Acells SCI-PHY 16-bit bus. FIFO clock, this motherboard capable servicing four logical devices running 155.52 Mbits/s (OC-3) line rates. DART Interface Card specially designed DART board allow connector pinout differences, power input, allow simple drop side digital loop back, outlined below next section. Fig. Testing DART board DART Interface Card DART BOARD Optic Fiber
RS-232 In-House Test Motherboard
Loopback Control
4.2. Drop side loop-back Interface Card provides capability drop-side digital loop back device time. FIFO stream routed four FIFOs. Because wanted 16-bit MHz, could tolerate gate delays. simple mechanical loop back jumper connector shorts -bit bus. mechanical switch selects which FIFO source, another switch selects destination PHY. Only source destination time. SCI-PHY motherboard connected Interface Card times order able configure monitor Devices.
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external Line Error tester generates SONET Acells drives them into optical Input. FIFO cells routed back FIFO through jumper block. device then transmits cells back Error Tester optical transceiver. Fig. Drop side loop-back DART Interface Card Digital Data Loopback Jumper Block logical devices DART BOARD
SCI-PHY Mother Board
Optic Fiber
error tester
device time PM5348 S/UNI-DUAL electrical, mechanical register details, please refer S/UNI-DUAL PM5348 Data Sheet available either from your local PMC-Sierra Inc. Representative from Page http://www.pmc-sierra.com PM5348 Dual User Network Interface (S/UNI-DUAL) monolithic integrated circuit that implements SONET/SDH processing Amapping functions Mbit/s Mbit/s AUser Network Interfaces. fully compliant with SONET requirements AForum User Network Interface specifications. S/UNI-DUAL software configurable, allowing feature selection without changes external wiring. S/UNI-DUAL receives SONET/SDH channels separate serial interfaces, recovers their corresponding clock data, processes section, line path overhead each channel. Each channel performs framing (A1, A2), descrambling, detects alarm conditions, monitors section, line, path interleaved parity (B1, B3), accumulating error counts each level performance monitoring purposes. Line path block error indications also accumulated each channel. Each channel S/UNI-DUAL interprets received payload pointers (H1, extracts synchronous payload envelope which carries received Acell payload.
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Each channel S/UNI-DUAL frames Apayload using cell delineation. error correction provided. Idle/unassigned cells dropped according programmable filter. Cells also dropped upon detection uncorrectable header check sequence error. Acell payloads descrambled. Legitimate Acells written four cell FIFO buffer. Acells read from each channel's FIFO synchronous interface with cell-based handshake using either split wide datapath, direct wide datapath direct wide datapath. Counts received Acell headers that errored uncorrectable, those that errored correctable, passed cells accumulated independently each channel's performance monitoring purposes. S/UNI-DUAL transmits SONET/SDH channels separate serial interfaces formats section, line, path overhead each channel. Each channel performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, creates section, line, path interleaved parity (B1, required allow performance monitoring end. Line path block error indications also inserted. Each channel S/UNI-DUAL generates payload pointer (H1, inserts synchronous payload envelope which carries Acell payload. supports insertion variety errors into transmit stream, such framing pattern errors, interleaved parity errors, illegal pointers, which useful system diagnostics. Acells written each channel's internally programmable-length 4-cell FIFO synchronous interface using either split wide datapath, direct wide datapath, direct wide datapath. Idle/unassigned cells automatically inserted when internal FIFO contains less than cellEach channel S/UNI-DUAL generates header check sequence scrambles payload Acells. Payload scrambling disabled. line rate clocks required directly S/UNI-DUAL synthesizes transmit clock recovers receive clocks using single 19.44 6.48 reference clock. S/UNI-DUAL configured, controlled monitored generic 8-bit microprocessor interface. implemented power, Volt CMOS technology. PECL compatible inputs, TTL/CMOS compatible outputs packaged MQFP package. S/UNI-DUAL register address register details, please refer S/UNI-DUAL PM5348 Data sheet available either from your local PMC-Sierra Inc. Representative from Page http://www.pmc-sierra.com
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microprocessor interface provides access S/UNI-DUAL device registers 140-pin SCI-PHY connector. microprocessor interface block provides normal test mode registers, logic required connect microprocessor interface. normal mode registers required normal operation, test mode registers used enhance testability S/UNIDUAL. S/UNI-DUAL address space extends from 0x000H 0x1FFH. address bits, address (A8) being most significant being least significant bit) access S/UNI-DUAL normal mode register space
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APPENDIX LAYOUT NOTES A.1. Background
DART board 6-layer board that both through-hole (surface mount technology) components. large placed side most discrete devices located solder side with power ground planes buried internally. routing traces located external sides accessibility reasons. Layer A.2. Schematic Label Component side Solder Side Trace Impedance Control Description signal traces mainly components Transmit Ground (labeled 'TA') ground power respectively. volt power plane Receive Ground Plane signal traces discrete components
reduce signal degradation reflection radiation, impedance traces that carry high speed signals such transmitted received data should treated microstrip transmission lines terminated with matching impedance. trace width calculated using formula 5.98 1.41
based following layer setup: Fig. Printed Circuit Board Stacking
Copper
dielectric
Ground Plane
dielectric dielectric
Copper Copper
Copper
Power Plane
where
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relative dielectric constant, nominally fibre glass epoxy thickness copper, fixed according weight copper selected. copper, thickness 2.88mil). This thickness ignored great enough. thickness dielectric. width copper
parameters specified. example, (including copper thickness both sides board) layer core selected, dielectric material that same relative dielectric constant added both sides core construct layer board. Since controlled impedance traces component side, only relevant calculating trace width. calculation reference design shown tables below:
Parameters Board Thickness (mil) Nominal (including copper thickness)
Separation between layers (mil) Separation between layers (mil) Separation between layers (mil) Relative dielectric constant
30.5
Parameter
Data
(mil) (mil) (Ohm) (mil)
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Since proportional width traces, small will result traces being thin accurately fabricated. Wider traces more precisely manufactured, they take much board space. Therefore, thickness board should chosen that traces take little board space possible still leaving enough margin allow accurate fabrication. speed signals traces. Power ground traces should made wide possible reduce line inductance. traces mils wide. A.3. Routing
Routing based design considerations well manufacturability. Several suggestions listed below: Turns corners should rounded curves avoid discontinuity signal path. Allow least clearance among vias, traces, pads prevent short reduce crosstalk. possible, allow more clearance around vias manufacturers have minimum clearance requirements. traces that between pads edge connector, clearance trace width used. However, number lengths such traces should kept minimum. differential signal pairs should equal length that both signals arrive inputs same time. They should also parallel close another long possible that noise will couple onto both lines become common mode noise which ignored differential inputs. Even though single ended inputs should parallel another close proximity, single ended signals that parallel another dropside interface speed signals sampled after they have settled down; therefore, they should cause concern. power ground traces should made wide possible provide impedance paths supply current well allow quick noise dissipation. oscillator used package. connections oscillator setup that oscillator with smaller footprint pin) also plugged FCT541 buffer with series source terminations must used. Since vias have impedance, avoid them where possible, especially critical traces such TXD± RXD±. Also where decoupling critical, place capacitors pins (component side) have vias series with capacitors.
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APPENDIX DART BOARD DROP SIDE CONNECTOR PINOUT system connector interfaces this DART board local Alayer drop side controller. total 140-pins allow following functionality: micro controller interface power, 5Vdc, ±10% ground control logic four logical devices wide parallel FIFO access control SCI-PHY DART SCI-PHY edge connector interface includes signals required connect DART board high layer protocol entity (i.e. processor). Cells written S/UNI-DUAL/s transmit FIFO read from S/UNI-DUAL/s receive FIFO using this interface. edge connector made dual line female connectors shown table below total pins. consists signals appropriate read write registers DUAL devices daughter board, provides necessary power ground. signal levels used this interface. Since there four logical devices DART board, below have four sets control signals such RCA, TCA, RRDENB, TWRENB. Fig. DART board Expansion Connector
CHASSIS RRDMPH3 CHASSIS RRA1 RRA0 RCA2 RCA3 RCA4 TCA2 TCA3
RCAPH3 CSB2 RRDEN4B RRDEN3B RRDEN2B TWREN4B TWREN3B TWREN2B TCA4
NU=Not Used This board defined
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20-PIN EXPANSION CONTROL SIGNALS Name Type Function Reserved CHASSIS Power Safety ground used Interface devices such Fiber Optic Transceiver UTP-5 Electrical Line interface. RCAMPH3 used DART board, connect. CSD2B Input Active low, microprocessor chip select used select S/UNI-DUAL internal registers. Chip select DUAL connector RRDEN4B Input Active Receive Read Enable used enable reading S/UNI receive FIFO device RRDEN3B RRDEN1B. RRDEN2B active receive read enable Input (RRDEN1B) used initiate reads from logical device SUNI-DUAL receive FIFO. When sampled using rising edge RFCLK, word read from SUNI-DUAL internal synchronous FIFO output RDAT[15:0] bus. When sampled high using rising edge RFCLK, read performed. RRDENxB must operate conjunction with RFCLK access SUNI-DUAL FIFO high enough instantaneous rate 19.44 MHz)as avoid FIFO overflows. Alayer device deassert RRDEN1B anytime unable accept another byte. When signal configured deasserted with zero octets opposed four) SUNI-DUAL FIFO, error condition hold read enable (RRDEN1B) active. this situation, signal identifies valid octets. RRA1 Input used DART board, defined RCMP Board. It's UTOPIA Level address RRA0
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RCA2 RCA3 RCA4
Output
TWREN4B TWREN3B TWREN2B
Input
TCA2 TCA4 TCA3
Output
Active high receive cell available (RCA) signal (polarity selectable S/UNI-DUAL) indicates when cell available first logical device. Used S/UNI chip notify hardware drop side that there least Acell ready read receive FIFO. configured de-asserted when either zero four words remain S/UNI-DUAL FIFO. updated default rising edge RFCLK it's active edge programmable. active transmit write enable Input (TWRENB) used initiate writes SUNIDUAL transmit FIFO. When sampled using rising edge TFCLK, word TDAT[15:0] written into SUNI-DUAL transmit FIFO. When sampled high using rising edge TFCLK, write performed. complete octet cell must written SUNI-DUAL transmit FIFO before inserted into SPE. transmit cell available (TCA) signal indicates when cell available S/UNI-DUAL transmit FIFO. When high, indicates that S/UNIDUAL transmit FIFO full complete cell written When goes low, indicates either that S/UNI-DUAL transmit FIFO near full accept more than four writes that transmit FIFO full. Selection made using register S/UNI-DUAL TACP FIFO Control register. reduce FIFO latency, FIFO depth which indicates "full" one, two, three four cells S/UNI-DUAL TACP FIFO Control register. programmed depth less than four, additional cells written after asserted. updated rising edge TFCLK. active polarity this signal programmable S/UNI-DUAL defaults active high. TCA1 connector
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20-PIN EXPANSION CONNECTOR Name Type Function RDAT[15:8] high order byte Received Output RDAT[8] FIFO cell word RDAT[15:0]. Please refer RDAT[9] S/UNI-DUAL data sheet word cell data RDAT[10] structure. RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] RXPRTY1 Output Programmable function receive parity bit. mode, it's receive parity Receive Data RDAT[15:0] split mode, this parity channel RDAT[15:8] 8-bit mode used. Power Ground (used analog digital ground) TXPRTY1 Input Programmable function transmit parity input transmit Acell Data Bus. mode, it's parity TDAT[15:0] 8-bit split mode, this parity channel TDAT[15:8]. 8bit mode, this used. TDAT[15:8] high order byte Transmit INPUT TDAT[8] FIFO cell word RDAT[15:0]. Please refer TDAT[9] S/UNI-DUAL data sheet word cell data TDAT[10] structure. TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15]
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100-PIN CONNECTOR Name Type Function Power 1,2,13 Ground, used Digital Ground(D), ,16,17 Transmit Analog Ground (TA) Receive Analog ,20,21 Ground (RA) ,24,25 ,28,29 ,41,44 ,45,48 ,49,52 ,53,56 ,57,69 ,70,75 ,76,81 ,82,90 ,91,94 ,95,99 ,100 TDAT[7:0] order byte transmit FIFO Input TDAT[0] cell word TDAT[15:0]. Please refer S/UNI5 TDAT[1] DUAL data sheet word cell data structure. TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TXPRTY0 Input Programmable function transmit parity input transmit Acell Data Bus. This input ignored mode. 8-bit split mode, this parity channel TDAT[7:0]. 8-bit mode, parity TDAT[7:0] input TXPRTY[0] checked. Power 7,8,35 Volts Power 36,63, 64,85, TSOC Input transmit start cell (TSOC) signal marks start cell TDAT[15:0] bus. When TSOC high, first octet cell present TDAT[15:0] stream. necessary TSOC present each cell. interrupt generated INTB signal TSOC high during byte other than first byte. TSOC sampled rising edge TFCLK
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TCA1
Output
TFCLK
Input
18,19,20 description Connect
TWREN1B RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RXPRTY0
Input Output
Output
transmit write clock (TFCLK) used write Acells SUNI-DUAL four cell transmit FIFO. TFCLK cycles 50MHz lower instantaneous rate. complete octet cell must written SUNI-DUAL FIFO before being inserted synchronous payload envelope (SPE). TDAT[15:0], TXPRTY, TWRENB TSOC sampled rising edge TFCLK. updated rising edge TFCLK. description 15,17 RDAT[7:0] order byte Received FIFO cell word RDAT[15:0]. Please refer S/UNI-DUAL data sheet word cell data structure.
RSOC
Output
RCA1 RRDEN1B
Output Input
Programmable function receive parity bit. mode, this held low. split mode, this parity channel RDAT[7:0] 8bit mode, this parity both channels. receive start cell (RSOC) signal marks start cell RDAT[15:0] bus. When RSOC high, first octet cell present RDAT[15:0] stream. RSOC updated rising edge RFCLK. 12,14, full description. connector pins details other three RRDENxB signals
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RFCLK
Input
A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[8]
Input
Input Output
Input
receive read clock (RFCLK) used read Acells from SUNI-DUAL receive FIFO. RFCLK must cycle lower instantaneous rate, high enough rate avoid FIFO overflow 19.44 155.52 line rate). RRDENB sampled using rising edge RFCLK. RSOC, RDAT[15:0], RXPRTY updated rising edge RFCLK. address A[7:0] selects specific registers during S/UNI-DUAL register accesses.
bi-directional data D[7:0] used during local microprocessor read write S/UNI-DUAL control status registers.
INTB
Open Drain Output
CSB1 RSTB
Input Input
Address used S/UNI-DUAL. When low, user accessible registers (0x000 0x0FF) available local microcontroller. When high, test mode registers (0x100 0x1FF) accessed. normal operation only lower locations defined used. active interrupt (INTB) signal goes when S/UNI-DUAL interrupt source active, that source unmasked. S/UNI-DUAL enabled report many alarms events interrupts. Examples loss signal (LOS), loss frame (LOF), line AIS, line remote defect indication (RDI), loss pointer (LOP), path AIS, path many others. INTB returns high when interrupt acknowledged appropriate register access. INTB open drain output. must pulled high with resistor. active chip select from local must access S/UNI-DUAL registers. active reset (RSTB) signal provides asynchronous S/UNI-DUAL reset.
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Input
Input
Input
active read enable (RDB) signal during S/UNI-DUAL register read accesses. S/UNI-DUAL drives D[7:0] with contents addressed register while low. Used active write strobe (WRB) signal during S/UNI-DUAL register write accesses. D[7:0] contents latched into addressed register rising edge while selected CSB1 CSB2 low. address latch enable (ALE) active high latches address A[7:0] when low. When high, internal S/UNI-DUAL address latches transparent. allows S/UNI-DUAL interface multiplexed address/data bus. S/UNI-DUAL integral pull resistor. Used.
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S/UNI DUAL AREFERENCE TRANSCEIVER BOARD
APPENDIX MECHANICAL DRAWINGS
.217
.100
Hold down post .100 .050 .010 .260 .437
.100
101911-8 Edge Connector
TEST POINTS
S/UNI
OPTICS
S/UNI-DUAL
PM5348
155-DUAL
DROP SIDE 140-pin connector
OPTICS
74FCT541
19.44mHz Osc.
S/UNI
155-DUAL
OPTICS
S/UNI-DUAL
PM5348
OPTICS
LED's
Board Dimensions
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APPENDIX DART BOARD PARTS LIST
Part Name Value Part Number Description Jedec Type SOT23 SOIC20W CAP200 SMDCAP1206 Q1-Q4 C89,C91,C117,C119 C3,C7,C21,C25, C76,C80,C81,C83, C112,C120-C123,C141,C142,C145 C146,C150,C151,C154,C155,C157 0.01µF CAP, CERAMIC Ceramic, decoupling, high frequency SMDCAP805 C2,C5,C8-C12,C15-C19,C22, C23,C27-C59,C64-C68,C73-C75, C82,C84,C86-C88,C90, C92,C103,C109-C111,C114-C116, C118,C124,C128-C139,C148 47PF 100µF CAPACITOR,16V CAPACITOR,16V NPO_805 ELECTROLYTIC TANT SMDCAP805 CAP320 SMDTANCAP_C C4,C20,C26,C113 C6,C13,C14,C24,C78,C98,C102 C105,C126,C140,C143,C144,C147 C149,C152,C153, C156 4.7µF Ceramic Cap. NON-POLARIZED Taiyo Yuden inc. LMK316BJ475ML-B, 10V, X5R, 20%, 1206 size
2N3904 74FCT541
SOT23-BASE 74FCT541DW, octal buffer Decoupling, Ceramic, decoupling, high frequency
TANTALUM 0.1µF CAP, CERAMIC
note inside this document section 3.16 3.17 Appendix next capacitor vendor sources
CONN100-AMP_103911-8 CONN20-AMP_103911-2 HEADER2-BASE INDUCTOR-FB,50,
103911-8 AMP_103911-2 DIGI-KEY S1011-36-ND FAIR-RITE 2743019447
AMP_103911-8 AMP_103911-2 JUMPER2 INDUCTOR_FB
P1,P3 J1,J2 L3-L32
SUBSTITUTE LCD_PMD-HPBR-5205 LED10-RED,25MA,2.1V 19.44MHZ OSC, TTL, RESISTOR-100,1% RESISTOR-200,1% RESISTOR-237,1% RESISTOR-27,5% RESISTOR-330,5% RESISTOR-4.7K,5% RESISTOR-49.9,1% RESISTOR-68.1,1% RESISTOR-681,1% 4.7K RES_ARRAY_15pos RES_ARRAY_8_pos SMA-BASE SUNIDUAL PM5348 TEST POINT HEADER TOTAL COMPONENT COUNT PPM, note Test Points only PMC-Sierra Inc. DIGI-KEY S1011-36-ND HPBR-5205
.18" .12" .12" high PMD-SOCKET DIP20_LED CRYS14 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 SOIC16 SOIC16 PQFP160 TST_PT_1 U6-U9 R3,R6,R11,R17,R51,R54,R58,R61 R40,R43,R45,R48 R7,R8 R66-R68,R72-R74,R78-R80,R84-R86 R13-R15,R26, R29-R39,R44,R49 R64,R65,R70,R71,R76,R77,R82,R83 R52,R53,R59,R60 R63,R69,R75,R81 RN1-RN3,RN5 RN4,RN6,RN7 J3,J4 U2,U3 TP3-TP17,TP19-TP35,TP39-TP42
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APPENDIX Ceramic Multilayer Capacitor Sources basic tolerance Stable ±15% tolerance over temperature: (X7R rated from +125°C from -55°C +85°C) small size Surface Mount, some only reflow qualified unpolarized Part below bulk, check Data Sheet other packaging
Manufacturer Taiyo Yuden Inc. Distributor's EMK325BJ475MN-B LMK316BJ475ML-B
Type
Footprint
Thick 1.9mm 1.6mm 1.6mm 1.9mm
1210 (0.12" .10") 1206 (0.12" .06") special factory order LMK316BJ475KL-B 1206 (0.12" .06") EMK325BJ475KN-B 1210 (0.12" .10") Manufacturer: Taiyo Yuden Inc. 16-20 Ueno 6-chome, Taito-ku, Tokyo, Japan Phone: 03-3833-5441, FAX: 03-3835-4754 Rep.: Bowman, Chicago, USA, 847-925-0888 Distributor Canada; Electro Source, 6875 Royal Rd., Burnaby 604-435-2533 Taiyo Yuden Westfield. London Road, High Combe Buckingham Shire HP11,1MA Phone:(44) 1494-464642 FAX: (44) 1494-474743 CC1206JX5R475K 6.3V 1206 (0.12" .06") internal Manufacturer's C3216X5R0J475K) Corp. America: 1600 Feehanville Drive, Mount Prospect, Ill. 60056 1996 Edition Electronic Components Distributor Catalog page 15-20 Phone: (847) 803-6100 FAX: (847) 803-6296 Distributor: Enerlec Sales, Brenda, Richmond Canada, 604-273-0882 2220RR475J8AB0C 2220 (0.22" .20") 2220RR475K8AB0C 2220 (0.22" .20") 2220RR475M8AB0C 2220 (0.22" .20") Philips Electronics Ltd., Milner Avenue, Scarborough, Ontario, Canada Compact Series Catalog Phone (416) 292-5161 FAX: (416) 292-4477 SM015C475KAJ240 3230 (0.32" .30") SM015C475MAJ240 3230 (0.32" .30") Corporation, Myrtle Beach, USA, SMPS Series Capacitors Catalog Phone: (803) 448-9411 FAX: (803) 448-1943 Limited, Aldershot England Phone: (252-336868 FAX: 252-346643 3736X7R475K1NT91A many 3736 (0.37" .36") Prestidio Components Inc., 7169 Construction Court, Diego, 92121 1997 Catalog; page A1122-1123 Phone: (619) 578-9390 FAX: 1-800-538-3880
PHILIPS
Prestidio
Vitramon
VJ2225Y475JXXAT 2225 (0.22" .25") VJ2225Y475KXXAT 2225 (0.22" .25") VJ2225Y475MXXAT 2225 (0.22" .25") Manufacturer: Vitramon, Route Monroe, 06468, Mail: 544, 06601 Phone (203) 268-6261 FAX: (203) 452-5670
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APPENDIX SCHEMATICS
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APPENDIX SCHEMATIC COMPONENT CROSS REFERENCE
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S/UNI DUAL AREFERENCE TRANSCEIVER BOARD
APPENDIX SCHEMATIC SIGNAL CROSS REFERENCE
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APPENDIX ARTWORK
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APPENDIX REFERENCES American National Standards Telecommunications, ANSI T1.105.03 1994 Bell Communications Research, Bellcore GR-253-CORE, Issue Dec. 1995 International Telecommunications Union, ITU-T Recommendation G.958 "Digital Line Systems Based Synchronous Digital Hierarchy Optical Fibre Cables" PMC-Sierra, PMC5348 databook, Issue January 1997, PMC-950919, "S/UNI-155-DUAL, Saturn User Network Interface 155.52 51.84 Mbit/s" PMC-Sierra, S/UNI-LITE (PM5347) Optical Reference Design (SORD board), PM5946, PMC-950112 Ott, Henry "Noise Reduction Techniques Electronic Systems", Second Edition, John Wiley Sons. Montrose, Mark "Printed Circuit Board Design Techniques Compliance", IEEE Press, 1995. Graham, Martin Johnson, Howard "High-Speed Digital Design: Handbook Black Magic", Prentice-Hall Inc, 1993. Tokin catalog EC-110E User's manual EC-111E, 1996, 1-408-432-8020
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CONTACTING PMC-SIERRA PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, Canada Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Applications Information: Site:
Seller will have obligation liability respect defects damage caused unauthorized use, mis-use, accident, external cause, installation error, normal wear tear. There warranties, representations guarantees kind, either express implied custom, regarding product performance, including those regarding quality, merchantability, fitness purpose, condition, design, title, infringement thirdparty rights, conformance with sample. Seller shall responsible loss damage whatever nature resulting from reliance upon, information contained this document. event will Seller liable Buyer other party loss profits, loss savings, punitive, exemplary, incidental, consequential special damages, even Seller knowledge possibility such potential loss damage even caused Seller's negligence. 1997 PMC-Sierra, Inc. PMC-960552(R1) Printed Canada Issue date: January, 1997
105-8555 Baxter Place Burnaby, Canada (604 )416-6000
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