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PMC-960552 ISSUE 1

PM5948 DART-BOARD

PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
PM5948 S / UNITM
155-DUAL
DART BOARD S / UNI-DUAL A REFERENCE TRANSCEIVER BOARD
Issue 1:
January, 1997
PMC-Sierra, Inc.
105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 (604 )415-6000
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
PMC-Sierra, Inc.
105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 (604 )415-6000
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
APPENDIX A: PCB LAYOUT NOTES .....................................1 A.1. Background...................................................1 A.2. Trace Impedance Control.......................................1 A.3. Routing.......................................................3 APPENDIX B: DART board DROP SIDE CONNECTOR PINOUT..............1 APPENDIX C: MECHANICAL DRAWINGS.................................1 APPENDIX D: DART board PARTS LIST..................................1 APPENDIX E: 4.7µF Ceramic Multilayer X5R and X7R Capacitor Sources.....1 APPENDIX F: SCHEMATICS............................................1 APPENDIX G: SCHEMATIC COMPONENT CROSS REFERENCE ...........1 APPENDIX H: SCHEMATIC SIGNAL CROSS REFERENCE .................1 APPENDIX I: PCB ARTWORK ............................................1 APPENDIX J: REFERENCES............................................1 CONTACTING PMC-SIERRA ............................................1
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
DUAL DART BOARD DUAL
SONET / SDH Fiber (LINE SIDE)
This 6 layer PCB contains two S / UNI-DUAL PM5348 chips. On the line side, each S / UNI-DUAL processes two, full duplex A packed, SONET / SDH 155 Mbit / s STS-3c / STM-1, or 51.8 Mbit / s (STS-2) data streams. This gives four logical A devices, each operating up to 155 Mbit / s in both receive and transmit directions for a board aggregate full duplex rate of 622 Mbit / s. The line side requires a stable 19.44 MHz (or 6.48 MHz for STS-2) reference clock to both PM5348 ICs. Clock jitter must be carefully controlled and, depending on the design, special attention must be given to buffers, propagation delays, clock skew, power supply decoupling, trace impedance and termination. The drop side provides a Saturn a Compliant Interface - PHYsical layer (SCIPHY) 16-bit Rx and 16 bit Tx bus. It may be clocked up to 50 MHz for an aggregate parallel transfer bandwidth of 800 megabits (16 bits x 50 MHz) in both receive and transmit directions. Configuration, control and status monitoring of the two S / UNI-DUAL chips is accomplished via the 140 pin connector using an 8-bit microcontroller on the external motherboard controller.
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
2. DART board IMPLEMENTATION 2.1. Important implementation principles To reduce digital and analog power / ground noise on the DART board, a multi-layer PCB with three ground planes is required. This simplifies design and reduces time to market. The 19.44 MHz reference TTL (not PECL) oscillator is buffered with a 74FCT541. A series transmission line termination method was used to reduce drive current and system noise. Transmission line traces of 75 characteristic impedance are implemented for the 19.44 Mhz reference clock. A compromise between 50 and 100 so that the traces are wide enough to be repeatable in manufacturing, and also have a high enough Zo to keep currents as low as possible. The connections used for the 155.52 Mbit / s PECL data, between the DUAL and the PMD, are wider 50 traces. 2.2. Block diagram Fig. 2 DART board block diagram
DART BOARD PM5948
Status
20 pin
PHY - 3 Ctrl
S / UNI-DUAL
PM5348
· four direct PHY controls · external Reference 19.44mHz · external FIFO clock (50mhz) · 16 bit RX & TX FIFO Bus PHY -2 Ctrl 8-bit uP I / F 100 pin
Tx / Rx 15:0 · generic 8-bit micro I / F · external RESET · +5VDC power, & Ground 20 pin A DATA BUS PHY - 1 Ctrl
PM5348
PHY - 0 Ctrl S / UNI-DUAL
Optical I / F
all three ground planes shorted at the connector
4 SONET / SDH OC-3
Optical I / F
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2.3. Power supply and ground layers The power supply is carefully distributed via power and ground planes. One power plane supplies the digital circuits directly and ferrite series elements are used to generate the other analog supplies. In addition, there are three separate ground planes that originate from the main drop side connector: Digital ground (D), line side Transmit Analog Ground (TA) and line side Receive Analog Ground (RA). To optimize jitter tolerance, the separate ground planes isolate the noisy digital circuits (grounds) from the more sensitive analog receive and transmit blocks. Fig. 3 Power and ground distribution
Power Connector
100µF Bulk +
10µF Bulk + +
Ferrite
Vcc (digital power) Layer #4 Analog Power
· · · Ferrite
.1µF plus 10nF caps
· · · Analog Power
.01µF caps
Star Ground Distribution
.1µF plus 10µF 10nF Bulk caps
TA (Transmit Ground -Layer #2) D (Digital Ground - Layer #3) RA (Receive Ground -Layer #5)
2.4. Optical line side interface The serial line side utilizes four PMD (Physical Media Device) Optical Transceiver modules. The receive optics are connect directly to the S / UNI-DUAL RXD+ / - inputs. To ensure that there is a clock in the absence of optical input, the signal detect (SD) output of the optics is connected to the ALOS- input of the S / UNI-DUAL (the ALOS+ input is grounded). In normal operation (good incoming signal) the S / UNI-DUAL device recovers the clock from the incoming data. In a loss of signal condition, the S / UNIDUAL will squelch the data on the receive data (RXD+ / -) pins and the phase lock loop will switch to the reference clock (19.44 MHz) to keep the recovered clock in range. This technique guarantees that the S / UNI-DUAL will generate a SONET LOS indication if the Optical Transceiver loses optical input.
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S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
S / UNI-DUAL
3K Signal Detect (SD) from a Optical or UTP-5 PMD 121(80) ALOS119(82) ALOS+ 3.7Vdc TTL Level input buffer 1 0
3K 3.7Vdc
3.7Vdc threshold differential PECL RXVR
2 TTL Level input buffer
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RA (Receive Analog Ground)
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S / UNI-DUAL
3.7Vdc
RXD RXD+
3.7Vdc
3.7Vdc threshold differential PECL RXVR
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
DART BOARD
0.01µF
Optical PMD
Ferrite
RXD+ R1AVD1
0.01µF RA
R1AVS1
3.7Vdc
TTL Level input buffer 1 0 3.7Vdc threshold differential PECL RXVR MUX 1 S
3K 112 REFCLK111 REFCLK+
S / UNI-DUAL
2 TTL Level input buffer
The DART board utilized a TTL (vs. PECL) 20ppm oscillator and a 74FCT541 high speed single ended TTL buffer. Fast slew rate FCT buffer is required to reduce clock jitter. A source series termination of 27 was used to DC drive the 75 ohm transmission line. The REFCLK+ is strapped to ground to enable single ended REFCLK- operation.
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S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
TAVS1 TAVS2 REFCLK+
DUAL #1
REFCLK-
REFCLKREFCLK+ TAVS2 TAVS1 DUAL #2
2.9. Drop side 50 MHz FIFO bus The drop side refers to the parallel FIFO Receive and Transmit data bus and its associated handshake control signals as shown below: The FIFO RFCLK and TFCLK clock can be 50 MHz and can present careful timing and termination design to ensure error free operation. Please refer to the data sheet for detail timing information. Please note the output electrical specs and that driving a DC termination load of 50 or even 100 is not possible. Series source terminations of about 27 could be used or if timing permits (ie. clock speeds slower than 50 MHz), a bus driver could be used for driving off-board. Fig. 13 Drop side - PHY Interface block diagram
DART BOARD
16-bit TX FIFO bus 16-bit RX FIFO bus DUAL #1
RX & TX control (RCA, TCA, RSOC, TSOC, RRDENB, RFCLK, TFCLK) DUAL #2
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The associated drop side PHY bus timing is illustrated below. For complete detailed timing information, please refer to the S / UNI-DUAL, PM5348 Data Book, PN# PMC950919. Fig. 14 Multi-PHY mode timing 16-bit, TX FIFO near empty option
TFCLK TWRENBn TCAn TSOC1 TDAT15:0 TXPRTY1:0
W(n-4)
W(n-3)
W(n-2)
W(n-1)
Fig. 15 Multi-PHY Mode Timing, 16-bit, receive FIFO empty and Tristate options
RFCLK RRDENB1 RRDENB2 RCA1 RCA2 RSOC1 RDAT15:0 RXPRTY1:0
W(n-1) W(n) W1 W2 W3 W4
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DART BOARD
8-bit data bus
control (RD, WR, A8:0, RST, INTB, RSTB) Decode CS1 CS2
DUAL #1
DUAL #2
2.11. Decoupling for Intrinsic Jitter on the DART
board
To optimize intrinsic jitter on this reference design, it is beneficial to decouple the 5 Vdc power pins, TAVD1 and TAVD2 as shown in the enclosed schematics. A series ferrite is required with a 1.0µF Tantalum in parallel with a 0.01µF ceramic decoupled to their respective analog ground pins, RAVD1 and RAVD2. 3. DESIGN CONSIDERATIONS
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3.3. What
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Unterminated lines (open line) should only be used for very short line lengths (less than 1 / 4 of an inch), or for low frequency signals. An unterminated line is shown below with resistor Re used to pull the PECL signal low: Fig. 17 Unterminated transmission line
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Parallel terminated lines offer the best terminations for speed and power consumption. The receiver end of the transmission line terminates and biases the signal. The terminating resistor is the same value as the characteristic impedance of the transmission line. Unfortunately this requires another voltage supply as the terminating voltage (VT) is Vcc - 2 Volts. A parallel terminated line is shown below where RT equals Zo: Fig. 19 Parallel terminated transmission line VT
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
0.01 µF Out + PECL Transmiter
Re 330
S / UNI-DUAL
Re 330
0.01 µF
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
Ferrite
0.1µF TA
800mVp-p differential
5Vp-p
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
0.01µF due to X L
XCeff
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
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S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
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S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
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S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
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Fig. 23 Clock recovery loop filter using ceramic X5R capacitors
RAVD2
RXD+ / RRCLK+ / -
Phase / Freq Detector
Prefilter
OpAmp
recovered clock
LF+ LFRAVD2 R2 C2 R1 C1 RE RAVS2 LFO
on-chip off-chip
RAVS2
2N3904
Line Rate (Mbit / s) 155.52
Table 1:
Recommended Component Values
Please see Appendix E for capacitor vendor details. A few suggested manufacturers of X5R and X7R ceramic capacitors are: Manufacturer PN# Taiyo Yuden LMK316BJ475ML Taiyo Yuden EMK325BJ475MN TDK CC1206JX5R475K PHILIPS 2220RR475K8AB0C AVX SM015C475KAJ240 Prestidio 3736X7R475K1NT91A Vitramon VJ2225Y475KXXAT
µF 4.7 4.7 4.7 4.7 4.7 4.7 4.7
Type X5R X5R X5R X7R X7R X7R X7R
VDC 10V 16V 6.3V 25V 50V 25V 25V
Footprint 1206 (0.12" by .10") 1210 (0.12" by .10") 1206 (0.12" by .06") 2220 (0.22" by .20") 3230 (0.32" by .30") 3736 (0.37" by .36") 2225 (0.22" by .25")
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RAVD2
RXD+ / RRCLK+ / -
Phase / Freq Detector
Prefilter
OpAmp
recovered clock
LF+ R2 LFR1 RAVD2 LFO
on-chip off-chip
RAVS2
C1a C1b
2N3904
RAVS2
Line Rate (Mbit / s) 51.84
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3.7Vdc
TTL Level input buffer 1 0 3.7Vdc threshold differential PECL RXVR MUX 1 S
3K 112 REFCLK111 REFCLK+
S / UNI-DUAL
2 TTL Level input buffer
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Fig. 27 Reference clock potential problems
Noise Overshoot Transmission Line Reflection Thresholds Slow dv / dt Undershoot
Ferrite
Ferrite 1uF .01uF
TAVD1
TAVS1
TTL / CMOS OSCILLATOR
buffer if required
Ferrite
SUNIDUAL
REFCLK-
transmission line & coupling components
.01uF
· .01uF
1uF .01uF
TAVD1
TAVS2 REFCLK+
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TTL buffer with about 50 source Z FCT541 TTL or CMOS OSCILLATOR
111 REFCLK+ TA
SUNI-DUAL PECL INPUTS
112 REFCLK-
very short traces
to another S / UNI-DUAL
Fig. 30 REFCLK using series source termination and one load
111 REFCLK+ TA TTL or CMOS OSCILLATOR
112 REFCLK-
TA The REFCLK+ signal must be connected to the TA (Transmit Analog Ground) and the signal source must be properly terminated. Also, very carefully decouple TAVD1 to TAVS1 and TAVD2 to TAVS2 as per schematic. Do not substitute / remove ferrites or capacitors.
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Fig. 31 Driving a 50 Ohm parallel termination load
S / UNI DUAL
REFCLKREFCLK+
TTL or CMOS OSC. TA
Too M 800mVVp-p & Cu any Co mpo rren t is T n 2.4 to 5Vp-p oo H ents igh
S / UNI DUAL REFCLK-
REFCLK+
RtVo( min) - Vi ( min) Vi
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d) Multidrop parallel termination with PECL load One may be tempted to connect the one clock trace to two different devices and terminate at the far end. The concern is that the transmit and receive grounds could be isolated by channels cut into the ground plane. Potential difference between the grounds will affect one of the reference clock inputs. For example, if the reference clock is terminated to the ground of one device, the other device will get a less than ideal signal. A second problem may arise if the clock signal trace crosses the cuts in the ground plane (i.e. from transmit ground island to receive ground island). In that case, ground return current from the receive side cannot follow the signal trace back to the driver. Instead, it will seek an alternative path of least inductance. Consequently, this ground current will induce common-mode noise on signals nearby. One solution may be to run a 50 ohm clock trace to the vicinity of the two inputs and then split into two 100 ohm traces. There will be no Zo discontinuity at the junction of the 50 and the two 100 traces. The two 100 traces will look like a 50 trace since they are in parallel. The following diagram illustrates this solution: Fig. 33 Multidrop parallel termination of the REFCLK
10 nF REFCLK+ 100 100 Ohm 50 Ohm 100 Ohm 100 10 nF REFCLKS / UNI 10 nF DUAL REFCLK+ 10 nF S / UNI DUAL REFCLK-
CMOS OSC
Transmit Analog Ground
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50 Ohm Zo PECL OSC RE 330 RE 330 Transmit Analog Ground Zo 50 Ohm 10 nF REFCLKS / UNI DUAL REFCLK+ 10 nF
100 2Zo
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Vendor
+ / -20ppm or better Yes Yes Yes Yes Yes No
+ / -100ppm Yes Yes Yes Yes Yes Yes
Oscillator Vendors
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RS-232 In-House Test Motherboard
Loopback Control
4.2. Drop side loop-back The Interface Card provides capability for drop-side digital loop back of one PHY device at a time. Any one of the PHY RX FIFO stream can be routed to any one of the four TX FIFOs. Because we wanted to run the 16-bit bus at 50 MHz, we could not tolerate gate delays. A simple mechanical loop back jumper connector shorts out the RX 16 -bit PHY bus to the TX bus. A mechanical switch selects which PHY is the FIFO source, and another switch selects the destination PHY. Only one PHY is the source and one PHY is the destination at any one time. The SCI-PHY motherboard can be connected to the Interface Card at all times in order to be able to configure and monitor the PHY Devices.
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An external Line Bit Error tester generates SONET A cells and drives them into the optical Input. The RX FIFO cells are routed back to the TX FIFO through the jumper block. The PHY device then transmits the cells back to the Bit Error Tester via the optical transceiver. Fig. 36 Drop side loop-back DART Interface Card Digital Data Loopback Jumper Block 4 PHY logical devices DART BOARD
SCI-PHY Mother Board
Optic Fiber
Bit error tester
one PHY device at a time 5. PM5348 S / UNI-DUAL For electrical, mechanical and register details, please refer to the S / UNI-DUAL PM5348 Data Sheet available either from your local PMC-Sierra Inc. Representative or from our Web Page at: http://www.pmc-sierra.com The PM5348 Dual User Network Interface (S / UNI-DUAL) is a monolithic integrated circuit that implements SONET / SDH processing and A mapping functions for two 155 Mbit / s or 51 Mbit / s A User Network Interfaces. It is fully compliant with SONET and SDH requirements and A Forum User Network Interface specifications. The S / UNI-DUAL is software configurable, allowing feature selection without changes to external wiring. The S / UNI-DUAL receives two SONET / SDH channels via separate bit serial interfaces, recovers their corresponding clock and data, and processes section, line and path overhead for each channel. Each channel performs framing (A1, A2), descrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path far end block error indications (M0 or M1, G1) are also accumulated for each channel. Each channel of the S / UNI-DUAL interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received A cell payload.
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The microprocessor interface provides access to the S / UNI-DUAL device registers via the 140-pin SCI-PHY connector. The microprocessor interface block provides normal and test mode registers, and the logic required to connect to the microprocessor interface. The normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the S / UNIDUAL. The S / UNI-DUAL address space extends from 0x000H to 0x1FFH. Of the 9 address bits, address bit 8 (A8) being the most significant bit and A0 being the least significant bit) is set low to access the S / UNI-DUAL normal mode register space .
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APPENDIX A: PCB LAYOUT NOTES A.1. Background
based on the following layer setup: Fig. 37 Printed Circuit Board Stacking
1 Oz Copper
dielectric r
Ground Plane
dielectric r dielectric r
1 Oz Copper 1 Oz Copper
1 Oz Copper
Power Plane
where
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The parameters h1, h2, and h3 can be specified. For example, if a 20 mil (including the copper thickness on both sides of the board) two layer core is selected, dielectric material that has the same relative dielectric constant can be added to both sides of the core to construct a 4 layer board. Since all the controlled impedance traces are on the component side, only h1 is relevant in calculating the trace width. The calculation for the reference design is shown in the tables below:
Parameters Board Thickness (mil) Nominal 62 (including copper thickness) 10
Separation between layers 1 and 2 (mil) Separation between layers 2 and 3 (mil) Separation between layers 3 and 4 (mil) Relative dielectric constant
Parameter
Data 4.2 10 1.4 50 17
h (mil) t (mil) for 1oz Zo (Ohm) W (mil)
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Since h1 is proportional to the width of the traces, a small h1 will result in the traces being too thin to be accurately fabricated. Wider traces can be more precisely manufactured, but they take up too much board space. Therefore, the thickness of the board should be chosen so that the traces take up as little board space as possible yet still leaving enough margin to allow accurate fabrication. The low speed signals use 8 to 10 mil traces. Power and ground traces should be made as wide as possible to reduce the line inductance. All 50 Ohm traces are 17 mils wide. A.3. Routing
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CHASSIS GND RRDMPH3 CHASSIS GND RRA1 RRA0 RCA2 RCA3 RCA4 TCA2 TCA3
NU RCAPH3 CSB2 RRDEN4B RRDEN3B RRDEN2B TWREN4B TWREN3B TWREN2B TCA4
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RCA2 RCA3 RCA4
Output
TWREN4B TWREN3B TWREN2B
Input
TCA2 TCA4 TCA3
Output
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
J3 100-PIN CONNECTOR S i g n al Name Type P I N Function GND Power 1, 2, 13 Ground, used on PCB as Digital Ground(D), , 16, 17 Transmit Analog Ground (TA) and Receive Analog , 20, 21 Ground (RA) , 24, 25 , 28, 29 , 41, 44 , 45, 48 , 49, 52 , 53, 56 , 57, 69 , 70, 75 , 76, 81 , 82, 90 , 91, 94 , 95, 99 , 100 TDAT7:0 is the low order byte of the transmit FIFO Input 3 TDAT0 cell word TDAT15:0. Please refer to the S / UNI5 TDAT1 DUAL data sheet for the 27 word cell data structure. 9 TDAT2 11 TDAT3 4 TDAT4 6 TDAT5 10 TDAT6 12 TDAT7 TXPRTY0 Input 14 Programmable function transmit parity input bit for the transmit A cell Data Bus. This input is ignored in 16 bit mode. In 8-bit split bus mode, this is the parity for channel #1 of TDAT7:0. In 8-bit bus mode, the parity of TDAT7:0 and input TXPRTY0 is checked. VCC Power 7, 8, 35 +5 Volts DC Power 36, 63, 64, 85, 86 TSOC Input 15 The transmit start of cell (TSOC) signal marks the start of cell on the TDAT15:0 bus. When TSOC is high, the first octet of the cell is present on the TDAT15:0 stream. It is not necessary for TSOC to be present at each cell. An interrupt may be generated on the INTB signal if TSOC is high during any byte other than the first byte. TSOC is sampled on the rising edge of TFCLK
PMC-Sierra, Inc.
REFERENCE DESIGN
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
TCA1 NC
Output
TFCLK
Input
See pin 18, 19, 20 of J1 for TCA description No Connect
TWREN1B RDAT0 RDAT1 RDAT2 RDAT3 RDAT4 RDAT5 RDAT6 RDAT7 RXPRTY0
Input Output
Output
The transmit write clock (TFCLK) is used to write A cells to the SUNI-DUAL four cell transmit FIFO. TFCLK cycles at a 50MHz or lower instantaneous rate. A complete 53 octet cell must be written to the SUNI-DUAL FIFO before being inserted in the synchronous payload envelope (SPE). TDAT15:0, TXPRTY, TWRENB and TSOC are sampled on the rising edge of TFCLK. TCA is updated on the rising edge of TFCLK. See description of J1 pin 13, 15, 17 RDAT7:0 is the low order byte of the Received FIFO cell word RDAT15:0. Please refer to the S / UNI-DUAL data sheet for the 27 word cell data structure.
Output
RCA1 RRDEN1B
Output Input
Programmable function receive parity bit. In 16 bit mode, this pin is held low. In split bus mode, this is the parity bit for for channel #1 on RDAT7:0 . In 8bit bus mode, this is the parity bit for both channels. The receive start of cell (RSOC) signal marks the start of cell on the RDAT15:0 bus. When RSOC is high, the first octet of the cell is present on the RDAT15:0 stream. RSOC is updated on the rising edge of RFCLK. See J1 pin 12, 14, & 16 for full description. See connector J1 pins 7, 9 & 11 for details on the other three RRDENxB signals
PMC-Sierra, Inc.
REFERENCE DESIGN
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
RFCLK
Input
Input & Output
Input
The receive read clock (RFCLK) is used to read A cells from the SUNI-DUAL receive FIFO. RFCLK must cycle at a 50 MHz or lower instantaneous rate, but at a high enough rate to avoid FIFO overflow ( 19.44 MHz @ 155.52 MHz line rate). RRDENB is sampled using the rising edge of RFCLK. RSOC, RDAT15:0, RXPRTY and RCA are updated on the rising edge of RFCLK. The address bus A7:0 selects specific registers during S / UNI-DUAL register accesses.
The bi-directional data bus D7:0 is used during by the local microprocessor to read and write to the S / UNI-DUAL control and status registers.
Open Drain Output
CSB1 RSTB
Input Input
Address bit 8 used by S / UNI-DUAL. When low, the user accessible registers (0x000 to 0x0FF) are available to the local microcontroller. When high, the test mode registers (0x100 to 0x1FF) can be accessed. In normal operation only the lower 256 locations are defined and used. The active low interrupt (INTB) signal goes low when a S / UNI-DUAL interrupt source is active, and that source is unmasked. The S / UNI-DUAL may be enabled to report many alarms or events via interrupts. Examples are loss of signal (LOS), loss of frame (LOF), line AIS, line remote defect indication (RDI), loss of pointer (LOP), path AIS, path RDI and many others. INTB returns high when the interrupt is acknowledged via an appropriate register access. INTB is an open drain output. and must be pulled high with a resistor. The active low chip select from the local uP must be low to access U2, S / UNI-DUAL #1 registers. The active low reset (RSTB) signal provides an asynchronous S / UNI-DUAL reset.
PMC-Sierra, Inc.
REFERENCE DESIGN
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
Input
RDY WRB
Input
The active low read enable (RDB) signal is low during S / UNI-DUAL register read accesses. The S / UNI-DUAL drives the D7:0 bus with the contents of the addressed register while RDB and CSB are low. Not Used The active low write strobe (WRB) signal is low during a S / UNI-DUAL register write accesses. The D7:0 bus contents are latched into the addressed register on the rising WRB edge while the selected CSB1 or CSB2 is low. The address latch enable (ALE) is active high and latches the address bus A7:0 when low. When ALE is high, the internal S / UNI-DUAL address latches are transparent. It allows the S / UNI-DUAL to interface to a multiplexed address / data bus. The S / UNI-DUAL ALE has an integral pull up resistor. Not Used.
PMC-Sierra, Inc.
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
APPENDIX C: MECHANICAL DRAWINGS
Hold down post .100 .050 .010 .260 .437
AMP 101911-8 Edge Connector
TEST POINTS
HP OPTICS
S / UNI-DUAL
PM5348
- 155-DUAL
DROP SIDE 140-pin connector
HP OPTICS
74FCT541
19.44mHz Osc.
155-DUAL
HP OPTICS
S / UNI-DUAL
PM5348
HP OPTICS
PCB Board Dimensions
PMC-Sierra, Inc.
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
APPENDIX D: DART BOARD PARTS LIST
1 2N3904 2 74FCT541
SOT23-BASE 74FCT541DW, FCT octal buffer Decoupling, 10 or 16V Ceramic, decoupling, high frequency Low ESR and low ESL
3 1.0 µF CAP TANTALUM 4 0.1µF CAP, CERAMIC
see app note inside this document section 3.16 and 3.17 and Appendix E next for capacitor vendor sources
P2 P1, P3 J1, J2 L3-L32
PMC-Sierra, Inc.
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
Footprint
Thick 1.9mm 1.6mm 1.6mm 1.9mm
PHILIPS
Prestidio
Vitramon
PMC-Sierra, Inc.
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
APPENDIX F: SCHEMATICS
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S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
APPENDIX G: SCHEMATIC COMPONENT CROSS REFERENCE
PMC-Sierra, Inc.
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APPENDIX H: SCHEMATIC SIGNAL CROSS REFERENCE
PMC-Sierra, Inc.
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PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
APPENDIX I: PCB ARTWORK
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
PMC-Sierra, Inc.
REFERENCE DESIGN
PMC-960552 ISSUE 1
PM5948 DART-BOARD
S / UNI - DUAL A REFERENCE TRANSCEIVER BOARD
CONTACTING PMC-SIERRA PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Applications Information: Web Site:
PMC-Sierra, Inc.
105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 (604 )416-6000