NUAL UATION SHEET EVAL FOLLO 3-Cell, Step-Up/Down, Two-Way Pager

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NUAL UATION SHEET EVAL FOLLO 3-Cell, Step-Up/Down, Two-Way Pager

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19-4771; 10/98
NUAL UATION SHEET EVAL FOLLO
3-Cell, Step-Up/Down, Two-Way Pager System
Regulated Step-Up/Step-Down Operation 80mA Output from Cells Efficiency 13µA Idle Mode(coast) Current Selectable Low-Noise Low-Current Operation Operating Frequency Synchronized Seven Times External Clock Source Operates 270kHz with External Clock Automatic Backup-Battery Switchover
_General Description
MAX769 complete buck/boost power supply monitoring system two-way pagers other lowpower digital communications devices. external components required. Included on-chip are: 80mA output, synchronous-rectified, buck/boost DC-DC converter with digitally controlled +1.8V +4.9V output. DC-DC converter unique, since provides regulated output battery inputs that both less than greater than output voltage, without using transformers. Three low-noise linear-regulator outputs Three DAC-controlled comparators softwaredriven, 3-channel conversion SPITM-compatible serial interface Reset low-battery (LBO) warning outputs Charger NiCd/NiMH, lithium battery, storage capacitor power system backup (typical), serial-controlled, open-drain MOSFET switches beeper vibrator drive evaluation MAX769 (MAX769EVKIT) available design prototyping.
Configuration appears data sheet.
MAX769
Ordering Information
PART MAX769EEI TEMP. RANGE -40°C +85°C PIN-PACKAGE QSOP
_Applications
Two-Way Pagers Receivers 3-Cell Powered, Hand-Held Equipment
_Typical Operating Circuit
INPUT ALKALINE BATTERIES 1.5V 5.5V LOW-BATTERY IN/OUT REJECT IN/OUT RSIN SD03 DR2IN DRGND
BATT
PGND REG2IN
SERIAL
MAX769
OUTPUT 2.85V ANALOG OUTPUT LOGIC OUTPUT RECEIVER NiCd STORAGE BATTERY CAPACITOR STACK
DRIVERS
REG2 REG1
INPUT OPTIONAL
SYNC
REG3 NICD
FILT
AGND
Idle Mode trademark Maxim Integrated Products. trademark Motorola, Inc.
Maxim Integrated Products
free samples latest literature: http://www.maxim-ic.com, phone 1-800-998-8800. small orders, phone 1-800-835-8769.
3-Cell, Step-Up/Down, Two-Way Pager System MAX769
ABSOLUTE MAXIMUM RATINGS
BATT, OUT, NICD, LBO, AGND.-0.3V REG1, REG2, OFS, REF, R2IN AGND .-0.3V (OUT 0.3V) SCL, SDO, SDI, SYNC, FILT, DR2IN, CH0, LBI, RSIN AGND.-0.3V (REG1 0.3V) REG3 .-0.3V (REG2 0.3V) DR1, DRGND .-0.3V (BATT 0.3V) PGND, DRGND AGND .-0.3V +0.3V PGND .-0.3V (OUT 0.3V) PGND .-0.3V (BATT 0.3V) Continuous Power Dissipation +70°C) QSOP (derate 8mW/°C above +70°C) .640mW Operating Temperature Range .-40°C +85°C Junction Temperature .+150°C Storage Temperature Range .-65°C +165°C Lead Temperature (soldering, 10sec) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(OUT 3.0V, BATT 3.6V, -40°C +85°C, unless otherwise noted. Typical values +25°C.) (Note PARAMETER GENERAL PERFORMANCE BATT Typical Operating Range (Note BATT Minimum Start-Up Voltage (Note Coast Mode Supply Current (Note Mode Supply Current (Note BATT Supply Current (Note NICD Input Current, Standby (Note NICD Input Supply Current, Backup (Note NICD Input Current, Power Fail (Note REG2 Supply Current (Note REG3 Supply Current (Note Supply Current (Note Reference Voltage DR1, On-Resistance DR1, Leakage Current Output Output High Logic Input Level Logic Input Level High Logic Input Current Coast Mode +25°C REG2, REG3 off, VOUT 2.8V REG2, REG3 Coast Mode Charger Backup Modes off, NICD 3.6V Backup Mode, NICD 3.6V, Charger Backup Modes off, BATT Incremental supply current when Incremental supply current when Incremental supply current when IREF 20µA, 1.8V 4.9V +25°C 120mA -40°C +85°C ISDO 100µA ISDO -100µA, from REG1 Includes SDI, SCL, DR2IN, SYNC Includes SDI, SCL, DR2IN, SYNC Logic Input 3.3V; includes SDI, SCL, DR2IN, SYNC VREG1 VREG1 -1.5% 1.28 1.5% 1350 CONDITIONS UNITS
3-Cell, Step-Up/Down, Two-Way Pager System
ELECTRICAL CHARACTERISTICS (continued)
(OUT 3.0V, BATT 3.6V, -40°C +85°C, unless otherwise noted. Typical values +25°C.) (Note PARAMETER Maximum Clock Rate Setup Time (tDS) Hold Time (tDH) Output Valid (tDO) Output Valid (tDV) Disable (tTR) Setup Time (tCSS) Hold Time (tCSH) Pulse Width High (tCSW) Pulse Width High (tCH, tCL) DC-DC CONVERTER Output Current, Mode (Note Output Current, Coast Mode (Note Error, Coast Mode (Note Error, Mode (Note Step Size (Note Load Regulation Line Regulation Maximum Duty Cycle Voltage Ripple Switch Current Limit On-Resistance (Note PHASE-LOCKED LOOP (PLL) Frequency, Free-Run Frequency, Locked Jitter (Note Capture Time (Note NICD CHARGER Current High Current Error, Backup Regulator Backup-Regulator On-Resistance (Note 0.2V (OUT NICD) 15mA_CHG 0.2V (OUT NICD) 1mA_CHG 2.8V, IOUT 20mA, NICD 3.3V Backup Mode, NICD 3.3V 0.45 -3.5 +25°C, FILT connected fSYNC 38.4kHz fSYNC 38.4kHz, FILT Network (22nF 10k) fSYNC 38.4kHz, FILT Network (22nF 10k) 268.8 Circuit Figure 3.0V, BATT 3.0V Circuit Figure 3.0V, BATT 3.0V Coast Mode, 1.8V 4.9V Mode, 1.8V 4.9V Coast Mode, 1.8V 4.9V IOUT 80mA, Mode BATT 1.6V 4.5V 3.0V IOUT 80mA, COUT 47µF with 0.25 During inductor charge cycle LX1, LX2, BATT 3.0V NMOS PMOS -3.5 -3.5 mVp-p duty cycle CONDITIONS UNITS SERIAL-INTERFACE TIMING SPECIFICATIONS (Note
MAX769
3-Cell, Step-Up/Down, Two-Way Pager System MAX769
ELECTRICAL CHARACTERISTICS (continued)
(OUT 3.0V, BATT 3.6V, -40°C +85°C, unless otherwise noted. Typical values +25°C.) (Note PARAMETER LINEAR REGULATORS REG1 PMOS On-Resistance REG1 Supply Rejection (Note REG1 Clamp Voltage REG2 Voltage Drop REG2 Load Regulation REG2 Supply Rejection (Note REG3 Output Voltage REG3 Supply Rejection (Note LBI/RSIN Input Threshold LBI/RSIN Input Hysteresis (Note LBI/RSIN Input Current LBO/RSO Output LBO/RSO Output Leakage LBO/RSO Response Time (Note Threshold Range (Note Threshold Range (Note Threshold Range (Note Threshold Resolution (Note Threshold Resolution (Note Threshold Resolution (Note Error Error Error Input Hysteresis (Note Input Hysteresis (Note Measures NICD Measures BATT thresholds 200mV, 800mV, 1270mV thresholds 1200mV, 3200mV, 5080mV thresholds 1200mV, 3200mV, 5080mV -2.0 15mV -3.0 60mV -3.0 60mV Measures NICD Measures BATT IOUT Output 5.5V 10mV overdrive 15mV 60mV 60mV 3.0V, IREG1 65mA 268.8kHz, CREG1 10µF ceramic IOUT 1mA, 4.9V +25°C -40°C +85°C IREG2 24mA, 3.0V, ROFS IREG2 0.1mA 24mA 268.8kHz, CREG1 10µF, ceramic, ROFS 15k, COFS 0.1µF, IREG2 15mA IREG3 268.8kHz, CREG1 ceramic Falling input 0.96 0.58 3.15 0.60 0.63 1.27 5.08 5.08 1.04 3.45 CONDITIONS UNITS
DATA-ACQUISITION VOLTAGE MONITORS
3-Cell, Step-Up/Down, Two-Way Pager System MAX769
ELECTRICAL CHARACTERISTICS (continued)
(OUT 3.0V, BATT 3.6V, -40°C +85°C, unless otherwise noted. Typical values +25°C.) (Note PARAMETER Input Hysteresis (Note Input Current Comparator Response Time (Note Note Note Note Note Note Note Note Note Note 0.2V 1.27V 10mV overdrive CONDITIONS -100 UNITS
Note Note Note Note Note Note Note
Specifications -40°C guaranteed design, production tested. This tested parameter, since powered from OUT, BATT. Minimum start-up voltage tested determining when pins draw least 15mA 0.5µs (min) 285kHz (min) repetition rate. This guarantees that will deliver least 200µA pin. This supply current drawn from pin. Current drain from battery depends voltages BATT DC-to-DC converter's efficiency. Current into BATT addition supply current OUT. This current roughly constant from Coast Mode. Current into NICD when NICD isn't being charged isn't regulating OUT. Current into NICD when NICD regulating OUT. Doesn't include current drawn from rest circuit. Measured setting regulation point 2.8V holding 3.0V. Current into NICD when BATT both This test guarantees that NICD won't draw significant current when main battery removed backup activated. Serial-interface timing specifications tested provided design guidance only. Serial-interface functionality tested clocking data 5MHz with duty-cycle clock checking proper operation. With below 2.5V, serial-interface clock frequency should reduced 1MHz ensure proper operation. This specification directly tested guaranteed correlation on-resistance current-limit tests. Measured using internal feedback network Coast-Mode error comparator regulate OUT. Doesn't include ripple voltage inductor currents. Measured using internal feedback network Run-Mode error comparator regulate OUT. Doesn't include ripple voltage inductor currents. Uses measurement techniques described error, Coast Mode, error Mode specifications. on-resistance either LX2. acquisition characteristics depend impedance FILT pin. specification tested provided design guidance only. limits this specification guaranteed provided design guidance only.
Typical Operating Characteristics
+25°C, unless otherwise noted.)
EFFICIENCY LOAD CURRENT (RUN MODE, VOUT 3.0V)
MAX769-01
EFFICIENCY LOAD CURRENT (COAST MODE, VOUT 3.0V)
MAX769-02
EFFICIENCY LOAD CURRENT (COAST MODE, VOUT 2.4V)
MAX769-03
1.5V 2.0V EFFICIENCY
5.0V 3.5V 2.5V 2.0V 1.5V
5.0V 3.5V 2.5V 2.0V 1.5V
EFFICIENCY
EFFICIENCY
5.0V 3.5V 2.5V
LOAD CURRENT (mA)
0.01 LOAD CURRENT (mA)
0.01 LOAD CURRENT (mA)
3-Cell, Step-Up/Down, Two-Way Pager System MAX769
Typical Operating Characteristics (continued)
+25°C, unless otherwise noted.)
NO-LOAD BATTERY CURRENT BATTERY VOLTAGE
VOUT 3.0V COAST MODE BATTERY CURRENT (µA)
MAX769-04
MAXIMUM LOAD CURRENT BATTERY VOLTAGE
COAST MODE VOUT 3.0V MODE
MAX769-05
START-UP BATTERY VOLTAGE LOAD CURRENT
VOUT 3.0V COAST MODE
MAX769-06
MAXIMUM LOAD CURRENT (mA)
START-UP BATTERY VOLTAGE
BATTERY VOLTAGE
BATTERY VOLTAGE
LOAD CURRENT (mA)
NICD CHARGING CURRENT NICD VOLTAGE
MAX769-07
ON-RESISTANCE VOUT
MAX769-08
NICD CHARGING CURRENT (mA)
15mA MODE VOUT 4.9V NICD VOLTAGE VOUT VOLTAGE
NOISE SPECTRUM (RUN MODE, SYNC OPERATION)
MAX769-09
REG2 NOISE SPECTRUM (RUN MODE)
MAX769-10
NOISE (dBµV) NOISE (dBV)
FREQUENCY (kHz)
1000 10,000 FREQUENCY (kHz)
3-Cell, Step-Up/Down, Two-Way Pager System
Description
NAME PGND RSIN FILT SYNC AGND DRGND DR2IN REG3 REG2 R2IN NICD REG1 BATT FUNCTION Connect inductor. internally connected NFET that switches PGND PFET that switches OUT. Serial Data Input Interface Serial Data Output Interface Power Ground. Source NFETs. Serial Clock Interface Open-Drain Output Comparator Reset Output. Open drain goes when RSIN drops below 0.6V. serial registers reset set) state well. 1.28V Reference. Bypass with capacitor. compared 7-bit that adjusts from 0.2V 1.27V. comparison result sent register. Reset Input. Triggers resets when input below 0.6V. Comparator with hysteresis (18mV). Low-Battery Input. Triggers internal serial bit. external network sets loop response adjust frequency lock time versus jitter: (22nF 10k). Sync Input Switch Rate. 38.4kHz input results 268.8kHz rate (seven times SYNC frequency). Resistor sets offset between REG1 other point) REG2. ROFS results 150mV. Analog Ground Ground Sources Open-Drain Switch. Activated serial-interface bit. Logic Input. ANDed with DR2ON control switch. Open-Drain Switch. DR2ON DR2IN pin. Regulator Output. serial interface. noise. 24mA REG2 Output. Linearly regulated voltage (voltage difference 10µA ROFS). REG2 isolates noise. REG2 Input. Connect OUT, REG1, another voltage source. 15mA Settable Charge Current from 3-Cell NiCd Stack. When NICD_REG_ON (Table NICD becomes input linear regulator OUT, DC-DC converter off. PFET Output Connected OUT. Output clamped such that cannot rise above 3.3V, regardless voltage OUT. DC-DC Converter Output Feedback Point. Digitally controlled from 1.8V 4.9V 100mV steps (Table Positive Connection Battery. powered from OUT. Chip Select Serial Interface Connect other inductor terminal. internally connected NFET that switches PGND PFET that switches BATT.
MAX769
3-Cell, Step-Up/Down, Two-Way Pager System MAX769
3-CELL BATTERY BATT SERIAL OV0-OV4 DAC0-DAC7 RESET CONTROL 7-BIT BACKUP REGULATOR AOUT FEEDBACK 1.28V REFERENCE CHG/REG CHARGE NICD BACKUP REGULATOR 1mA/15mA CPRS 10µA 3.3V REG2 REG3 1.0V REG2 10µF R2IN COFS 0.1µF ROFS NICD CLAMP WHEN 3.3V CLAMP REG1 10µF 47µF SYNC FILT 22nF PGND 68µH 22µF
MAX769
0.6V CPLB FROM NICD FROM BATTERY RUN/ COAST
(PFM COAST)
0.6V RSIN
REG3 1.0V
DR2IN
DRGND
AGND
Figure MAX769 Block Diagram
3-Cell, Step-Up/Down, Two-Way Pager System
_Detailed Description
MAX769 contains several functional blocks that simplify integration power-supply monitoring functions within 3-cell powered system. They described following subsections. REG1 output clamps 3.3V. This arrangement limits VREG1 acceptable voltage logic when programmed higher voltage (typically >4V) charging (see Charger Circuit Backup Linear Regulator sections).
MAX769
Voltage Regulators
Regulator outputs include following: OUT: Main switch-mode buck/boost output REG1: switch output voltage clamp. Switches REG1 clamps REG1 3.3V when 3.4V more. REG2: Linear-regulated, 24mA low-noise output that regulates that VOUT VREG2 difference voltage (10µA ROFS). Output peak-to-peak ripple typically with 10µF bypass capacitor REG2. REG2 clamps output 3.3V when 3.4V more. REG3: Low-noise, linear regulator that supplies 2mA.
Low-Noise Analog Supply (REG2) REG2 linear, 24mA low-dropout regulating circuit whose input R2IN. REG2 output (VREG2) ROFS. ROFS does absolute voltage, rather offset level from R2IN (Figure VREG2 VREG2 VR2IN 10µA ROFS
Typically R2IN tied OUT, which case: VOUT VREG2 10µA ROFS ROFS adjusts REG1 REG2 allow REG2 noise rejection traded voltage drop consequent efficiency loss. (typical) value sets 150mV voltage difference. R2IN typically supplied from REG1, connected elsewhere long voltage applied R2IN does exceed VOUT. lowest output noise REG2, connect R2IN REG1. Note that REG2 output also clamps 3.3V when 3.4V higher.
Main DC-DC Boost Converter (OUT) main DC-DC converter's output. supplies current from internal synchronous-rectified buck/ boost regulator needs external FETs voltagesetting resistors. output voltage (VOUT) adjusted from 1.8V 4.9V 100mV steps (Tables internal control using serial-data command. supply 80mA, less current supplied other regulators (REG1, REG2, REG3).
also into low-current, pulse-skipping Coast Mode (13µA typical quiescent current) resetting RUN/COAST serial input bit. supplies 40mA Coast Mode. Typically, when changing from Coast Mode, lower voltage also (Table further reduce system operating current. extent this reduction depends minimum operating voltage system components when they standby sleep states. 1.8V; however, some Mode functions limited when VOUT below 2.5V: allowed serial-interface clock rate reduced. Internal on-resistance increases.
Low-Noise, Analog Supply (REG3) REG3 low-noise linear regulator that supplies 2mA. REG3's input internally connected REG2.
Frequency Synchronization
DC-DC converter switching frequency pulsewidth-modulation (PWM) mode nominally 270kHz synchronization clock supplied FILT tied REF. used, filter network connected FILT, clock applied SYNC, internal oscillator locks seven times input clock rate. MAX769 designed 38.4kHz SYNC input hence 268.8kHz operating frequency. switching frequency unaffected serial-data clock rate.
Voltage Detectors (LBO Reset)
MAX769 contains voltage-detector inputs: RSIN. RSIN comparator outputs open-drain pins (LBO RSO) real-time hardware output. also readable serial interface. Both RSIN trigger 0.6V input threshold have about 18mV hysteresis. also triggers MAX769 internal power-on reset (POR).
Logic Supply (REG1) REG1 regulator conventional sense, rather PFET that acts either switch voltage clamp, depending programmed voltage. When 3.3V less, REG1 operates switch. When 3.4V more,
3-Cell, Step-Up/Down, Two-Way Pager System MAX769
3-CELL ALKALINE BATTERY
22µF BATT PGND
68µH
MBR0520L
REG1 270k DR2IN DRGND 250k
47µF 3.0V LOGIC
0.1µF
REG1
MAX769
R2IN
10µF COFS 0.1µF 10µF ROFS,
SERIAL
DRIVERS
REG2
2.85V ANALOG RCVR 1.3M
REG3
RESET 3-CELL NiCd 100k
38.4kHz 22nF
SYNC FILT
RSIN NICD
470k
AGND
Figure Standard Application Circuit
7-Bit (CH0 Input CH1, CH2)
Three analog channels compared 7-bit, serially programmed digital-to-analog converter DAC). voltage varied 10mV steps from 200mV VREF 1LSB 1.27V) (Table external input, while signals internally generated from NICD BATT pins. NICD BATT internally divided four before being compared DAC. comparison threshold voltages each channel described following equations: (CH0: 10mV (CH1: NICD) 40mV (CH2: BATT) 40mV
where decimal equivalent binary code DAC0-DAC6 (Table DAC0 LSB. code 1111111 equates 127. When zeros programmed, comparators turn off. CH0, CH1, comparison results reside three locations output serial data (Table data delayed read cycle. other words, each result comparison made against voltage programmed during previous serial-write operation. analog-to-digital (A/D) conversion performed channel using system software step through successive-approximation routine input partially known, setting voltage near estimated point checking successive bits.
3-Cell, Step-Up/Down, Two-Way Pager System
faster shortcut used battery measurements when goal "go, determination. this type test, simply desired limit, supplies result next serial-write operation. instance which this shortcut saves time during battery-impedance check. unloaded battery voltage first measured, time allows, using techniques described previous paragraph. Then magnitude loaded voltage drop quickly checked with single comparison within desired limit. circuitry invoked both Coast Modes. Functions that programmed Coast Mode (Table REG2 REG3 NICD charger (Note: This overload turned Coast Mode when other loads present) Backup regulator CH0, CH1, CH2, Functions that always turn Coast Mode are: SYNC circuits DC-DC control circuits
MAX769
Open-Drain Drivers
open-drain drivers (DR1 DR2) activated serial interface. grounded (typical) NFETs that sink 120mA. maximum sink current limited on-resistance package dissipation about 240mA total sink current both switches. Note that designed sink current only from main battery (BATT) cannot pulled above BATT. controlled external input (DR2IN) well serial input bit. DR2IN ANDed with DR2ON serialcontrol bit, allowing drive audio beeper. audio-frequency clock applied DR2IN, ON/OFF gating applied DR2ON. Both DR2IN (pin DR2ON (serial bit) must high switch
Power-On Reset
MAX769 internal circuit (VOUT 1.6V) ensure orderly power-up when battery first applied. This feature separate from comparator; however, goes during operation, serial registers same predetermined states power-up. states each register listed Table Note that MAX769 always comes reset Coast Mode; consequently, cannot supply full power until Mode selected serial command. System software cannot exercise full load current until Mode enabled.
Charger Circuit
charger current source from NICD activated serial (Table current source charge small 3-cell NiCd NiMH battery (typically coin cell) 1-cell lithium battery. charge current either 15mA 1mA. sets maximum charge float) voltage. When charging implemented, VOUT must also high enough allow sufficient headroom charger current source. VOUT VNICD difference should normally between 0.2V 0.5V. Charger current NICD voltage graphed Typical Operating Characteristics. Note also that charging current reduces current available other loads.
Coast Mode/Voltage Selection
Reduce operating current setting RUN/COAST serial input. This shifts DC-DC boost converter from low-noise operation (Run Mode) very operating current mode (Coast Mode) which switching pulses only provided needed satisfy load. further reduce operating current Coast Mode, lower VOUT using OV0-OV4 serial bits. MAX769 starts Coast Mode. Select Mode with serial interface after power-up. Various circuit functions disabled follows: Functions that always remain Coast Mode are: Serial Reference (REF) REG1 LBI, RSIN (and LBO, RSO)
Backup Linear Regulator
BACKUP serial input turns backup regulator, which sources current from NICD OUT. This regulator backs using rechargeable battery NICD) when main battery BATT) depleted removed. backup regulator pass device's resistance typically typically supply 20mA with only 100mV dropout.
3-Cell, Step-Up/Down, Two-Way Pager System MAX769
Table Serial-Bit Assignments
(MSB) DAC6 DAC5 DR2_ON DAC4 DR1_ON LBO_Sets_ BACKUP DAC3 REG3_ON BACKUP DAC2 REG2_ON 15mA_CHG DAC1 RUN/ COAST 1mA_CHG DAC0
Table Serial-Bit Power-On Reset (POR) States
Table Input-Bit Function Description
INPUT RUN/COAST REG2_ON, REG3_ON DR1, 1mA_CHG, 15mA_CHG FUNCTION Mode, Coast Mode (POR state Coast Mode). Turns selected regulator (POR state off). Turns selected switch (POR state off). Turns selected charge current NICD. both set, charge current 15mA (POR state off). Turns backup linear regulator from NICD disables DC-DC converter (POR state BACKUP off). Setting this overrides 1mA_CHG, 15mA_CHG, LBO_Sets_BACKUP (Figure Allows turn backup regulator disable DC-DC converter (POR state connection between BACKUP). Sets Output Voltage (POR state VOUT 3.0V). Sets 7-bit voltage conversion (POR state zeros with comparators off).
BACKUP
LBO_Sets_BACKUP OV0-OV4 DAC0-DAC6
Table Serial Output Data
(MSB) D3-D0 FUNCTION CH_OUT output bits. indicates that selected channel (CH_) voltage greater than voltage that less than 0.6V.
CH2_OUT
CH1_OUT
CH0_OUT
3-Cell, Step-Up/Down, Two-Way Pager System
Table VOUT Output Voltage
SERIAL-DATA
LBO_SETS_BACKUP BACKUP REGULATOR BACKUP 1mA_CHG 15mA_CHG CHARGER CONTROL
VOUT
DC-DC converter charging circuitry disabled when backup regulator turned other functions remain active. Activate BACKUP manually serial command, trigger automatically LBO.
MAX769
Automatic Backup
Setting LBO_Sets_BACKUP serial (Table programs that when goes low, backup regulator automatically turns without instructions from microprocessor (µP). When LBO_Sets_BACKUP backup regulator turned only setting BACKUP bit. BACKUP also overrides LBO_Sets_BACKUP bit. Figure shows logic this function. main battery depleted NiCd battery drained during backup, goes while backup regulator supplying used monitor REG1). When falls, serial registers reset their states (with DC-DC converter Coast Mode backup regulator off, Tables This prevents from getting hung with DC-DC converter when main battery inserted. This sequence required because MAX769 default "DC-DC converter when coming reset, (still reset RSO) would able provide device with serial instructions turn
Serial Interface
MAX769 SPI-compatible serial interface. serial-interface lines Chip Select (CS), Serial Clock (SCL), Serial Data (SDI), Serial Data (SDO). Serial input data arranged 8-bit bytes. Most bytes contain 3-bit address pointer (R2, along with bits input data (D4-D0). common operations such selecting Coast Mode, activating REG2 REG3, turning DR2, only (R2, address register needs written. serial input data format MAX769 operations outlined Tables
Figure Logic Charger Control BACKUP LBO_Sets_BACKUP Serial Input Bits
3-Cell, Step-Up/Down, Two-Way Pager System
Serial data clocked first. Input data latched rising edge, output data shifted falling edge. When goes low, immediately contains output (D7). clocked until falling clock edge that follows first rising clock edge after Chip Select. timing diagrams Figures writes reads concurrently, necessary perform dummy writes order read output data. Four output data bits (D7-D4, Table sent from each time serial operation occurs.
MAX769
When address pointers. However, when remaining bits (R1, D4-D0) become programming bits. This violation programming etiquette sometimes address bits other times data bits) allows loaded with only write operation. Writing zeros turns CH0, CH1, comparators, NICD BATT voltage-sensing resistors minimize current consumption. This reduces current drain from about 30µA.
tCSH SCLK
tCSS
tCSH
DOUT
Figure Detailed Serial-Interface Timing
Figure SCL, SDO, Serial Timing
3-Cell, Step-Up/Down, Two-Way Pager System
Applications Information
Component Selection
MAX769 requires minimal design calculation optimized component values shown Figure However, some flexibility component selection still allowed, described following text. list suitable components provided Table Inductor nominally 68µH, values from 47µH 100µH should satisfactory. inductor current rating should 300mA more full output current (80mA) needed. less output current required, inductor current rating reduced proportionally should never less than 150mA. Inductor resistance should minimized best efficiency, since MAX769 N-channel switch resistance typically 0.9, efficiency does improve significantly coil resistances below 0.4. Filter capacitors C1-C4 should low-ESR types (tantalum ceramic) lowest ripple best noise rejection. values shown Figure optimized each output's rated current. Lower required output current allows smaller capacitance values. Resistors RSIN inputs voltage which outputs trigger. voltage threshold both 0.6V. resistors required desired trip voltage, (Figure VTRIP, calculated R2[(VTRIP(LBO) 0.6) R4[(VTRIP(LBO) 0.6) minimize battery drain, large values (>100k) above equations; 470k good starting value. Low-Noise Analog Supply (REG2) section information selecting ROFS. Since open-drain outputs, pull-up resistors usually required. Normally these will pulled REG1. 100k recommended compromise between response time current drain, although other values used. Since high (open circuit) during normal operation, current normally does flow pull-up resistors until low-battery reset event occurs. from external logic powered from REG1, open-drain logic devices that pulled REG1.
MAX769
Board Layout Noise Reduction
MAX769 makes every effort internal design minimize noise EMI. Nevertheless, prudent layout practices still suggested best performance. Recommendations follows: Keep trace lengths LX1, LX2, well PGND, short wide possible. Since toggle between VBATT VOUT fast rate, minimizing trace length serves reduce excess board area that might antenna. Place filter capacitors OUT, REG1, REG2, REG3 close their respective pins possible more than 0.5mm away). Consider using inductor shielded inductor will minimize radiated noise, essential. Toroids will also exhibit performance similar that shielded coils. Keep power components uppermost part minimize coupling other parts circuit. LX1, LX2, OUT, PGND pins located uppermost part facilitate board layout. Other pins this area digital affected close proximity switching nodes. separate short, wide ground trace PGND ground side BATT filter capacitors. this trace ground plane.
Table External Components
SUPPLIER INDUCTORS (68µH) Coilcraft Murata DT1608C-223, DT1608C-683 LQH4N680K CD54-680 Sumida CDR74B-680 CD73-680 CAPACITORS Marcon Sprague Polystor series THCR series 595D series C3216 series A-10300 Tantalum Ceramic Tantalum Ceramic Farads 0.58, 3.18mm high, shielded 1.9, 2.6mm high, current, cost 0.46, 4.5mm high 0.33, 4.5mm high, shielded 0.33, 3.5mm high PART COMMENTS
Logic Levels
Note that since MAX769's internal logic powered from REG1, input logic levels digital inputs (DR2IN, RUN, SYNC, SDI) well logic output level governed voltage REG1. Logic-high inputs these pins should exceed VREG1. Digital inputs should either driven
STORAGE CAPACITOR (optional NICD pin)
3-Cell, Step-Up/Down, Two-Way Pager System MAX769
Configuration
VIEW
PGND RSIN FILT SYNC BATT REG1
MAX769
NICD R2IN REG2 REG3 DR2IN DRGND AGND
QSOP
_Package Information
QSOP.EPS

NUAL UATION SHEET EVAL FOLLO 3-Cell, Step-Up/Down, Two-Way Pager

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