System ACEMPM Solution DS087 (v1.2) June 2002 Advance Produc
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System ACEMPM Solution
DS087 (v1.2) June 2002
Advance Product Specification
Summary
System level, high capacity, pre-configured solution VirtexSeries FPGAs, Virtex-II Series Platform FPGAs, SpartanFPGAs Industry standard Flash memory combined with Xilinx controller technology single package Effortless density migration: XCCACEM16-BG388I Megabit (Mb)) XCCACEM32-BG388I XCCACEM64-BG388I densities available 388-pin Ball Grid Array package I/O: 1.8V, 2.5V, 3.3V Configuration rates second (Mb/s) Flexible configuration solution: SelectMAP (control four FPGAs) Slave-Serial Concurrent Slave-Serial eight separate chains) Patented compression technology compression) JTAG interface allows: Access standard Flash memory Boundary Scan testing Native interface standard Flash memory provided for: External parallel programming Processor access unused Flash memory locations Supports eight separate design sets (selectable mode pins JTAG), enabling systems reconfigure FPGAs different functions Compatible with IEEE Standard 1532 User-friendly software format program bitstreams into standard Flash patented Flash programming engine Internet Reconfigurable Logic (IRL) upgradeable system
Description
System Multi-Package Module (MPM) solution addresses need space-efficient, pre-engineered, high-density configuration solution multiple FPGA systems. System technology ground-breaking in-system programmable configuration solution that provides substantial savings development effort cost over traditional PROM embedded solutions high capacity FPGA systems. shown Figure System solution multi-package module that includes System controller, configuration PROM, Flash Memory. System four major interfaces. (See Figure boundary scan JTAG interface provided boundary scan test boundary-scan-based Flash memory programming. system control interface provides input system clock, design selection pins, system configuration control signals, system configuration status signals. native Flash memory interface provides direct read write access Flash memory unit. target FPGA interface provides signals configure target FPGAs Slave-Serial, concurrent Slave-Serial, SelectMAP configuration modes. Separate power pins provide voltage compatibility control target FPGA configuration interface system control/status interface. Figure complete view components schematic signals System MPM.
2002 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
DS087 (v1.2) June 2002 Advance Product Specification
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System ACEMPM Solution
16/32/64 Mbit Flash Memory Metal Package: TSOP Dimensions: PROM XC18V01 Package: VQ44 Dimensions: Module Virtex XCV50E Configuration Controller Package: CS144 Dimensions:
System BG388 Complete Assembly Dimensions:
DS087_01_081501
Figure System Assembly
System
Boundary Scan Interface System Control Interface
XCV50E Configuration Controller
PROM
Slave-Serial SelectMAP
Target FPGA Interface
Native Flash Memory
Flash Memory
ds087_02_091001
Figure System Interfaces
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DS087 (v1.2) June 2002 Advance Product Specification
System ACEMPM Solution
System
RESET 4.7k 3.3v
XCV50E
4.7k 3.3v
XC18V01
OE/Reset DEVRDY FCMRESET SYSRESET SYSCLK BITSTRSEL[0-2] STATUS[0-3] CFG_MODE[0-2] CFG_CLK CFG_BUSY CFG_INIT CFG_DONE CFG_PROG CFG_WRITE CFG_CS[0-3] CFG_DATA[0-7]
Flash
RESET FLASH_IO_LEVEL* /BYTE A0-A21 DQ0-DQ15 ACC/WP RY/BY
RESET A0-A21 DQ0-DQ15 RY/BY FCM_ENABLE SYSRESET CCLK INIT DONE PROGRAM
A0-A21 DQ0-DQ15 RY/BY FCM_ENABLE FLASH_VCCO CFG_VCCO CTRL_VCCO VCCO VCCO
SYSCLK BITSTRSEL[0-2] STATUS[0-3] CFG_MODE[0-2] CFG_CLK CFG_BUSY CFG_INIT CFG_DONE VCCO 2,3,4,5 CFG_PROG CFG_WRITE CFG_CS[0-3]
CFG_DATA[0-7] XCCACEM64 only; XCCACEM32 XCCACEM64 only. XCCACEM64; BYTE XCCACEM16 XCCACE32.
XCCACEM16 XCCACEM32 only. XCCACEM64 only. XCCACEM64; ACC/WP XCCACEM32. apply ACC/WP. apply RESET.
DS087_03_091701
Figure System schematic
DS087 (v1.2) June 2002 Advance Product Specification
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System ACEMPM Solution
Descriptions
This section provides native Flash interface, Boundary Scan, target FPGA configuration pinout information. with restrictions. Note Table descriptions restrictions.
Notes: native Flash memory interface pins connected System controller (except where explicitly noted description). FCM_ENABLE must held externally access Flash memory without contention with System controller.
Native Flash Interface Pins
native Flash memory pins routed pins System ball-grid-array. Thus, Flash memory available system direct read write access Table Native Flash Memory Interface Pins Name A0-A21 DQ0-DQ15 RESET Type
Description Flash memory address bus. exists XCCACEM64 only. exists XCCACEM32 XCCACEM64 only. Flash memory data bus. DQ15 becomes XCCACEM16 XCCACEM32 when BYTE mode active. Flash memory hardware reset. When asserted, Flash operations immediately terminated Flash reset read mode. When RESET held High, Flash memory into standby mode. apply RESET pin. RESET connected System controller that maximum tolerance Flash memory chip enable. When RESET held High, Flash memory into standby mode. Flash memory output enable. Flash memory write enable. Flash memory ready/busy signal. Open-drain output. When Low, RD/BY signal indicates that Flash actively erasing, programming, resetting. XCCACEM16 XCCACEM32 only. Flash memory hardware write protect. Flash memory accelerated mode pin. apply XCCACEM32 WP/ACC pin. XCCACEM32 WP/ACC connected System controller that maximum tolerance XCCACEM64 independent rest System used Flash memory into accelerated program operation. Flash memory XCCACEM64 only. This must connected 3.3V compatibility with System controller. Flash memory byte-wide data mode. XCCACEM16 XCCACEM32 only. This must connected 3.3V compatibility with System controller thus only 16-bit, word mode available accessing Flash memory system.
RY/BY
Output
Input
FLASH_IO_LEVEL BYTE
Input Input
Boundary Scan Pins
System controller (Virtex-E XCV50E) System controller PROM (XC18V01) both IEEE Standard 1149.1 compatible devices. System connects these devices into internal scan chain comprised XC18V01 device followed XCV50E device. internal scan chain accessible through boundary scan test access port (TAP) BG388 package. Table
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DS087 (v1.2) June 2002 Advance Product Specification
System ACEMPM Solution
Table IEEE 1149.1 Boundary Scan Pins Name Type Input Description IEEE 1149.1 test clock pin. System connected XCV50E XC18V01 pins. default, XCV50E internal pull-up resistor pin. IEEE 1149.1 test mode select pin. System connected XCV50E XC18V01 pins which have internal pull-up resistors. IEEE 1149.1 test data input pin. System connected XC18V01 which internal pull-up resistor. IEEE 1149.1 test data output pin. System connected XCV50E which default internal pull-up resistor.
Input
Input Output
Target FPGA Configuration Pins
Table provides target FPGA configuration pins. Table Target FPGA Configuration Pins Name CFG_DATA[0] Type Output Description Slave-Serial configuration mode, CFG_DATA[0] serial data signal Serial-Slave Chain connected first FPGA Slave-Serial Chain Slave-SelectMAP configuration mode, CFG_DATA[0] data SelectMAP connected target FPGAs. Slave-Serial configuration mode, CFG_DATA[1] serial data signal Serial-Slave Chain connected first FPGA Slave-Serial Chain Slave-SelectMAP configuration mode, CFG_DATA[1] data SelectMAP connected target FPGAs. Slave-Serial configuration mode, CFG_DATA[2] serial data signal Serial-Slave Chain connected first FPGA Slave-Serial Chain Slave-SelectMAP configuration mode, CFG_DATA[2] data SelectMAP connected target FPGAs. Slave-Serial configuration mode, CFG_DATA[3] serial data signal Serial-Slave Chain connected first FPGA Slave-Serial Chain Slave-SelectMAP configuration mode, CFG_DATA[3] data SelectMAP connected target FPGAs. Slave-Serial configuration mode, CFG_DATA[4] serial data signal Serial-Slave Chain connected first FPGA Slave-Serial Chain Slave-SelectMAP configuration mode, CFG_DATA[4] data SelectMAP connected target FPGAs. Slave-Serial configuration mode, CFG_DATA[5] serial data signal Serial-Slave Chain connected first FPGA Slave-Serial Chain Slave-SelectMAP configuration mode, CFG_DATA[5] data SelectMAP connected target FPGAs.
CFG_DATA[1]
Output
CFG_DATA[2]
Output
CFG_DATA[3]
Output
CFG_DATA[4]
Output
CFG_DATA[5]
Output
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System ACEMPM Solution Table Target FPGA Configuration Pins (Continued) Name CFG_DATA[6] Type Output Description Slave-Serial configuration mode, CFG_DATA[6] serial data signal Serial-Slave Chain connected first FPGA Slave-Serial Chain Slave-SelectMAP configuration mode, CFG_DATA[6] data SelectMAP connected target FPGAs. Slave-Serial configuration mode, CFG_DATA[7] serial data signal Serial-Slave Chain connected first FPGA Slave-Serial Chain Slave-SelectMAP configuration mode, CFG_DATA[7] data SelectMAP connected target FPGAs. CFG_MODE pins configuration mode target FPGAs. Connect CFG_MODE[0] target FPGAs. CFG_MODE pins configuration mode target FPGAs. Connect CFG_MODE[1] target FPGAs. CFG_MODE pins configuration mode target FPGAs. Connect CFG_MODE[2] target FPGAs. CFG_CCLK configuration clock source target FPGAs. CFG_CCLK derived from SYSCLK. CFG_CCLK frequency half SYSCLK frequency. Connect CFG_CCLK CCLK target FPGAs. CFG_PROG pulsed beginning configuration download reset configuration state target FPGAs. CFG_PROG connected PROG_B target FPGAs. Target FPGA INIT monitor pin. start configuration process, System controller waits INIT High before initiating delivery configuration data through CFG_DATA pins. CFG_INIT connected INIT target FPGAs. When CFG_BUSY High, CFG_DATA outputs held. target FPGA configuration mode Slave-SelectMAP CFG_CCLK greater than MHz, connect CFG_BUSY BUSY target FPGAs. Otherwise, pull-down CFG_BUSY GND. CFG_DONE monitors DONE status target FPGAs. Connect CFG_DONE DONE target FPGAs. DONE must pulled High with external 330- pull-up resistor. BitGen option DriveDONE should left default "NO" setting when generating bitstreams Xilinx FPGAs. Slave-SelectMAP write-enable pin. Connect CFG_WRITE RDWR_B target FPGAs. Slave-SelectMAP chip-enable target FPGA Connect CFG_CS[0] CS_B target FPGA Slave-SelectMAP chip-enable target FPGA Connect CFG_CS[1] CS_B target FPGA Slave-SelectMAP chip-enable target FPGA Connect CFG_CS[2] CS_B target FPGA Slave-SelectMAP chip-enable target FPGA Connect CFG_CS[3] CS_B target FPGA
CFG_DATA[7]
Output
CFG_MODE[0] CFG_MODE[1] CFG_MODE[2] CFG_CCLK
Output Output Output Output
CFG_PROG
Output
CFG_INIT
Input
CFG_BUSY
Input
CFG_DONE
Input
CFG_WRITE CFG_CS[0] CFG_CS[1] CFG_CS[2] CFG_CS[3]
Output Output Output Output Output
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DS087 (v1.2) June 2002 Advance Product Specification
System ACEMPM Solution
System Control Status Pins
Table provides system control status pins. Table System Control Status Pins Name FCM_ENABLE Type Input Description System controller enable. When this held Low, System controller (XCV50E) pins tied Flash memory 3-stated allowing external peripherals access Flash memory without contention. System FPGA reset pin. FCMRESET connected XCV50E PROGRAM pin. Applying pulse FCMRESET resets XCV50E forces XCV50E reconfigure itself from XC18V01 PROM. (The XCV50E automatically configures itself from XC18V01 PROM power-up.) System FPGA DONE pin. DEVRDY connected XCV50E DONE pin. When DEVRDY High, XCV50E configured ready operation. SYSCLK system clock input System control logic. Hold SYSRESET High least SYSCLK cycles reset System control logic. Upon release from reset condition, System initiates download procedure target FPGAs. BITSTRSEL pins determine which eight configuration data streams download target FPGA. STATUS pins indicate status System control logic.
FCMRESET
Input
DEVRDY
Output
SYSCLK SYSRESET
Input Input
BITSTRSEL[2-0] STATUS[3-0]
Input Output
Power Ground Pins
System requires least power supplies: 1.8V supplies power System configuration controller XCV50E) core; 3.3V supplies power Flash memory configuration controller PROM XC18V01). Additional power supplies required output voltage compatibility pins: FLASH_VCCO, CFG_VCCO, CTRL_VCCO. Figure Table description System power pins.
System VCCint1 VCCint2 FLASH_VCCO
1.8v 3.3v
XILINX Virtex-II
CTRL_VCCO Compatible with Control Circuits Control Circuits CTRL_VCCO BITSTRSEL[0-2] SYSCLK SYSRESET System Signals Control Signals
CFG_VCCO Compatible with Target FPGAs
CFG_VCCO Configuration Signals Slave-Serial Slave-SelectMAP
XILINX XILINX Spartan-II Virtex-II
DS087_04_090601
Figure Power Pins
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System ACEMPM Solution
Table Power Ground Pins Name VCCint1 Type Power Description 1.8V power supply pins Virtex-E XCV50E configuration controller core. 1.8V power supply should rise prior simultaneously FLASH_VCCO, CTRL_VCCO, CFG_VCCO power supplies.Otherwise, XCV50E device might draw excessive current. 3.3V power supply pins Flash memory XC18V01 PROM. 3.3V power supply banks connecting Virtex-E XCV50E controller Flash memory. Configurable power supply banks target FPGA configuration interface. Connect this power voltage that compatible with target FPGA configuration pins. Configurable power supply banks system interface. Connect this power voltage that compatible with system control status monitor signals. Ground.
VCCint2 FLASH_VCCO CFG_VCCO
Power Power Power
CTRL_VCCO
Power
Ground
Pinout
Table provides System pinout. Unlisted sites connects. Table System Pinout Name XCCACEM16-BG388I XCCACEM32-BG388I XCCACEM64-BG388I
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System ACEMPM Solution
Table System Pinout (Continued) Name DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 RESET RY/BY FLASH_IO_LEVEL FCM_ENABLE FCMRESET DEVRDY SYSCLK SYSRESET XCCACEM16-BG388I AD26 AC25 AB26 AA26 AD25 AC26 AB25 AA25 AE23 AE26 AD26 AC25 AB26 AA26 AD25 AC26 AB25 AA25 AE23 AE26 XCCACEM32-BG388I XCCACEM64-BG388I AD26 AC25 AB26 AA26 AD25 AC26 AB25 AA25 AE23 AE26
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System ACEMPM Solution Table System Pinout (Continued) Name BITSTRSEL[0] BITSTRSEL[1] BITSTRSEL[2] STATUS[0] STATUS[1] STATUS[2] STATUS[3] CFG_DATA[0] CFG_DATA[1] CFG_DATA[2] CFG_DATA[3] CFG_DATA[4] CFG_DATA[5] CFG_DATA[6] CFG_DATA[7] CFG_MODE[0] CFG_MODE[1] CFG_MODE[2] CFG_CCLK CFG_BUSY CFG_INIT CFG_PROG CFG_DONE CFG_WRITE CFG_CS[0] CFG_CS[1] CFG_CS[2] CFG_CS[3] CTRL_VCCO CFG_VCCO FLASH_VCCO VCCint1 XCCACEM16-BG388I A16, B14, J26, L26, AF13, C10, D13, D14, A16, B14, J26, L26, AF13, C10, D13, D14, XCCACEM32-BG388I A16, B14, J26, L26, AF13, C10, D13, D14, XCCACEM64-BG388I
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System ACEMPM Solution
Table System Pinout (Continued) Name VCCint2 XCCACEM16-BG388I AA23, AB4, AB23, AC4, AC11, AC12, AC13, AC18, AC19, AC20, D17, D18, D21, D22, D23, E23, H23, J23, N23, P23, V26, A26, AA3, AB24, AD16, AD22, AE2, AE11, AE12, AE18, AE22, AE25, AF1, AF26, B15, B19, B22, B25, D10, D11, F23, H25, K23, L11, L12, L13, L14, L15, L16, M11, M12, M13, M14, M15, M16, M23, N11, N12, N13, N14, N15, N16, P11, P12, P13, P14, P15, P16, R11, R12, R13, R14, R15, R16, R23, T11, T12, T13, T14, T15, T16, T23, XCCACEM32-BG388I AA23, AB4, AB23, AC4, AC11, AC12, AC13, AC18, AC19, AC20, D17, D18, D21, D22, D23, E23, H23, J23, N23, P23, V26, A26, AA3, AB24, AD16, AD22, AE2, AE11, AE12, AE18, AE22, AE25, AF1, AF26, B15, B19, B22, B25, D10, D11, F23, H25, K23, L11, L12, L13, L14, L15, L16, M11, M12, M13, M14, M15, M16, M23, N11, N12, N13, N14, N15, N16, P11, P12, P13, P14, P15, P16, R11, R12, R13, R14, R15, R16, R23, T11, T12, T13, T14, T15, T16, T23, XCCACEM64-BG388I AA23, AB4, AB23, AC4, AC11, AC12, AC13, AC18, AC19, AC20, D17, D18, D21, D22, D23, E23, H23, J23, N23, P23, V26, A26, AA3, AB24, AD16, AD22, AE2, AE11, AE12, AE18, AE22, AE25, AF1, AF26, B15, B19, B22, B25, D10, D11, F23, H25, K23, L11, L12, L13, L14, L15, L16, M11, M12, M13, M14, M15, M16, M23, N11, N12, N13, N14, N15, N16, P11, P12, P13, P14, P15, P16, R11, R12, R13, R14, R15, R16, R23, T11, T12, T13, T14, T15, T16, T23,
Configuration Overview
System engineered high-speed configuration high-density FPGAs. Multiple configuration modes supported target FPGAs including Concurrent Slave-Serial mode, Slave-SelectMAP mode, Slave-Parallel mode. System handles storage eight separate configuration data sets. Each data optionally compressed reduce overall storage requirements. default data automatically downloaded target FPGAs system power-up. eight data sets selected reconfigure target FPGAs time during system operation.
Configuration Modes
System supports high-speed FPGA configuration Slave-Serial Slave-SelectMAP configuration modes. System solution pre-engineered storage delivery system with direct support high-density high-speed configuration needs Virtex-II family. example, System configure Virtex-II XC2V6000, which requires 19,759,968 configuration bits, Slave-Serial mode milliseconds Slave-SelectMAP mode milliseconds. fact, System configure XC2V6000 devices concurrently Slave-Serial mode milliseconds.See Table maximum configuration rates. Table FPGA configuration compatibility cross-reference. Table System FPGA configuration signal cross-reference.
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System ACEMPM Solution
Table Maximum Configuration Rates Maximum Configuration Clock (CFG_CCLK) Rate SYSCLK Rate) Average Configuration Clock Rate SYSCLK Rate)
Configuration Mode Slave-SelectMAP Slave-Serial Concurrent Slave-Serial Chains Concurrent Slave-Serial Chains Concurrent Slave-Serial Chains
Maximum System Clock Rate (SYSCLK)
Maximum Average Combined Configuration Rate Mb/s Mb/s Mb/s Mb/s chain) Mb/s Mb/s chain) Mb/s Mb/s chain)
Table FPGA Configuration Compatibility Cross-Reference General Description Serial Configuration Mode Parallel Configuration Mode Clock Source External Data Path 1-bit Delivery Method Cascade through FPGAs daisy-chain style Chip-selected device configuration data Virtex-II Slave-Serial Virtex Virtex-E Slave-Serial Spartan-II Slave-Serial
External
8-bits
SlaveSelectMAP
SelectMAP
Slave-Parallel
Table System FPGA Configuration Signal Cross-Reference FPGA Configuration Signal Configuration Mode Configuration Clock Configuration Data System CFG_MODE[2:0] CFG_CLK CFG_DATA[7:0] Virtex-II CCLK DIN/D0 PROG_B INIT_B BUSY Virtex/ Virtex-E CCLK DIN/D0 PROGRAM INIT BUSY Spartan-II CCLK DIN/D0 PROGRAM INIT BUSY
Configuration Reset Configuration Configuration Busy
CFG_PROG CFG_INIT CFG_BUSY
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System ACEMPM Solution
Table System FPGA Configuration Signal Cross-Reference FPGA Configuration Signal Configuration Done SelectMAP/SlaveParallel Read/Write Signal SelectMAP/SlaveParallel Chip Select Signal System CFG_DONE CFG_WRITE Virtex-II DONE RDWR_B Virtex/ Virtex-E DONE WRITE Spartan-II DONE WRITE
CFG_CS[3:0]
CS_B
Slave-Serial
Similar Xilinx PROM solution, System single package solution that supports configuration single, cascaded chain Slave-Serial FPGAs. With maximum configuration clock rate MHz, System twice fast nearest Xilinx PROM configuration solution Slave-Serial mode. System additional support concurrently configuring multiple chains Slave-Serial FPGAs. Multiple data output pins System concurrently supply bitstreams eight Slave-Serial FPGA chains. Although each Slave-Serial chain maximum configuration clock rate MHz, maximum delivery rate Mb/s maintained across concurrent Slave-Serial FPGA chains cumulative maximum Mb/s. (152 Mb/s maximum read rate from Flash memory System MPM.) Concurrent Slave-Serial configuration mode, bitstreams individual Slave-Serial chains interleaved optimized concurrent configuration two, four, eight Slave-Serial FPGA chains. Configuration time storage requirements optimal when data stream sizes equivalent across concurrent Slave-Serial FPGA chains. connectivity between System Slave-Serial FPGA chain similar connectivity between Xilinx PROM Slave-Serial FPGA chain. configuration signals between Concurrent Slave-Serial FPGA chains common except that data first chain originates from System CFG_DATA[0] pin, data second chain originates from System CFG_DATA[1] pin, etc. Figure schematic Slave-Serial configuration signal connections, Table list Slave-Serial configuration signals. voltage compatibility System configuration interface configurable CFG_VCCO pin. CFG_VCCO should connected voltage level that compatible with target FPGAs. Typically, CFG_VCCO connected either 3.3V Consult target FPGA data sheet appropriate configuration signal voltage level. Identical configuration multiple target FPGAs from bitstream achieved through appropriate configuration signal connections. Figure shows example FPGAs that identically configured from single bitstream. Table provides Slave-Serial configuration signals.
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System ACEMPM Solution
Configuration Modes
SelectMAP
Chip Selects Devices
Flash Memory
System Configuration Controller Mb/s
SelectMAP
FPGA
FPGA
FPGA
FPGA
Slave-Serial
Flash Memory
System Mb/s Serial data stream Configuration Controller
FPGA
FPGA
FPGA
Concurrent Slave-Serial
Flash Memory
System Configuration Controller
Mb/s Serial data stream chains 66Mb/s chain Serial data stream
FPGA FPGA
FPGA
FPGA
FPGA
FPGA
ds087_05_091701
Figure System Configuration Modes
CFG_VCCO
System
3.3v FLASH_IO_LEVEL FCM_ENABLE Source BITSTRSEL[0-2] SYSCLK BITSTRSEL[0-2] STATUS[0-3] SYSRESET CFG_VCCO CFG_DATA[0-7] CFG_MODE[2] CFG_MODE[1] CFG_MODE[0] CFG_CCLK CFG_INIT CFG_DONE CFG_PROG BUSY 4.7k
CFG_DATA[0]
4.7k
FPGA
(Chain Device
FPGA
(Chain Device
CCLK INIT_B DONE PROG_B
DOUT
CCLK INIT_B DONE PROG_B
DOUT
Chain0 Cascaded FPGAs
CFG_DATA[1-7] Concurrent Slave-Serial FPGA Chains (1-7) Supply voltage CFG_VCCO that compatible with FPGA configuration pins. Only XCCACEM16; Combined ACC/WP XCCACEM32; Separate XCCACEM64. CFG_DATA[0] systems with slave-serial chain; CFG_DATA[0-1] systems with concurrent slave-serial chains; CFG_DATA[0-3] systems with four concurrent slave-serial chains; CFG_DATA[0-7] systems with eight concurrent slave-serial chains.
DS087_05_091201
Figure Slave-Serial Configuration Mode
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System ACEMPM Solution
CFG_VCCO
System
3.3V FLASH_IO_LEVEL FCM_ENABLE Source BITSTRSEL[0-2] SYSCLK BITSTRSEL[0-2] STATUS[0-3] SYSRESET
CFG_VCCO CFG_DATA[0] CFG_MODE[2] CFG_MODE[1] CFG_MODE[0] CFG_CCLK CFG_INIT CFG_DONE CFG_PROG BUSY
CFG_DATA[0]
FPGA
CFG_DATA[0]
FPGA
CCLK INIT_B DONE PROG_B
CCLK INIT_B DONE PROG_B Identical FPGAs
Supply voltage CFG_VCCO that compatible with FPGA configuration pins. Combined ACC/WP XCCACEM32; Separate XCCACEM64.
DS087_07_091701
Figure Example Slave-Serial Configuration Identically Configured Xilinx FPGAs
Table Slave-Serial FPGA Configuration Signals System CFG_MODE[0] CFG_MODE[1] CFG_MODE[2] CFG_CCLK CFG_PROG CFG_INIT CFG_DONE CFG_DATA[0] CFG_DATA[1] CFG_DATA[2] CFG_DATA[3] Single Slave-Serial Chain FPGAs FPGAs FPGAs CCLK FPGAs PROG_B FPGAs INIT_B FPGAs DONE FPGAs first FPGA Chain Slave-Serial Chains FPGAs FPGAs FPGAs CCLK FPGAs PROG_B FPGAs INIT_B FPGAs DONE FPGAs first FPGA Chain first FPGA Chain Four Slave-Serial Chains FPGAs FPGAs FPGAs CCLK FPGAs PROG_B FPGAs INIT_B FPGAs DONE FPGAs first FPGA Chain first FPGA Chain first FPGA Chain first FPGA Chain Eight Slave-Serial Chains FPGAs FPGAs FPGAs CCLK FPGAs PROG_B FPGAs INIT_B FPGAs DONE FPGAs first FPGA Chain first FPGA Chain first FPGA Chain first FPGA Chain
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System ACEMPM Solution Table Slave-Serial FPGA Configuration Signals (Continued) System CFG_DATA[4] CFG_DATA[5] CFG_DATA[6] CFG_DATA[7] Single Slave-Serial Chain Slave-Serial Chains Four Slave-Serial Chains Eight Slave-Serial Chains first FPGA Chain first FPGA Chain first FPGA Chain first FPGA Chain
Although Table lists configuration signals only one, two, four, eight Slave-Serial chain systems, number Slave-Serial chains from eight supported System software. System software assigns data streams each Slave-Serial chain starting from CFG_DATA[0] CFG_DATA[N-1] where number Slave-Serial chains system.
Slave-SelectMAP/Slave-Parallel
System conveniently supports high-speed, sequential configuration four Xilinx FPGAs 8-bit-wide SelectMAP configuration four Spartan-II devices 8-bit-wide Slave-Parallel bus. System generates maximum configuration clock rate MHz. maximum delivery rate Mb/s. (152 Mb/s maximum read rate from Flash memory System MPM.)
connectivity between System FPGAs SelectMAP similar connectivity between Xilinx PROM Slave-SelectMAP FPGA with addition CFG_WRITE separate CFG_CS (chip select) signals. configuration signals from System common target FPGAs SelectMAP bus, except that CS_B signal first FPGA must connected System CFG_CS[0] pin, CS_B signal second FPGA must connected System CFG_CS[1] pin, etc. Figure schematic diagram Slave-SelectMAP configuration connections, Table list Slave-SelectMAP connections four target FPGAs. Spartan-II Slave-Parallel mode same structure protocol Slave-SelectMAP mode. Therefore, Slave-SelectMAP figure table apply Spartan-II Slave-Parallel mode with appropriate signal name translations noted Table
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System ACEMPM Solution
CFG_VCCO
System
FPGA
(CFG_CS[0])
FPGA
(CFG_CS[1])
3.3V FLASH_IO_LEVEL FCM_ENABLE Source BITSTRSEL[0-2] SYSCLK BITSTRSEL[0-2] STATUS[0-3] SYSRESET CFG_VCCO CFG_DATA[7:0] CFG_MODE[2:0] CFG_CCLK CFG_INIT CFG_DONE CFG_PROG CFG_WRITE BUSY CFG_CS[0-3]
CFG_CS[0] CS_B D[7:0] M[2:0] CCLK INIT_B DONE PROG_B RDWR_B BUSY
CFG_CS[1] CS_B D[7:0] M[2:0] CCLK INIT_B DONE PROG_B RDWR_B BUSY
SelectMAP FPGAs (2-3)
Supply voltage CFG_VCCO that compatible with FPGA configuration pins. Combined ACC/WP XCCACEM32; Separate XCCACEM64. CFG_CS[0] systems with slave-SelectMAP FPGA CFG_CS[0-1] systems with slaveSelectMAP FPGAs; CFG_CS[0-2] systems with three slave-SelectMAP FPGAs; CFG_CS[0-3] systems with four slave-SelectMAP FPGAs.
ds087_08_91001
Figure Slave-SelectMAP Configuration Mode
Table Slave-SelectMAP FPGA Configuration Signals System CFG_MODE[0] CFG_MODE[1] CFG_MODE[2] CFG_CCLK CFG_PROG CFG_INIT CFG_BUSY CFG_DONE CFG_DATA[0-7] CFG_WRITE CFG_CS[0] CFG_CS[1] CFG_CS[2] CFG_CS[3] CCLK PROG_B INIT_B BUSY DONE D[0-7] RDWR_B CS_B CS_B CS_B CS_B FPGA CCLK PROG_B INIT_B BUSY DONE D[0-7] RDWR_B FPGA CCLK PROG_B INIT_B BUSY DONE D[0-7] RDWR_B FPGA CCLK PROG_B INIT_B BUSY DONE D[0-7] RDWR_B FPGA
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System ACEMPM Solution Identical configuration multiple target FPGAs from single bitstream achieved through appropriate connections. Figure example FPGAs that simultaneously configured from single bitstream.
CFG_VCCO
System software assigns bitstreams target FPGAs order, starting from CFG_CS[0] through CFG_CS[N-1] where number Slave-SelectMAP devices system. four devices.
System
FPGA
FPGA
3.3V FLASH_IO_LEVEL FCM_ENABLE Source BITSTRSEL[0-2] SYSCLK BITSTRSEL [0-2] STATUS[0-3] SYSRESET Identical SelectMAP FPGAs CFG_VCCO CFG_DATA[7:0] CFG_MODE[2:0] CFG_CCLK CFG_INIT CFG_DONE CFG_PROG CFG_WRITE BUSY CFG_CS[0] CFG_CS[0] CS_B D[7:0] M[2:0] CCLK INIT_B DONE PROG_B RDWR_B BUSY CFG_CS[0] CS_B D[7:0] M[2:0] CCLK INIT_B DONE PROG_B RDWR_B BUSY
Supply voltage CFG_VCCO that compatible with FPGA configuration pins. Combined ACC/WP XCCACEM32; Separate XCCACEM64.
DS087_09_091001
Figure Example Slave-SelectMAP Configuration Identically Configured FPGAs
Configuration Data
configuration data sets target FPGAs stored standard, high-density Flash memory unit System MPM.
System product family offers data storage capacity Flash memory vendor's data sheets additional information about Flash memory unit System MPM. Table Flash memory data sheet references.
Data Storage
System integrates standard Flash memory unit storage configuration data sets. Table Table Flash Memory Storage System XCCACEM16-BG388I XCCACEM32-BG388I XCCACEM64-BG388I Flash Device Am29LV160DT Am29LV320DT Am29LV641DH Flash Density Flash Speed Grade Flash Organization 16-bit 8-bit) 16-bit 8-bit) 16-bit
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Table Flash Memory Data Sheet References System XCCACEM16-BG388I XCCACEM32-BG388I XCCACEM64-BG388I Flash Device Am29LV160DT Am29LV320DT Am29LV641DH Flash Data Sheet
Data Organization
Flash memory data array begins with data directory. There eight directory entries that correspond binary value BITSTRSEL[2-0] setting. Each directory entry bytes long. main elements directory entry are: configuration processing options data set, starting address actual data location, length data bytes. Figure details System directory structure. System software composes entire Flash memory image automatically calculates directory information from given data streams user selected options.
Flash Memory Array Data Directory
Configuration Data Compression
System software gives option compress data streams percent. System data stream stored compressed format within System MPM. System decompresses data streams real time delivery target FPGAs. compression performance data-dependent. Encrypted Virtex-II bitstreams compressible.
Configuration Data Security
Data security available Virtex-II bitstreams through standard Virtex-II encryption technology.
ENTRY 15(MSB) ENTRY 0(LSB)
BITSTRSEL[2:0] "011" ENTRY ENTRY ENTRY ENTRY ENTRY ENTRY
PROCESSING OPTIONS bits) START ADDR (lower bits) START ADDR (upper bits) Data BYTE SIZE (lower bits) Data BYTE SIZE (upper bits) Reserved 16-bit word Reserved 16-bit word Reserved 16-bit word
0388h
Start Data
DS087_09_081501
Figure Flash Memory Organization
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System ACEMPM Solution
Configuration Sequence
System configuration sequence automatically initiated power-up initial system configuration triggered later during system operation using SYSRESET signal reconfigure system. configuration sequence follows: Sample BITSTRSEL[2:0] pins determine data download. Pulse CFG_PROGRAM clear target FPGAs prepare them configuration. Wait CFG_INIT High which indicates target FPGAs ready receive data. Table Control Configuration Timing Symbol TSYSRESET TSSEL THSEL Description SYSRESET pulse BITSTRSEL[2:0] setup time SYSCLK BITSTRSEL[2:0] hold time from SYSCLK Units SYSCLK cycles Find data from data directory structure Flash memory. Deliver data target FPGAs according configuration processing options specified directory. Check DONE High indicating successful configuration.
Configuration Control Timing
Table shows configuration control timing details.
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Configuration Data Selection
System provides opportunity store eight separate configuration data sets target FPGAs system. System BITSTRSEL[0-2] pins determine which eight possible data sets download. data downloaded configure target FPGAs automatically system power-up, data downloaded reconfigure target FPGAs upon activation System SYSRESET pin. Table beginning configuration sequence (initiated power-up SYSRESET pin), System samples BITSTRSEL[2-0] pins determine data download. Then, System downloads data target FPGAs. Table Configuration Data Selection BITSTRSEL[2:0] Settings BITSTRSEL[2:0] Selected Data Data Data Data Data Data Data Data Data
Configuration Status
System reports status through four status pins (STATUS[3-0]). status System available times. Table definitions status signals. Table Status Definitions
STATUS STATUS STATUS STATUS
Status Definition Reset system ready Successful Slave-Serial SlaveSelectMAP configuration Configuration error (CFG_DONE High) Decompression error Invalid controller state (internal error) Invalid configuration data blank flash memory Reserved wait state;. JTAG Flash commands (erase, blank-check, program, verify) issued.
System hardwired power-up configuration. shown example Figure System actively controlled monitored microcontroller.
Microprocessor Peripheral Interface CTRL_SYSRESET CTRL_ BITSTRSEL[0-2] CTRL_ STATUS[0-3]
System
SYSRESET BITSTRSEL[0-2] STATUS[0-3]
Table provides corrective action status errors.
DS087_12_091001
Figure Example Microprocessor-Based Data Selection, Configuration Control, Configuration Status Monitor
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Table Corrective Action Status Errors Status Error Configuration Error (CFG_DONE High) Decompression Error Invalid Controller State Invalid Configuration Data Blank Flash Memory Corrective Action Check that target FPGA DONE pins connected CFG_DONE with external 330- pull-up resistor. Perform SYSRESET sequence re-initialize System controller restart configuration. Perform SYSRESET sequence re-initialize System controller restart configuration Erase reprogram Flash memory. Perform SYSRESET sequence re-initialize System controller restart configuration. Table Typical Flash Memory Programming Methods (Continued) Programming Method/Tool Third-party programmers Microprocessor Interface Native Flash Interface Boundary Scan Native Flash Interface Unit Location Off-board Phase(s) Preproduction Remote Upgrade
Programming Flash Memory
System provides interfaces accessing internal Flash memory unit: native Flash memory interface Boundary Scan port. native Flash memory interface provides direct access Flash memory pins reading writing. Boundary Scan port provides indirect access Flash memory pins Boundary Scan logic System controller (XCV50E), whose Boundary Scannable pins connected Flash memory pins. Table Drive FCM_ENABLE before using native Flash memory interface.
In-system
System Software
System software provides direct programming support Xilinx Parallel Cable System Boundary Scan port. System software takes advantage Flash memory programming engine that integrated into System controller's Boundary Scan logic. Table Typical Flash Memory Programming Methods Programming Method/Tool System software Boundary Scan tools Automatic Test Equipment Interface Boundary Scan Boundary Scan Native Flash Interface Unit Location In-system Phase(s) Prototype development debug Development test production Test production
Boundary Scan Tools
System software generate serial vector format (SVF) files System operations. These files executed through Boundary Scan test tool.
Automatic Test Equipment
Automatic test equipment (ATE) vendors support in-system Flash memory programming. System MPM's native Flash interface provides virtual access every Flash memory ATE. During programming operation, must hold FCM_ENABLE signal System ensure that there will contention between System controller native Flash interface signals. Test access points required native Flash memory interface signals System FCM_ENABLE signal.
In-system
Third-Party Programmers
Third-party programmer vendors support stand-alone programming System through native Flash memory interface. System programming times should equivalent programming times stand-alone Flash memory units.
In-system
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Embedded Microprocessor
embedded microprocessor used remotely upgrade System data sets. embedded microprocessor program Flash memory System using native Flash memory interface directly control Flash memory four-wire Boundary Scan port. native Flash memory interface provides direct read access, well write access, Flash memory. Flash memory data sheet proper Flash memory programming protocol. FCM_ENABLE signal System must held during external access Flash memory. Otherwise, contention between microprocessor System configuration controller occur. System software generate file programming System Flash memory through System Boundary Scan interface. Xilinx application note (XAPP058) provides reference code solutions programming device through Boundary Scan from file.
Software Support
standard Xilinx design flow followed development FPGA design sets. Xilinx design software packages used develop design from which .bit configuration file(s) generated each target FPGA. Xilinx PROM File Formatter tool then used compile .bit file(s) into single image downloading Slave-Serial chain FPGAs single SelectMAP FPGA. output from Xilinx PROM File Formatter .MCS PROM image. .MCS PROM images that configure target FPGA(s) connected System called design set. System store eight data sets. System software used compile multiple data sets into single Flash memory image. Flash memory image stored .MPM file. .MPM file standard Intel (.MCS) file. assignment each data target FPGA chain SelectMAP device defined within System software. System software also program final Flash memory image into System through Xilinx Parallel Cable III, generate file programming System using alternate, Boundary Scan-based programming method. Details System software described System Technology Software User Guide. Figure shows System software flow.
Xilinx Design Software/Tools
FOUNDATION
Multiple Designs file(s)
ALLIANCE
FOUNDATION
PROM File Formatter
file(s)
File
System Flash Memory
DS087_13_091701
System Software
Figure System Software Flow
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System ACEMPM Solution
IEEE 1149.1 Boundary Scan
Xilinx Virtex-E XCV50E XC18V01 PROMs System support IEEE 1149.1 Boundary Scan. Although Flash memory does support Boundary Scan, signal pins Flash memory BG388 package connected boundary scannable pins XCV50E device (with exception XCCACEM64's pin). Thus, System supports Boundary Scan significant signals System XCV50E's Boundary Scan register. Although XC18V01 supports Boundary Scan register, most signals solely internal System MPM. Signals from XC18V01 device that reach external BG388 sites redundantly tied XCV50E device. Thus, Boundary Scan effectively performed solely with XCV50E Boundary Scan functions. Figure
Boundary Scan Test Requirements
System FCMRESET signal drives XCV50E /PROGRAM pin. active-Low PROGRAM XCV50E device resets XCV50E's Boundary Scan test access port (TAP) controller. FCM_ENABLE signal must driven during Boundary Scan test. Boundary Scan test functionality undefined during System initialization phase. Therefore, boundary scan testing must wait until after initialization phase complete. special System Boundary Scan description language (BSDL) file required proper Boundary Scan test operation with Virtex-E XCV50E device. XCCACEM16_BG388.BSD, XCCACEM32_BG388.BSD, XCCACEM64.BSD files available from Xilinx BSDL website under software support pages
http://www.support.xilinx.com
System
XCV50E Flash
RESET A0-A21*1 DQ0-DQ15 ACC/WP RY/BY RESET A0-A21*1 DQ0-DQ15 RY/BY Boundary Scan Register
XC18V01
ACC*2
Most XC18V01 signals remain inside except status signals shared with XCV50E
XCV50E boundary scan scan most signal pins board test
XCCACEM64 only; XCCACEM32 XCCACEM64 only. ACC/WP XCCACEM32; XCCACEM64 separate pins. RY/BY XCCACEM16 XCCACE32 only. Boundary scan register only conceptually depicted. System BSDL file accurate boundary-scan register information.
ds087_14_091701
Figure System Boundary Scan Mode
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Timing
Figure Boundary Scan timing requirements.
TCKMIN
TMSS TMSH
TDIS TDIH
TDOV
DS087_15_091001
Figure Boundary Scan Timing Diagram
Parameters
Table provides Boundary Scan characteristics. Table Boundary Scan Characteristics Symbol TCKMIN1 TCKMIN2 TMSS TMSH TDIS TDIH TDOV Parameter minimum clock period minimum clock period, Bypass Mode setup time hold time setup time hold time valid delay Units
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Absolute Maximum Ratings
Table provides absolute maximum ratings. Table Absolute Maximum Ratings Symbol
VCCint1 VCCint2 FLASH_VCCO CFG_VCCO CTRL_VCCO
Description 1.8V supply voltage relative 3.3V supply voltage relative Flash interface power supply Configuration interface power supply System interface power supply Input voltage with respect Voltage applied 3-state output. Longest 1.8V supply voltage rise time 1.71 Storage temperature (ambient)
-0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5
Units
VCCint1_r TSTG
Recommended Operating Conditions
Table provides recommended operating conditions. Table Recommended Operating Conditions Symbol VCCint1 VCCint2 Description 1.8V supply voltage relative 3.3.V supply voltage relative Unit
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Quality Reliability Characteristics
Characteristics Over Operating Conditions
Table provides characteristics over operating conditions. Table Characteristics Over Operating Conditions Symbol VDRINT1 ICCINT1Q ICCINT2Q COUT Description Data retention VCCint1 voltage Quiescent VCCINT1 supply current Quiescent VCCINT2 supply current Input leakage current Input capacitance Output capacitance Unit
Input Output Levels Over Operating Conditions
Three primary interfaces (the Boundary Scan interface, system control interface, target FPGA interface) System have level compatibility control pins. Figure Figure FLASH_VCCO controls internal Flash memory interface Boundary Scan interface. FLASH_VCCO must connected 3.3V power supply. Boundary Scan ports (TCK, TMS, TDI, TDO) internal Flash memory interface pins follow 3.3V input output level specification. CTRL_VCCO controls system control interface, CFG_VCCO controls target FPGA interface. input output level specifications system control target FPGA interface pins depend voltage connection CTRL_VCCO CFG_VCCO pins. Table input output level specifications each VCCO voltage level.
Table Input Output Levels Over Operating Conditions VCCO Voltage Level
-0.5 -0.5 -0.5
VIL, 0.7V VCCO
VIH, VCCO
VIH, 1.95
VOL, 0.4V
VOH, VCCO
IOL,
IOH,
Characteristics Over Operating Conditions
Table provides characteristics over operating conditions. Table Characteristics Over Operating Conditions Timing Parameter FSYS TSCL TSCH TSYSRESET TCYC
DS087 (v1.2) June 2002 Advance Product Specification
Description Maximum SYSCLK frequency SYSCLK time SYSCLK High time Minimum SYSRESET pulse time CFG_CCLK period CFG_CCLK time CFG_CCLK High time
Unit SYSCLK cycles
3.75 3.75 66.5
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Quality Reliability Characteristics
Table provides quality reliability characteristics. Table Quality Reliability Characteristics Symbol VESD Description Data retention Program/erase cycles Electrostatic discharge (HBM) (Note million (Note 1500 Unit Years Cycles Volts
Notes: Flash memory data sheet.
System Power-On Power Supply Requirements
System requires supply voltages: 1.8V 3.3V. 1.8V supplies power embedded XCV50E configuration controller core. 3.3V supplies power remaining XCV50E power pins other devices. 3.3V supply must applied after simultaneous 1.8V supply. embedded XCV50E XC18V01 require monotonic power supply ramps. XCV50E requires 1.8V supply ramp nominal voltage less than milliseconds. Figure
1.8V VCCint1=1.8V 0.0V 3.3V VCCint2=3.3V 0.0V DEVRDY V1V2
Before programming operations performed, programmer must wait XCV50E's initialization phase complete. programmer wait either maximum initialization time System DEVRDY signal High which indicates initialization phase. After initialization phase complete, device ready operation. Table power-on power supply requirements.
FCMRESET
DS087_16_060701
Figure Power-On Power Supply Requirements Table Power-On Power Supply Requirements Parameter TV1V2 TRDY TRST I1.8 Description 1.8V power supply ramp 0-1.8 1.8V 3.3V power sequence delay Initialization time after 3.3V FCMRESET System controller reset 1.8V supply current Minimum Maximum
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Ordering Information
XCCACEM16 BG388 Device Number Package Type XCCACEM16 XCCACEM32 XCCACEM64 Industrial -40° +85° BG388 388-site Ball Grid Array
DS087_17_091001
Operating Range/Processing
Valid Ordering Combinations
Valid Ordering Combinations XCCACEM16BG388I XCCACEM32BG388I XCCACEM64BG388I Description System System System
Revision History
following table shows revision history this document. Date 09/25/01 01/18/02 06/07/02 Version Initial Xilinx release. Minor edits done. Added "Virtex Series FPGAs" "Virtex-II Series Platform FPGAs" Summary. Revision
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