4-BIT SINGLE-CHIP MICROCONTROLLER INTEGRATED CIRCUIT DESCRIP

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4-BIT SINGLE-CHIP MICROCONTROLLER INTEGRATED CIRCUIT DESCRIP

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PD753036, 753036(A)
4-BIT SINGLE-CHIP MICROCONTROLLER
INTEGRATED CIRCUIT
DESCRIPTION
µPD753036 75XL series 4-bit single-chip microcontroller chips data processing capability comparable that 8-bit microcontroller. on-chip controller/driver with larger capacity extended functions compared with conventional µPD75336, provide high-speed operation supply voltage supplied small plastic TQFP package suitable small sets using panels. stricter quality assurance program applies µPD753036(A) compared µPD753036 (standard model). terms NEC's quality grading, this "special" grade product.) details functions refer following User's Manual.
µPD753036 User's Manual: U10201E
FEATURES
voltage operation
driven batteries
Internal programmable controller/driver Internal converter which operated
voltage 8-bit resolution channels (successive approximation type)
On-chip memory
Program memory (ROM): 16384 bits Data memory (RAM): bits
Capable high-speed operation variable instruction execution time power saving 0.95, 1.91, 3.81, 15.3 4.19 MHz) 0.67, 1.33, 2.67, 10.7 MHz) 32.768 kHz)
Small plastic TQFP
Suitable small sets such cameras
One-time PROM: PD75P3036
APPLICATION
Radio transmitter/receiver, compact disc player, rice cooker, home bakery, etc.
ORDERING INFORMATION
Part number Package 80-pin plastic 0.65 pitch) 80-pin plastic TQFP (fine pitch) pitch) 80-pin plastic 0.65 pitch) Quality grade Standard Standard Special
Remark indicates code suffix.
Please refer "Quality Grades Semiconductor Devices" (Document C11531E) published Corporation know specification quality grade devices recommended applications.
Unless otherwise specified, µPD753036 treated representative model throughout this document.
information this document subject change without notice. Before using this document, please confirm that this latest version. devices/types available every country. Please check with local representative availability additional information. Document U11353EJ4V0DS00 (4th edition) Date Published June 2000 CP(K) Printed Japan mark shows major revised points.
1996, 2000
µPD753036, 753036(A)
Functional Outline
Parameter Minimum instruction execution time Function 0.95, 1.91, 3.81, 15.3 (main system clock: @4.19 operation) 0.67, 1.33, 2.67, 10.7 (main system clock: @6.0 operation) (subsystem clock: @32.768 operation) General purpose register 16384 bits bits 4-bit operation: banks 8-bit operation: banks Also used segment pins On-chip pull-up resistors specified using mask option withstand voltage On-chip pull-up resistors specified using software:
On-chip memory
Input/ output port
CMOS input CMOS input/output port output N-ch open-drain input/output pins Total
Segment selection: Display mode selection: 12/16/20 segments (can changed port output unit max. Static duty (1/2 bias) duty (1/2 bias) duty (1/3 bias) duty (1/3 bias)
controller/driver
On-chip split resistor drive specified using mask option Timer channels 8-bit timer/event counter: channels (16-bit timer/event counter, career generator, timer with gate) Basic interval/watchdog timer: channel Watch timer: channel 3-wire serial mode selected transferring first 2-wire serial mode mode 8-bit resolution channels (1.8 bits 524, 262, 65.5 (main system clock: @4.19 operation) 750, 375, 93.8 (main system clock: @6.0 operation) (main system clock: @4.19 operation subsystem clock: @32.768 operation) 2.93, 5.86, 46.9 (main system clock: @6.0 operation) External: Internal: External: Internal: Ceramic crystal oscillator main system clock oscillation Crystal oscillator subsystem clock oscillation STOP/HALT mode 80-pin plastic 0.65 pitch) 80-pin plastic TQFP (fine pitch) pitch)
Serial interface
converter sequential buffer (BSB) Clock output (PCL)
Buzzer output (BUZ)
Vectored interrupts Test input System clock oscillator
Standby function Power supply voltage Package
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
CONTENTS
CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTION Port Pins Non-Port Pins Input/Output Circuits Recommended Connections Unused Pins
SWITCHING FUNCTION BETWEEN MODE MODE Difference between Setting Method Stack Bank Select Register (SBS). MEMORY CONFIGURATION PERIPHERAL HARDWARE FUNCTIONS Digital Port Clock Generator Subsystem Clock Oscillator Control Functions Clock Output Circuit Basic Interval Timer/Watchdog Timer Watch Timer Timer/Event Counter Serial Interface Controller/Driver 6.10 Converter 6.11 Sequential Buffer INTERRUPT FUNCTION TEST FUNCTION STANDBY FUNCTION RESET FUNCTION MASK OPTION INSTRUCTION SETS ELECTRICAL CHARACTERISTICS CHARACTERISTIC CURVE (reference) PACKAGE DRAWINGS
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
RECOMMENDED SOLDERING CONDITIONS APPENDIX µPD75336, 753036, 75P3036 FUNCTION LIST APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
CONFIGURATION (TOP VIEW)
80-pin plastic 0.65 pitch)
80-pin plastic TQFP (fine pitch) pitch)
P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 RESET Note
S31/BP7 S30/BP6 S29/BP5 S28/BP4 S27/BP3 S26/BP2 S25/BP1 S24/BP0
AVREF AVSS
P83/AN7 P82/AN6 P81/TI2 P80/TI1 P31/SYNC P30/LCDCL P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1
Note Connect (Internally Connected) directly VDD.
P00/INT4 P01/SCK P02/SO/SB0
COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2
COM0
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80-P83 BP0-BP7 KR0-KR7 SB0, RESET S12-S31 COM0-COM3 Port Port Port Port Port Port Port Port Port Port Return Serial Clock Serial Input Serial Output Serial Data Reset Segment Output 12-31 Common Output VLC0-VLC2 BIAS LCDCL SYNC TI0-TI2 PTO0-PTO2 AVREF AVSS AN0-AN7 INT2 XT1, Power Supply Power Supply Bias Control Clock Synchronization Timer Input Programmable Timer Output Buzzer Clock Programmable Clock Analog Reference Analog Ground Analog Input External Test Input Main System Clock Oscillation Subsystem Clock Oscillation Positive Power Supply Ground Internally Connected
INT0, INT1, INT4 External Vectored Interrupt
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
BLOCK DIAGRAM
TI0/P13 PTO0/P20 AN0-AN5 AN6/P82 AN7/P83 AVREF AVSS
8-bit timer/event counter
INTT0 TOUT0
converter Basic interval timer/ watchdog timer
Port0 Port1 Program counter (14) Bank Port2 Port3 Port4 Port5 General reg. Program memory (ROM) 16384 bits Decode control Port6 Port7 Data memory (RAM) bits Port8
P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80-P83
INTBT INTT1
TI1/P80 PTO1/P21 TI2/P81 PTO2/PCL/P22 BUZ/P23 SI/SB1/P03 S0/SB0/P02 SCK/P01
INT0/P10 INT1/P11 INT4/P00 INT2/P12 KR0/P60KR7/P73
8-bit timer/event counter 8-bit timer/event counter
Cascaded 16-bit timer/ event timer
INTT2 Watch timer INTW fLCD Clocked serial interface
INTCSI TOUT0
S12-S23
controller/ driver fx/2N Clock output control PCL/P22 Clock divider clock
System clock generator
Interrupt control
fLCD
seq. buffer (16)
Stand Main control
S24/BP0S31/BP7 COM0-COM3 VLC0 VLC1 VLC2 BIAS LCDCL/P30 SYNC/P31
RESET XT1XT2
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
FUNCTION Port Pins (1/2)
Alternate Function INT4 SO/SB0 SI/SB1 Input INT0 INT1 INT2 Input/Output PTO0 PTO1 PCL/PTO2 Input/Output LCDCL SYNC Programmable 4-bit input/output port (PORT3). This port specified input/output units. Connections on-chip pull-up resistor specified software 4-bit units. N-ch open-drain 4-bit input/output port (PORT4). pull-up resistor contained bit-wise (mask option). open-drain mode, withstands N-ch open-drain 4-bit input/output port (PORT5). pull-up resistor contained bit-wise (mask option). open-drain mode, withstands High level (when pullup resistors contained) high impedance High level (when pullup resistors provided) high impedance Input 4-bit input port (PORT1) Connections on-chip pull-up resistors specified software 4-bit units. P10/INT0 select noise eliminating circuit. 4-bit input/output port (PORT2) Connections on-chip pull-up resistors specified software 4-bit units. Input 8-bit Access State after Reset Input Circuit Type Note
Name
Input/Output Input
Function 4-bit input port (PORT0). P03, connections on-chip pull-up resistors specified software 3-bit units.
Input
P40-P43 Note Input/Output
P50-P53 Note Input/Output
Notes
Circled characters indicate Schmitt-trigger input. on-chip pull-up resistors specified mask option (when used N-ch open-drain input port), level input leakage current increases when input manipulation instruction executed.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Port Pins (2/2)
Alternate Function Input/Output Input/Output Output Output 1-bit output port (BIT PORT) Also used segment output pins. Note 4-bit input/output port (PORT8). Connections on-chip pull-up resistors specified software 4-bit units. Input 8-bit Access State after Reset Input Circuit Type Note
Name
Input/Output Input/Output
Function Programmable 4-bit input/output port (PORT6). This port specified input/output bit-wise. Connections on-chip pull-up resistors specified software 4-bit units. 4-bit input/output port (PORT7). Connections on-chip pull-up resistors specified software 4-bit units.
Input
Notes
Circled characters indicate Schmitt-trigger input. through select VLC1 input source. However, output levels change depending external circuit through VLC1. Example Because through mutually connected inside µPD753036, output levels through determined
PD753036
VLC1
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Non-Port Pins (1/2)
Alternate Function Output Clock output Optional frequency output (for buzzer output system clock trimming) Serial clock input/output Serial data output Serial data input/output Serial data input Serial data input/output Edge detection vectored interrupt input (both rising edge falling edge detection)
Edge detection vectored interrupt input (detection edge selected) INT0/P10 select noise eliminator.
Name PTO0 PTO1 PTO2
Input/Output Input
Function Inputs external event pulses timer/event counter.
State after Reset Input
Circuit Type Note
Timer/event counter output
Input
SO/SB0
Input/Output
Input
SI/SB1
INT4
Input
Input
INT0
Input
Noise eliminator/ asynch selectable Asynchronous Asynchronous
Input
INT1 INT2 AN0-AN5 KR0-KR3 KR4-KR7 S12-S23 S24-S31 COM0-COM3 -VLC2 Input Input Output Output Output Input Input
P60-P63 P70-P73 BP0-BP7
Edge-detection-testable input
Input Input
Analog signal input converter
converter reference voltage input converter reference Falling edge detection testable input Falling edge detection testable input Segment signal output Segment signal output Common signal output drive power On-chip split resistor enable (mask option). Output external split resistor disconnect
Input Input Note Note Note
BIAS
Output
Note
Notes
Circled characters indicate Schmitt trigger input. Each display output selects following VLCX input source. S12-S31: VLC1, COM0-COM2: VLC2, COM3: VLC0. When split resistor contained level When split resistor contained High-impedance
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Non-Port Pins (2/2)
Alternate Function State after Reset Input Input Circuit Type Note
Name LCDCL Note SYNC Note
Input/Output Output Output Input
Function Clock output externally expanded driver Clock output externally expanded driver sync Crystal/ceramic connection main system clock oscillator. When inputting external clock, input external clock reverse phase external clock Crystal connection subsystem clock oscillator. When external clock used, input external clock reverse phase external clock XT2. used 1-bit input (test) pin. System reset input (low level active) Internally connected. Connect directly VDD. Positive power supply
Input
RESET
Input
Notes Circled characters indicate Schmitt-trigger input. These pins provided future system expansion. present, these pins used only pins P31.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Input/Output Circuits
µPD753036 input/output circuits shown schematically. (1/3)
TYPE TYPE Data P-ch N-ch Output disable N-ch P-ch
CMOS specification input buffer. TYPE
Push-pull output that placed output high impedance (both P-ch, N-ch off). TYPE P.U.R. P.U.R. enable Data Type Output disable P-ch
IN/OUT
Schmitt trigger input having hysteresis characteristic.
Type
P.U.R. Pull-Up Resistor TYPE TYPE P.U.R. P.U.R. enable P.U.R. enable Data Output disable Type P.U.R P-ch
P-ch
IN/OUT
Type
Type P.U.R. Pull-Up Resistor
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
(2/3)
TYPE P.U.R. P.U.R. enable Data Output disable Type P-ch IN/OUT data
Type
TYPE
VLC0 VLC1 P-ch N-ch
P-ch N-ch
P-ch N-ch
VLC2 N-ch
P-ch N-ch
N-ch P-ch
P.U.R. Pull-Up Resistor
TYPE P.U.R. P.U.R. enable P-ch P-ch
TYPE
Output disable Data Output disable Output disable
data IN/OUT port data Output disable
Type
N-ch
Type
P.U.R. Pull-Up Resistor
TYPE
TYPE VLC0 P-ch N-ch P.U.R. P.U.R. enable P-ch IN/OUT P-ch N-ch data VLC2 P-ch N-ch N-ch P.U.R. Pull-Up Resistor N-ch Data Output disable N-ch
VLC1
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
(3/3)
TYPE P.U.R. (Mask Option) IN/OUT Data Output disable Input instruction P-ch P.U.R.Note
Type
TYPE
N-ch (+13 withstand voltage)
P.U.R. enable Data Type Output disable
P-ch
IN/OUT
Voltage limitation circuit (+13 withstand voltage) Note This pull-up resistor operates only when input instruction executed without pull-up resistor connected using mask option (current flows from when low). TYPE
Port inputNote Type
P.U.R. Pull-Up Resistor TYPE
AVREF P-ch N-ch Sampling AVSS Input enable Reference voltage
AVSS Reference voltage (From voltage series resistor string)
ADEN
N-ch
AVSS
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Recommended Connections Unused Pins
Table 3-1. List Recommended Connections Unused Pins
P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL/PTO2 P23/BUZ P30/LCDCL P31/SYNC P40-P43 P50-P53 Input: Connect VSS. Output: Connect VSS. connect pull-up resistor using mask option.) P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80/TI1, P81/TI2 P82/AN6, P83/AN7 S12-S23 S24/BP0-S31/BP7 COM0-COM3 VLC0-VLC2 BIAS Connect Only VLC0-VLC2 unused, connect VSS. other cases, connection required. Connect Leave unconnected Connect Connect Leave unconnected Input: Individually connect resistor Output: Leave unconnected Input: Individually connect resistor Output: Leave unconnected Connect Connect Recommended Connection Connect Connect individually resistor
Note Note AN0-AN5
Connect directly
Note
When subsystem clock used, SOS. internal feedback resistor).
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
SWITCHING FUNCTION BETWEEN MODE MODE Difference between
µPD753036 following modes: either which selected. mode switched Stack Bank Select register (SBS). mode: mode: Upward compatible with PD75336. used 75XL with capacity bytes. Incompatible with µPD75336. used 75XL CPU's including those products whose capacity more than Kbytes. Table 4-1. Differences between Mode Mode
Mode Program memory (bytes) Number stack bytes subroutine instructions !addr1 instruction CALLA !addr1 instruction CALL !addr instruction CALLF !faddr instruction 3-machine cycles 2-machine cycles 4-machine cycles 3-machine cycles 16384 bytes bytes Mode
available
Available
Caution supports program area exceeding bytes 75XL series. Therefore, this mode useful enhancing software compatibility with products exceeding bytes. When mode selected, number stack bytes used increased byte stack compared with mode. When CALL !addr instruction CALLF !faddr instruction used, number machine cycles becomes greater Therefore, mode efficiency processing capability more important than software compatibility.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Setting Method Stack Bank Select Register (SBS)
Switching between mode mode done SBS. Figure shows format. 4-bit memory manipulation instruction. When using mode, must initialized Note beginning program. When using mode, must initialized Note. Note desired numbers must positions. Figure 4-1. Stack Bank Select Register Format
Address F84H SBS3 SBS0 Symbol
SBS2 SBS1
Stack area specification Memory bank Memory bank Memory bank Prohibited
sure
Mode switching specification mode mode
Caution Since SBS. after RESET signal generated, operates mode. When executing instruction mode, SBS. select mode.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
MEMORY CONFIGURATION
Program memory (ROM) 16384 bits
Addresses 0000H 0001H Vector table wherein program start address values time RESET signal generated written. Reset start possible arbitrary address. Addresses 0002H-000DH Vector table wherein program start address values vectored interrupts written. Interrupt execution start arbitrary address. Addresses 0020H-007FH Table area referenced GETI instruction Note. Note GETI instruction realizes 1-byte instruction behalf arbitrary 2-byte instruction, 3-byte instruction, 1-byte instructions. used decrease program steps.
Data memory (RAM)
Data area words bits (000H-2FFH) Peripheral hardware area words bits (F80H-FFFH)
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Figure 5-1. Program Memory
0000H
Internal reset start address (high-order bits)
0002H INTBT/INT4 start address
(Iow-order bits) (high-order bits) (Iow-order bits) (high-order bits) (Iow-order bits) (high-order bits) (Iow-order bits) (high-order bits) (Iow-order bits) (high-order bits) (Iow-order bits) CALL !addr instruction subroutine entry address CALLF !faddr instruction entry address Branch address BCXA, BCDE, !addr, !addr1Note CALLA !addr1Note instruction
0004H INT0 start address
0006H INT1 start address
0008H INTCSI start address
BRCB !caddr instruction branch address
000AH INTT0 start address
000CH
INTT1,INTT2 start address (high-order bits)
(Iow-order bits) $addr instruction relative branch address (-15 +16)
0020H GETI instruction reference table 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH
Branch destination address subroutine entry address when GETI instruction executed
BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address
Note
performed only mode.
Remark addition above, branch taken address indicated changing only low-order bits executing PCDE, PCXA instruction.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Figure 5-2. Data Memory
Data memory 000H General purpose register area 01FH 020H (224 0FFH 100H (236 1EBH 1ECH Display data memory Stack areaNote Data area static (768 1FFH 200H Memory bank
2FFH
incorporated
F80H
Peripheral hardware area
FFFH
Note stack area, memory bank selected among memory bank 0-2.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
PERIPHERAL HARDWARE FUNCTIONS Digital Port
following four types ports available: CMOS input (PORT0 pins pins pins
CMOS (PORT2, pins N-ch open-drain (PORT4 port output (BP0 through BP7) Total
pins Table 6-1. Types Features Digital Ports
Port Name PORT0
Function 4-bit input
Operation Features When using serial interface function, dual function function output port depending operation mode. 4-bit input port
Remarks Also used INT4, SCK, SO/SB0, SI/SB1 pins.
PORT1
Also used INT0INT2 pins. Also used PTO0PTO2, PCL, pins. Also used LCDCL, SYNC pins. On-chip pull-up resistor specified bit-wise mask option.
PORT2
4-bit
input mode output mode 4-bit units. input mode output mode 1-bit units.
PORT3
PORT4
PORT5
4-bit (N-channel open-drain, withstand voltage) 4-bit
input mode output mode 4-bit units.
Ports paired data input/ output 8-bit units.
PORT6
input mode output mode 1-bit units. input mode output mode 4-bit units.
Ports paired data input/ output 8-bit units.
Also used KR0-KR3 pins.
PORT7
Also used KR4-KR7 pins.
PORT8
input mode output mode 4-bit units 1-bit output Outputs data bit-wise. switched drive segment output S24-S31 software.
Also used TI1, TI2, AN6, pins.
BP0-BP7
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Clock Generator
clock generator provides clock signals peripheral hardware configuration shown Figure 6-1. operation clock generation circuit determined processor clock control register (PCC) system clock control register (SCC). types system clocks available: main system clock subsystem clock. Furthermore, instruction execution time changed. 0.95, 1.91, 3.81, 15.3 (main system clock: 4.19 operation) 0.67, 1.33, 2.67, 10.7 (main system clock: operation) (subsystem clock: 32.768 operation) Figure 6-1. Clock Generator Block Diagram
Basic interval timer (BT) Timer/event counter Serial interface Watch timer controller/driver converter INT0 noise eliminator Clock output circuit 1/1~1/4096 Divider 1/16
Main system clock oscillator Subsystems clock oscillator controller/driver Watch timer
Selector WM.3 SCC3 Internal SCC0 PCC0 PCC1 PCC2 HALTNote STOPNote PCC3 HALT Oscillation stop Selector
Divider INT0 noise eliminator Clock output circuit
PCC2, PCC3 Clear
STOP
Wait release signal from RESET signal
Standby release signal from interrupt control circuit
Note Instruction execution
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Remarks Main system clock frequency Subsystem clock frequency clock PCC: Processor Clock Control Register SCC: System Clock Control Register Clock cycle (tCY) clock equal machine cycle instruction.
Subsystem Clock Oscillator Control Functions
µPD753036 subsystem clock oscillator following control functions.
Selects software whether on-chip feedback resistor used notNote. Reduces current consumption decreasing drive current on-chip inverter when supply voltage
high (VDD Note When subsystem clock used, SOS.0 internal feedback resistor), connect VSS, open lower supply current that consumed subsystem clock oscillator. above functions used switching bits sub-oscillator control register (SOS). (Refer Figure 6-2.) Figure 6-2. Subsystem Clock Oscillator
SOS.0
Feedback resistor Inverter SOS.1
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Clock Output Circuit
clock output circuit provided output clock pulses from P22/PCL/PTO2 pin, used apply remote control waveform outputs supply clock pulses peripheral LSIs.
Clock output (PCL): 524, 262, 65.5 (main system clock: 4.19 operation)
750, 375, 93.8 (main system clock: operation) Figure 6-3. Clock Output Circuit Block Diagram
From clock generator fX/23 Selector fX/24 fX/26 Selector PCL/P22PTO2 From timer/event counter (channel Output buffer
PORT2.2 CLOM3 CLOM1 CLOM0 CLOM output latch
PMGB Port mode specification
Internal
Remark Special care been taken designing chip that small-width pulses output when switching clock output enable/disable.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Basic Interval Timer/Watchdog Timer
basic interval timer/watchdog timer following functions.
Interval timer operation generate reference time interrupt Watchdog timer operation detect runaway program reset Selects counts wait time when standby mode released Reads contents counting Figure Basic Interval Timer/Watchdog Timer Block Diagram
From clock generator fX/25 fX/27 fX/29 fX/212 Clear Clear
Basic interval timer (8-bit frequency divider)
interrupt request flag Vectored interrupt IRQBT request signal
Wait release signal when standby released.
Internal reset signal WDSET1Note
BTM3 BTM2 BTM1 BTM0 BSET1Note Internal
Note Instruction execution
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Watch Timer
µPD753036 channel watch timer. functions watch timer follows:
Sets test flag (IRQM) with interval. standby mode released IRQM. interval created both main system clock (4.19 MHz) subsystem clock (32.768 kHz). Convenient program debugging checking interval becomes times shorter (3.91 with
fast feed mode.
Outputs frequencies (2.048, 4.096, 32.768 kHz) (P23), usable buzzer trimming
system clock frequencies.
Clears frequency divider make clock start with zero seconds.
Figure 6-5. Watch Timer Block Diagram
(512 1.95 (256 3.91 From clock generator (32.768 kHz) (32.768 kHz) Selector
fLCD
(32.768 kHz)
Divider
Selector INTW IRQW signal
Clear
Selector
Output buffer P23/BUZ
PORT2.3 output latch
PMGB Port input/ output mode
test instruction
Internal
values enclosed parentheses applied when 4.19 32.768 kHz.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Timer/Event Counter
µPD753036 three channels timer/event counters. configuration shown Figures through 6-8. functions timer/event counter follows:
Programmable interval timer operation Square wave output frequency PTOn pin. 0-2) Event counter operation Divides frequency signal input 1-Nth original signal outputs divided frequency PTOn (frequency division operation).
Supplies serial shift clock serial interface circuit. Reads counting value.
timer/event counter operates following four modes mode register. Table 6-2. Operation Modes Timer/Event Counter
Channel Channel Mode 8-bit timer/event counter mode Gate control function pulse generator mode 16-bit timer/event counter mode Gate control function Carrier generator mode NoNote NoNote Channel Channel
Note Used gate control signal generation
Data Sheet U11353EJ4V0DS00
PORT1.3 Input buffer TI0/P13 From clock generator fx/24 fx/26 fx/28 fx/210
Data Sheet U11353EJ4V0DS00
Figure 6-6. Timer/Event Counter Block Diagram (channel
Internal SET1Note TM06 TM05 TM04 TM03 TM02 TMOD0 Modulo register
TOE0 enable flag
PORT2.0 PGMB Port input/output output latch mode serial interface
TOUT0 Match Comparator Reset Count register Clear INTT0 IRQT0 signal TOUT Output buffer P20/PTO0
Timer operation start RESET IRQT0 clear signal
timer/event counter (channel
µPD753036, 753036(A)
Note Instruction execution Caution When setting TM0, sure bits
Figure 6-7. Timer/Event Counter Block Diagram (channel
Internal SET1
Note
TM16 TM15 TM14 TM13 TM12 TM11 TM10 Decoder TMOD1 PORT1.2 Modulo register Input buffer TI1/P80
Data Sheet U11353EJ4V0DS00
Timer/event counter output (channel
TOE1 enable flag
PORT2.1 output latch
PMGB.2
Port input/output mode
Comparator Count register Clear
Match
TOUT Reset
P21/PTO1 Output buffer
From clock generator
fx/2 fx/26 fx/28 fx/210 fx/212
RESET Timer operation start timer/event counter mode Selector IRQT1 signal
µPD753036, 753036(A)
Timer/event counter match signal (channel (When 16-bit timer/event counter mode)
Timer/event counter reload signal (channel
INTT1 IRQT1 signal
Timer/event counter comparator (channel (When 16-bit timer/event counter mode)
Note Instruction execution
Selector
Selector
TI2/P81 fx/2 From clock fx/24 generator fx/26 fx/28 fx/210
Data Sheet U11353EJ4V0DS00
Count register Clear
Reset Overflow Carrier generator mode
Selector
SET1
Note
Figure 6-8. Timer/Event Counter Block Diagram (channel
Internal
TM26 TM25 TM24 TM23 TM22 TM21 TM20
TMOD2H TMOD2
TGCE
TOE2REMC NRZB
Reload
Modulo register high level period setup
PORT1.2 Decoder
Modulo register
PORT2.2 PMGB.2 Port output latch input/output
Comparator
P22/PCL/PTO2
Match
Input buffer
TOUT
Output buffer
Timer/event counter clock input (channel
16-bit timer/event counter mode
INTT2 IRQT2 signal IRQT2 clear signal
Timer operation start
RESET Timer event counter TOUT (channel
Timer/event counter clear signal (channel (When 16-bit timer/event counter mode) Timer/event counter match signal (channel (When 16-bit timer/event counter mode) Timer/event counter match signal (channel (When carrier generator mode)
From clock generator
µPD753036, 753036(A)
Note Instruction execution
µPD753036, 753036(A)
Serial Interface
µPD753036 incorporates clock-synchronous 8-bit serial interface used following four modes.
Operation stop mode 3-wire serial mode 2-wire serial mode mode
Data Sheet U11353EJ4V0DS00
ACKE
P02/SO/SB0
Selector release/ command/ acknowledge detection circuit RELD CMDD ACKD
Busy/ acknowledge output circuit
BSYE
ACKT
test CSIM P03/SI/SB1 Selector
Data Sheet U11353EJ4V0DS00
Figure 6-9. Serial Interface Block Diagram
Internal manipulation SBIC RELT CMDT Shift register (SIO) latch test
Slave address register (SVA) Match signal Address comparator
P01/SCK Serial clock counter
INTCSI INTCSI control circuit IRQCSI signal
µPD753036, 753036(A)
output Iatch
Serial clock control circuit
Serial clock selector
fX/23 fX/24 fX/26 TOUT0 (from timer/event counter (channel
External
µPD753036, 753036(A)
Controller/Driver
µPD753036 incorporates display controller which generates segment common signals according display data memory contents incorporates segment common drivers which drive panel directly. µPD753036 controller/driver functions follows:
Display data memory read automatically operation segment common signals
generated.
Display mode selected from among following five:
Static duty (time multiplexing bias duty (time multiplexing bias duty (time multiplexing bias duty (time multiplexing bias
frame frequency selected from among four each display mode. maximum segment signal output pins (S12-S31) four common signal port output (COM0COM3).
segment signal output pins (S24-S27 S28-S31) changed port output 4-pin units. Split-resistor incorporated supply drive power. (Mask option)
Various bias methods drive voltages applicable. When display off, current flow split resistor cut.
Display data memory used display used normal data memory. also operate using subsystem clock.
Data Sheet U11353EJ4V0DS00
drive mode changer
Display data memory 1FFH 1FEH
Data Sheet U11353EJ4V0DS00
Figure 6-10. Controller/Driver Block Diagram
Internal 1F8H 1ECH
Display control register
Port output latch
Port mode register group
1F9H
Display mode register
Timing controller
fLCD
Multiplexer
Selector
µPD753036, 753036(A)
Segment driver
Common driver
drive voltage control
S31/BP7
S30/BP6
S24/BP0
COM3 COM2 COM1 COM0
VLC2
VLC1
VLC0
P31/ P30/ SYNC LCDCL
µPD753036, 753036(A)
6.10 Converter
µPD753036 incorporates 8-bit resolution converter with analog input (AN0-AN7).
uses successive approximation method. Figure 6-11. Converter Block Diagram
Internal
ADEN ADM6 ADM5 ADM4
Multiplexer AN6/P82 AN7/P83 Sample hold circuit
Control circuit
Comparator
register
decoder
AVREF Series resistor string AVSS ADEN
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
6.11 Sequential Buffer Bits
sequential buffer (BSB) special data memory manipulation manipulation easily performed changing address specification specification sequence, therefore useful when processing long data bit-wise. Figure 6-12. Sequential Buffer Format
Address Symbol FC3H FC2H FC1H FC0H
BSB3
BSB2
BSB1
BSB0
register
DECS
INCS
Remarks
pmem.@L addressing, specified moves corresponding register. pmem.@L addressing, manipulated regardless MBE/MBS specification.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
INTERRUPT FUNCTION TEST FUNCTION
µPD753036 eight interrupt sources test sources. test sources, INT2 types edge-detected testable inputs. interrupt control circuit µPD753036 following functions: Interrupt function
Vectored interrupt function hardware control, enabling/disabling interrupt acceptance interrupt enable flag interrupt master enable flag (IME). interrupt start address. Nesting wherein order priority specified interrupt priority select register (IPS). Test function interrupt request flag interrupt generated checked software. Release standby mode. release interrupt selected interrupt enable flag.
Test function
Test request flag generation checked software. Release standby mode. test source released selected test enable
Data Sheet U11353EJ4V0DS00
INTBT INT4/P00 INT0/P10 INT1/P11
Note
Selector
Figure 7-1. Interrupt Control Circuit Block Diagram
Internal
Interruput enable flag
IST1
IST0
Decoder IRQBT
VRQn
Both edge detector Edge detector Edge detector INTCS1 INTT0 INTT1 INTT2 INTW
IRQ4 IRQ0 IRQ1 IRQCS1 IRQT0 IRQT1 IRQT2 IRQW IRQ2 Standby release signal Priority control circuit Vector table address generator
Data Sheet U11353EJ4V0DS00
INT2/P12
Rising edge detector
Selector
KR0/P60 KR3/P63
Falling edge detector
µPD753036, 753036(A)
Note Noise eliminator (Standby release disable when noise eliminator selected.)
µPD753036, 753036(A)
STANDBY FUNCTION
order save power consumption while program standby mode, types standby modes (STOP mode HALT mode) provided µPD753036. Table 8-1. Operation Status Standby Mode
STOP Mode instruction System clock when STOP instruction Settable only when main system clock used. main system clock stops oscillation. HALT Mode HALT instruction Settable both main system clock subsystem clock. Only halts (oscillation continues). Operation. (The IRQBT reference interval) Note Operable
Note
Operation status
Clock generator
Basic interval timer
Operation stops
Serial interface
Operable only when external input selected serial clock. Operable only when signal input T10-T12 pins specified count clock. Operable when selected count clock. Operable only when selected LCDCL. INT1, operable. Only INT0 operated. Note operation stops.
Timer/event counter
Operable
Note
Watch timer
Operable
driver controller
Operable
External interrupt
Release signal
Interrupt request signal sent from operable hardware enabled interrupt enable flag. Test request signal sent from test source enabled test enable flag RESET signal
Notes
Cannot operate only when main system clock stops. operate only when noise eliminator used (IM02 edge detection mode register(IM0).
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
RESET FUNCTION
There reset inputs: external RESET signal reset signal sent from basic interval timer/watchdog timer. When either reset signals input, internal reset signal generated. Figure shows circuit diagram above inputs. Figure 9-1. Configuration Reset Function
RESET
Internal reset signal
Reset signal sent from basic interval timer/watchdog timer WD
Internal
RESET signal generation, each device initialized listed Table 9-1. Figure shows timing chart reset operation. Figure 9-2. Reset Operation RESET Signal Generation
Wait Note
RESET signal generated Operating mode standby mode HALT mode Internal reset operation Operating mode
Note
following times selected mask option. 17/fX (21.8 operation, 31.3 4.19 operation) 15/fX (5.46 operation, 7.81 4.19 operation)
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Table 9-1. Status Each Device After Reset (1/2)
RESET Signal Generation Standby Mode Sets low-order bits program memory's address 0000H PC13-PC8 contents address 0001H PC7-PC0. Held Sets program memory's address 0000H MBE. Undefined 1000B Held Held Undefined RESET Signal Generation Operation Sets low-order bits program memory's address 0000H PC13-PC8 contents address 0001H PC7-PC0. Undefined Sets program memory's address 0000H MBE. Undefined 1000B Undefined Undefined Undefined
Hardware Program counter (PC)
Carry flag (CY) Skip flag (SK0-SK2) Interrupt status flag (IST0, Bank enable flag (MBE, RBE)
Stack pointer (SP) Stack bank select register (SBS) Data memory (RAM) General-purpose register Bank select register (MBS, RBS) Basic interval timer/watchdog timer Timer/event counter (T0) Counter (BT) Mode register (BTM) Watchdog timer enable flag (WDTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT Timer/event counter (T1) Counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT Timer/event counter (T2) Counter (T2) Modulo register (TMOD2) High level period setting modulo register (TMOD2H) Mode register (TM2) TOE2, TOUT REMC, NRZ, NRZB TGCE Watch timer Mode register (WM)
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Table 9-1. Status Each Device After Reset (2/2)
RESET Signal Generation Standby Mode Held Held Reset Cleared Held RESET Signal Generation Operation Undefined Undefined Reset Cleared Undefined
Hardware Serial interface Shift register (SIO) Operating mode register (CSIM) control register (SBIC) Slave address register (SVA) Clock generator, clock output circuit Processor clock control register (PCC) System clock control register (SCC) Clock output mode register (CLOM)
Sub-oscillator control register (SOS) controller/ driver Interrupt function Display mode register (LCDM) Display control register (LCDC) Interrupt request flag Interrupt enable flag Interrupt master enable flag (IME) INT0, mode registers (IM0, IM1, IM2) Interrupt priority selection register (IPS) Digital port Output buffer Output latch mode registers (PMGA, PMGB, BMGC) Pull-up resistor setting register (POGA, POGB) sequential buffer (BSB0-BSB3)
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
MASK OPTION
µPD753036 following mask options.
P40-P43, P50-P53 mask options
On-chip pull-up resistors connected. On-chip pull-up resistors specifiable bit-wise. On-chip pull-up resistors specifiable.
VLC0-VLC2 pin, BIAS mask option
On-chip dividing resistor drive connected. Dividing resistor connected. Four (TYP.) dividing resistors connected same time. Four (TYP.) dividing resistors connected same time.
Standby function mask option
Wait times selected RESET signal. 217/fX (21.8ms MHz, 31.3ms 4.19MHz) 215/fX (5.46ms MHz, 7.81ms 4.19MHz)
Subsystem clock mask option
internal feedback resistor selected. Internal feedback resistor used. (Switched ON/OFF software) Internal feedback resistor cannot used. (Switched hardware)
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
INSTRUCTION SETS
Expression formats specification methods operands operand written operand column each instruction accordance with specification method operand expression format instruction. details, refer RA75X Assembler Package User's Manual Language (U12385E). there several elements, them selected. Capital letters symbols words written they are. immediate data, appropriate numbers labels written. Instead labels such mem, fmem, pmem, bit, symbols registers specified. However, there restrictions labels that written fmem pmem. details, refer User's Manual.
Representation format reg1 rp'1 rpa1 fmem pmem addr addr1 caddr faddr taddr PORTn
Specification Method XA', BC', DE', XA', BC', DE',
HL+, HL-, 4-bit immediate data label 8-bit immediate data label 8-bit immediate data label 2-bit immediate data label
Note
FB0H-FBFH, FF0H-FFFH immediate data label FC0H-FFFH immediate data label 0000H-3FFFH immediate data label 0000H-3FFFH immediate data label mode only) 12-bit immediate data label 11-bit immediate data label 20H-7FH immediate data (where label PORT0-PORT8 IEBT, IET0-IET2, IE0-IE2, IE4, IECSI, RB0-RB3 MB0, MB1, MB2, MB15
Note only used even address 8-bit data processing.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Legend explanation operation PORTn register, 4-bit accumulator register register register register register register register register pair; 8-bit accumulator register pair register pair register pair expanded register pair expanded register pair expanded register pair expanded register pair Program counter Stack pointer Carry flag, accumulator Program status word Memory bank enable flag Register bank enable flag Port 0-8) Interrupt master enable flag Interrupt priority selection register Interrupt enable flag Register bank selection register Memory bank selection register Processor clock control register Separation between address contents addressed Hexadecimal data
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Explanation symbols under addressing area column
(MBS 0-2, (000H-07FH) (F80H-FFFH) (MBS 0-2, fmem FB0H-FBFH, FF0H-FFFH pmem FC0H-FFFH addr 0000H-3FFFH addr, addr1 (Current (Current (Current (Current caddr 0000H-0FFFH 1000H-1FFFH 2000H-2FFFH 3000H-3FFFH faddr 0000H-07FFH taddr 0020H-007FH addr1 0000H-3FFFH (PC13, (PC13, (PC13, (PC13, 00B) 01B) 10B) 11B)
Data memory addressing
Program memory addressing
Remarks
indicates memory bank that accessed. independently set. independently set. indicate areas that addressed.
Explanation number machine cycles column denotes number machine cycles required skip operation when skip instruction executed. value varies follows.
When skip made: When skipped instruction 2-byte instruction: When skipped instruction 3-byte instructionNote:
Note 3-byte instruction: !addr, !addr1, CALL !addr CALLA !addr1 instruction Caution GETI instruction skipped machine cycle. machine cycle equal cycle clock tCY); time selected from among four types setting PCC.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Number Machine Cycles reg1 (HL) (HL), then (HL), then (rpa1) (HL) (HL) (HL) (mem) (mem) (mem) (mem) reg1 reg1 rp'1 (HL) (HL), then (HL), then (rpa1) (HL) (mem) (mem) reg1 String effect String effect
Instruction Group Transfer
Mnemonic
Operand
Number Bytes
Operation
Addressing Area
Skip Condition
reg1, rp2, @HL+ @HL- @rpa1 @HL, @HL, mem, mem, reg1 reg1, rp'1,
String effect
@HL+ @HL- @rpa1 reg1
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Number Machine Cycles
Instruction Group Table reference
Mnemonic
Operand
Number Bytes
Operation (PC13-8+DE)ROM (PC13-8+XA)ROM (B1,0+CDE)ROM (B1,0+CXA)ROM (fmem.bit) (pmem7-2+L3-2.bit(L1-0)) (H+mem3-0.bit) (fmem.bit) (pmem7-2+L3-2.bit(L1-0)) (H+mem3-0.bit) A+n4 XA+n8 A+(HL) XA+rp' rp'1 rp'1+XA A+(HL)+CY XA+rp'+CY rp'1, rp'1+XA+CY A-(HL) XA-rp' rp'1 rp'1-XA A-(HL)-CY XA-rp'-CY rp'1, rp'1-XA-CY
Addressing Area
Skip Condition
MOVT
@PCDE @PCXA @BCDENote @BCXANote
carry carry carry carry carry
transfer
MOV1
fmem.bit pmem.@L @H+mem.bit fmem.bit, pmem.@L, @H+mem.bit,
Operation
ADDS
rp'1,
ADDC
rp'1,
SUBS
rp'1,
borrow borrow borrow
SUBC
rp'1,
Note
Only low-order 2-bits valid register.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Number Machine Cycles (HL) rp'1 rp'1 (HL) rp'1 rp'1 (HL) rp'1 rp'1 An-1 reg+1 rp1+1 (HL) (HL)+1 (mem) (mem)+1 reg-1 rp'-1 Skip Skip (HL) Skip (HL) Skip (HL) Skip Skip Skip CY=1 reg=0 rp1=00H (HL)=0 (mem)=0 reg=FH rp'=FFH reg=n4 (HL) (HL) (HL) A=reg XA=rp'
Instruction Group Operation
Mnemonic
Operand
Number Bytes
Operation
Addressing Area
Skip Condition
rp'1,
rp'1,
rp'1,
Accumulator manipulation
RORC
Increment Decrement
INCS
DECS
Comparison
reg, @HL,
Carry flag manipulation
SET1 CLR1 NOT1
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Number Machine Cycles (mem.bit) (fmem.bit) (pmem7-2+L3-2.bit(L1-0)) (H+mem3-0.bit) (mem.bit) (fmem.bit) (pmem7-2+L3-2.bit(L1-0)) (H+mem3-0.bit) Skip (mem.bit)=1 Skip (fmem.bit)=1 Skip (pmem7-2+L3-2.bit(L1-0))=1 Skip (H+mem3-0.bit)=1 Skip (mem.bit)=0 Skip (fmem.bit)=0 Skip (pmem7-2+L3-2.bit(L1-0))=0 Skip (H+mem3-0.bit)=0 Skip (fmem.bit)=1 clear Skip (pmem7-2+L3-2.bit(L1-0))=1 clear Skip (H+mem3-0.bit)=1 clear (fmem.bit) (pmem7-2+L3-2.bit(L1-0)) (H+mem3-0.bit) (fmem.bit) (pmem7-2+L3-2.bit(L1-0)) (H+mem3-0.bit) (fmem.bit) (pmem7-2+L3-2.bit(L1-0)) (H+mem3-0.bit)
Instruction Group Memory manipulation
Mnemonic
Operand
Number Bytes
Operation
Addressing Area
Skip Condition
SET1
mem.bit fmem.bit pmem.@L @H+mem.bit
CLR1
mem.bit fmem.bit pmem.@L @H+mem.bit
mem.bit fmem.bit pmem.@L @H+mem.bit
(mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1
mem.bit fmem.bit pmem.@L @H+mem.bit
SKTCLR
fmem.bit pmem.@L @H+mem.bit
AND1
fmem.bit pmem.@L @H+mem.bit
fmem.bit pmem.@L @H+mem.bit
XOR1
fmem.bit pmem.@L @H+mem.bit
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Instruction Group Branch Number Bytes Number Machine Cycles Addressing Area
Mnemonic
Operand
Operation PC13-0 addr Select appropriate instruction from among !addr, BRCB !caddr, $addr according assembler being used. !addr BRCB !caddr $addr PC13-0 addr1 Select appropriate instruction from following according assembler being used. !addr !addr1 BRCB !caddr $sddr1 PC13-0 addr PC13-0 addr PC13-0 addr1 PC13-0 PC13-8+DE PC13-0 PC13-8+XA PC13-0 B1,0+CDE PC13-0 B1,0+CXA PC13-0 addr1 PC13-0 PC13,12+caddr11-0 (SP-5)(SP-6)(SP-3)(SP-4) PC13-0 (SP-2) MBE, PC13-0 addr1, SP-6 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, PC12 PC13-0 addr, SP-4 (SP-5)(SP-6)(SP-3)(SP-4) PC13-0 (SP-2) MBE, PC13-0 addr, SP-6 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, PC12 PC13-0 000+faddr, SP-4 (SP-5)(SP-6)(SP-3)(SP-4) PC13-0 (SP-2) MBE, PC13-0 000+faddr, SP-6
Skip Condition
BRNote1
addr
addr1
!addr $addr $addr1 PCDE PCXA BCDENote BCXANote BRANote BRCB !addr1 !caddr
Subroutine stack control
CALLANote !addr1
CALLNote
!addr
CALLFNote !faddr
Notes
above operations shaded boxes performed only mode. other operations performed only mode. Only low-order bits valid register.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Number Machine Cycles
Instruction Group Subroutine stack control
Mnemonic
Operand
Number Bytes
Operation MBE, RBE, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP+4 MBE, (SP+4) PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP+6
Addressing Area
Skip Condition
RETNote
RETSNote
MBE, RBE, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP+4 then skip unconditionally MBE, (SP+4) PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP+6 then skip unconditionally
Unconditional
RETINote
MBE, RBE, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) (SP+4)(SP+5), SP+6 PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) (SP+4)(SP+5), SP+6
PUSH
(SP-1)(SP-2) SP-2 (SP-1) MBS, (SP-2) RBS, SP-2 (SP+1)(SP), SP+2 (SP+1), (SP), SP+2 IME(IPS.3) IME(IPS.3) PORTn PORTn+1, PORTn PORTn PORTn+1, PORTn HALT Mode (PCC.2 STOP Mode (PCC.3 Operation 0-8) 2-8)
Interrupt control
Input/output
INNote
PORTn PORTn
OUTNote
PORTn, PORTn,
control
HALT STOP
Notes
above operations shaded boxes performed only mode. other operations performed only mode. While instruction instruction being executed, must must
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Number Machine Cycles
Instruction Group Special
Mnemonic
Operand
Number Bytes
Operation
Addressing Area
Skip Condition
0-3) 0-2,
------------
GETINotes taddr
When instruction PC13-0 (taddr)5-0+(taddr+1)
When TCALL instruction (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, PC12 PC13-0 (taddr)5-0+(taddr+1) SP-4
------------
When instruction other than TCALL instructions (taddr) (taddr+1) instruction executed When instruction PC13-0 (taddr)5-0+(taddr+1) PC14
Depending reference instruction
-------------
When TCALL instruction (SP-5)(SP-6)(SP-3)(SP-4) PC13-0 (SP-2) MBE, PC13-0 (taddr)5-0+(taddr+1) SP-6
-------------
When instruction other than TCALL instructions (taddr) (taddr+1) instruction executed
Depending reference instruction
Notes
shaded applicable only mode. other area applicable only mode. TCALL instructions table definition assembler pseudo instructions GETI instruction.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Input voltage Symbol Other than ports Ports Pull-up resistor provided N-ch open drain Conditions Ratings -0.3 +7.0 -0.3 -0.3 -0.3 -0.3 Total pins Low-level output current Total pins Ambient operating temperature Storage temperature Tstg +85Note +150 Unit
Output voltage High-level output current
Note
drive normal mode, +85°C
Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. Capacitance
Parameter Input capacitance Output capacitance capacitance Symbol COUT Pins other than tested pins: Conditions MIN. TYP. MAX. Unit
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Main System Clock Oscillator Characteristics +85°C,
Oscillator Ceramic oscillator Recommended Circuit Parameter Oscillation frequency Note Conditions MIN. TYP. MAX. Note Unit
Oscillation stabilization timeNote
After reached MIN. value oscillation voltage range
Crystal resonator
Oscillation frequency Note
6.0Note
Oscillation stabilization timeNote
Note
External clock
input frequency Note
input high-, low-level widths tXL) 83.3
Notes
oscillation frequency input frequency shown above indicate characteristics oscillator only. instruction execution time, refer Characteristics. oscillation frequency 4.19 select processor clock control register (PCC) 0011. 0011, machine cycle less than 0.95 falling short rated value 0.95
oscillation stabilization time time required oscillation stabilized after been applied STOP mode been released.
Caution When using main system clock oscillator, wire portion enclosed dotted line above figure follows prevent adverse influences wiring capacitance: Keep wiring length short possible. cross wiring with other signal lines. route wiring vicinity line through which high alternating current flows. Always keep ground point capacitor oscillator same potential ground power supply pattern through which high current flows. extract signals from oscillator.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Subsystem Clock Oscillator Characteristics +85°C,
Oscillator Crystal resonator Recommended Circuit Parameter Oscillation frequency XT)Note Conditions MIN. TYP. 32.768 MAX. Unit
Oscillation stabilization timeNote
External clock
input frequency XT)Note
input high-, low-level widths XTH, XTL)
Notes
oscillation frequency shown above indicate characteristics oscillator only. instruction execution time, refer Characteristics. oscillation stabilization time time required oscillation stabilized after been applied.
Caution When using subsystem clock oscillator, wire portion enclosed dotted line above figure follows prevent adverse influences wiring capacitance: Keep wiring length short possible. cross wiring with other signal lines. route wiring vicinity line through which high alternating current flows. Always keep ground point capacitor oscillator same potential ground power supply pattern through which high current flows. extract signals from oscillator. subsystem clock oscillator amplification factor reduce current consumption more susceptible noise than main system clock oscillator. Therefore, exercise utmost care wiring subsystem clock oscillator.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Recommended Oscillator Constants Ceramic resonator +80°C)
Oscillator Constant (pF) Corp. CCR1000K2 CCR4.19MC3 CCR5.0MC3 CCR6.0MC3 FCR4.19MC5 FCR5.0MC5 FCR6.0MC5 Murata Mfg. Co., Ltd. CSB1000JNote CSA2.00MG040 CST2.00MG040 CSA4.19MG CST4.19MGW CSA4.19MGU CST4.19MGWU CSA6.00MG CST6.00MGW CSA6.00MGU CST6.00MGWU Kyocera Corp. KBR-1000F/Y KBR-2.0MS KBR-4.19MKC KBR-4.19MSB PBRC 4.19A PBRC 4.19B KBR-6.0MKC KBR-6.0MSB PBRC 6.00A PBRC 6.00B Capacitor-contained model Capacitor-contained model Capacitor-contained model 4.19 4.19 4.19 4.19 Capacitor-contained model Capacitor-contained model Capacitor-contained model Capacitor-contained model Capacitor-contained model Capacitor-contained model Oscillation Voltage Range MIN. MAX. Capacitor-contained model
Manufacturer
Part Number
Frequency (MHz)
Remark
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Note When using CSB1000J (1.0 MHz) Murata Mfg. Co., Ltd. ceramic resonator, limiting resistor necessary (refer figure below). resistor necessary when using other recommended resonators.
CSB1000J
Caution oscillator constants oscillation voltage range indicate conditions stable oscillation guarantee accuracy oscillation frequency. application circuit requires accuracy oscillation frequency, necessary oscillation frequency resonator application circuit. this, necessary directly contact manufacturer resonator being used.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Characteristics +85°C,
Parameter Low-level output current High-level input voltage VIH2 Ports 6-8, RESET VIH1 Symbol Total pins Ports VIH3 Ports Pull-up resistor provided N-ch open drain VIH4 Low-level input voltage VIL2 Ports 6-8, RESET VIL1 Ports VIL3 High-level output voltage Low-level output voltage VOL1 SCK, ports 6-8, BP0-BP7 -1.0 SCK, ports 2-8, BP0-BP7 VOL2 SB0, N-ch open drain Pull-up resistor High-level input leakage current ILIH1 ILIH2 ILIH3 Low-level input leakage current ILIL1 ILIL2 ILIL3 Pins other than Ports (N-ch open drain) Pins other than ports Ports (N-ch open drain) When input instruction executed Port (N-ch open drain) When input instruction executed High-level output leakage current ILOH2 Low-level output leakage current Internal pull-up resistor Ports 0-3, (except P00) Ports (when mask option selected) ILOL VOUT VOUT ILOH1 VOUT Conditions MIN. TYP. MAX. Unit
SCK, SO/SB0, SB1, ports Ports (Pull-up resistor provided) Ports (N-ch open drain)
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Characteristics +85°C,
Parameter drive voltage Symbol VLCD VAC0 Conditions +85°C 85°C VAC0 currentNote IVAC RLCD1 RLCD2 VODC ±1.0 VLCD0 VLCD VLCD1 VLCD VLCD2 VLCD VODS ±0.5 VLCD ±0.2 VAC0 ±10% MIN. TYP. MAX. ±0.2 Unit
divider resistorNote output voltage deviation
Note
(common) output voltage deviationNote (segment) Supply currentNote IDD1
6.00 MHzNote crystal oscillation 4.19 MHzNote crystal oscillation
±10%Note ±10% HALT mode
Note
0.33 0.05 0.02
12.0 13.8
IDD2
±10% ±10% ±10%Note
IDD1
±10%Note HALT mode ±10% ±10% ±10% ±10% 25°C ±10% 25°C Lowvoltage mode
Note
IDD2
IDD3
32.768 kHzNote crystal oscillation
Lowvoltage modeNote
current consumption mode Note
IDD4
HALT mode
±10% ±10%
±10%
power consumption mode Note
IDD5
Note
±10% ±10% 25°C
STOP mode
0.02
Notes
Clear VAC0 low-current mode STOP mode. When VAC0 current increases about Either RLCD1 RLCD2 selected mask option. Voltage deviation difference between ideal values (VLCDn; segment common outputs output voltage. current flowing through internal pull-up resistor divider resistor included. Including case when subsystem clock oscillates. When device operates high-speed mode with processor clock control register (PCC) 0011. When device operates low-speed mode with 0000. When device operates subsystem clock, with system clock control register (SCC) 1001 oscillation main system clock stopped. When sub-oscillator control register (SOS) 0000.
When 0010. When sub-oscillator feedback resistor used don't care).
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Characteristics +85°C,
Parameter clock cycle timeNote Symbol Conditions Operates with main system clock Operates with subsystem clock MIN. 0.67 0.95 TYP. MAX. Unit
(minimum instruction execution time machine cycle) TI0, TI1, input frequency
TI0, TI1, input high-, low-level widths Interrupt input high-, low-level widths
tTIH,
0.48
tINTH, INTL
INT0
IM02 IM02
Note
INT1, KR0-KR7 RESET low-level width tRSL
Notes
cycle time (minimum instruction execution time) clock determined oscillation frequency connected resonator (and external clock), system clock control register (SCC), processor clock control register (PCC). figure right shows supply voltage cycle time characteristics when device operates with main system clock.
Cycle time
(with main system clock) Operation guaranteed range
128/fX depending setting interrupt mode register (IM0).
Supply voltage
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Serial transfer operation 2-wire 3-wire serial modes (SCK internal clock output): +85°C,
Parameter cycle time Symbol tKCY1 Conditions MIN. 1300 3800 high-, low-level widths Note tKL1, tKH1 setup time (vs. tSIK1 tKSI1 tKCY1/2-50 tKCY1/2-150 Note hold time (vs. Note output delay time
Note
TYP.
MAX.
Unit
tKSO1
1000
Notes
Read when using 2-wire serial mode. respectively indicate load resistance load capacitance output line.
2-wire 3-wire serial modes (SCK external clock input): +85°C,
Parameter cycle time Symbol tKCY2 Conditions MIN. 3200 high-, low-level widths tKL2, tKH2 Note setup time (vs. tSIK2 Note hold time (vs. SONote output delay time tKSI2 1600
Note
TYP.
MAX.
Unit
tKSO2
1000
Notes
Read when using 2-wire serial mode. respectively indicate load resistance load capacitance output line.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
mode (SCK internal clock output (master)): +85°C,
Parameter cycle time Symbol tKCY3 Conditions MIN. 1300 3800 high-, low-level widths tKL3, tKH3 SB0, setup time (vs. SB0, hold time (vs. SB0, output delay time SB0, SB0, SB0, low-level width SB0, high-level width tKSB tSBK tSBL tSBH tKSI3 tKSO3
Note
TYP.
MAX.
Unit
tKCY3/2-50 tKCY3/2-150
tSIK3
KCY3/2 tKCY3 tKCY3 tKCY3 tKCY3 1000
Note
respectively indicate load resistance load capacitance output lines.
mode (SCK external clock input (slave)): +85°C,
Parameter cycle time Symbol tKCY4 Conditions MIN. 3200 high-, low-level widths tKL4, tKH4 SB0, setup time (vs. SB0, hold time (vs. SB0, output delay time SB0, SB0, SB0, low-level width SB0, high-level width tKSB tSBK tSBL tSBH tKSI4 tKSO4
Note
TYP.
MAX.
Unit
1600
tSIK4
KCY4/2 tKCY4 tKCY4 tKCY4 tKCY4 1000
Note
respectively indicate load resistance load capacitance output lines.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Converter Characteristics +85°C, AVREF AVSS VSS)
Parameter Resolution Absolute accuracyNote AVREF AVREF Conversion time Sampling time Analog input voltage Analog input impedance current tCONV tSAMP VIAN IREF Note Note 1000 0.25 Symbol Conditions MIN. TYP. MAX. 168/f 44/fX AVREF Unit
Notes
Absolute accuracy excluding quantization error (±1/2LSB) Time until conversion (EOC after execution conversion start instruction (40.1 4.19 MHz). Time until sampling after execution conversion start instruction (10.5 4.19 MHz).
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
timing test points (except inputs)
(MIN.) (MAX.)
(MIN.) (MAX.)
(MIN.) (MAX.)
(MIN.) (MAX.)
Clock timing
1/fX input
1/fXT tXTL tXTH input
TI0, TI1, timing
1/fTI tTIL tTIH
TI0, TI1,
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Serial transfer timing 3-wire serial mode
tKCY1, tKL1, tKH1,
tSIK1,
tKSI1,
Input data
tKSO1,
Output data
2-wire serial mode
tKCY1, tKL1, tKH1,
tSIK1,
tKSI1,
SB0,
tKSO1,
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Serial transfer timing release signal transfer
tKCY3, tKL3, tKH3,
tKSB tSBL tSBH tSBK tSIK3, tKSI3,
SB0, tKSO3,
Command signal transfer
tKCY3, tKL3, tKSB tSBK tSIK3, tKSI3, tKH3,
SB0, tKSO3,
Interrupt input timing
tINTL tINTH
INT0, KR0-7
RESET input timing
tRSL
RESET
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Data retention characteristics data memory STOP mode supply voltage +85°C)
Parameter Data retention power supply current Release signal setup time Oscillation stabilization wait timeNote Symbol VDDDR tSREL tWAIT Released RESET Released interrupt request Conditions MIN. Note Note TYP. MAX. Unit
Notes
oscillation stabilization wait time time during which stops operating prevent unstable operation when oscillation started. Either 217/fX 215/fX selected mask option. basic interval timer mode register (BTM). (Refer table below.)
BTM3 BTM2 BTM1 BTM0 4.19 220/f (approx. 217/f (approx. 31.3 215/f (approx. 7.81 213/f (approx. 1.95 Wait Time 220/f (approx. 217/f (approx. 21.8 215/f (approx. 5.46 213/f (approx. 1.37
Data retention timing (when STOP mode released RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
STOP instruction execution
tSREL
RESET
tWAIT
Data retention timing (standby release signal: when STOP mode released interrupt signal)
HALT mode STOP mode Data retention mode Operation mode
STOP instruction execution Standby release signal (interrupt request)
tSREL
tWAIT
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
CHARACTERISTIC CURVE (reference)
(main system clock: crystal resonator)
0011 0010 0001 0000 Main system clock HALT mode oscillation
Supply current (mA)
0.05 Subsystem clock operation mode (SOS.1 Subsystem clock HALT mode (SOS.1 Main system clock STOP mode oscillation (SOS.1 Subsystem clock HALT mode (SOS.1 Main system clock STOP mode oscillation (SOS.1 0.01
0.005
Crystal resonator Crystal resonator
32.768
0.001 Supply voltage
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
(main system clock: 4.19 crystal resonator)
0011 0010 0001 0000 Main system clock HALT mode oscillation
Supply current (mA)
0.05 Subsystem clock operation mode (SOS.1 Subsystem clock HALT mode (SOS.1 Main system clock STOP mode oscillation (SOS.1 Subsystem clock HALT mode (SOS.1 Main system clock STOP mode oscillation (SOS.1 0.01
0.005
32.768
Crystal resonator Crystal resonator
4.19
0.001 Supply voltage
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
(ports 6-8)
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
(ports 6-8)
25°C)
[mA]
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
PACKAGE DRAWINGS
80-PIN PLASTIC (14x14)
detail lead
NOTE Each lead centerline located within 0.13 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 17.2±0.4 14.0±0.2 14.0±0.2 17.2±0.4 0.825 0.825 0.30±0.10 0.13 0.65 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 2.7±0.1 0.1±0.1 5°±5° MAX. S80GC-65-3B9-6
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
PLASTIC TQFP (FINE PITCH) (12x12)
detail lead
NOTE
ITEM MILLIMETERS 14.00±0.20 12.00±0.20 12.00±0.20 14.00±0.20 1.25 1.25 0.22 +0.05 -0.04 0.10 0.50 (T.P.) 1.00±0.20 0.50±0.20 0.145 +0.055 -0.045 0.10 1.05±0.07 0.10±0.05 5°±5° 1.27 MAX. P80GK-50-BE9-6
Each lead centerline located within 0.10 true position (T.P.) maximum material condition.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
RECOMMENDED SOLDERING CONDITIONS
Solder µPD753036 under following recommended conditions. details recommended soldering conditions, refer Information Document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended, consult NEC. Table 15-1. Soldering Conditions Surface Mount Type 80-pin plastic 0.65 pitch)
80-pin plastic 0.65 pitch)
Symbol Recommended Condition IR35-00-3 VP15-00-3 WS60-00-1
Soldering Method Infrared reflow Wave soldering
Soldering Conditions Package peak temperature: 235°C, Time: seconds max. (210°C min.), Number times: max. Package peak temperature: 215°C, Time: seconds max. (200°C min.), Number times: max. Soldering bath temperature: 260°C max., Time: seconds max., Number times: Preheating temperature: 120°C max. (package surface temperature)
Partial heating
temperature: 300°C max., Time: seconds max. (per side device)
80-pin plastic TQFP (fine pitch) pitch)
Symbol Recommended Condition IR35-107-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235°C, Time: seconds max. (210°C min.), Number times: max., Exposure limit: daysNote (after that, prebake 125°C hours) Package peak temperature: 215°C, Time: seconds max. (200°C min.), Number times: max., Exposure limit: daysNote (after that, prebake 125°C hours) temperature: 300°C max., Time: seconds max. (per side device)
VP15-107-2
Partial heating
Note
After opening pack, store 25°C less less allowable storage period.
Caution different soldering methods together (except partial heating).
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
APPENDIX µPD75336, 753036, 75P3036 FUNCTION LIST
Parameter Program memory
µPD75336
Mask 0000H-3F7FH (16256 bits)
µPD753036
Mask 0000H-3FFFH (16384 bits) 000H-2FFH (768 bits)
µPD75P3036
One-time PROM 0000H-3FFFH (16384 bits)
Data memory
Instruction execution time When main system clock selected When subsystem clock selected connection 50-53 Stack register
High-End 0.95, 1.91, 15.3 4.19 operation)
75XL 0.95, 1.91, 3.81, 15.3 4.19 operation) 0.67, 1.33, 2.67, 10.7 operation)
32.768 operation)
P22/PCL P30-P33 None
P22/PCL/PTO2 P30/MD0-P33/MD3 P81/T12 SBS.3 mode selection SBS.3 mode selection n00H-nFFH 0-2) When mode: 2-byte stack When mode: 3-byte stack
Stack area Subroutine call instruction stack operation Instruction !addr1 CALLA !addr1 MOVT @BCDE MOVT @BCXA BCDE BCXA CALL !addr
000H-0FFH 2-byte stack
Unavailable
When mode: unavailable When mode: available Available
machine cycles
mode: machine cycles, mode: machine cycles mode: machine cycles, mode: machine cycles channels Basic interval timer/watchdog timer: channel 8-bit timer/event counter: channels (can used 16-bit timer/event counter, career generator, timer with gate) Watch timer: channel
CALLF !faddr
machine cycles
Timer
channels Basic interval timer: channel 8-bit timer/event counter: channels Watch timer: channel
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
µPD75336
524, 262, 65.5 (Main system clock: 4.19 operation)
Parameter Clock output (PCL)
µPD753036
µPD75P3036
524, 262, 65.5 (Main system clock: 4.19 operation) 750, 375, 93.8 (Main system clock: operation) (Main system clock: during 4.19 operation subsystem clock: 32.768 operation) 2.93, 5.86, 46.9 (Main system clock: operation)
output (BUZ)
(Main system clock: 4.19 operation, subsystem clock: 32.762 operation)
Serial interface
modes available 3-wire serial mode MSB/LSB selected transfer first 2-wire serial mode mode None Contained
register
Feedback resistor flag (SOS.0) Sub-oscillator current flag (SOS.1)
None
Contained
Register bank selection register (RBS) Standby release INT0 Vectored interrupt Operating supply voltage Operating ambient temperature Package
External: internal: +85°C 80-pin plastic TQFP (fine pitch) pitch) 80-pin plastic 0.65 pitch) External: internal:
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
APPENDIX DEVELOPMENT TOOLS
following development tools provided system development using µPD753036. 75XL series, relocatable assemblers common entire series used combination with device file each product type. Language processor
RA75X relocatable assembler Part number (product name)
Host machine PC-9800 series MS-DOSVer. 3.30 Ver. PC/ATcompatible machines
Note
Distribution media 3.5-inch
µS5A13RA75X
Refer
3.5-inch
µS7B13RA75X
Device file
Host machine PC-9800 series MS-DOS Ver. 3.30 Ver. PC/AT compatible machines
Note
Distribution media 3.5-inch
Part number (product name)
µS5A13DF753036
Refer
3.5-inch
µS7B13DF753036
Note
Ver.5.00 upper versions Ver.5.00 have task swap function, cannot used this software.
Remark operation assembler device file guaranteed only above host machines OSs.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
PROM write tools
Hardware PG-1500 PG-1500 PROM programmer which enables program single chip microcontrollers containing PROM stand-alone host machine operation connecting attached board optional programmer adapter PG-1500. also enables program typical PROM devices Kbits Mbits. PROM programmer adapter µPD75P3036GC. Connect programmer adapter PG-1500 use. PA-75P316GK PROM programmer adapter µPD75P3036GK. Connect programmer adapter PG-1500 use. PROM programmer adapter µPD75P3036KK-T. Connect programmer adapter PG-1500 use. PG-1500 host machine connected serial parallel interfaces PG-1500 controlled host machine. Host machine PC-9800 series MS-DOS Ver. 3.30 Ver. Note PC/AT compatible machines Refer 3.5-inch Distribution media 3.5-inch Part number (product name)
PA-75P328GC
PA-75P3036KK-T
Software
PG-1500 controller
µS5A13PG1500
µS7B13PG1500
Note
Ver.5.00 upper versions Ver.5.00 have task swap function, cannot used this software.
Remark operation PG-1500 controller guaranteed only above host machines OSs.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Debugging tool in-circuit emulators (IE-75000-R IE-75001-R) available program debugging tool
µPD753036.
system configurations described follows.
Hardware IE-75000-RNote In-circuit emulator debugging hardware software when developing application systems that series 75XL series. When developing µPD753036 subseries, emulation board IE-75300-R-EM emulation probe EP-75336GC-R EP-75336GK-R that sold separately must used with IE-75000-R. connecting with host machine PROM programmer, efficient debugging made. contains emulation board IE-75000-R-EM which connected. In-circuit emulator debugging hardware software when developing application systems that series 75XL series. When developing
IE-75001-R
µPD753036 sub-series, emulation board IE-75300-R-EM emulation probe EP-75336GC-R EP-75336GK-R which sold separately must used with IE-75001-R. debug system efficiently connecting host machine PROM programmer.
IE-75300-R-EM Emulation board evaluating application systems that µPD753036 subseries. must used with IE-75000-R IE-75001-R. Emulation probe µPD753036GC. must connected IE-75000-R IE-75001-R) IE-75300-R-EM. supplied with 80-pin conversion socket EV-9200GC-80 which facilitates connection target system. Emulation probe µPD753036GK. must connected IE-75000-R IE-75001-R) IE-75300-R-EM. supplied with 80-pin conversion adapter TGK-080SDW which facilitates connection target system. Connects IE-75000-R IE-75001-R host machine RS-232C Centronics controls above hardware host machine. Host machine PC-9800 series MS-DOS Ver. 3.30 Ver. Note PC/AT compatible machines Refer 3.5-inch 5-inch Distribution media 3.5-inch 5-inch Part number (product name)
EP-75336GC-R
EV-9200GC-80 EP-75336GK-R
TGK-080SDWNote Software control program
µS5A13IE75X µS5A10IE75X µS7B13IE75X µS7B10IE75X
Notes
Maintenance parts This product Tokyo Eletech Corp. further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672)
Ver.5.00 upper versions Ver.5.00 have task swap function, cannot used this software.
Remarks
operation control program guaranteed only above host machines OSs. µPD753036 subseries consists µPD753036 75P3036.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
following OS's supported.
DOSVersion Ver. 5.02 Ver. J6.1/VNote J6.3/VNote Ver. Ver. 6.22 5.0/VNote 6.2/VNote J5.02/VNote
MS-DOS
DOS
Note
Only English version supported.
Caution Ver.5.00 upper versions Ver.5.0 have task swap function, cannot used this software.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
APPENDIX RELATED DOCUMENTS
Some following related documents preliminary. Device Related Documents
Document Japanese English U11353E (this document) U11575E U10201E U10453E
Document Name
µPD753036 Data Sheet µPD75P3036 Data Sheet µPD753036 User's Manual
75XL Series Selection Guide
U11353J U11575J U10201J U10453J
Development Tool Related Documents
Document Japanese IE-75000 R/IE-75001-R User's Manual Hardware IE-75300-R-EM User's Manual EP-75336GC/GK-R User's Manual PG-1500 User's Manual RA75X Assembler Package User's Manual Software PG-1500 Controller User's Manual Operation Language Structured Assembler Preprocessor PC-9800 Series (MS-DOS) Base Series DOS) Base EEU-846 U11354J U10644J U11940J U12622J U12385J U12598J EEU-704 EEU-5008 English EEU-1416 U11354E U10644E U11940E U12622E U12385E U12598E EEU-1291 U10540E
Document Name
Other Documents
Document Japanese SEMICONDUCTOR SELECTION GUIDE Products Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Guide Microcontroller-Related Products Third Parties X13769X C10535J C11531J C10983J C11892J U11416J C10535E C11531E C10983E C11892E English
Document Name
Caution above related documents subject change without notice. design purpose, etc., sure latest documents.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
[MEMO]
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
[MEMO]
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
[MEMO]
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U11353EJ4V0DS00
µPD753036, 753036(A)
[MEMO]
MS-DOS either registered trademark trademark Microsoft Corporation United States and/or other countries. DOS, PC/AT, trademarks Corporation.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
information this document current June, 2000. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

4-BIT SINGLE-CHIP MICROCONTROLLER INTEGRATED CIRCUIT DESCRIP

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