DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE PM73
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
PM7344 S/UNI
S/UNI-MPH
SATURN QUAD T1/E1 MULTI-PHY USER NETWORK INTERFACE DEVICE
DATA SHEET
ISSUE JUNE 1998
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
PUBLIC REVISION HISTORY Issue Issue Date June 1998 August 1996 Details Change Data Sheet Reformatted Change Technical Content. Generated data sheet from PMC-940873, Doc, Issue released
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
CONTENTS FEATURES APPLICATIONS REFERENCES APPLICATION EXAMPLES BLOCK DIAGRAM. DESCRIPTION DIAGRAM DESCRIPTION FUNCTIONAL DESCRIPTION 9.10 9.11 9.12 9.13 DIGITAL RECEIVE INTERFACE (DRIF) PULSE DENSITY VIOLATION DETECTOR (PDVD). T1/E1 FRAMER (FRMR). ALARM INTEGRATOR (ALMI) INBAND LOOPBACK CODE DETECTOR (IBCD). PERFORMANCE MONITOR COUNTERS (PMON) ORIENTED CODE DETECTOR (RBOC) HDLC RECEIVER (RFDL) T1/E1 FRAMING INSERTIONS (TRAN) INBAND LOOPBACK CODE GENERATOR (XIBC). PULSE DENSITY ENFORCER (XPDE) ORIENTED CODE GENERATOR (XBOC). HDLC TRANSMITTER XFDL)
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21
DIGITAL TRANSMIT INTERFACE (DTIF) DIGITAL JITTER ATTENUATOR RECEIVE ACELL PROCESSOR (RXCP) RECEIVE CELL FIFO (RXFF) TRANSMIT ACELL PROCESSOR (TXCP). TRANSMIT CELL FIFO (TXFF) SATURN COMPATIBLE MULTI-PHY INTERFACE (MPHY) MICROPROCESSOR INTERFACE (MPIF)
REGISTER DESCRIPTION. NORMAL MODE REGISTER DESCRIPTION. 11.1 REGISTERS X49-X4FH: LATCHING PERFORMANCE DATA
TEST FEATURES DESCRIPTION 12.1 12.2 TEST MODE JTAG TEST PORT.
FUNCTIONAL TIMING OPERATION 14.1 14.2 USING JT2F USING DIGITAL JITTER ATTENUATOR 14.2.1 DEFAULT APPLICATION. 14.2.2 DATA BURST APPLICATION 14.3 JTAG SUPPORT 14.3.1 BOUNDARY SCAN CELLS
ABSOLUTE MAXIMUM RATINGS.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
CAPACITANCE D.C. CHARACTERISTICS MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS S/UNI-MPH TIMING CHARACTERISTICS ORDERING THERMAL INFORMATION MECHANICAL INFORMATION.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
LIST REGISTERS REGISTERS 000H, 100H, 200H 300H: RECEIVE CONFIGURATION. REGISTERS 001H, 101H, 201H 301H: TRANSMIT CONFIGURATION REGISTERS 002H, 102H, 202H 302H: DATALINK OPTIONS. REGISTERS 003H, 103H, 203H 303H: RECEIVE INTERFACE CONFIGURATION REGISTERS 004H, 104H, 204H 304H: TRANSMIT INTERFACE CONFIGURATION REGISTERS 005H, 105H, 205H 305H: RECEIVE DATA LINK. REGISTERS 006H, 106H, 206H 306H: TRANSMIT DATA LINK REGISTERS 007H, 107H, 207H 307H: TRANSMIT TIMING OPTIONS. REGISTERS 008H, 108H, 208H 308H: INTERRUPT SOURCE REGISTERS 009H, 109H, 209H 309H: INTERRUPT SOURCE REGISTERS 00AH, 10AH, 20AH 30AH: DIAGNOSTICS FIFO PARITY CONTROL REGISTER 00BH: MASTER TEST REGISTER 00CH: REVISION/CHIP ID/GLOBAL MONITORING UPDATE. REGISTERS 00DH SOURCE SELECTION/INTERRUPT REGISTERS 00EH CLOCK ACTIVITY MONITOR. REGISTER 010H, 110H, 210H 310H: CDRC CONFIGURATION. REGISTERS 011H, 111H, 211H 311H: CDRC INTERRUPT ENABLE REGISTERS 012H, 112H, 212H 312H: CDRC INTERRUPT STATUS REGISTERS 013H, 113H, 213H 313H: ALTERNATE LOSS SIGNAL STATUS REGISTERS 014H, 114H, 214H 314H: ALMI CONFIGURATION
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
REGISTERS 015H, 115H, 215H 315H: ALMI INTERRUPT ENABLE REGISTERS 016H, 116H, 216H 316H: ALMI INTERRUPT STATUS REGISTERS 017H, 117H, 217H 317H: ALMI ALARM DETECTION STATUS REGISTERS 018H, 118H, 218H 318H: DJAT INTERRUPT STATUS REGISTER 019H, 119H, 219H 319H: DJAT REFERENCE CLOCK DIVISOR (N1) CONTROL REGISTERS 01AH, 11AH, 21AH 31AH: DJAT OUTPUT CLOCK DIVISOR (N2) CONTROL REGISTERS 01BH, 11BH, 21BH 31BH: DJAT CONFIGURATION. REGISTERS 01CH, 11CH, 21CH 31CH: T1-FRMR CONFIGURATION. REGISTERS 01DH, 11DH, 21DH 31DH: T1-FRMR INTERRUPT ENABLE1 REGISTERS 01EH, 11EH, 21EH 31EH: T1-FRMR INTERRUPT STATUS. REGISTERS 020H, 120H, 220H 320H: E1-FRMR FRAME ALIGNMENT OPTIONS REGISTERS 021H, 121H, 221H 321H: E1-FRMR MAINTENANCE MODE OPTIONS REGISTERS 022H, 122H, 222H 322H: E1-FRMR FRAMING STATUS INTERRUPT ENABLE REGISTERS 023H, 123H, 223H 323H: E1-FRMR MAINTENANCE/ALARM STATUS INTERRUPT ENABLE REGISTERS 024H, 124H, 224H 324H: E1-FRMR FRAMING STATUS INTERRUPT INDICATION REGISTERS 025H, 125H, 225H 325H: E1-FRMR MAINTENANCE/ALARM STATUS INTERRUPT INDICATION REGISTERS 026H, 126H, 226H 326H: E1-FRMR FRAMING STATUS. REGISTERS 027H, 127H, 227H 327H: E1-FRMR MAINTENANCE/ALARM STATUS
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
REGISTERS 028H, 128H, 228H 328H: E1-FRMR INTERNATIONAL/NATIONAL BITS REGISTERS 02AH, 12AH, 22AH 32AH: E1-FRMR ERROR COUNTER REGISTERS 02BH, 12BH, 22BH 32BH: E1-FRMR ERROR COUNTER REGISTERS 030H, 130H, 230H 330H: RBOC ENABLE REGISTERS 031H, 131H, 231H 331H: RBOC CODE STATUS REGISTERS 034H, 134H, 234H 334H: XFDL CONFIGURATION REGISTERS 035H, 135H, 235H 335H: XFDL INTERRUPT STATUS REGISTERS 036H, 136H, 236H 336H: XFDL TRANSMIT DATA REGISTERS 038H, 138H, 238H 338H: RFDL CONFIGURATION REGISTERS 039H, 139H, 239H 339H: RFDL INTERRUPT CONTROL/STATUS REGISTERS 03AH, 13AH, 23AH 33AH: RFDL STATUS REGISTERS 03BH, 13BH, 23BH 33BH: RFDL RECEIVE DATA REGISTERS 03CH, 13CH, 23CH 33CH: IBCD CONFIGURATION. REGISTERS 03DH, 13DH, 23DH 33DH: IBCD INTERRUPT ENABLE/STATUS REGISTERS 03EH, 13EH, 23EH 33EH: IBCD ACTIVATE CODE REGISTERS 03FH, 13FH, 23FH 33FH: IBCD DEACTIVATE CODE. REGISTERS 040H, 140H, 240H 340H: T1-TRAN CONFIGURATION. REGISTERS 041H, 141H, 241H 341H: T1-TRAN ALARM TRANSMIT. REGISTERS 042H, 142H, 242H 342H: XIBC CONTROL REGISTERS 043H, 143H, 243H 343H: XIBC LOOPBACK CODE. REGISTERS 044H, 144H, 244H 344H: E1-TRAN CONFIGURATION
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
REGISTERS 045H, 145H, 245H 345H: E1-TRAN TRANSMIT ALARM/DIAGNOSTIC CONTROL. REGISTERS 046H, 146H, 246H 346H: E1-TRAN INTERNATIONAL/NATIONAL CONTROL. REGISTERS 048H, 148H, 248H 348H: PMON CONTROL/STATUS. REGISTERS 049H, 149H, 249H 349H: PMON FRAMING ERROR COUNT. REGISTERS 04AH, 14AH, 24AH 34AH: PMON BLOCK ERROR COUNT REGISTERS 04BH, 14BH, 24BH 34BH: PMON BLOCK ERROR COUNT REGISTERS 04CH, 14CH, 24CH 34CH: PMON ERROR COUNT REGISTERS 04DH, 14DH, 24DH 34DH: PMON ERROR COUNT MSB. REGISTERS 04EH, 14EH, 24EH 34EH: PMON LINE CODE VIOLATION COUNT REGISTERS 04FH, 14FH, 24FH 34FH: PMON LINE CODE VIOLATION COUNT REGISTERS 055H, 155H, 255H 355H: PDVD INTERRUPT ENABLE/STATUS REGISTERS 057H, 157H, 257H 357H: XBOC CODE REGISTERS 059H, 159H, 259H 359H: XPDE INTERRUPT ENABLE/STATUS REGISTERS 064H, 164H, 264H 364H: RXCP UNCORRECTABLE ERROR EVENT COUNT REGISTERS 065H, 165H, 265H 365H: RXCP UNCORRECTABLE ERROR EVENT COUNT REGISTERS 068H, 168H, 268H 368H: RXCP CORRECTABLE ERROR EVENT COUNT
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
REGISTERS 069H, 169H, 269H 369H: RXCP CORRECTABLE ERROR EVENT COUNT REGISTERS 06AH, 16AH, 26AH 36AH: RXCP IDLE/UNASSIGNED CELL COUNT REGISTERS 06BH, 16BH, 26BH 36BH: RXCP IDLE/UNASSIGNED CELL COUNT REGISTERS 06CH, 16CH, 26CH 36CH: RXCP RECEIVE CELL COUNT LSB. REGISTERS 06DH, 16DH, 26DH 36DH: RXCP RECEIVE CELL COUNT MSB. REGISTERS 06EH, 16EH, 26EH 36EH: TXCP TRANSMIT CELL COUNT LSB. REGISTERS 06FH, 16FH, 26FH 36FH: TXCP TRANSMIT CELL COUNT MSB. REGISTERS 070H, 170H, 270H 370H: RXCP CONTROL. REGISTERS 071H, 171H, 271H 371H: RXCP FRAMING CONTROL REGISTERS 072H, 172H, 272H 372H: RXCP INTERRUPT ENABLE/STATUS REGISTERS 073H, 173H, 273H 373H: RXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTERS 074H, 174H, 274H 374H: RXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTERS 075H, 175H, 275H 375H: RXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTERS 076H, 176H, 276H 376H: RXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTERS 077H, 177H, 277H 377H: RXCP IDLE/UNASSIGNED CELL MASK: OCTET REGISTERS 078H, 178H, 278H 378H: RXCP IDLE/UNASSIGNED CELL MASK: OCTET
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
REGISTERS 079H, 179H, 279H 379H: RXCP IDLE/UNASSIGNED CELL MASK: OCTET REGISTERS 07AH, 17AH, 27AH 37AH: RXCP IDLE/UNASSIGNED CELL MASK: OCTET REGISTERS 07BH, 17BH, 27BH 37BH: RXCP USER-PROGRAMMABLE MATCH PATTERN: OCTET REGISTERS 07CH, 17CH, 27CH 37CH: RXCP USER-PROGRAMMABLE MATCH PATTERN: OCTET REGISTERS 07DH, 17DH, 27DH 37DH: RXCP USER-PROGRAMMABLE MATCH PATTERN: OCTET REGISTERS 07EH, 17EH, 27EH 37EH: RXCP USER-PROGRAMMABLE MATCH PATTERN: OCTET REGISTERS 07FH, 17FH, 27FH 37FH: RXCP USER-PROGRAMMABLE MATCH MASK: OCTET. REGISTERS 080H, 180H, 280H 380H: RXCP USER-PROGRAMMABLE MATCH MASK: OCTET. REGISTERS 081H, 181H, 281H 381H: RXCP USER-PROGRAMMABLE MATCH MASK: OCTET. REGISTERS 082H, 182H, 282H 382H: RXCP USER-PROGRAMMABLE MATCH MASK: OCTET. REGISTERS 083H, 183H, 283H 383H: RXCP CONTROL/STATUS REGISTERS 084H, 184H, 284H 384H: RXCP COUNT THRESHOLD1 REGISTERS 088H, 188H, 288H 388H: TXCP CONTROL REGISTERS 089H, 189H, 289H 389H: TXCP INTERRUPT ENABLE/STATUS CONTROL REGISTERS 08AH, 18AH, 28AH 38AH: TXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTERS 08BH, 18BH, 28BH 38BH: TXCP IDLE/UNASSIGNED CELL PATTERN: OCTET
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
REGISTERS 08CH, 18CH, 28CH 38CH: TXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTERS 08DH, 18DH, 28DH 38DH: TXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTERS 08EH, 18EH, 28EH 38EH: TXCP IDLE/UNASSIGNED CELL PATTERN: OCTET REGISTERS 08FH, 18FH, 28FH 38FH: TXCP IDLE/UNASSIGNED CELL PAYLOAD. REGISTER 00BH: MASTER TEST
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
LIST FIGURES FIGURE EXAMPLE MULTI-PHY AUNI FIGURE EXAMPLE PORT CARRYING MULTIPLEXED AUNI SIGNALS. FIGURE EXAMPLE MULTI-PHY ADDRESSING APPLICATION FIGURE NORMAL OPERATING MODE. FIGURE LOOPBACK MODES. FIGURE JITTER TOLERANCE SPECIFICATION. FIGURE JITTER TOLERANCE SPECIFICATION (ALGSEL FIGURE JITTER TOLERANCE SPECIFICATION (ALGSEL FIGURE JITTER TOLERANCE. FIGURE JITTER TOLERANCE FIGURE DJAT MINIMUM JITTER TOLERANCE XCLK ACCURACY CASE) FIGURE DJAT MINIMUM JITTER TOLERANCE XCLK ACCURACY CASE) FIGURE JITTER TRANSFER FIGURE JITTER TRANSFER. FIGURE CELL DELINEATION STATE DIAGRAM. FIGURE VERIFICATION STATE DIAGRAM FIGURE TRANSMIT TIMING OPTIONS FIGURE ARBITRARY RATE TRANSMIT INTERFACE FIGURE ARBITRARY RATE RECEIVE INTERFACE FIGURE (6.312 MBIT/S) TRANSMIT INTERFACE
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
FIGURE (6.312 MBIT/S) RECEIVE INTERFACE. FIGURE DIRECT-PHY SELECTION TRANSMIT CELL INTERFACE (MPHEN FIGURE DIRECT-PHY SELECTION RECEIVE CELL INTERFACE (MPHEN FIGURE MULTI-PHY ADDRESSING TRANSMIT CELL INTERFACE (MPHEN FIGURE MULTI-PHY ADDRESSING RECEIVE CELL INTERFACE (MPHEN FIGURE TYPICAL DATA FRAME. FIGURE RFDL NORMAL DATA ABORT SEQUENCE. FIGURE RFDL FIFO OVERRUN FIGURE XFDL NORMAL DATA SEQUENCE FIGURE XFDL UNDERRUN SEQUENCE FIGURE FRAMER EXAMPLE. FIGURE BOUNDARY SCAN ARCHITECTURE. FIGURE CONTROLLER FINITE STATE MACHINE FIGURE INPUT OBSERVATION CELL (IN_CELL) FIGURE OUTPUT CELL (OUT_CELL). FIGURE BIDIRECTIONAL CELL (IO_CELL). FIGURE LAYOUT OUTPUT ENABLE BIDIRECTIONAL CELLS. FIGURE MICROPROCESSOR READ ACCESS TIMING FIGURE MICROPROCESSOR WRITE ACCESS TIMING FIGURE XCLK INPUT TIMING JITTER ATTENUATION FIGURE TCLKI INPUT TIMING
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
FIGURE DIGITAL RECEIVE INTERFACE INPUT TIMING DIAGRAM. FIGURE TRANSMIT DATA LINK INPUT TIMING DIAGRAM FIGURE RECEIVE DATA LINK OUTPUT TIMING DIAGRAM. FIGURE TRANSMIT INTERFACE OUTPUT TIMING DIAGRAM FIGURE TRANSMIT DATA LINK INTERFACE OUTPUT TIMING DIAGRAM FIGURE RECEIVE DATA LINK INTERFACE OUTPUT TIMING DIAGRAM FIGURE TRANSMIT CELL INTERFACE TIMING DIAGRAM. FIGURE RECEIVE CELL INTERFACE TIMING DIAGRAM FIGURE JTAG PORT INTERFACE TIMING DIAGRAM
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
LIST TABLES TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE NORMAL MODE REGISTER MEMORY READING S/UNI-MPH INPUTS TEST MODE CONTROLLING OUTPUTS TEST MODE BOUNDARY SCAN REGISTER INSTRUCTION REGISTER. MICROPROCESSOR READ ACCESS (FIGURE MICROPROCESSOR WRITE ACCESS (FIGURE XCLK INPUT JITTER ATTENUATION (FIGURE 40). TCLKI INPUT (FIGURE 41).
TABLE DIGITAL RECEIVE INTERFACE INPUT TIMING (FIGURE TABLE TRANSMIT DATA LINK INPUT TIMING (FIGURE TABLE RECEIVE DATA LINK OUTPUT TIMING (FIGURE TABLE TRANSMIT INTERFACE OUTPUT TIMING (FIGURE 45). TABLE TRANSMIT DATA LINK INTERFACE OUTPUT TIMING (FIGURE TABLE RECEIVE DATA LINK INTERFACE OUTPUT TIMING (FIGURE TABLE TRANSMIT CELL INTERFACE TIMING (FIGURE TABLE RECEIVE CELL INTERFACE TIMING (FIGURE 49). TABLE JTAG PORT INTERFACE TIMING (FIGURE TABLE S/UNI-MPH ORDERING INFORMATION TABLE S/UNI-MPH THERMAL INFORMATION
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
FEATURES Single chip quad AUser Network Interface operating 1.544 Mbit/s 2.048 Mbit/s. Implements AForum User Network Interface Specification V3.1 transmission rates. Implements Aphysical layer Broadband ISDN according ITU-T Recommendation I.432. Implements direct cell mapping into transmission systems according ITU-T Recommendation G.804. Implements (with external framer device) direct cell mapping into (6.312 Mbit/s) transmission systems according ITU-T Recommendation G.804. Integrates quad full-featured T1/E1 framer/transmitter terminating four duplex 1.544 Mbit/s DS-1 signals four duplex 2.048 Mbit/s signals. Integrates quad Acell processor mapping Acells into other arbitrary rate streams using (Header Check Sequence Error Correction) cell delineation. Provides Saturn Compatible Interface (SCI-PHYTM) FIFO buffers both transmit receive paths with parity support Utopia Level compatible multi-PHY control signals. Software compatible with PM4341A T1XC, PM6341 E1XC, PM7345 S/UNI-PDH. Provides standard signal P1149.1 JTAG test port boundary scan board test purposes. Provides generic 8-bit microprocessor interface configuration, control, status monitoring. power, +5V, CMOS technology rectangular (14mm 20mm) PQFP package.
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
framer section: Recovers clock data using digital phase locked loop high jitter tolerance. direct clock input provided allow clock recovery bypassed. Accepts dual rail single rail digital inputs. Supports B8ZS line code. Accepts gapped data streams support higher rate demultiplexing. Frames format signals. Provides loss signal detection, red, yellow, alarm detection. Red, yellow, alarms integrated industry specifications. Detects violations ANSI T1.403 12.5% pulse density rule over moving window. Provides programmable framed unframed in-band loopback code detection. Supports line path performance monitoring according ANSI specifications. Accumulators provided counting: CRC-6 errors second; Framing errors second; Line code violations 4095 second; Loss frame change frame alignment events second.
Provides bit-oriented code detection, HDLC interface terminating data link. Supports polled, interrupt-driven, servicing HDLC interface. Extracts data link mode.
transmitter section: Formats data format signals.
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Detects violations ANSI T1.403 12.5% pulse density rule over moving window optionally stuffs ones maintain minimum ones density. Allows insertion framed unframed in-band loopback code sequences. Allows insertion data link mode. Supports transmission alarm indication signal (AIS) yellow alarm signal formats. Provides bit-oriented code generation HDLC interface generating data link. Supports polled, interrupt-driven, servicing HDLC interface. Supports B8ZS line code. Provides dual rail single rail digital output signals.
receiver section: Recovers clock data using digital phase locked loop high jitter tolerance. direct clock input provided allow clock recovery bypassed. Accepts dual rail single rail digital inputs. Supports HDB3 line code. Accepts gapped data streams support higher rate demultiplexing. Frames G.704 2048 kbit/s signal within Frames multiframe alignment when enabled. Frames signalling multiframe alignment when enabled. Provides loss signal detection, indicates loss frame alignment (OOF), loss signalling multiframe alignment loss multiframe alignment. Supports line path performance monitoring according ITU-T recommendations. Accumulators provided counting:
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
CRC-4 errors 1000 second; block errors 1000 second; Frame sync errors second; Line code violations 8191 second;
Indicates reception remote alarm. Indicates reception alarm indication signal (AIS). Declares alarms using Q.516 recommended integration periods. Provides HDLC interface terminating data link. Supports polled, interrupt-driven, servicing HDLC interface. Optionally extracts data link from timeslot kbit/s), which used receive common channel signalling, from combination national bits timeslot non-frame alignment signal frames kbit/s kbit/s).
transmitter section: Formats data create G.704 2048 kbit/s signal. Optionally inserts signalling multiframe alignment signal. Optionally inserts multiframe structure including optional transmission block errors. Supports transmission alarm indication signal (AIS), timeslot AIS, remote alarm signal remote multiframe alarm signal. Provides HDLC interface generating data link. Supports polled, interrupt-driven, servicing HDLC interface. Optionally inserts data link into timeslot kbit/s), which used transmit common channel signalling, into combination national bits timeslot non-frame alignment signal frames kbit/s kbit/s). Supports HDB3 line code. Provides dual rail single rail digital output signals.
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
receive Acell processor section: Provides Aframing using cell delineation. Provides cell descrambling, header check sequence (HCS) error detection, idle/unassigned cell filtering, accumulates number received idle/unassigned cells, number received cells written FIFO, number errors. Provides four cell FIFO rate decoupling between line, higher layer processing entity. Provides synchronous 8-bit wide FIFO with receive byte parity generation timing compatible with Saturn Compatible Interface Specification (SCI-PHYTM) multi-PHY interfaces. four receive Acell processors serviced single 8-bit wide multiPHY interface.
transmit Acell processor section: Provides optional Acell scrambling, generation/insertion, programmable idle/unassigned cell insertion, diagnostics features accumulates transmitted cells read from FIFO. Provides four cell FIFO rate decoupling between line, higher layer processing entity. Provides synchronous 8-bit wide FIFO with transmit byte parity checking timing compatible with Saturn Compatible Interface Specification (SCI-PHYTM) multi-PHY interfaces. four transmit Acell processors serviced single 8-bit wide multiPHY interface.
Loopback features: Provides line loopback, payload loopback, diagnostic loopback.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
APPLICATIONS ASwitches Supporting Ports ASwitches Supporting Ports Carrying Multiplexed Signals ASwitches Supporting STS-3/STM-1 Other SONET/SDH Ports Carrying Tributary Mapped Signals ACustomer Premise Equipment Supporting Multiple Ports
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
REFERENCES American National Standard Telecommunications Digital Hierarchy Electrical Interfaces, ANSI T1.102-1992. American National Standard Telecommunications Digital Hierarchy Formats Specifications, ANSI T1.107-1991. American National Standard Telecommunications Carrier Customer Installation Metallic Interface Specification, ANSI T1.403-1989 American National Standard Telecommunications Integrated Services Digital Network (ISDN) Primary Rate- Customer Installation Metallic Interfaces Layer Specification, ANSI T1.408-1990 Bell Communications Research Rate Digital Service Monitoring Unit Functional Specification, TA-TSY-000147, Issue October, 1987. Bell Communications Research Alarm Indication Signal Requirements Objectives, TR-TSY-000191 Issue 1986. Bell Communications Research Extended Superframe Format Interface Specification, TR-TSY-000194 Issue December 1987. (Replaced TRTSY-000499) Bell Communications Research Transport Systems Generic Requirements (TSGR): Common Requirement, TR-TSY-000499, Issue December, 1989. AT&T Requirements Interfacing Digital Terminal Equipment Services Employing Extended Superframe Format, PUB54016, October 1984. AT&T, 62411 Accunet T1.5 "Service Description Interface Specification" December, 1990. CCITT Book, Recommendation Q.516, "Operations maintenance functions", Vol. Fasc. VI.5, 1984. ITU-T Recommendation G.703, "Physical/Electrical Characteristics Hierarchical Digital Interfaces", Rev.1, 1991. ITU-T Recommendation G.704, "Synchronous Frame Structures Used Primary Secondary Hierarchical Levels", Rev.1, 1991.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
ITU-T Recommendation G.706, "Frame Alignment Cyclic Redundancy Check (CRC) Procedures Relating Basic Frame Structures Defined Recommendation G.704", Rev.1, 1991. ITU-T Recommendation G.737, "Characteristics External Access Equipment Operating 2048 kbit/s Offering Synchronous Digital Access kbit/s and/or kbit/s", Blue Book Fasc. III.4, 1988. ITU-T Recommendation G.738, "Characteristics Primary Multiplex Equipment Operating 2048 kbit/s Offering Synchronous Digital Access kbit/s and/or kbit/s", Blue Book Fasc. III.4, 1988. ITU-T Recommendation G.739, "Characteristics External Access Equipment Operating 2048 kbit/s Offering Synchronous Digital Access kbit/s and/or kbit/s", Blue Book Fasc. III.4, 1988. ITU-T Recommendation G.742, "Second Order Digital Multiplex Equipment Operating 8448 kbit/s Using Positive Justification", Blue Book Fasc. III.4, 1988. ITU-T Recommendation G.821, "Error Performance International Digital Connection Forming Part Integrated Services Digital Network", Blue Book Fasc. III.5, 1988. ITU-T Recommendation G.823, "The Control Jitter Wander Within Digital Networks Which Based 2048 kbit/s Hierarchy", 1993. ITU-T Recommendation O.151, "Error Performance Measuring Equipment Operating Primary Rate Above", Rev. Oct. 1992. CCITT Blue Book, Recommendation O.162, "Equipment Perform Service Monitoring 2048 kbit/s Signals", Vol. Fascicle IV.4, 1988. ITU-T, Recommendation I.432 "B-ISDN User-Network Interface Physical Layer Specification", August 1992. ITU-T, Draft Recommendation G.804 "ACell Mapping into Plesiochronous Digital Hierarchy (PDH)", January 1993. ITU-T, Draft Recommendation G.832 "Transport Elements Networks: Frame Multiplexing Structures", January 1993. ETSI DE/TM-1015 "Transmission Multiplexing (TM); Generic Functional Requirements Transmission Equipment, Part Generic Processes Performance", Version 1.0, November, 1993.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
AForum, V3.1, August, 1994 "AUser-Network Interface Specification" AForum, Level V2.00 APHY Data Path Interface", February 1994. AForum, Level V0.8 "UTOPIA, ATM-PHY Interface Specification", April 1995. PMC-Sierra, Inc., "(SCI-PHYTM) SATURN Compliant Interface APHY Devices", Issue July 1994.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
APPLICATION EXAMPLES Figure Example Multi-PHY AUNI
1.544 Transmit Reference Clock
PM7344 S/UNI-MPH
SCI-PHY Multi-PHY ACell
PM4314 QDSX Quad DSX-1/E1 Analog Line Interface
Quad T1/E1 Multi-PHY User Network Interface
DSX-1 Analog Interfaces
Generic Microprocessor
12.352
Crystal Oscillator Clock 37.056
Example shows PM7344 S/UNI-MPH used with PM4314 QDSX implement quad T1/E1 where signals presented DSX-1 electrical interfaces. this example, DSX-1 line interface functions provided QDSX framing functions provided S/UNI-MPH. Note that many other standard DSX-1 line interface devices also compatible with S/UNI-MPH. S/UNI-MPH also provides Acell processing functions associated with layer, including implementation SCI-PHY multi-PHY interface Alayer device(s). combination QDSX device with S/UNI-MPH allows both ANSI/ITU compliant DSX1/E1 analog signals AForum G.804 compliant DS1/E1 digital signals processed. G.804 specifications define Acell mappings variety transmission formats, including 1.544 Mbit/s 2.048 Mbit/s formats.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Figure Signals
Example Port Carrying Multiplexed AUNI
1.544 Transmit Reference Clock
6.312 Optional Transmit Reference Clock
44.736 Transmit Reference Clock
DSX-3 Line Interface With Clock Recovery
DSX-3 Analog Interface
PM7344 S/UNI-MPH Quad T1/E1 Multi-PHY User Network Interface
PM8313 D3MX Integrated Multiplexer
12.352 1.544
PM7344 S/UNI-MPH
SCI-PHYMulti-PHY ACell
Quad T1/E1 Multi-PHY User Network Interface
Generic Microprocessor
Crystal Oscillator Clock 12.352
Example shows seven PM7344 S/UNI-MPH devices used with PM8313 D3MX device generic DSX-3 device being used implement port where carries multiplex signals. this example, each S/UNI-MPH provides four duplex signals D3MX device which, turn, performs asynchronous multiplex demultiplex function required these into signal. D3MX traditional format C-bit parity format when performing this multiplex. Note that D3MX also configured G.747 multiplexing three signals into each seven signals within overall signal. Many generic DSX-3 line interface unit devices used with D3MX implement DSX-3 electrical interface high speed line side such system. Each S/UNI-MPH device implements function four streams. seven S/UNI-MPH devices serviced common Alayer device through shared (SCI-PHY multi-PHY bus.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Figure
Example Multi-PHY Addressing Application
TSOC TDAT[7:0] TXPRTY TCAMPH TWA[1:0] TWRMPHB TFCLK
ORDENB[1] ODAT[7:0]
load
3-to-N decoder
Single-PHY Multi-PHY interface switch
UTOPIA OPRTY[0] LEVEL OSOC COMPLIANT OFCLK EGRESS OAVALID DEVICE OADDR[4:0]
OCA[1]
S/UNI-MPH RSOC RDAT[7:0] RXPRTY RCAMPH RRA[1:0] RRDMPHB RFCLK
OMASTER OPOLL OBUS8 OTSEN N-to-1
TSOC TDAT[7:0] TXPRTY TCAMPH TWA[1:0] TWRMPHB TFCLK RSOC RDAT[7:0] RXPRTY RCAMPH RRA[1:0] RRDMPHB RFCLK
S/UNI-MPH
Backward Loopback Cells
load 3-to-N decoder
IWRENB[1] IDAT[7:0]
Single-PHY Multi-PHY interface switch
UTOPIA IPRTY[0] ISOC LEVEL COMPLIANT IFCLK IAVALID INGRESS IADDR[4:0] DEVICE ICA[1]
IMASTER IPOLL IBUS8
TSOC TDAT[7:0] TXPRTY TCAMPH TWA[1:0] TWRMPHB TFCLK RSOC RDAT[7:0] RXPRTY RCAMPH RRA[1:0] RRDMPHB RFCLK
N-to-1
S/UNI-MPH
Example shows (where number from PM7344 S/UNI-MPH devices used with UTOPIA Level compliant ingress egress devices. S/UNI-MPH supports address polling sampling least significant address bits (RRA[1:0] TWA[1:0]) generating cell available status selected entity. also holds last state RRA[1:0] TWA[1:0] before assertion RRDMPHB TWRMPHB, respectively, thus latching address resolved polling process. only support logic that required select between S/UNI-MPH devices.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Note that oscillator frequency less than equal MHz. DS-1 case data rate 1.536 Mbits/s (1.544 Mbits/s payload bits frame bits frame) each DS-1 port. Thus, aggregate throughput less than 6.144 Mbyte/s with DS-1 ports; therefore, clock oscillator frequency MHz.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
BLOCK DIAGRAM Figure Normal Operating Mode
TDLCLK/TDLUDR[4:1] TDLSIG/TDLINT[4:1]
TCLKI TFPI/TOHI
TRSTB
XCLK
HDLC Transmitter
Oriented Code Transmitter T1/E1 Framing Insertion Inband Loopback Code Generator
JTAG Test Access Port
TCLKO[4:1] TDP/TDD[4:1] TDN/TOHO[4:1]
Digital Transmit Interface
Pulse Density Enforcer
ACell Processor
Cell FIFO MultiPHY
TSOC TDAT[7:0] TXPRTY TCA[4:1] TCAMPH/TWRENB[4] TWA[1]/TWRENB[3] TWA[0]/TWRENB[2] TWRMPHB /TWRENB[1] TFCLK RSOC RDAT[7:0] RXPRTY RCA[4:1] RCAMPH/RRDENB[4] RRA[1]/RRDENB[3] RRA[0]/RRDENB[2] RRDMPHB /RRDENB[1] RFCLK
RCLKI[4:1] RDP/RDD[4:1] RDN/RLCV/ ROH[4:1]
Digital Receive Interface Pulse Density Violation Detector
T1/E1 Framer Inband Oriented Performance Code Monitor Code Detector Receiver
ACell Processor
Cell FIFO
HDLC Receiver
Alarms Integrator
Microprocessor
D[7:0] A[10:0] RSTB INTB
RDLSIG/RDLINT[4:1]
Figure
Loopback Modes
RDLCLK/RDLEOM[4:1]
HDLC Transmitter
Oriented Code Transmitter T1/E1 Framing Insertion Inband Loopback Code Generator PAYLOAD LOOPBACK T1/E1 Framer ACell Processor ACell Processor
JTAG Test Access Port
Digital Transmit Interface LINE LOOPBACK
Pulse Density Enforcer DIAGNOSTIC LOOPBACK
Cell FIFO MultiPHY
Digital Receive Interface Pulse Density Violation Detector
Cell FIFO
HDLC Receiver
Oriented Code Receiver
Performance Monitor
Inband Code Detector
Alarms Integrator
Microprocessor
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MPHEN
RCLKO
PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
DESCRIPTION PM7344 SATURN Quad T1/E1 Multi-PHY User Network Interface (S/UNIMPH) monolithic integrated circuit that implements T1/E1 processing Amapping functions four 1.544 Mbit/s 2.048 Mbit/s AUser Network Interfaces. also used conjunction with external framing devices, implement Auser network interfaces other rates. example, quad (6.312 Mbit/s) interface realized with four external framers single S/UNI-MPH. fully compliant with both ANSI requirements AForum specifications. S/UNI-MPH software configurable, allowing feature selection without changes external wiring. receive side, when configured processing, S/UNI-MPH recovers clock data configured frame either common DS-1 signal formats; ESF. Clock recovery also bypassed. S/UNIMPH also supports detection various alarm conditions such loss signal, pulse density violation, alarm, yellow alarm, alarm. S/UNI-MPH detects indicates presence yellow patterns also integrates yellow, red, alarms industry specifications. Performance monitoring with accumulation CRC-6 errors, framing errors, line code violations, loss frame events provided. S/UNI-MPH also detects presence in-band loopback codes, oriented codes, detects terminates HDLC messages data link. receive side, when configured processing, S/UNI-MPH recovers clock data configured frame basic G.704 2048 kbit/s signal also frame signalling multiframe alignment signal multiframe alignment signal. Clock recovery also bypassed. S/UNI-MPH also supports detection various alarm conditions such loss signal, loss frame, loss signalling multiframe, loss multiframe, reception remote alarm signal, remote multiframe alarm signal, alarm indication signal, timeslot alarm indication signal. S/UNI-MPH detects indicates presence remote alarm patterns also integrates alarms industry specifications. Performance monitoring with accumulation CRC-4 errors, block errors, framing errors, line code violation provided. S/UNI-MPH also detects terminates HDLC messages data link. data link extracted from timeslot extracted from national bits.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
both configurations, S/UNI-MPH interprets received frame alignment extracts transmission format payload which carries received Acell payload. S/UNI-MPH frames Apayload using cell delineation. error correction optionally provided. Idle/unassigned cells dropped according programmable filter. Cells also dropped upon detection uncorrectable header check sequence error. Acell payloads descrambled. Valid, assigned cells written four cell FIFO buffer. These cells read from FIFO using synchronous wide datapath interface with cellbased handshake. Counts received Acell headers that errored uncorrectable, those that errored correctable passed cells accumulated independently performance monitoring purposes. multi-PHY interface allows four receive FIFOs (one each port) serviced single wide bus. transmit side, when configured processing, S/UNI-MPH generates framing formats. S/UNI-MPH also generate in-band loopback codes, oriented codes, transmit HDLC messages data link. transmit side, when configured processing, S/UNI-MPH generates framing basic G.704 2048 kbit/s signal. signalling multiframe alignment signal optionally inserted multiframe structure optionally inserted. HDLC messages data link transmitted. data link inserted into timeslot inserted into national bits. both configurations, S/UNI-MPH generates transmitted frame inserts transmit Acell payload into transmission format payload appropriately. Acells written internal programmable-length 4-cell FIFO using synchronous wide datapath interface. Idle/unassigned cells automatically inserted when internal FIFO contains less than cell. S/UNI-MPH generates header check sequence scrambles payload Acells. Each these transmit Acell processing functions enabled bypassed. multi-PHY interface allows four transmit FIFOs (one each port) serviced single wide bus.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
S/UNI-MPH configured, controlled monitored generic 8-bit microprocessor interface. S/UNI-MPH also provides standard signal P1149.1 JTAG test port boundary scan board test purposes.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
DIAGRAM
A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] VDD_DC[3] VSS_DC[3] RSTB MPHEN XCLK TCLKI TFPI/TOHI TRSTB
RDP[1]/RDD[1] RDN[1]/RLCV[1]/ROH[1] RCLKI[1] RDP[2]/RDD[2] RDN[2]/RLCV[2]/ROH[2] RCLKI[2] RDP[3]/RDD[3] RDN[3]/RLCV[3]/ROH[3] RCLKI[3] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] VDD_AC[0] VSS_AC[0] VDD_DC[0] VSS_DC[0] TCLKO[1] TDP[1]/TDD[1] TDN[1]/TOHO[1] TCLKO[2] TDP[2]/TDD[2] TDN[2]/TOHO[2] TDLCLK[1]/TDLUDR[1] TDLCLK[2]/TDLUDR[2] TDLCLK[3]/TDLUDR[3] TDLCLK[4]/TDLUDR[4] INTB RDP[4]/RDD[4] RDN[4]/RLCV[4]/ROH[4] RCLKI[4] TSOC TXPRTY TFCLK
Index
PM7344 S/UNI-MPH View
RDLSIG[4]/RDLINT[4] RDLSIG[3]/RDLINT[3] RDLSIG[2]/RDLINT[2] RDLSIG[1]/RDLINT[1] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0] VDD_AC[2] VSS_AC[2] VDD_DC[2] VSS_DC[2] RXPRTY RSOC RCAMPH/RRDENB[4] RRA[1]/RRDENB[3] RRA[0]/RRDENB[2] RRDMPHB/RRDENB[1] RDLCLK[4]/RDLEOM[4] RDLCLK[3]/RDLEOM[3] RDLCLK[2]/RDLEOM[2] RDLCLK[1]/RDLEOM[1] RFCLK TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TWRMPHB/TWRENB[1]
TDLSIG[1]/TDLINT[1] TDLSIG[2]/TDLINT[2] TDLSIG[3]/TDLINT[3] TDLSIG[4]/TDLINT[4] TDP[3]/TDD[3] TDN[3]/TOHO[3] TCLKO[3] TDP[4]/TDD[4] TDN[4]/TOHO[4] TCLKO[4] RCLKO VDD_AC[1] VSS_AC[1] VDD_DC[1] VSS_DC[1] TCA[1] TCA[2] TCA[3] TCA[4] RCA[1] RCA[2] RCA[3] RCA[4] TCAMPH/TWRENB[4] TWA[1]/TWRENB[3] TWA[0]/TWRENB[2]
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
DESCRIPTION Name RDP[4] RDP[3] RDP[2] RDP[1]/ Type Input Function Receive Digital Positive Line Pulse (RDP). This signal available when S/UNI-MPH configured receive dual-rail formatted data. input enabled either waveforms. When enabled NRZ, enabled sampled rising falling edge RCLKI. When enabled clock recovered from inputs. Receive Digital Data (RDD). When S/UNI-MPH configured receive single-rail data when T1/E1 framers bypassed, this signal contains receive data stream. enabled sampled rising falling edge RCLKI.
RDD[4] RDD[3] RDD[2] RDD[1]
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name RDN[4] RDN[3] RDN[2] RDN[1]/
Type Input
Function Receive Digital Negative Line Pulse (RDN). This signal available when S/UNI-MPH configured receive dual-rail formatted data. input enabled either waveforms. When enabled NRZ, enabled sampled rising falling edge RCLKI. When enabled clock recovered from inputs.
RLCV[4] RLCV[3] RLCV[2] RLCV[1]/
Receive Line Code Violation Indication (RLCV). When S/UNI-MPH configured receive single-rail data, this signal contains line code violation indications that detected upstream line interface unit (LIU). RLCV enabled sampled rising falling edge RCLKI. Receive Overhead Mask (ROH). When S/UNI-MPH configured bypass T1/E1 framers, this signal indicates framing overhead receive stream, thus allowing S/UNI-MPH provide user network interface arbitrary rates (such 6.312 Mbit/s rate). configured active high active low, enabled sampled rising falling edge RCLKI.
ROH[4] ROH[3] ROH[2] ROH[1]
RCLKI[4] RCLKI[3] RCLKI[2] RCLKI[1]
Input
Receive Line Clock Input (RCLKI). This signal externally recovered line clock that enabled sample inputs rising falling edge when input format enabled dual-rail NRZ; sample RLCV/ROH inputs rising falling edge when input format enabled single-rail, when T1/E1 framers bypassed. RCLKI must operate frequencies less than equal MHz.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name RCLKO
Type Output
Function Receive Clock Output (RCLKO). This signal recovered from inputs input format dual-rail RZ), from RCLKI input input format T1/E1 framers bypassed). four sets RDP/RDN RCLKI signals selected source RCLKO using internal registers. Receive Data Link Signal (RDLSIG). RDLSIG signal available this when internal HDLC receiver (RFDL) disabled from use. When S/UNI-MPH configured receive T1-ESF formatted data, RDLSIG contains data stream extracted from facility data link; when S/UNI-MPH configured receive T1-SF formatted data, RDLSIG output held low; when S/UNIMPH configured receive formatted data, RDLSIG contains data stream extracted from timeslot data stream made combination national bits. RDLSIG updated falling edge RDLCLK. Receive Data Link Interrupt (RDLINT). RDLINT signal available this when RFDL enabled. RDLINT goes high when event occurs which changes status HDLC receiver.
RDLSIG[4] RDLSIG[3] RDLSIG[2] RDLSIG[1]/
Output
RDLINT[4] RDLINT[3] RDLINT[2] RDLINT[1]
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name RDLCLK[4] RDLCLK[3] RDLCLK[2] RDLCLK[1]/
Type Output
Function Receive Data Link Clock (RDLCLK). RDLCLK signal available this when internal HDLC receiver (RFDL) disabled from use. RDLCLK used process data stream contained RDLSIG. When S/UNIMPH configured receive T1-SF formatted data, when T1/E1 framers bypassed, RDLCLK held low. other formats rising edge RDLCLK used sample data RDLSIG. Receive Data Link Message (RDLEOM). RDLEOM signal available this when RFDL enabled. RDLEOM goes high when last byte received sequence read from RFDL FIFO buffer, when FIFO buffer overrun.
RDLEOM[4] RDLEOM[3] RDLEOM[2] RDLEOM[1]
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name TDLSIG[4] TDLSIG[3] TDLSIG[2] TDLSIG[1]/
Type
Function Transmit Data Link Signal (TDLSIG). TDLSIG signal input this when internal HDLC transmitter (XFDL) disabled from use. TDLSIG source data stream inserted into data link. When S/UNI-MPH configured transmit T1-ESF formatted data, TDLSIG contains data stream inserted facility data link; when S/UNI-MPH configured transmit T1-SF formatted data, TDLSIG ignored; when S/UNI-MPH configured transmit formatted data, TDLSIG contains data stream inserted timeslot data stream inserted combination national bits. TDLSIG sampled rising edge TDLCLK. Transmit Data Link Interrupt (TDLINT). TDLINT signal output this when XFDL enabled. TDLINT goes high when last data byte written XFDL been transmission processor intervention required either write control information message, provide more data.
TDLINT[4] TDLINT[3] TDLINT[2] TDLINT[1]
TDLCLK[4] TDLCLK[3] TDLCLK[2] TDLCLK[1]/
Output
Transmit Data Link Clock (TDLCLK). TDLCLK signal available this when internal HDLC transmitter (XFDL) disabled from use. rising edge TDLCLK used sample data stream contained TDLSIG input. When S/UNI-MPH configured transmit T1-SF formatted data, when T1/E1 framers bypassed, TDLCLK held low. Transmit Data Link Underrun (TDLUDR). TDLUDR signal available this when XFDL enabled. TDLUDR goes high when processor failed service TDLINT interrupt before transmit buffer emptied.
TDLUDR[4] TDLUDR[3] TDLUDR[2] TDLUDR[1]
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name TCLKO[4] TCLKO[3] TCLKO[2] TCLKO[1]
Type Output
Function Transmit Clock Output (TCLKO). TDN, outputs enabled updated rising falling edge TCLKO. TCLKO transmit clock that adequately jitter wander free absolute terms permit acceptable transmission signal generated. Depending configuration S/UNIMPH, TCLKO derived from TCLKI, RCLKO, XCLK, with without jitter attenuation. Transmit Digital Positive Line Pulse (TDP). This signal available when S/UNIMPH configured transmit dual-rail data. signal formatted either waveforms, enabled updated rising falling edge TCLKO. Transmit Digital Data (TDD). This signal available when S/UNI-MPH configured transmit single-rail data, when T1/E1 framers bypassed. signal enabled updated rising falling edge TCLKO.
TDP[4] TDP[3] TDP[2] TDP[1]/
Output
TDD[4] TDD[3] TDD[2] TDD[1]
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name TDN[4] TDN[3] TDN[2] TDN[1]/
Type Output
Function Transmit Digital Negative Line Pulse (TDN). This signal available when S/UNIMPH configured transmit dual-rail data. signal formatted either waveforms, enabled updated rising falling edge TCLKO. When configured single-rail data, unused. Transmit Overhead Mask Output (TOHO). When S/UNI-MPH configured bypass T1/E1 transmit framers, this signal indicates placeholder positions framing overhead transmit stream. TOHO connected external framer device provide user network interface arbitrary rates rate (for which TOHO specially conditioned operate with Transwitch JT2F framer). Acell stream configured byte aligned TOHO which case number TCLKO periods between active TOHO edges must divisible eight). TOHO configured active high active low, enabled updated rising falling edge TCLKO.
TOHO[4] TOHO[3] TOHO[2] TOHO[1]
TCLKI
Input
Transmit Clock Input (TCLKI). This signal provides transmit direction timing (when S/UNI-MPH loop timed). S/UNI-MPH configured ignore TCLKI input utilize XCLK instead. default requirement TCLKI 1.544 clock 2.048 clock arbitrary rates, TCLKI must less than equal MHz.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name TFPI
Type Input
Function Transmit Frame Position (TFPI). This signal provides transmit frame position indication four T1/E1 framers. TFPI used applications where transmit frames must aligned common reference. these applications, TFPI activated clock period every (T1) (E1) TCLKI periods multiple thereof). such alignment required, TFPI tied low. TFPI configured active high active low, enabled sampled rising falling edge TCLKI. Transmit Overhead Mask Input (TOHI). This signal identifies placeholder bits transmit stream arbitrary rate interfaces. delayed version TOHI appears four TOHO outputs. Downstream framing insertion devices overwrite placeholder positions with overhead specific particular frame format (for example 6.312 Mbit/s format). TOHI configured active high active low, enabled sampled rising falling edge TCLKI.
TOHI
XCLK/
Input
Crystal Clock Input (XCLK). This signal provides timing framer portion S/UNI-MPH. Depending configuration S/UNI-MPH, XCLK must nominally nominal line rate. clock used clock recovery digital phase locked loop T1/E1 framer, while clock used jitter attenuator S/UNI-MPH. This clock tied T1/E1 framers bypassed. default requirement XCLK 37.056 clock 49.152 clock Vector Clock (VCLK). VCLK signal used during S/UNI-MPH production test verify internal functionality.
VCLK
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name MPHEN
Type Input
Function Multiphy Enable (MPHEN). This input selects configuration receive transmit cell interfaces. When MPHEN high, cell interfaces configured multi-phy addressing signals TWRMPHB, TWA[1:0], TCAMPH, RRDMPHB, RRA[1:0], RCAMPH active. When MPHEN low, cell interfaces configured direct selection signals TWRENB[4:1] RRDENB[4:1] active. Receive FIFO Read Clock (RFCLK). This signal used read Acells from receive FIFOs. RFCLK must cycle lower instantaneous rate, high enough rate avoid FIFO overflow.
RFCLK
Input
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name RRDMPHB
Type Input
Function Receive Multi-Phy Read Enable (RRDMPHB). RRDMPHB signal available this when input MPHEN high. RRDMPHB used initiate reads from receive FIFOs. When sampled using rising edge RFCLK, byte read from receive FIFO selected RRA[1:0] address available) output RDAT[7:0]. When sampled high using rising edge RFCLK, read performed RDAT[7:0] RSOC tristated. RRDMPHB must operate conjunction with RFCLK access FIFOs high enough instantaneous rate avoid FIFO overflows. Alayer device deassert RRDMPHB anytime unable accept another byte. Receive Read Enable (RRDENB[1]). RRDENB[1] signal available this when input MPHEN low. RRDENB[1] used initiate reads from receive FIFO When sampled using rising edge RFCLK (and remaining three RRDENBs remain high), byte read from #1's synchronous FIFO output RDAT[7:0] available. When sampled high using rising edge RFCLK, read performed RDAT[7:0] RSOC tristated. RRDENB[1] must operate conjunction with RFCLK access FIFOs high enough instantaneous rate avoid FIFO overflows. Alayer device deassert RRDENB[1] anytime unable accept another byte.
RRDENB[1]
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name RRA[0]
Type Input
Function Receive Read Address (RRA[0]). RRA[0] signal available this when input MPHEN high. RRA[0] used (along with RRA[1]) select FIFO (and hence port) that read from using RRDMPHB signal. RRA[0] sampled rising edge RFCLK together with RRDMPHB. Receive Read Enable (RRDENB[2]). RRDENB[2] signal available this when input MPHEN low. RRDENB[2] used initiate reads from receive FIFO When sampled using rising edge RFCLK (and remaining three RRDENBs remain high), byte read from #2's synchronous FIFO output RDAT[7:0] available. When sampled high using rising edge RFCLK, read performed RDAT[7:0] RSOC tristated. RRDENB[2] must operate conjunction with RFCLK access FIFOs high enough instantaneous rate avoid FIFO overflows. Alayer device deassert RRDENB[2] anytime unable accept another byte.
RRDENB[2]
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name RRA[1]
Type Input
Function Receive Read Address (RRA[1]). RRA[1] signal available this when input MPHEN high. RRA[1] used (along with RRA[0]) select FIFO (and hence port) that read from using RRDMPHB signal. RRA[1] sampled rising edge RFCLK together with RRDMPHB. Receive Read Enable (RRDENB[3]). RRDENB[3] signal available this when input MPHEN low. RRDENB[3] used initiate reads from receive FIFO When sampled using rising edge RFCLK (and remaining three RRDENBs remain high), byte read from #3's synchronous FIFO output RDAT[7:0] available. When sampled high using rising edge RFCLK, read performed RDAT[7:0] RSOC tristated. RRDENB[3] must operate conjunction with RFCLK access FIFOs high enough instantaneous rate avoid FIFO overflows. Alayer device deassert RRDENB[3] anytime unable accept another byte.
RRDENB[3]
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name RCAMPH
Type
Function Receive Multi-Phy Cell Available (RCAMPH). RCAMPH signal output this when input MPHEN high. This signal indicates when cell available receive FIFO port selected RRA[1:0]. RCAMPH configured deasserted when either zero four bytes remain selected/addressed FIFO. RCAMPH will thus transition rising edge RFCLK after 53rd 48th byte been output being polled same Receive Read Enable (RRDENB[4]). RRDENB[4] signal input this when input MPHEN low. RRDENB[4] used initiate reads from receive FIFO When sampled using rising edge RFCLK (and remaining three RRDENBs remain high), byte read from #4's synchronous FIFO output RDAT[7:0] available. When sampled high using rising edge RFCLK, read performed RDAT[7:0] RSOC tristated. RRDENB[4] must operate conjunction with RFCLK access FIFOs high enough instantaneous rate avoid FIFO overflows. Alayer device deassert RRDENB[4] anytime unable accept another byte.
RRDENB[4]
RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7]
Tristate Output
Receive Cell Data (RDAT[7:0]). This carries Acell octets that read from selected receive FIFO. RDAT[7:0] updated rising edge RFCLK tristated when RRDENB[n]/RRDMPHB high.
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name RXPRTY
Type Tristate Output
Function Receive Parity (RXPRTY). This signal indicates parity RDAT[7:0] bus. even parity selection made using register. RXPRTY updated rising edge RFCLK tristated when RRDENB[4:1]/RRDMPHB high. Receive Start Cell (RSOC). This signal marks start cell RDAT[7:0] bus. When RSOC high, first octet cell present RDAT[7:0] stream. RSOC updated rising edge RFCLK tristated when RRDENB[4:1]/RRDMPHB high. Receive Cell Available (RCA[4:1]). These output signals indicate when cell available receive FIFO corresponding port. RCA[4:1] configured deasserted when either zero four bytes remain FIFO. RCA[4:1] will thus transition rising edge RFCLK after 53rd 48th byte been output. Transmit FIFO Write Clock (TFCLK). This signal used write Acells four cell transmit FIFOs. TFCLK cycles lower instantaneous rate. complete octet cell must written FIFO before being inserted transmit stream. Idle/unassigned cells inserted when complete cell available. Transmit Cell Data (TDAT[7:0]). This carries Acell octets that written selected transmit FIFO. TDAT[7:0] sampled rising edge TFCLK considered valid only when TWRENB[n]/TWRMPHB simultaneously asserted.
RSOC
Tristate Output
RCA[4] RCA[3] RCA[2] RCA[1]
Output
TFCLK
Input
TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7]
Input
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Name TXPRTY
Type Input
Function Transmit parity (TXPRTY). This signal indicates parity TDAT[7:0] bus. even parity selection made using register. TXPRTY sampled rising edge TFCLK considered valid only when TWRENB[n]/TWRMPHB simultaneously asserted. parity error indicated status maskable interrupt. Cells with parity errors inserted transmit stream, TXPRTY input unused.
TWRMPHB
Input
Transmit Multi-Phy Write Enable (TWRMPHB). TWRMPHB signal available this when input MPHEN high. This active input used initiate writes transmit FIFOs. When sampled using rising edge TFCLK, byte TDAT[7:0] written into transmit FIFO selected TWA[1:0] address bus. When sampled high using rising edge TFCLK, write performed. complete octet cell must written transmit FIFO before inserted into transmit stream. Idle/unassigned cells inserted when complete cell available. Transmit Write Enable (TWRENB[1]). TWRENB[1] signal available this when input MPHEN low. TWRENB[1] used initiate writes transmit FIFO When sampled using rising edge TFCLK (and remaining three TWRENBs remain high), byte written #1's synchronous FIFO. When sampled high using rising edge TFCLK, write performed. TWRENB[1] must operate conjunction with TFCLK access FIFOs high enough instantaneous rate avoid FIFO overflows. Alayer device deassert TWRENB[1] anytime unable provide another byte.
TWRENB[1]
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name TWA[0]
Type Input
Function Transmit Write Address (TWA[0]). TWA[0] signal available this when input MPHEN high. TWA[0] used (along with TWA[1]) select FIFO (and hence port) that written using TWRMPHB signal. TWA[0] sampled rising edge TFCLK together with TWRMPHB. Transmit Write Enable (TWRENB[2]). TWRENB[2] signal available this when input MPHEN low. TWRENB[2] used initiate writes transmit FIFO When sampled using rising edge TFCLK (and remaining three TWRENBs remain high), byte written #2's synchronous FIFO. When sampled high using rising edge TFCLK, write performed. TWRENB[2] must operate conjunction with TFCLK access FIFOs high enough instantaneous rate avoid FIFO overflows. Alayer device deassert TWRENB[2] anytime unable provide another byte.
TWRENB[2]
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name TWA[1]
Type Input
Function Transmit Write Address (TWA[1]). TWA[1] signal available this when input MPHEN high. TWA[1] used (along with TWA[0]) select FIFO (and hence port) that written using TWRMPHB signal. TWA[1] sampled rising edge TFCLK together with TWRMPHB. Transmit Write Enable (TWRENB[3]). TWRENB[3] signal available this when input MPHEN low. TWRENB[3] used initiate writes transmit FIFO When sampled using rising edge TFCLK (and remaining three TWRENBs remain high), byte written #3's synchronous FIFO. When sampled high using rising edge TFCLK, write performed. TWRENB[3] must operate conjunction with TFCLK access FIFOs high enough instantaneous rate avoid FIFO overflows. Alayer device deassert TWRENB[3] anytime unable provide another byte.
TWRENB[3]
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name TCAMPH
Type
Function Transmit Multi-Phy Cell Available (TCAMPH). TCAMPH signal output this when input MPHEN high. This signal indicates when cell available transmit FIFO port selected TWA[1:0]. When high, TCAMPH indicates that corresponding transmit FIFO full complete cell written. When TCAMPH goes low, configured indicate either that corresponding transmit FIFO near full accept more than four writes that corresponding transmit FIFO full. TCAMPH will thus transition rising edge TFCLK which 52nd 48th byte sampled being polled same use. reduce FIFO latency, FIFO depth which TCAMPH indicates "full" one, two, three four cells. Transmit Write Enable (TWRENB[4]). TWRENB[4] signal input this when input MPHEN low. TWRENB[4] used initiate writes transmit FIFO When sampled using rising edge TFCLK (and remaining three TWRENBs remain high), byte written #4's synchronous FIFO. When sampled high using rising edge TFCLK, write performed. TWRENB[4] must operate conjunction with TFCLK access FIFOs high enough instantaneous rate avoid FIFO overflows. Alayer device deassert TWRENB[4] anytime unable provide another byte.
TWRENB[4]
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name TSOC
Type Input
Function Transmit Start Cell (TSOC). This input marks start cell TDAT[7:0] bus. When TSOC high, first octet cell present TDAT[7:0] stream. necessary TSOC present each cell. interrupt generated TSOC high during byte other than first byte. TSOC sampled rising edge TFCLK Transmit Cell Available (TCA[4:1]). These output signals indicate when cell available transmit FIFO corresponding port. When high, indicates that corresponding transmit FIFO full complete cell written. When goes low, configured indicate either that corresponding transmit FIFO near full accept more than four writes that corresponding transmit FIFO full. TCA[4:1] will thus transition rising edge TFLCK which 52nd 48th byte sampled. reduce FIFO latency, FIFO depth which indicates "full" one, two, three four cells. Active Open-Drain Interrupt (INTB). This signal goes when unmasked interrupt event detected internal interrupt sources, including internal HDLC transceivers. Note that INTB will remain until active, unmasked interrupt sources acknowledged their source. Active Chip Select (CSB). This signal must enable S/UNI-MPH register accesses. used, (RDB determine register reads writes) then should tied inverted version RSTB.
TCA[4] TCA[3] TCA[2] TCA[1]
Output
INTB
Output
Input
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
Type
Function Bidirectional Data (D[7:0]). This used during S/UNI-MPH read write accesses.
Input
Active Read Enable (RDB). This signal pulsed enable S/UNI-MPH register read access. S/UNI-MPH drives D[7:0] with contents addressed register while both low. Active Write Strobe (WRB). This signal pulsed enable S/UNI-MPH register write access. D[7:0] clocked into addressed register rising edge while low. Address Latch Enable (ALE). This signal latches address contents, A[10:0], when low, allowing S/UNI-MPH interfaced multiplexed address/data bus. When high, address latches transparent. integral pull-up resistor. Active Reset (RSTB). This signal asynchronously reset S/UNI-MPH. RSTB Schmitt-trigger input with integral pull-up resistor.
Input
Input
RSTB
Input
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Name A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10]
Type Input
Function Address (A[10:0]). This selects specific registers during S/UNI-MPH register accesses.
Input
Test Clock (TCK). This signal provides timing test operations that carried using IEEE P1149.1 test access port. Test Mode Select (TMS). This signal controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor. Test Data Input (TDI). This signal carries test data into S/UNI-MPH IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor. Test Data Output (TDO). This signal carries test data S/UNI-MPH IEEE P1149.1 test access port. updated falling edge TCK. tri-state output which inactive except when scanning data progress.
Input
Input
Tristate Output
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Name TRSTB
Type Input
Function Active Test Reset (TRSTB). This signal provides asynchronous S/UNI-MPH test access port reset IEEE P1149.1 test access port. TRSTB Schmitt triggered input with integral pull resistor. TRSTB must asserted during power sequence. Note that used, TRSTB must connected RSTB input.
VDD_AC[2] VDD_AC[1] VDD_AC[0] VDD_DC[3] VDD_DC[2] VDD_DC[1] VDD_DC[0] VSS_AC[2] VSS_AC[1] VSS_AC[0] VSS_DC[3] VSS_DC[2] VSS_DC[1] VSS_DC[0]
Power
Ring Power (VDD_AC[2:0]). These pins should connected well decoupled common with VDD_DC[3:0] Power (VDD_DC[3:0]). These pins should connected well decoupled common with VDD_AC[2:0]. Ring Ground (VSS_AC[2:0]). These pins should connected common with VSS_DC[3:0]. Ground (VSS_DC[3:0]). These pins should connected common with VSS_AC[2:0].
Power
Ground
Ground
Notes Description: VDD_DC[3:0] VSS_DC[3:0] ground connections, respectively, core circuitry drive output pads device. VDD_AC[2:0] VSS_AC[2:0] ground connections, respectively, switching ring circuitry device. These power supply connections must utilized must connect common ground rail, appropriate. There impedance connection within S/UNI-MPH between core, ring supply rails. Failure properly make these connections result improper operation damage device. Inputs RSTB, TMS, TDI, TRSTB have integral pull-up resistors.
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
TDLSIG/TDLINT[4:1] pins have integral pull-up resistors default being inputs after reset. D[7:0], TCLKO[4:1], RCLKO, RDAT[7:0], RCA[4:1], RXPRTY, RSOC, TCA[4:1], TCAMPH RCAMPH bidirectionals have drive capability. other outputs bidirectionals have drive capability. inputs bidirectionals present minimum capacitive loading operate logic levels. When internal RFDL enabled, RDLINT[x] output goes high: when number bytes specified RFDL Interrupt Status/Control Register have been received data link, immediately detection RFDL FIFO buffer overrun, immediately detection message, immediately detection abort condition, immediately detection transition from receiving ones flags. interrupt cleared start next RFDL Data Register read that results empty FIFO buffer. This independent FIFO buffer fill level which interrupt programmed. there still data remaining buffer, RDLINT will remain high. interrupt RFDL FIFO buffer overrun condition cleared RFDL Data Register read RFDL Status Register read. RDLINT output always forced disabling RFDL (setting RFDL Configuration Register logic disabling internal HDLC receiver S/UNI-MPH Receive Data Link Configuration Register), forcing RFDL terminate reception (setting RFDL Configuration Register logic RDLINT output forced disabling interrupts with RFDL Interrupt Status/Control Register. However, internal interrupt latch cleared, state this latch still read through RFDL Interrupt Status/Control Register. RDLEOM[x] output goes high: immediately detection RFDL FIFO buffer overrun, when data byte written into RFDL FIFO buffer message condition read,
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
when data byte written into RFDL FIFO buffer abort condition read, when data byte written into RFDL FIFO buffer transition from receiving ones flags read. RDLEOM[x] reading RFDL Status Register disabling RFDL. each TDLUDR[x] output: TDLUDR[x] output goes high when processor unable service TDLINT[x] request more data before specific time-out period. This period dependent upon frequency TDLCLK: TDLCLK frequency (ESF full rate), time-out TDLCLK frequency (half FDL), time-out
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
FUNCTIONAL DESCRIPTION Digital Receive Interface (DRIF) Digital Receive Interface provides control over various input options available multifunctional digital receive pins RDP/RDD RDN/RLCV/ROH. When configured dual-rail input, multifunctional pins become inputs. These inputs enabled receive either return-to-zero (RZ) non-return-to-zero (NRZ) signals; input signals sampled either rising falling edge RCLKI. When interface configured single-rail input, multifunctional pins become RLCV inputs, which sampled either rising falling RCLKI edge. Finally, when T1/E1 framers bypassed, multifunction pins become inputs, which support arbitrary rate interfaces such 6.312 Mbit rate. S/UNI-MPH contains internal logic that allows interfaced directly Transwitch JT2F framer device. single S/UNI-MPH along with four JT2Fs used implement quad user network interface. Clock Data Recovery Clock Data Recovery function contained DRIF block active when clock recovery enabled interfaces dual-rail input configuration. CDRC provides clock data recovery, B8ZS/HDB3 decoding, bipolar violation detection, loss signal detection. recovers clock from incoming data pulses using digital phase-locked-loop recovers data. Loss signal declared after exceeding programmed threshold consecutive periods absence pulses both positive negative line pulse inputs removed after occurrence single line pulse. alternate loss signal removal criteria requires that minimum pulse density requirements satisfied before loss signal removed. enabled, microprocessor interrupt generated when loss signal detected when signal returns. input jitter tolerance interfaces complies with Bellcore Document TA-TSY-000170 with AT&T specification 62411. tolerance measured with QRSS sequence 20-1 with zero restriction). CDRC block provides algorithms clock recovery that result differing jitter tolerance characteristics. first algorithm (when ALGSEL register logic provides good frequency jitter tolerance, high frequency tolerance close 62411 limit. second algorithm (when ALGSEL logic provides much better high frequency jitter tolerance, approaching 0.5UIpp (Unit Intervals peak-to-peak), expense frequency
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tolerance; frequency tolerance second algorithm approximately that first algorithm. jitter tolerance with ALGSEL shown following illustration. Figure Jitter Tolerance Specification
SPEC. REGION
SINEWAVE JITTER AMPLITUDE (UI) SCALE
CDRC MAX. TOLERANCE
(ALGSEL=0)
CDRC MAX. TOLERANCE
(ALGSEL=1)
AT&T SPEC. BELLCORE SPEC.
0.31
0.70
SINEWAVE JITTER FREQUENCY, SCALE
input jitter tolerance interfaces complies with ITU-T Recommendation G.823. tolerance measured with 215-1 sequence. jitter tolerance with ALGSEL shown following illustrations.
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Figure
Jitter Tolerance Specification (ALGSEL
Measurement Limit
Measured CDRC Jitter Tolerance (ALGSEL
Jitter Amplitude (UIp-p)
G823 Jitter Tolerance Specification
0.01 Jitter Frequency (Hz) 100K
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Figure
Jitter Tolerance Specification (ALGSEL
Measurement Limit
Jitter Amplitude (UIp-p)
Measured CDRC Jitter Tolerance (ALGSEL
G823 Jitter Tolerance Specification
Jitter Frequence (Hz)
Pulse Density Violation Detector (PDVD) Pulse Density Violation Detection function provided PDVD block. This block detects pulse density violations ANSI T1.403 requirement that there ones each every time window 8(N+1) data bits (where equal through 23). PDVD also detects periods consecutive zeros incoming data. Pulse density violation detection provided through internal register bit. interrupt generated signal consecutive zero event change state pulse density violation indication.
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100K
0.01
PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
T1/E1 Framer (FRMR) framing function provided FRMR block. This block searches framing position incoming data stream. searches framing pattern following frame formats: ESF. When searching frame, FRMR examines each (SF), each 4*193 (ESF) framing candidates. frame format, FRMR searches frame alignment multiframe alignment incoming stream. time required find frame alignment error-free stream containing randomly distributed channel data (i.e. each channel data probability being dependent upon framing format. FRMR determines frame alignment within 4.4ms, times 100. FRMR determines frame alignment within 15ms, times 100. formatted signals, FRMR determines frame alignment within 1ms, times 100. When FRMR found frame alignment, incoming data continuously monitored framing errors, CRC-6 error events (ESF only), severe errored framing events. FRMR also detects loss frame, based selectable ratio framing errors. When FRMR found frame alignment, incoming data monitored frame alignment signal errors. Upon detecting multiframe alignment, FRMR monitors incoming data multiframe alignment pattern errors, CRC-4 errors. FRMR also detects loss frame, loss multiframe, based user-selectable criteria. FRMR extracts yellow alarm signal bits T1-SF T1-ESF framing formats. FRMR extracts debounces remote alarm indication signal framing format.
Alarm Integrator (ALMI) Alarm Integration function provided ALMI block. This block detects presence yellow, red, Carrier Fail Alarms (CFA) formats. block also detects presence CFA. alarm detection integration compatible with specifications defined ANSI T1.403-1989, TR-TSY-000191, Q.516. formats, ALMI block declares presence yellow when yellow pattern been received ms); yellow removed when yellow pattern been absent ms).
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
presence declared when out-of-frame condition been present 2.55 ms); removed when out-of-frame condition been absent 16.6 ms). presence declared when out-of-frame condition all-ones data stream have been present (±100 ms); removed when condition been absent 16.8 (±500 ms). formats, ALMI block declares presence when outof-frame condition been present ms); removed when out-of-frame condition been absent ms). presence declared when out-of-frame condition all-ones data stream have been present ms); removed when condition been absent ms). alarm detection algorithms operate presence random 10-3 error rate. ALMI also indicates presence absence yellow, red, alarm signal conditions over 40ms, intervals, respectively, allowing external microprocessor integrate alarm conditions software with user-specific algorithms. Alarm indication provided through internal register bits. Inband Loopback Code Detector (IBCD) Inband Loopback Code Detection function provided IBCD block. This block detects presence either programmable loopback code sequences, ACTIVATE DEACTIVATE, either framed unframed data streams. inband code sequences expected overwritten framing framed data streams. Each code sequence defined repetition programmed code stream least seconds. code sequence detection timing compatible with specifications defined T1.403, TA-TSY-000312, TR-TSY-000303. ACTIVATE DEACTIVATE code indication provided through internal register bits. interrupt generated indicate when either code status changed. Performance Monitor Counters (PMON) Performance Monitor Counters function provided PMON block. data stream, PMON accumulates CRC-6 error events, frame synchronization error events, line code violation events, loss frame events, optionally, change frame alignment (COFA) events with saturating
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counters over consecutive intervals defined period supplied transfer clock signal (typically second). data stream, PMON accumulates CRC-4 error events, frame synchronization error events, line code violation events, block error events with saturating counters over consecutive intervals defined period supplied transfer clock signal (typically second). When transfer clock signal applied, PMON transfers counter values into holding registers resets counters begin accumulating events interval. counters reset such manner that error events occurring during reset missed. Generation transfer clock within S/UNI-MPH performed writing counter register location. holding register addresses contiguous facilitate polling operations. Oriented Code Detector (RBOC) Oriented Code detection function provided RBOC block. This block detects presence possible oriented codes transmitted facility data link channel T1-ESF framing format, defined ANSI T1.403 TR-TSY-000194. oriented codes received facility data link channel 16-bit sequence consisting ones, zero, code bits, trailing zero (111111110xxxxxx0) which repeated least times. RBOC enabled declare received code valid been observed times times. Valid BOCs indicated through internal status register. bits ones (111111) valid code been detected. interrupt generated signal when detected code been validated, optionally, when valid code removed (i.e. bits ones idle state). HDLC Receiver (RFDL) HDLC Receiver function provided RFDL block. RFDL microprocessor peripheral used receive LAPD/HDLC frames facility data link (FDL) interfaces, timeslot National bits timeslot interfaces.
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RFDL detects change from flag characters first byte data, removes stuffed zeros incoming data stream, receives frame data, calculates CRC-CCITT frame check sequence (FCS). Received data placed into 4-level FIFO buffer. Status Register contains bits which indicate overrun, message, flag detected, buffered data available. message, Status Register also indicates status number valid bits final data byte. Interrupts generated when one, three bytes (programmable RFDL configuration register) stored FIFO buffer. Interrupts also generated when terminating flag sequence, abort sequence, FIFO buffer overrun detected. When internal HDLC receiver disabled, serial data extracted FRMR block output RDLSIG[x] updated falling clock edge output RDLCLK[x] pin. T1/E1 Framing Insertions (TRAN) Basic Transmitter function provided TRAN block. TRAN block inserts T1-SF T1-ESF framing 1.544 Mbit/s data stream basic framing multiframe 2.048 Mbit/s data stream.
data link provided framing formats. TRAN interfaces XFDL XBOC blocks provide variety data link sources including oriented codes (T1-ESF format only) LAPD messages. Support provided transmission framed unframed inband code sequences format only) transmission yellow signals formats. line code transmit data stream selected AMI, B8ZS, HDB3.
9.10
Inband Loopback Code Generator (XIBC) Inband Loopback Code Generator function provided XIBC block. This block generates stream inband loopback codes inserted into data stream. stream consists continuous repetitions specific code either framed unframed. When XIBC enabled generate framed stream, framing overwrites inband code pattern. contents
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code length programmable from bits. XIBC interfaces directly TRAN Basic Transmitter block. 9.11 Pulse Density Enforcer (XPDE) Pulse Density Enforcer function provided XPDE block. Pulse density enforcement enabled register within XPDE. This block monitors transmit AMI-coded stream, detecting when stream about violate ANSI T1.403 12.5% pulse density rule over moving 192-bit window. density violation detected, XPDE enabled insert logic into digital stream ensure resultant output longer violates pulse density requirement. When XPDE disabled from inserting logic transmit stream from TRAN passed through unaltered. 9.12 Oriented Code Generator (XBOC) Oriented Code Generator function provided XBOC block. This block transmits possible oriented codes facility data link channel T1-ESF framing format, defined ANSI T1.403. oriented codes transmitted facility data link channel 16-bit sequence consisting ones, zero, code bits, trailing zero (111111110xxxxxx0) which repeated long code 111111. transmitted oriented codes have priority over data transmitted facility data link except yellow CFA. code transmitted programmed writing code register. 9.13 HDLC Transmitter XFDL) HDLC Transmitter function provided XFDL block. This block interfaces with TRAN block. XFDL used under microprocessor control transmit HDLC data frames facility data link T1-ESF frame format, timeslot National bits timeslot frame format. XFDL performs data serialization, generation, zero-bit stuffing, well flag, idle, abort sequence insertion. Data transmitted provided interrupt-driven basis writing doublebuffered transmit data register. CRC-CCITT frame check sequence appended data frame, followed idle flag sequences. transmit data register underflows, abort sequence automatically transmitted.
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When enabled use, XFDL continuously transmits flag character (01111110). Data bytes transmitted written into Transmit Data Register. After parallel-to-serial conversion each data byte, interrupt generated signal controller write next byte into Transmit Data Register. After last data frame byte transmitted, word insertion been enabled), flag insertion been enabled) transmitted. XFDL then returns transmission flag characters. there more than five consecutive ones transmit data data, zero stuffed into serial data output. This prevents unintentional transmission flag abort characters. Abort characters continuously transmitted time setting control bit. During transmission, underrun situation occur data written Transmit Data Register before previous byte been depleted. this case, abort sequence transmitted, controlling processor notified TDLUDR signal. Optionally, interrupt underrun signals independently enabled also generate interrupt INTB output, providing means notify controlling processor changes XFDL operating status. When internal HDLC transmitter disabled, serial data transmitted facility data link timeslot timeslot input TDLSIG[x] timed clock rate output TDLCLK[x] pin. 9.14 Digital Transmit Interface (DTIF) Digital Transmit Interface provides control over various output options available multifunctional digital transmit pins TDP/TDD TDN/TOHP When configured dual-rail output, multifunctional pins become outputs. These outputs formatted either return-to-zero (RZ) non-return-to-zero (NRZ) signals updated either rising falling edge TCLKO. When interface configured single-rail output, when T1/E1 framers bypassed, multifunctional pins become TOHO outputs, which enabled updated either rising falling TCLKO edge. When T1/E1 framers bypassed, arbitrary rate interfaces, such 6.312 Mbit/s rate supported.
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
9.15
Digital Jitter Attenuator Digital Jitter Attenuator (DJAT) function contained DTIF block used attenuate jitter transmit clock when required. DJAT function normally enabled S/UNI-MPH loop-timed from RCLKO, transmit clock (TCLKI) requires jitter attenuation before transmission. block receives jittered data from TRAN block stores this data FIFO. data emerges from DJAT timed jitter attenuated clock, TCLKO. DJAT generates jitter-free 1.544/2.048 TCLKO clock adaptively dividing XCLK input according phase difference between generated TCLKO input data clock DJAT (TCLKI RCLKO). Phase variations input clock with jitter frequency above (for format) (for formats) attenuated octave jitter frequency. Phase variations below these jitter frequencies tracked TCLKO. Jitter Characteristics DJAT provides excellent jitter tolerance jitter attenuation while generating minimal residual jitter. accommodate UIpp input jitter jitter frequencies above interfaces (for interfaces). jitter frequencies below more correctly called wander, tolerance increases decade. most applications DJAT will limit jitter tolerance lower jitter frequencies only. DJAT block meets frequency jitter tolerance requirements AT&T 62411 interfaces, ITU-T G.823 interfaces. Outgoing jitter dominated generated residual jitter cases where incoming jitter insignificant. This residual jitter directly related clock digital phase locked loop. interfaces, DJAT meets jitter attenuation requirements AT&T 62411. DJAT meets implied jitter attenuation requirements specified ANSI T1.408, type customer interface specified ANSI T1.403. interfaces, DJAT meets jitter attenuation requirements ITU-T Recommendations G.737, G.738, G.739, G.742.
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Jitter Tolerance Jitter tolerance maximum input phase jitter given jitter frequency that device accept without exceeding linear operating range, corrupting data. DJAT, input jitter tolerance Unit Intervals peak-to-peak (UIpp) interface with worst case frequency offset input jitter tolerance UIpp interface with worst case frequency offset UIpp with frequency offset. frequency offset difference between frequency XCLK divided that input data clock. These tolerances shown Figure Figure below: Figure Jitter Amplitude, UIpp
unacceptable acceptable DJAT minimum tolerance
Jitter Tolerance
0.01
0.3k
100k
Jitter Frequency,
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Figure Jitter Amplitude,
Jitter Tolerance
DJAT minimum tolerance
G.823 unacceptable Region
acceptable
0.01
Jitter Frequency,
100k
accuracy XCLK frequency that DJAT reference input clock used generate jitter-free TCLKO have effect minimum jitter tolerance. interfaces, DJAT reference clock accuracy ±200 from 1.544 MHz, XCLK input accuracy ±100 from 37.056 MHz. interfaces, reference clock accuracy from 2.048 MHz, XCLK input accuracy ±100 from 49.152 MHz. minimum jitter tolerance various differences between frequency reference clock XCLK/24 shown Figure Figure
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Figure
DJAT Minimum Jitter Tolerance XCLK Accuracy Case)
DJAT Minimum Jitter Tolerance
frequency offset (PLL XCLK)
XCLK Accuracy
Figure
DJAT Minimum Jitter Tolerance XCLK Accuracy Case) 42.4
DJAT Minimum Jitter Tolerance
34.9
frequency offset (PLL XCLK) XCLK Accuracy Jitter Transfer
output jitter jitter frequencies from (for interfaces) from (for interfaces) more than greater than input jitter, excluding 0.042 residual jitter. Jitter frequencies above 6.6/8.8
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
attenuated level octave, shown Figure Figure below: Figure Jitter Gain (dB)
62411 DJAT response 62411 43802
Jitter Transfer
Jitter Frequency,
Figure Jitter Gain (dB)
Jitter Transfer
G.737, G738, G.739, G.742 DJAT response
-19.5
Jitter Frequency,
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
9.16
Receive ACell Processor (RXCP) Receive ACell Processor (RXCP) Block integrates circuitry support cell delineation, cell payload descrambling, header check sequence (HCS) verification idle/unassigned cell filtering. RXCP cell delineates framed cell streams. Overhead bits (the framing interfaces, timeslots interfaces) indicated FRMR block. Overhead bits arbitrary rate interfaces indicated ROHM input. Cell delineation process framing Acell boundaries using header check sequence (HCS) field found Acell header. CRC-8 calculation over first octets Acell header. When performing delineation, correct calculations assumed indicate cell boundaries. RXCP performs sequential hunt correct sequence. While performing this hunt, cell delineation state machine HUNT state. When correct found, RXCP locks particular cell boundary enters PRESYNC state. This state verifies that previously detected pattern false indication. pattern false indication then incorrect should received within next DELTA cells. that point transition back HUNT state executed. incorrect found PRESYNC state then transition SYNC state made. this state synchronization relinquished until ALPHA consecutive incorrect patterns found. such event transition made back HUNT state. state diagram cell delineation process shown Figure
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Figure
Cell delineation State Diagram
correct (bit bit)
HUNT
Incorrect (cell cell)
PRESYNC
ALPHA consecutive incorrect HCS's (cell cell)
SYNC
DELTA consecutive correct HCS's (cell cell)
values ALPHA DELTA determine robustness delineation method. ALPHA determines robustness against false misalignments errors. DELTA determines robustness against false delineation synchronization process. ALPHA chosen DELTA chosen recommended ITU-T Recommendation I.432. Loss cell delineation (LCD) detected counting number incorrect cells while HUNT state. counter value stored RXCP Count Threshold register. threshold default value which results format detection time format detection time RXCP descrambles cell payload field using self synchronizing descrambler with polynomial cell header descrambled. Note that cell payload scrambling optional S/UNI-MPH. CRC-8 calculation over first octets Acell header. RXCP verifies received using accumulation polynomial, coset polynomial added (modulo received octet before comparison with calculated result required AForum specification, ITU-T Recommendation I.432. RXCP programmed drop cells containing error filter cells based and/or octet cell header. Filtering according
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particular and/or octet header pattern programmable through RXCP configuration/control registers. More precisely, filtering performed when filtering enabled when errors found when checking enabled. Otherwise, cells passed regardless error conditions. Cells dropped pattern invalid filtering 'Match Pattern' 'Match Mask' registers programmed with certain blocking pattern. Idle cells automatically filtered. they required filtered, then that filtering criterion (i.e. cell header pattern) must programmed through Idle/Unassigned Cell Pattern Mask registers. Acells, Idle/Unassigned cells identified standardized header pattern 'H00, 'H00, 'H00 'H01 first octets followed valid octet. While cell delineation state machine SYNC state, verification circuit implements state machine shown figure normal operation, verification state machine remains 'Correction' state. Incoming cells containing errors passed receive FIFO. Incoming single-bit errors optionally corrected, resulting cell passed FIFO. Upon detection single-bit error multi-bit error, state machine transitions 'Detection' state. programmable hysteresis provided when dropping cells based errors. When cell with error detected, RXCP programmed continue discard cells until (where cells received with correct HCS. cell discarded (see Figure 16). Note that dropping cells errors only occurs while cell delineation state machine SYNC state (see Figure 15).
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Figure
Verification State Diagram
ADELINEATION SYNC STATE
ALPHA consecutive incorrect HCS's HUNT state)
Multi-bit Error Detected (Cell discarded) Cell Accepted Correction
Single-bit Error Detected (Error corrected cell accepted) Detection Cell Discarded
DELTA consecutive correct HCS's (From PRESYNC state)
Errors Detected Consecutive Cells (M'th Cell Accepted)
RXCP accumulates number received assigned cells, received unassigned/idle cells, cells containing correctable error cells containing uncorrectable error, saturating counters. 9.17 Receive Cell FIFO (RXFF) Receive FIFO (RXFF) provides FIFO management S/UNI-MPH receive cell interface. receive FIFO hold four cells (note that effective working FIFO depth actually three cells because four complete cells being held FIFO, next information transmitted RXCP even part null cell, will cause FIFO overflow). FIFO provides cell rate decoupling function between transmission system physical layer Alayer. general, management functions include filling receive FIFO, indicating when receive FIFO contains cells, maintaining receive FIFO read write pointers, detecting FIFO overrun underrun conditions.
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
Saturn Compatible Interface (SCI-PHYTM) FIFO provided. This synchronous FIFO accepts read clock (RFCLK) read enable signal from MPHY block. receive FIFO output tristated when read enable inactive. interface indicates start cell (RSOC) receive cell available status (RCA) when data read from receive FIFO (using rising edges RFCLK while read enable active). status changes from available unavailable when FIFO byte read accesses away from being empty when FIFO empty, when REMPTY4 logic This RXFF indicates FIFO overruns using maskable interrupt register bits. FIFO reset FIFO overrun, causing cells lost. 9.18 Transmit ACell Processor (TXCP) Transmit Cell Processor (TXCP) Block integrates circuitry support Acell payload scrambling, header check sequence (HCS) generation, idle/unassigned cell generation. TXCP scrambles cell payload field using self synchronizing scrambler with polynomial header portion cells scrambled. Note that cell payload scrambling optional S/UNI-MPH. generated using polynomial, coset polynomial added (modulo calculated octet required AForum specification, ITU-T Recommendation I.432. resultant octet optionally overwrites octet transmit cell. When transmit FIFO empty, TXCP inserts idle/unassigned cells. idle/unassigned cell header fully programmable using five internal registers. Similarly, octet information field programmed with repeating pattern using internal register. TXCP accumulates number transmitted assigned cells saturating counter. T1/E1 formats, cell octets byte aligned with transmission overhead (the framing format, timeslots 0/16 format). arbitrary rate interfaces, cell octets optionally aligned overhead indication signal (TOHI). 9.19 Transmit Cell FIFO (TXFF) Transmit FIFO (TXFF) provides FIFO management S/UNI-MPH transmit cell interface. transmit FIFO hold four cells. FIFO depth programmed one, two, three, four cells. FIFO provides
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cell rate decoupling function between transmission system physical layer Alayer. general, management functions include emptying cells from transmit FIFO, indicating when transmit FIFO full, maintaining transmit FIFO read write pointers detecting FIFO overrun condition. Saturn Compatible Interface (SCI-PHYTM) FIFO provided. This synchronous FIFO accepts write clock (TFCLK), start cell indication (TSOC), write enable signal from MPHY block. interface provides transmit cell available status (TCA) which transition from available unavailable when transmit FIFO near full accept more than writes (when TFULL4 logic when FIFO full accept more writes (default). TXFF indicates FIFO overruns using maskable interrupt register bits. Writes TXFF while FIFO full (i.e. overruns) ignored. 9.20 Saturn Compatible Multi-PHY Interface (MPHY) Saturn Compatible Multi-PHY Interface block (MPHY) permits four receive cell FIFOs (RXFF) four transmit cell FIFOs (TXFF) share single cell interface S/UNI-MPH. interface modes supported: multi-phy addressing (when MPHEN input high) direct selection (when MPHEN input low). When multi-phy addressing enabled, four possible transmit/receive FIFOs selected TWA[1:0]/RRA[1:0] address signals respectively. cell available signal each four transmit/receive FIFOs also selected TWA[1:0]/RRA[1:0]. While cell transfer progress to/from particular FIFO, cell available indications from remaining three FIFOs polled using TWA[1:0] RRA[1:0]. These indications available RCAMPH (for three remaining RXFFs) TCAMPH (for three remaining TXFFs). cell available indication from active FIFO only valid cell transfer four reads/writes before cell transfer depending configuration FIFO). cell available indications also directly available TCA[4:1] RCA[4:1] when multi-phy addressing mode enabled. When direct selection enabled, four possible transmit/receive FIFOs selected corresponding TWRENB[4:1]/RRDENB[4:1] signal respectively. cell available status each transmit receive FIFOs directly available RCA[4:1] TCA[4:1].
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DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
9.21
Microprocessor Interface (MPIF) Microprocessor Interface allows S/UNI-MPH configured, controlled monitored using internal registers.
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REGISTER DESCRIPTION Table Normal Mode Register Memory Address 000H 001H 002H 003H 004H 005H 006H 007H 008H 009H 00AH 100H 101H 102H 103H 104H 105H 106H 107H 108H 109H 10AH 200H 201H 202H 203H 204H 205H 206H 207H 208H 209H 20AH 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH Receive Configuration Transmit Configuration Datalink Options Receive Interface Configuration Transmit Interface Configuration Receive Datalink Transmit Datalink Transmit Timing Options Interrupt Source Interrupt Source Diagnostics Master Test Revision/Chip ID/Global Monitoring Update Source Selection/Interrupt Clock Activity Monitor 30BH 30CH 30DH 30EH 30FH 310H 311H Reserved Reserved Reserved Reserved Reserved CDRC Configuration CDRC Interrupt Enable Register
00BH 00CH 00DH 00EH 10BH 10CH 10DH 10EH 00FH 010H 011H 10FH 110H 111H 20BH 20CH 20DH 20EH 20FH 210H 211H
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Address 012H 013H 014H 015H 016H 017H 018H 019H 01AH 01BH 01CH 01DH 01EH 01FH 020H 021H 022H 023H 024H 025H 026H 027H 112H 113H 114H 115H 116H 117H 118H 119H 11AH 11BH 11CH 11DH 11EH 11FH 120H 121H 122H 123H 124H 125H 126H 127H 212H 213H 214H 215H 216H 217H 218H 219H 21AH 21BH 21CH 21DH 21EH 21FH 220H 221H 222H 223H 224H 225H 226H 227H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H 322H 323H 324H 325H 326H 327H
Register
CDRC Interrupt Status Alternate Loss Signal ALMI Configuration ALMI Interrupt Enable ALMI Interrupt Status ALMI Alarm Detection Status DJAT Interrupt Status DJAT Reference Clock Divisor (N1) Control DJAT Output Clock Divisor (N2) Control DJAT Configuration T1-FRMR Configuration T1-FRMR Interrupt Enable T1-FRMR Interrupt Status Reserved E1-FRMR block Framing Alignment Options E1-FRMR Maintenance Mode Options E1-FRMR Framing Status Interrupt Enable E1-FRMR Maintenance/Alarm Status Interrupt Enable E1-FRMR Framing Status Interrupt Indication E1-FRMR Maintenance/Alarm Status Interrupt Indication E1-FRMR Framing Status E1-FRMR Maintenance/Alarm Status
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Address 028H 029H 02AH 02BH 02CH 02FH 030H 031H 032H 033H 034H 035H 036H 037H 038H 039H 03AH 03BH 03CH 03DH 03EH 03FH 040H 041H 042H 043H 128H 129H 12AH 12BH 12CH 12FH 130H 131H 132H 133H 134H 135H 136H 137H 138H 139H 13AH 13BH 13CH 13DH 13EH 13FH 140H 141H 142H 143H 228H 229H 22AH 22BH 22CH 22FH 230H 231H 232H 233H 234H 235H 236H 237H 238H 239H 23AH 23BH 23CH 23DH 23EH 23FH 240H 241H 242H 243H 328H 329H 32AH 32BH
Register
E1-FRMR International/National Bits
E1-FRMR block Error Count E1-FRMR block Error Count
32CH Reserved 32FH 330H 331H 332H 333H 334H 335H 336H 337H 338H 339H 33AH 33BH 33CH 33DH 33EH 33FH 340H 341FH 342H 343H RBOC Enable RBOC Code Status Reserved XFDL Configuration XFDL Interrupt Status XFDL Transmit Data Reserved RFDL Configuration RFDL Interrupt Control/Status RFDL Status RFDL Receive Data IBCD Configuration IBCD Interrupt Enable/Status IBCD Activate Code IBCD Deactivate Code T1-TRAN Configuration T1-TRAN Alarm Transmit XIBC Control XIBC Loopback Code
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Address 044H 045H 046H 047H 048H 049H 04AH 04BH 04CH 04DH 04EH 04FH 050H 054H 055H 056H 057H 058H 059H 05AH 063H 064H 065H 066H 067H 144H 145H 146H 147H 148H 149H 14AH 14BH 14CH 14DH 14EH 14FH 150H 154H 155H 156H 157H 158H 159H 15AH 163H 164H 165H 166H 167H 244H 245H 246H 247H 248H 249H 24AH 24BH 24CH 24DH 24EH 24FH 250H 254H 255H 256H 257H 258H 259H 25AH 263H 264H 265H 266H 267H 344H 345H 346H 347H 348H 349H 34AH 34BH 34CH 34DH 34EH 34FH 350H 354H 355H 356H 357H 358H 359H 35AH 363H 364H 365H 366H 367H
Register
E1-TRAN Configuration E1-TRAN Transmit Alarm/Diagnostic Control E1-TRAN International/National Control Reserved PMON Control/Status PMON Count PMON FEBE Count (LSB) PMON FEBE Count (MSB) PMON Count (LSB) PMON Count (MSB) PMON Count (LSB) PMON Count (MSB) Reserved PDVD Interrupt Enable/Status Reserved XBOC Code Reserved XPDE Interrupt Enable/Status Reserved RXCP Uncorrectable Error Count RXCP Uncorrectable Error Count Reserved Reserved
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Address 068H 069H 06AH 06BH 06CH 06DH 06EH 06FH 070H 071H 072H 073H 074H 075H 076H 077H 078H 079H 07AH 168H 169H 16AH 16BH 16CH 16DH 16EH 16FH 170H 171H 172H 173H 174H 175H 176H 177H 178H 179H 17AH 268H 269H 26AH 26BH 26CH 26DH 26EH 26FH 270H 271H 272H 273H 274H 275H 276H 277H 278H 279H 27AH 368H 369H 36AH 36BH 36CH 36DH 36EH 36FH 370H 371H 372H 373H 374H 375H 376H 377H 378H 379H 37AH
Register
RXCP Correctable Error Count RXCP Correctable Error Count RXCP Idle/Unassigned Cell Count RXCP Idle/Unassigned Cell Count RXCP Receive Cell Count RXCP Receive Cell Count TXCP Transmit Cell Count TXCP Transmit Cell Count RXCP Control RXCP Framing Control RXCP Interrupt Enable/Status RXCP Idle/Unassigned Cell Pattern: octet RXCP Idle/Unassigned Cell Pattern: octet RXCP Idle/Unassigned Cell Pattern: octet RXCP Idle/Unassigned Cell Pattern: octet RXCP Idle/Unassigned Cell Mask: octet RXCP Idle/Unassigned Cell Mask: octet RXCP Idle/Unassigned Cell Mask: octet RXCP Idle/Unassigned Cell Mask: octet
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Address 07BH 07CH 07DH 07EH 07FH 080H 081H 082H 083H 084H 085H 087H 088H 089H 08AH 08BH 08CH 08DH 17BH 17CH 17DH 17EH 17FH 180H 181H 182H 183H 184H 185H 187H 188H 189H 18AH 18BH 18CH 18DH 27BH 27CH 27DH 27EH 27FH 280H 281H 282H 283H 284H 285H 287H 288H 289H 28AH 28BH 28CH 28DH 37BH 37CH 37DH 37EH 37FH 380H 381H 382H 383H 384H 385H 387H 388H 389H 38AH 38BH 38CH 38DH
Register
RXCP User-Programmable Cell Pattern: octet RXCP User-Programmable Cell Pattern: octet RXCP User-Programmable Cell Pattern: octet RXCP User-Programmable Cell Pattern: octet RXCP User-Programmable Cell Mask: octet RXCP User-Programmable Cell Mask: octet RXCP User-Programmable Cell Mask: octet RXCP User-Programmable Cell Mask: octet RXCP Control/Status RXCP Count Threshold Reserved TXCP Control TXCP Interrupt Enable/Status TXCP Idle/Unassigned Cell Pattern: octet TXCP Idle/Unassigned Cell Pattern: octet TXCP Idle/Unassigned Cell Pattern: octet TXCP Idle/Unassigned Cell Pattern: octet
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Address 08EH 08FH 090H 0FFH 18EH 18FH 190H 1FFH 28EH 28FH 290H 2FFH 38EH 38FH 390H 3FFH
Register
TXCP Idle/Unassigned Cell Pattern: octet TXCP Idle/Unassigned Cell Payload Reserved Reserved Test
400H-7FFH
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NORMAL MODE REGISTER DESCRIPTION Normal mode registers used configure monitor operation S/UNI-MPH. Normal mode registers opposed test mode registers) selected when A[10] low. Notes Normal Mode Register Bits: Writing values into unused register bits effect. Reading back unused bits produce either logic logic hence, unused register bits should masked software when read. configuration bits that written into also read back. This allows processor controlling S/UNI-MPH determine programming state chip. Writeable normal mode register bits cleared zero upon reset unless otherwise noted. Writing into read-only normal mode register locations does affect S/UNI-MPH operation unless otherwise noted.
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Registers 000H, 100H, 200H 300H: Receive Configuration Type Function WORDERR CNTNFAS RXDMAGAT Unused Unused Unused MODE[1] MODE[0] Default
These registers used configure receive interfaces S/UNI-MPH. WORDERR: When format enabled, WORDERR determines frame alignment signal (FAS) errors reported. When WORDERR logic more errors seven word results single framing error count. When WORDERR logic each error word results single framing error count. CNTNFAS: When format enabled, CNTNFAS determines whether nonframe alignment signal (NFAS) errors reported. When CNTNFAS logic zero time slot NFAS frames results increment framing error count. WORDERR also logic word defined eight bits comprising pattern time slot next NFAS frame. When CNTNFAS logic only errors affect framing error count. RXDMAGAT: RXDMAGAT selects gating RDLINT[x] output with RDLEOM[x] output when internal HDLC receiver used with DMA. When RXDMAGAT logic RDLINT[x] output gated with RDLEOM output that RDLINT forced logic when RDLEOM logic When RXDMAGAT logic RDLINT[x] RDLEOM[x] outputs operate independently.
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PM7344 S/UNI-MPH
DATA SHEET PMC-950449 ISSUE MULTI-PHY USER NETWORK INTERFACE
MODE [1:0]: MODE[1:0] bits determine configuration each physical interface receiver S/UNI-MPH. four interfaces must configured identically writing these bits each four Receive Configuration registers. MODE[1] MODE[0] Configuration 1.544 Mbit/s AUNI 2.048 Mbit/s AUNI 6.312 Mbit/s AUNI This configuration requires external framer. Arbitrary Format Mbit/s) This configuration relies external device identify overhead bits arbitrary transmission format.
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Registers 001H, 101H, 201H 301H: Transmit Configuration Type Function LCDEN AISEN REDEN OOFEN LOSEN TAISEN MODE[1] MODE[0] Default
These registers used configure transmit interfaces S/UNI-MPH. LCDEN: LCDEN enables receive loss cell delineation indication automatically generate receive failure indication transmit stream. This operates regardless framer selected E1). When LCDEN logic declaration alarm causes yellow alarm (T1) remote alarm indication (E1) transmitted duration alarm. When LCDEN logic assertion alarm does cause transmission receive failure indication. AISEN: AISEN enables alarm indication signal carrier failure alarm automatically generate receive failure indication transmit stream. This operates regardless framer selected E1). When AISEN logic declaration causes yellow alarm (T1) remote alarm indication (E1) transmitted duration CFA. When AISEN logic assertion does cause transmission receive failure indication. REDEN: REDEN enables carrier failure alarm (persistent frame) indication automatically generate receive failure indication transmit stream. This operates regardless format selected When REDEN logic declaration causes yellow alarm (T1)
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remote alarm indication (E1) transmitted duration CFA. When REDEN logic assertion does cause transmission receive failure indication. OOFEN: OOFEN enables receive frame indication automatically generate receive failure indication transmit stream. This operates regardless format selected E1). When OOFEN logic declaration alarm causes yellow alarm (T1) remote alarm indication (E1) transmitted duration alarm. When OOFEN logic assertion alarm does cause transmission receive failure indication. LOSEN: LOSEN enables receive loss signal indication automatically generate receive failure indication transmit stream. This operates regardless format selected E1). When LOSEN logic declaration alarm causes yellow alarm (T1) remote alarm indication (E1) transmitted duration alarm. alarm removed when pulse density requirements format satisfied. When LOSEN logic assertion alarm does cause transmission receive failure indication. TAISEN: When format selected, TAISEN enables generation unframed all-ones alarm TDP/TDD[x] TDN/TOHO[x] multifunction pins. When TAISEN logic TUNI logic bi-polar TDP[x] TDN[x] outputs forced pulse alternately, creating all-ones signal; when TAISEN TUNI bot
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