405GPr Power 405GPr Embedded Processor PowerPC® 32-bit RISC

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405GPr Power 405GPr Embedded Processor PowerPC® 32-bit RISC

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Part Number 405GPr Revision 2.02 August 2005
405GPr
Power 405GPr Embedded Processor
PowerPC® 32-bit RISC processor core operating 400MHz with 16KB D-caches Synchronous DRAM (SDRAM) interface operating 133MHz 32-bit interface non-ECC applications 40-bit interface serves bits data plus check bits applications on-chip memory (OCM) External peripheral Flash ROM/Boot interface Direct support 16-, 32-bit SRAM external peripherals eight devices External Mastering supported support external peripherals, internal UART memory Scatter-gather chaining supported Four channels Revision compliant interface (32-bit, 66MHz) Unique software-accessible 64-bit chip number (ECID). Synchronous asynchronous interface Internal external Arbiter Ethernet 10/100Mbps (full-duplex) support with media independent interface (MII) Programmable interrupt controller supports external internal edge triggered levelsensitive interrupts Programmable timers serial ports (16550 compatible UART) interface General purpose (GPIO) available Supports JTAG board level testing Internal processor local (PLB) runs SDRAM interface frequency Supports PowerPC processor boot from memory
Description
Designed specifically address embedded applications, PowerPC 405GPr (PPC405GPr) provides high-performance, low-power solution that interfaces wide range peripherals incorporating on-chip power management features lower power dissipation requirements. This chip contains high-performance RISC processor core, SDRAM controller, interface, Ethernet interface, control external peripherals, with scatter-gather support, serial ports, interface, general purpose I/O. Technology: CMOS SA-27E, 0.18 (0.11 Leff) Package: 456-ball (35mm 27mm) enhanced plastic ball grid array (E-PBGA) both leaded lead-free versions Power (typical): 0.72W 266MHz
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Contents
Ordering, PVR, JTAG Information Address Support On-Chip Memory (OCM) Interface SDRAM Memory Controller External Peripheral Controller (EBC) Controller Serial Interface Interface General Purpose (GPIO) Controller Universal Interrupt Controller (UIC) 10/100 Mbps Ethernet JTAG Signal List Spread Spectrum Clocking Strapping
Tables
System Memory Address Address Signals Listed Alphabetically Signals Listed Ball Assignment Summary Signal Functional Description Absolute Maximum Ratings Package Thermal Specifications Recommended Operating Conditions Input Capacitance Electrical Characteristics Clocking Specifications Peripheral Interface Clock Timings Specifications-Group Specifications-Group PPC405GPr Legacy Mode Strapping Assignments PPC405GPr Mode Strapping Assignments
AMCC
Revision 2.02 August 2005
Figures
405GPr Power 405GPr Embedded Processor
PPC405GPr Embedded Controller Functional Block Diagram 27mm, 456-Ball E-PBGA Package 35mm, 456-Ball E-PBGA Package 5V-Tolerant Input Current Input Setup Hold Waveform Output Delay Float Timing Waveform
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Ordering, PVR, JTAG Information
Processor Frequency 266MHz 266MHz 266MHz 266MHz 266MHz 266MHz 266MHz 266MHz 333MHz2 333MHz2 333MHz2 333MHz2 333MHz2 333MHz2 333MHz2 333MHz2 400MHz 400MHz 400MHz 400MHz 400MHz 400MHz 400MHz 400MHz Level
Product Name PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr
Order Part Number1 PPC405GPr-3BB266 PPC405GPr-3JB266 PPC405GPr-3BB266Z PPC405GPr-3JB266Z PPC405GPr-3DB266 PPC405GPr-3KB266 PPC405GPr-3DB266Z PPC405GPr-3KB266Z PPC405GPr-3BB333 PPC405GPr-3JB333 PPC405GPr-3BB333Z PPC405GPr-3JB333Z PPC405GPr-3DB333 PPC405GPr-3KB333 PPC405GPr-3DB333Z PPC405GPr-3KB333Z PPC405GPr-3BB400 PPC405GPr-3JB400 PPC405GPr-3BB400Z PPC405GPr-3JB400Z PPC405GPr-3DB400 PPC405GPr-3KB400 PPC405GPr-3DB400Z PPC405GPr-3KB400Z
Package 35mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 27mm, E-PBGA 27mm, E-PBGA 27mm, E-PBGA 27mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 27mm, E-PBGA 27mm, E-PBGA 27mm, E-PBGA 27mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 27mm, E-PBGA 27mm, E-PBGA 27mm, E-PBGA 27mm, E-PBGA
Value 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951
JTAG 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049
Notes Order Part Number indicates tape-and-reel shipping package. Otherwise, chips shipped tray. 333MHz parts operated 266MHz less, operational temperature range extended 105°C
part number contains revision code. This refers mask revision number included part numbering scheme identification purposes only. (Processor Version Register) software accessible contains additional information about revision level part. Refer PowerPC 405GPr Embedded Processor User's Manual details register content.
AMCC
Revision 2.02 August 2005
Order Part Number
405GPr Power 405GPr Embedded Processor
PPC405GPr3BB266x
Shipping Package Blank Tray Tape reel Part Number Grade Reliability Processor Speed 266MHz 333MHz 400MHz Revision Level
Package Operational Case Temperature 35mm, E-PBGA, -40°C +85°C 27mm, E-PBGA, -40°C +85°C 35mm, E-PBGA lead-free, -40°C +85°C 27mm, E-PBGA lead-free, -40°C +85°C
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
PPC405GPr Embedded Controller Functional Block Diagram
Universal Interrupt Controller Clock Control Reset Timers Power Mgmt DOCM IOCM SRAM DCRs Control GPIO UART UART
PPC405 Processor Core JTAG 16KB D-Cache Trace
16KB I-Cache
On-chip Peripheral (OPB)
Controller (4-Channel)
Bridge
Ethernet
Code Decompression (CodePackTM)
Processor Local (PLB)
SDRAM Controller
External Controller
External Master Controller
Bridge
13-bit addr 32-bit data
32-bit addr 32-bit data
(async) (sync)
PPC405GPr designed using IBM® Microelectronics Blue Logicmethodology which major functional blocks integrated together create application-specific ASIC product. This approach provides consistent create complex ASICs using CoreConnectBus Architecture.
AMCC
Revision 2.02 August 2005
Address Support
405GPr Power 405GPr Embedded Processor
PPC405GPr incorporates simple separate address maps. first address defines possible address regions that processor access. second address Device Configuration Registers (DCRs). DCRs accessed software running PPC405GPr processor through mtdcr mfdcr instructions.
System Memory Address System Memory
Function Subfunction SDRAM, External Peripherals, Memory Note: address ranges listed right above functions. Peripheral Boot Boot Configuration Registers Interrupt Acknowledge Special Cycle Local Configuration Registers UART0 UART1 Internal Peripherals IIC0 Arbiter GPIO Controller Registers Ethernet Controller Registers
Start Address 0x00000000 0xE8010000 0xEC000000 0xEEE00000 0xEF500000 0xF0000000 0xFFE00000 0xFFFE0000 0xE8000000 0xE8800000 0xEEC00000 0xEED00000 0xEF400000 0xEF600300 0xEF600400 0xEF600500 0xEF600600 0xEF600700 0xEF600800
Address 0xE7FFFFFF 0xE87FFFFF 0xEEBFFFFF 0xEF3FFFFF 0xEF5FFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xE800FFFF 0xEBFFFFFF 0xEEC00007 0xEED00003 0xEF40003F 0xEF600307 0xEF600407 0xEF60051F 0xEF60063F 0xEF60077F 0xEF6008FF
Size 3712MB 44MB 256MB 128KB 64KB 56MB 128B 256B
General
Boot-up
Notes: When peripheral boot selected, peripheral bank automatically configured reset address range listed above. boot selected, PLB-to-PCI mapping automatically configured reset address range listed above. After boot process, software reassign boot memory regions other uses. address ranges listed above reserved.
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Address Device Configuration Registers
Function Total Address Space1 function: Reserved Memory Controller Registers External Controller Registers Decompression Controller Registers Reserved On-Chip Memory Controller Registers Reserved Registers Reserved Bridge Registers Electronic Chip (ECID) Reserved Clock, Control, Interrupt Routing, Reset Power Management Interrupt Controller Reserved Controller Registers Reserved Ethernet Registers Reserved Notes: address space addressable with bits (1024 unique addresses). Each unique address represents single 32-bit (word) register, kiloword (KW) (which equals KB). 0x000 0x010 0x012 0x014 0x016 0x018 0x020 0x080 0x090 0x0A0 0x0A8 0x0AA 0x0B0 0x0B8 0x0C0 0x0D0 0x100 0x140 0x180 0x200 0x00F 0x011 0x013 0x015 0x017 0x01F 0x07F 0x08F 0x09F 0x0A7 0x0A9 0x0AF 0x0B7 0x0BF 0x0CF 0x0FF 0x13F 0x17F 0x1FF 0x3FF 128W 512W Start Address 0x000 Address 0x3FF Size (4KB)1
AMCC
Revision 2.02 August 2005
On-Chip Memory (OCM)
405GPr Power 405GPr Embedded Processor
feature comprises memory controller one-port static (SRAM) accessed processor core. Features include: Low-latency access critical instructions data Performance identical cache hits without misses Contents change only under program control
Interface
interface core provides mechanism connecting devices local PowerPC processor local memory. This interface compliant with version Specification. Features include: Internal arbiter external devices speeds 66MHz. Internal arbiter optional disabled systems which employ external arbiter. frequency 66MHz Synchronous operation fractions speed 33MHz maximum Asynchronous operation from frequency 66MHz maximum 32-bit address/data Power Management: Power Management v1.1 compliant Supports 1:1, 2:1, 3:1, clock ratios from Buffering between PCI: target 64-byte write post buffer target 96-byte read prefetch buffer slave 32-byte write post buffer slave 64-byte read prefetch buffer Error tracking/status Supports target side configuration Supports processor access address spaces: Single-byte reads writes memory single-beat prefetch-burst reads single-beat writes Single-byte configuration reads writes (type type interrupt acknowledge special cycle
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Supports target access address spaces Supports PowerPC processor boot from memory
SDRAM Memory Controller
PPC405GPr Memory Controller core provides latency access path SDRAM memory. variety system memory configurations supported. memory controller supports four physical banks. 256MB bank supported, maximum 1GB. Memory timings, address bank sizes, memory addressing modes programmable. Features include: 11x8 13x11 addressing SDRAM 4-bank) 32-bit memory interface support Programmable address compare each bank memory Industry standard 168-pin DIMMS supported (some configurations) PC-133 support memory 256MB bank Programmable address mapping timing Auto refresh Page mode accesses with open pages Power management (self-refresh) Error checking correction (ECC) support Standard single-error correct, double-error detect coverage Aligned nibble error detect Address error logging
External Peripheral Controller (EBC)
Supports eight banks ROM, EPROM, SRAM, Flash memory, slave peripherals 66MHz operation Burst non-burst devices 16-, 32-bit byte-addressable data width support Latch data Ready Programmable clock time-out counter with disable Ready Programmable access timing device 0-255 wait states non-bursting devices 0-31 burst wait states first access wait states subsequent accesses
AMCC
Revision 2.02 August 2005
405GPr Power 405GPr Embedded Processor
Programmable CSon, CSoff relative address Programmable OEon, WEon, WEoff clock cycles) relative Programmable address mapping Peripheral Device pacing with external "Ready" External master interface Write posting from external master Read prefetching external master reads Bursting capable from external master Allows external master access non-EBC slaves External master control slaves access control
Controller
Supports following transfers: Memory-to-memory transfers Buffered peripheral memory transfers Buffered memory peripheral transfers Four channels Scatter/gather capability programming multiple operations 16-, 32-bit peripheral support (OPB external) 32-bit addressing Address increment decrement Internal 32-byte data buffering capability Supports internal external peripherals Support memory mapped peripherals Support peripherals running slower frequency buses
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Serial Interface
8-pin UART 4-pin UART interface provided Selectable internal external serial clock allow wide range baud rates Register compatibility with NS16550 register Complete status reporting capability Transmitter receiver each buffered with 16-byte FIFOs when FIFO mode Fully programmable serial-interface characteristics Supports using internal engine
Interface
Compliant with Philips® Semiconductors Specification, dated 1995 Operation 100kHz 400kHz 8-bit data 7-bit address Slave transmitter receiver Master transmitter receiver Multiple masters Supports fixed interface independent byte data buffers Fifteen memory-mapped, fully programmable configuration registers programmable interrupt request signal Provides full management protocol Programmable error recovery
General Purpose (GPIO) Controller
Controller functions GPIO registers programmed accessed memory-mapped master accesses GPIOs pin-shared with other functions. DCRs control whether particular that GPIO capabilities acts GPIO used another purpose. GPIOs multiplexed with: chip selects external interrupts nine instruction trace pins Each GPIO output separately programmable emulate open-drain driver (i.e., drives zero, threestated output
AMCC
Revision 2.02 August 2005
Universal Interrupt Controller (UIC)
405GPr Power 405GPr Embedded Processor
Universal Interrupt Controller (UIC) provides control, status, communications necessary between various sources interrupts local PowerPC processor. Features include: Supports external internal interrupts Seven interrupts mapped same GPIOs PPC405GP. other interrupts mapped GPIOs. Edge triggered level-sensitive Positive negative active Non-critical critical interrupt processor core Programmable critical interrupt priority ordering Programmable critical interrupt vector faster vector processing
10/100 Mbps Ethernet
Capable handling full/half duplex 100Mbps 10Mbps operation Uses medium independent interface (MII) physical layer (PHY included chip)
JTAG
IEEE 1149.1 test access port RISCWatch debugger support JTAG Boundary Scan Description Language (BSDL)
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
27mm, 456-Ball E-PBGA Package
View
Reserved area ejector mark Corner shape chamfered rounded
Gold Gate Release Corresponds Ball Location
Notes: dimensions
This package available leaded lead-free configurations.
0.20
0.20 27.0 25.0
0.25 0.35
Bottom View
27.0
Thermal Balls
Mold Compound
Substrate
0.60 SOLDERBALL 0.30 0.10 0.5±0.1 2.65
AMCC
Revision 2.02 August 2005
35mm, 456-Ball E-PBGA Package
405GPr Power 405GPr Embedded Processor
View
Reserved area ejector mark Corner shape chamfered rounded
Gold Gate Release Corresponds Ball Location
30.0
Notes: dimensions
This package available leaded lead-free configurations.
0.20
0.20 35.0 31.75
0.25 0.35
Bottom View
35.0
Thermal Balls
1.27
Mold Compound
Substrate
0.75 0.15 SOLDERBALL 0.30 0.15 0.6±0.1 2.65
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Lists
PPC405GPr embedded controller available 456-ball E-PBGA leaded lead-free package. 456ball package available sizes-35 millimeters millimeters. this section there tables that correlate external signals physical package (ball) which they appear. following table lists external signals alphabetical order shows ball number which signal appears. Multiplexed signals shown with default signal (following reset) brackets alternate signal brackets. Multiplexed signals appear alphabetically multiple times list-once each signal name ball. page number listed gives page "Signal Functional Description" page where signals indicated interface group begin.
Signals Listed Alphabetically
Signal Name AGND AVDD BankSel0 BankSel1 BankSel2 BankSel3 BE0[PCIC0] BE1[PCIC1] BE2[PCIC2] BE3[PCIC3] BusReq ClkEn0 ClkEn1 DMAAck0 DMAAck1 DMAAck2 DMAAck3 DMAReq0 DMAReq1 DMAReq2 DMAReq3 DQM0 DQM1 DQM2 DQM3 DQMCB ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMCMDClk EMCMDIO[PHYMDIO] EMCTxD0 EMCTxD1 EMCTxD2 EMCTxD3 EMCTxEn Ball AB24 AC24 AD17 AF17 AE15 AC14 AB23 AB25 AC25 AC12 AC10 AC15 AE14 AF15 AF14 AD13 AF13 AF12 AE13 AD12 AD26
(Sheet
Interface Group Page
System System SDRAM
SDRAM
External Master Peripheral SDRAM SDRAM
External Slave Peripheral
External Slave Peripheral
SDRAM SDRAM
SDRAM
Ethernet Ethernet Ethernet Ethernet
AMCC
Revision 2.02 August 2005
Signals Listed Alphabetically
Signal Name EMCTxErr EOT0/TC0 EOT1/TC1 EOT2/TC2 EOT3/TC3 ExtAck ExtReq ExtReset Ball Ethernet
405GPr Power 405GPr Embedded Processor
(Sheet
Interface Group Page
External Slave Peripheral External Master Peripheral External Master Peripheral External Master Peripheral
Ground Note: L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, T11-T16 also thermal balls. L11-L16 M11-M16 N11-N16 P11-P16 R11-R16 T11-T16 AA26
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Signals Listed Alphabetically
Signal Name Ball AB13 AB14 AB18 AB22 AC23 AD24 AE25 AF11 AF16 AF21 AF25 AF26 AF18 AA24 AB26 AA24
(Sheet
Interface Group Page
Ground Note: L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, T11-T16 also thermal balls.
Gnt[PCIReq0] GPIO1[TS1E] GPIO2[TS2E] GPIO3[TS1O] GPIO4[TS2O] GPIO5[TS3] GPIO6[TS4] GPIO7[TS5] GPIO8[TS6] GPIO9[TrcClk] [GPIO10]PerCS1 [GPIO11]PerCS2 [GPIO12]PerCS3 [GPIO13]PerCS4 [GPIO14]PerCS5 [GPIO15]PerCS6 [GPIO16]PerCS7 [GPIO17]IRQ0 [GPIO18]IRQ1 [GPIO19]IRQ2 [GPIO20]IRQ3 [GPIO21]IRQ4 [GPIO22]IRQ5 [GPIO23]IRQ6 GPIO24 Halt HoldAck HoldPri HoldReq IICSCL IICSDA IRQ0[GPIO17] IRQ1[GPIO18] IRQ2[GPIO19] IRQ3[GPIO20] IRQ4[GPIO21] IRQ5[GPIO22] IRQ6[GPIO23]
System
System
System
System External Master Peripheral External Master Peripheral External Master Peripheral Internal Peripheral Internal Peripheral
Interrupts
AMCC
Revision 2.02 August 2005
Signals Listed Alphabetically
Signal Name MemAddr0 MemAddr1 MemAddr2 MemAddr3 MemAddr4 MemAddr5 MemAddr6 MemAddr7 MemAddr8 MemAddr9 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut1 MemData0 MemData1 MemData2 MemData3 MemData4 MemData5 MemData6 MemData7 MemData8 MemData9 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 Ball AE22 AC21 AE21 AD21 AF22 AE20 AC19 AE19 AD19 AC18 AF19 AD18 AC17 AC26 AA23 AC13 AE12 AD11 AC11 AF10 AE11 AD10
405GPr Power 405GPr Embedded Processor
(Sheet
Interface Group Page
SDRAM Note: During cycle MemAddr0 least significant (lsb) this bus.
SDRAM
SDRAM Note: MemData0 most significant (msb) this bus.
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Signals Listed Alphabetically
Signal Name Ball AA22 AB19 AB20 AB21 AD14 AE10
(Sheet
Interface Group Page
OVDD
Output driver voltage
PCIAD0 PCIAD1 PCIAD2 PCIAD3 PCIAD4 PCIAD5 PCIAD6 PCIAD7 PCIAD8 PCIAD9 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCIC0[BE0] PCIC1[BE1] PCIC2[BE2] PCIC3[BE3]
Note: PCIAD31 most significant (msb) this bus.
AMCC
Revision 2.02 August 2005
Signals Listed Alphabetically
Signal Name PCIClk PCIDevSel PCIFrame PCIGnt0[Req] PCIGnt1 PCIGnt2 PCIGnt3 PCIGnt4 PCIGnt5 PCIIDSel PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0[Gnt] PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY PerAddr0 PerAddr1 PerAddr2 PerAddr3 PerAddr4 PerAddr5 PerAddr6 PerAddr7 PerAddr8 PerAddr9 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk Ball
405GPr Power 405GPr Embedded Processor
(Sheet
Interface Group Page
External Slave Peripheral
External Slave Peripheral External Master Peripheral
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Signals Listed Alphabetically
Signal Name PerCS0 PerCS1[GPIO10] PerCS2[GPIO11] PerCS3[GPIO12] PerCS4[GPIO13] PerCS5[GPIO14] PerCS6[GPIO15] PerCS7[GPIO16] PerData0 PerData1 PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerData8 PerData9 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 PerErr PerOE PerPar0 PerPar1 PerPar2 PerPar3 PerReady PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 [PerWE]PCIINT PHYCol PHYCrS PHYRxClk PHYMDIO[EMCMDIO] PHYRxD0 PHYRxD1 PHYRxD2 PHYRxD3 PHYRxDV Ball AA25 AF20 AD26 AE23 AF23 AC20 AD20
(Sheet
Interface Group Page
External Slave Peripheral
External Slave Peripheral
External Master Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet
AMCC
Revision 2.02 August 2005
Signals Listed Alphabetically
Signal Name PHYRxErr PHYTxClk Ball AF24 AF41 AD25 AD22 AE24 AD23 AC22 AE26 AF18 AE18 AD15 AD16 AE16 AE17 Ethernet Ethernet SDRAM
405GPr Power 405GPr Embedded Processor
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Interface Group Page
Reserved
Other Note: must tied OVDD GND. other reserved pins should left unconnected. System System System JTAG JTAG JTAG System System JTAG JTAG
Req[PCIGnt0] SysClk SysErr SysReset TestEn TmrClk TRST [TS1E]GPIO1 [TS2E]GPIO2 [TS1O]GPIO3 [TS2O]GPIO4 [TS3]GPIO5 [TS4]GPIO6 [TS5]GPIO7 [TS6]GPIO8 [TrcClk]GPIO9 UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_CTS/UART1_DSR UART1_DSR/UART1_CTS UART1_DTR/UART1_RTS UART1_RTS/UART1_DTR UART1_Rx UART1_Tx UARTSerClk
System
Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Signals Listed Alphabetically
Signal Name Ball AB10 AB11 AB12 AB15 AB16 AB17 AC16
(Sheet
Interface Group Page
Logic voltage
SDRAM
AMCC
Revision 2.02 August 2005
Signals Listed Ball Assignment
Ball Signal Name PerAddr1 PerCS3[GPIO12] PerAddr8 DMAReq3 PerAddr15 PerCS6[GPIO15] PerAddr19 PerAddr25 PerAddr26 PerAddr28 PerAddr29 PCIAD0 PCIAD3 PCIAD7 GPIO3[TS1O] PCIAD9 PCIReq3 SysClk PerErr PerCS0 PerAddr2 PerAddr3 PerAddr5 PerAddr9 PerAddr12 PerCS4[GPIO13] PerCS5[GPIO14] PerCS7[GPIO16] PerAddr21 PerAddr24 PCIStop EMCMDClk PCIDevSel PCIGnt3 Ball
405GPr Power 405GPr Embedded Processor
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Ball Signal Name PerWBE3 PerWBE0 PerPar0 PerAddr0 PerAddr4 PerAddr7 PerAddr11 PerAddr14 PerAddr17 PerAddr20 PerAddr23 PerAddr22 DMAReq1 PerAddr31 DMAAck0 PCIAD4 GPIO1[TS1E] PCIC0[BE0] GPIO24 PCIAD10 SysReset TmrClk AVDD TestEn PerPar3 PerWBE1 PerReady PerClk OVDD OVDD OVDD Ball Signal Name OVDD OVDD OVDD AGND Reserved Reserved PHYTxClk PCIParity PerBLast EOT0/TC0 PerWBE2 OVDD OVDD PCIGnt2 PCIC1[BE1] PCIAD15 PerData29 EOT1/TC1 PerPar2 PerPar1 OVDD OVDD PCIReq4 PCISErr PCIPErr PCITRDY PerData30 PerData28 PerData31 OVDD OVDD PerData2 HoldAck PerData1 PerData0
Signal Name DMAAck2 DMAAck1 PCIAD1 OVDD PCIAD6 PCIReq2 PCIClk PCIAD8 PCIAD11 PCIAD12 PCIReset PerR/W PerOE PerCS1[GPIO10] PerCS2[GPIO11] PerAddr6 PerAddr10 PerAddr13 PerAddr16 PerAddr18 DMAReq2 DMAAck3 OVDD PerAddr27 PerAddr30 DMAReq0 PCIAD2 PCIAD5 PCIReq0[Gnt] GPIO2[TS2E] PCIReq1 PCIAD13 PCIINT[PerWE] Reserved PCIAD14 PerData12 PerData17 PerData14 PerData15
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405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Signals Listed Ball Assignment
Ball AA22 AA23 AA24 Signal Name PerData23 PerData26 PerData25 PerData27 PCIIRDY PCIFrame PCIReq5 EMCTxD0 PerData20 OVDD PerData22 PerData24 EMCTxEn PCIC2[BE2] EMCTxErr PCIAD16 PerData21 PerData18 PerData19 PCIAD17 EMCTxD2 EMCTxD1 MemData23 DQM3 MemData22 OVDD OVDD MemClkOut1 IRQ6[GPIO23] Ball AB26
(Sheet
Ball AD10 AD11 AD12 AD13 AD14 AD15 AD16 Signal Name PCIAD26 PCIAD23 EMCTxD3 PCIIDSel PerData8 PerData4 BusReq PerData6 PCIAD25 PCIAD24 PCIAD27 PCIC3[BE3] HoldPri ExtReset PerData3 PCIGnt1 PCIAD28 PCIAD30 MemData8 MemData6 MemData2 ECC7 ECC3 OVDD UART0_RI UART0_RTS Ball AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 Signal Name PCIGnt0[Req] PHYRxErr OVDD PCIAD29 HoldReq EOT2/TC2 MemData31 MemData29 IRQ1[GPIO18] PHYRxDV IRQ0[GPIO17] PCIAD31 MemData30 MemData27 MemData28 MemData26 OVDD OVDD PHYCrS IRQ2[GPIO19] IRQ3[GPIO20] EOT3/TC3 MemData25 ExtAck ExtReq OVDD OVDD Reserved IRQ4[GPIO21] IRQ5[GPIO22] Reserved UART0_DCD MemAddr7 MemAddr5 MemAddr2 MemAddr0 PHYRxD0
Signal Name
PCIAD19 PCIGnt5 PCIAD18 PCIAD21 PerData11 PerData13 PerData10 PerData16 PCIGnt4 OVDD PCIAD20 PCIAD22 PerData9 PerData7 OVDD PerData5 Halt UART1_Rx UART1_Tx UART1_DSR/ UART1_CTS MemData19 DQM2 GPIO8[TS6]
AMCC
Revision 2.02 August 2005
Signals Listed Ball Assignment
Ball AA25 AA26 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 Signal Name PHYCol MemData24 MemData21 GPIO9[TrcClk] UART0_CTS OVDD OVDD OVDD OVDD OVDD OVDD ClkEn0 Ball AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26
405GPr Power 405GPr Embedded Processor
(Sheet
Ball AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 Signal Name BankSel0 MemAddr11 MemAddr8 PHYRxD3 MemAddr3 SysErr EMCMDIO [PHYMDIO] UART0_DSR MemData16 MemData15 MemData14 IICSDA GPIO6[TS4] MemData9 OVDD MemData5 MemData1 ECC6 ECC0 BankSel2 UART0_Rx UARTSerClk Ball AE26 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal Name TRST UART0_DTR UART0_Tx Reserved GPIO7[TS5] MemData11 MemData7 MemData4 ECC5 ECC4 ECC2 ECC1 BankSel1 GPIO4[TS2O] MemAddr10 PHYRxClk MemAddr4 PHYRxD1
Signal Name MemData12 GPIO5[TS3] DQM1 MemData3 DQM0 MemData0 BankSel3 DQMCB MemAddr12 MemAddr9 MemAddr6 PHYRxD2 MemAddr1 ClkEn1 MemClkOut0 MemData20 UART1_RTS/ UART1_DTR MemData18 MemData17 IICSCL MemData13 MemData10
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Signal List
following table provides summary number package pins associated with each functional interface group.
Summary
Group
Ethernet SDRAM External peripheral External master Internal peripheral Interrupts JTAG System Total Signal Pins OVDD Thermal (and Gnd) Reserved Total Pins
Pins
Multiplexed Pins table "Signal Functional Description" page each external signal listed along with description signal function. Some signals multiplexed same (ball) that used different functions. Multiplexed signals shown default signal with secondary signal square brackets (for example, GPIO1[TS1E]). Active-low signals (for example, RAS) marked with overline. expected that single application particular will always programmed serve same function. flexibility multiplexing allows single chip offer richer selection than would otherwise possible. addition multiplexing, many pins also multi-purpose. example, peripheral controller address pins used outputs PPC405GPr broadcast address external slave devices when PPC405GPr control external bus. When, during course normal chip operation, external master gains ownership external bus, these same pins used inputs which driven external master received PPC405GPr. this example, pins also bidirectional, serving both inputs outputs. Intialization Strapping group pins used strapped inputs during system reset. These pins function strapped inputs only during reset used other functions during normal operation (see "Strapping" page 51). Note that these pins strapping considered multiplexing since strapping function programmable.
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Revision 2.02 August 2005
Pull-Up Pull-Down Resistors
405GPr Power 405GPr Embedded Processor
Pull-up pull-down resistors used strapping during reset retain unused undriven inputs appropriate state. recommended pull-up value +3.3V (10k used tolerant I/Os) pull-down value GND, applies only individually terminated signals. prevent possible damage device, I/Os capable becoming outputs must never tied together terminated through common resistor. your system-level test methodology permits, input-only signals connected together terminated through either common resistor directly +3.3V GND. When resistor used, value must ensure that grouped I/Os reach valid logic zero logic state when accounting total input current into PPC405GPr. Unused I/Os some interfaces, possible turn input receivers some signals means settings register CPC0_CR1. When this gating capability applied unused signals, necessary terminate them. Refer PowerPC 405GPr Embedded Processor User's Manual details. receiver gating used, termination some pins necessary when they unused. Although PPC405GPr requires only pull-up pull-down terminations specified "Signal Functional Description" page good design practice terminate unused inputs configure I/Os such that they always drive. unused, receiver gating used, peripheral, SDRAM, buses should configured terminated follows: Peripheral interface-PerAddr0:31, PerData0:31, control signals driven default. Terminate PerReady high PerError low. SDRAM-Program SDRAM0_CFG[EMDULR]=1 SDRAM0_CFG[DCE]=1. This causes PPC405GPr actively drive SDRAM address, data, control signals. PCI-The pull-up requirements given Signal Functional Description apply only when interface being used. When bridge unused, configure controller park actively drive PCIAD31:0, PCIC3:0[BE3:0], remaining control signals doing following: Strap PPC405GPr disable internal arbiter operate interface synchronous mode. Individually connect PCISErr, PCIPErr, PCITRDY, PCIStop through resistors +3.3V. Terminate PCIReq1:5 +3.3V. Terminate PCIReq0[Gnt] GND. External Control Signals peripheral control signals (PerCS0:7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck, ExtAck) high-impedance state when ExtReset=0. addition, detailed PowerPC 405GPr Embedded Processor User's Manual, peripheral controller programmed EBC0_CFG float some these control signals between transactions and/or when external master owns peripheral bus. result, pullup resistor should added those control signals where undriven state affect devices receiving that particular signal. following table lists signals provided PPC405GPr. Please refer "Signals Listed Alphabetically" page number which each signal assigned.
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Signal Functional Description
(Sheet Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Control Signals" page
Signal Name Description Type
Notes
Interface
PCIAD31:0 PCIC3:0[BE3:0] Address/Data Bus. Multiplexed address data bus. command byte enables. parity. Parity even across PCIAD0:31 PCIC0:3[BE0:3]. PCIParity valid cycle after either address data phase. device that drove PCIAD0:31 responsible driving PCIParity next clock. PCIFrame driven current master indicate beginning duration access. PCIIRDY driven current master. Assertion PCIIRDY indicates that initiator ready transfer data. target current transaction drives PCITRDY. Assertion PCITRDY indicates that target ready transfer data. target current transaction assert PCIStop indicate requesting master that wants current transaction. PCIDevSel driven target current transaction. target asserts PCIDevSel when decoded address command encoding claims transaction. PCIIDSel used during configuration cycles select slave interface configuration. PCISErr used reporting address parity errors catastrophic failures detected target. PCIPErr used reporting data parity errors transactions. PCIPErr driven active device receiving PCIAD0:31, PCIC0:3[BE0:3], PCIParity, clocks following data which parity detected. PCIClk used asynchronous clock when asynchronous mode. unused when interface operated synchronously with bus. specific reset. interrupt. Open-drain output (two states; open circuit) Peripheral write enable. when four PerWBE0:3 write byte enables low. Multipurpose signal, used PCIReq0 when internal arbiter used, when external arbiter used. Used PCIReq1:5 input when internal arbiter used. tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V
PCIParity
PCIFrame PCIIRDY PCITRDY
PCIStop
PCIDevSel
PCIIDSel PCISErr
PCIPErr
PCIClk
tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V
PCIReset
PCIINT[PerWE]
PCIReq0[Gnt] PCIReq1:5
AMCC
Revision 2.02 August 2005
Signal Functional Description
405GPr Power 405GPr Embedded Processor
(Sheet Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Control Signals" page
Signal Name PCIGnt0[Req] Description Gnt0 when internal arbiter used when external arbiter used. Used PCIGnt1:5 output when internal arbiter used. Type tolerant 3.3V tolerant 3.3V
Notes
PCIGnt1:5
Ethernet Interface
PHYRxD3:0 EMCTxD3:0 PHYRxErr PHYRxClk Received data. This nibble wide from PHY. data synchronous with PHYRxClk. Transmit data. nibble wide data towards net. data synchronous PHYTxClk. Receive Error. This signal comes from synchronous PHYRxClk. Receiver Medium clock. This signal generated PHY. Receive Data Valid. Data Data valid when this signal activated. Deassertion this signal indicates frame reception. Carrier Sense signal from PHY. This asynchronous signal. Transmit Error. This signal generated Ethernet controller, connected synchronous with PHYTxClk. informs that error detected. Transmit Enable. This signal driven EMAC PHY. Data valid during active state this signal. Deassertion this signal indicates frame transmission. This signal synchronous PHYTxClk. This clock comes from Medium Transmit clock. Collision signal from PHY. This asynchronous signal. Management Data Clock. MDClk sourced PHY. This clock period 400ns, adjustable EMAC0_STACR[OPBC]. Management information transferred synchronously with respect this clock. Management Data Input/Output bidirectional signal between Ethernet controller PHY. used transfer control status information. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PHYRxDV
PHYCrS
EMCTxErr
EMCTxEn
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PHYTxClk PHYCol
EMCMDClk
EMCMDIO[PHYMDIO]
tolerant 3.3V LVTTL
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Signal Functional Description
(Sheet Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Control Signals" page
Signal Name Description Type
Notes
SDRAM Interface
Memory data bus. Notes: MemData0 most significant (msb). MemData31 least significant (lsb). Memory address bus. Notes: MemAddr12 most significant (msb). MemAddr0 least significant (lsb). Bank Address supporting internal banks. Address Strobe. Column Address Strobe. byte lane: (MemData0:7), (MemData8:15), (MemData16:23), (MemData24:31) check bits. check bits 0:7. Select four external SDRAM banks. Write Enable. SDRAM Clock Enable. copies SDRAM clock allows, some cases, glueless SDRAM attach without requiring this signal repowered zero-delay buffer.
MemData0:31
3.3V LVTTL
MemAddr12:0
3.3V LVTTL
BA1:0
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
DQM0:3
3.3V LVTTL
DQMCB ECC0:7 BankSel0:3 ClkEn0:1 MemClkOut0:1
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
External Slave Peripheral Interface
PerData0:31 Peripheral data used PPC405GPr when external master mode, otherwise used external master. Note: PerData0 most significant (msb) this bus. Peripheral address used PPC405GPr when external master mode, otherwise used external master. Note: PerAddr0 most significant (msb) this bus. Peripheral byte parity signals. outputs, these pins byte-enables which valid entire cycle write-byte-enables which valid each byte each data transfer, allowing partial word transactions. outputs, pins used either pripheral controller controller depending upon type transfer involved. Used inputs when external master owns external interface. Peripheral write enable. when four PerWBE0:3 write byte enables low. interrupt. Open-drain output (two states; open circuit) tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PerAddr0:31
PerPar0:3
PerWBE0:3
tolerant 3.3V LVTTL
[PerWE]PCIINT
tolerant 3.3V
AMCC
Revision 2.02 August 2005
Signal Functional Description
405GPr Power 405GPr Embedded Processor
(Sheet Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Control Signals" page
Signal Name PerCS0 Description Peripheral chip select bank Seven additional peripheral chip selects General Purpose I/O. access this function, software must toggle bit. Used either peripheral controller controller depending upon type transfer involved. When PPC405GPr master, enables selected device drive bus. Used PPC405GPr when external master mode, output either peripheral controller controller depending upon type transfer involved. High indicates read from memory, indicates write memory. Otherwise used external master input indicate direction data transfer. Used peripheral slave indicate ready transfer data. Used PPC405GPr when external master mode, otherwise used external master. Indicates last transfer memory access. DMAReq0:3 used slave peripherals indicate they prepared transfer data. DMAAck0:3 used PPC405GPr cause peripheral transfer data. Transfer/Terminal Count. Type tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Notes
PerCS1:7[GPIO10:16]
O[I/O]
PerOE
tolerant 3.3V LVTTL
PerR/W
tolerant 3.3V LVTTL
PerReady
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PerBLast
DMAReq0:3 DMAAck0:3 EOT0:3/TC0:3
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Signal Functional Description
(Sheet Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Control Signals" page
Signal Name Description Type
Notes
External Master Peripheral Interface
PerClk ExtReset HoldReq HoldAck ExtReq ExtAck HoldPri BusReq PerErr Peripheral clock used external master synchronous peripheral slaves. Peripheral reset used external master synchronous peripheral slaves. Hold Request, used external master request ownership peripheral bus. Hold Acknowledge, used PPC405GPr transfer ownership peripheral external master. ExtReq used external master indicate prepared transfer data. ExtAck used PPC405GPr indicate data transfer cycle. Used external master indicate priority given external master tenure. Used when PPC405GPr needs regain control peripheral interface from external master. input used indicate PPC405GPr that external slave peripheral error occurred. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Internal Peripheral Interface
UARTSerClk Serial Clock used provide alternate clock internally generated serial clock. Used cases where allowable internally generated baud rates satisfactory. This input individually connected either UART. UART0 Serial Data UART0 Serial Data Out. UART0 Data Carrier Detect. UART0 Data Ready. UART0 Clear Send. UART0 Data Terminal Ready. UART0 Request Send. UART0 Ring Indicator. UART1 Serial Data tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RTS UART0_RI UART1_Rx
AMCC
Revision 2.02 August 2005
Signal Functional Description
405GPr Power 405GPr Embedded Processor
(Sheet Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Control Signals" page
Signal Name UART1_Tx UART1 Serial Data Out. UART1 Data Ready UART1 Clear Send. access this function, software must toggle bit. UART1 Request Send UART1 Data Terminal Ready. access this function, software must toggle bit. Serial Clock. Serial Data. Description Type tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Notes
UART1_DSR/ UART1_CTS
UART1_RTS/ UART1_DTR
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
IICSCL IICSDA
Interrupts Interface
Interrupt requests General Purpose I/O. access this function, software must toggle bit. tolerant 3.3V LVTTL
IRQ0:6[GPIO17:23]
I[I/O]
JTAG Interface
TRST Test data JTAG test mode select. Test data out. JTAG test clock. frequency this input range from 25MHz. JTAG reset. TRST must power-on initialize JTAG controller normal operation PPC405GPr. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
System Interface
SysClk Main system clock input. Main system reset. External logic drive this bidirectional (minimum cycles) initiate system reset. system reset also initiated software. Implemented open-drain output (two states; open circuit). Clean voltage input PLL. Clean Ground input PLL. when Machine Check generated. Halt from external debugger. tolerant 3.3V LVTTL tolerant 3.3V LVTTL
SysReset
AVDD AGND SysErr Halt
tolerant 3.3V LVTTL tolerant 3.3V LVTTL
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Signal Functional Description
(Sheet Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Control Signals" page
Signal Name GPIO1[TS1E] GPIO2[TS2E] Description General Purpose Even Trace execution status. access this function, software must toggle bit. General Purpose Trace execution status. access this function, software must toggle bit. General Purpose Trace execution status. access this function, software must toggle bit. General Purpose Trace status. access this function, software must toggle bit. General Purpose Trace interface clock. toggling signal that always half core frequency. access this function, software must toggle bit. Note: Initialization strapping must hold this during reset. General Purpose I/O. Note: pull-up initialization strapping resistor must rather than order overcome internal pull-down resistor. Test Enable. Used only manufacturing tests. Pull down normal operation. external clock input that used clock timers core. Type tolerant 3.3V LVTTL
Notes
I/O[O]
GPIO3[TS1O]
I/O[O]
tolerant 3.3V LVTTL
GPIO4[TS2O]
I/O[O]
tolerant 3.3V LVTTL
GPIO5:8[TS3:6]
I/O[O]
tolerant 3.3V LVTTL
GPIO9[TrcClk]
I/O[O]
tolerant 3.3V LVTTL
GPIO24
3.3V LVTTL w/pull-down 1.8V CMOS w/pull-down tolerant 3.3V LVTTL
TestEn TmrClk
Trace Interface
[TS1E]GPIO1 [TS2E]GPIO2 Even Trace execution status. access this function, software must toggle General Purpose I/O. Trace execution status. access this function, software must toggle General Purpose I/O. Trace execution status. access this function, software must toggle General Purpose I/O. tolerant 3.3V LVTTL
O[I/O]
[TS1O]GPIO3
O[I/O]
tolerant 3.3V LVTTL
[TS2O]GPIO4
O[I/O]
tolerant 3.3V LVTTL
[TS3:6]GPIO5:8
Trace status. access this function, software must toggle O[I/O] General Purpose I/O.
tolerant 3.3V LVTTL
AMCC
Revision 2.02 August 2005
Signal Functional Description
405GPr Power 405GPr Embedded Processor
(Sheet Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Control Signals" page
Signal Name Description Trace interface clock. toggling signal that always half core frequency. access this function, software must toggle General Purpose I/O. Note: Initialization strapping must hold this during reset. Type
Notes
[TrcClk]GPIO9
O[I/O]
tolerant 3.3V LVTTL
Ground pins
Ground Note: L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, T11-T16 also thermal balls.
OVDD pins
OVDD Output driver voltage-3.3V.
pins
Logic voltage-1.8V.
Other pins
Reserved Reserved-Except AF4, connect signals, voltage, ground these pins. must tied OVDD GND.
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Absolute Maximum Ratings
absolute maximum ratings below stress ratings only. Operation beyond these maximum ratings cause permanent damage device
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface) Supply Voltage Input Voltage (1.8V CMOS receivers) Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Notes: specified voltages with respect GND. Empirical data indicates that chip voltages should begin ramp-up within each other. There should never voltage present pins before OVDD within operating range. Symbol OVDD AVDD TSTG Value +1.95 +3.6 +1.95 -0.6 0.45 -0.6 OVDD -0.6 OVDD +150 +120 Unit
Package Thermal Specifications
PPC405GPr designed operate within case temperature range -40°C +85°C3. Thermal resistance values E-PBGA packages (leaded lead-free) convection environment follows: Airflow ft/min (m/sec) Symbol Unit Package-Thermal Resistance
35mm, 456-balls-Junction-to-Case 35mm, 456-balls-Case-to-Ambient1 27mm, 456-balls-Junction-to-Case 27mm, 456-balls-Case-to-Ambient1 Notes: chip mounted JEDEC 2S2P card without heat sink. chip mounted card with least signal power planes, following relationships exist: Case temperature, measured center case surface with device soldered circuit board. TCMax TJMax where TJMax maximum junction temperature power consumption. 333MHz operated 266MHz less operate +105°C. where ambient temperature power consumption. (0.51) (1.02) °C/W °C/W °C/W °C/W
AMCC
Revision 2.02 August 2005
405GPr Power 405GPr Embedded Processor
Recommended Operating Conditions
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability. Notes: drivers meet specifications. "5V-Tolerant Input Current" page 333MHz operated 266MHz less operate +105°C.
Parameter Logic Supply Voltage (266 &333MHz) Logic Supply Voltage (400MHz) Supply Voltage Supply Voltage Input Logic High (1.8V CMOS receivers) Input Logic High (3.3V LVTTL receivers) Input Logic High (5.0V LVTTL receivers) Input Logic (1.8V CMOS receivers) Input Logic (3.3/5.0V LVTTL receivers) Output Logic High Output Logic 3.3V Input Current pull-up pull-down) Input Current (with internal pull-down) Tolerant Input Current Input Allowable Overshoot (1.8V CMOS receivers) Input Allowable Overshoot (3.3V LVTTL receivers) Input Allowable Overshoot (5.0V LVTTL receivers) Input Allowable Undershoot Output Allowable Overshoot Output Allowable Undershoot Case Temperature Symbol OVDD AVDD IIL1 IIL2 IIL4 VIMAO1.8 VIMAO3 VIMAO5 VIMAU VOMAO VOMAU3 -0.6 -0.6 OVDD Minimum 0.65VDD Typical 1.85 Maximum OVDD 0.65VDD OVDD VDD) -325 OVDD Unit Notes
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
5V-Tolerant Input Current
Input Current (µA) -100 -150 -200 -250 -300 -350 Input Voltage
Input Capacitance
Parameter 3.3V LVTTL tolerant LVTTL only pins Symbol CIN1 CIN2 CIN3 CIN4 Maximum Unit Notes
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Revision 2.02 August 2005
Electrical Characteristics
Parameter Active Operating Current (VDD)-266MHz Active Operating Current (VDD)-333MHz Active Operating Current (VDD)-400MHz Active Operating Current (OVDD) Input current Active Operating Power-266 Active Operating Power-333MHz Active Operating Power-400MHz Note:
405GPr Power 405GPr Embedded Processor
Symbol IODD IPLL
Typical 0.72 0.76 0.82
Maximum 1.92 2.07 2.23
Unit
maximum current power values listed above guaranteed highest obtainable. These values dependent many factors including type applications running, clock rates, internal functional capabilities, external interface usage, case temperature, power supply voltages. Your specific application produce significantly different results. (logic) current power primarily dependent applications running internal chip functions (DMA, PCI, Ethernet, on). OVDD (I/O) current power primarily dependent capacitive loading, frequency, utilization external buses. following information provides details about conditions under which listed values were obtained: general, values were measured using PPC405GPr Evaluation Board with four devices, external master peripheral bus, external wrap-back Ethernet port. clock rates, 133.3MHz, PerClk 66.6MHz, SysClk 33.3MHz. Typical current power characterized +1.8V, OVDD +3.3V, while running various applications under Linux operating system. Maximum current power characterized +1.9V, OVDD +3.6V, while running applications designed maximize power consumption. external master heavily loads with transfers targeting SDRAM while internal controller further increases SDRAM traffic. AVDD should derived from using following circuit:
AVDD
AGND
inductor (equivalent MuRata LQH3C2R2M34) chip ferrite bead (equivalent MuRata BLM31A700S) tantalum monolithic ceramic capacitor with dielectric equivalent 0.01 monolithic ceramic capacitor with dielectric equivalent
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Test Conditions Clock timing switching characteristics specified accordance with operating conditions shown table "Recommended Operating Conditions." signals other than signals, specifications characterized OVDD +85°C with 50pF test load shown figure right. signals there different test load circuits, rising edge falling edge shown figures right.
Output
50pF
signals other than
Output
Rising edge
10pF
Output
10pF
OVDD
Falling edge
AMCC
Revision 2.02 August 2005
Clocking Specifications
Symbol SysClk Input SCFC SCTC SCTCS SCTCH SCTCL Clock input frequency Clock period Processor clock frequency Processor clock period Parameter
405GPr Power 405GPr Embedded Processor
Units
266.66/333.33/400 3.75/3/2.5
66.66 0.15
Clock edge stability (phase jitter, cycle cycle) Clock input high time Clock input time nominal period nominal period
nominal period nominal period
Note: Input slew rate 1V/ns between 0.8V 2.0V MemClkOut Output MCOFC MCOTC MCOTCS MCOTCH MCOTCL TrcClk Output TCFC TCTC TCTCS TCTCH TCTCL Other Clocks VCOFC VCOFC PLBFC OPBFC frequency frequency 333MHz 400MHz frequency frequency 1000 1333 133.33 66.66 Clock output frequency Clock period Clock edge stability (phase jitter, cycle cycle) Clock output high time Clock output time nominal period nominal period nominal period nominal period Clock output frequency 266MHz Clock period 266MHz Clock edge stability (phase jitter, cycle cycle) Clock output high time Clock output time nominal period nominal period nominal period nominal period 133.33
Clocking Waveform
2.0V 1.5V 0.8V
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Spread Spectrum Clocking
Care must taken when using spread spectrum clock generator (SSCG) with PPC405GPr. This controller uses clock generation inside chip. accuracy with which follows SSCG referred tracking skew. bandwidth phase angle determine much tracking skew there between SSCG given frequency deviation modulation frequency. When using SSCG with PPC405GPr following conditions must met: frequency deviation must violate minimum clock cycle time. Therefore, when operating PPC405GPr with more internal clocks their maximum supported frequency, SSCG only lower frequency. maximum frequency deviation cannot exceed -3%, modulation frequency cannot exceed 40kHz. some cases, on-board PPC405GPr peripherals impose more stringent requirements (see Note peripheral clock (PerClk) logic that synchronous peripheral since this clock tracks modulation. SDRAM MemClkOut since also tracks modulation. Notes: serial port baud rates synchronous modulated clock. serial port tolerance approximately 1.5% baud rate before framing errors begin occur. 1.5% tolerance assumes that connected device running precise baud rates. external serial clock used baud rate unaffected modulation. Operation PPC405GPr Bridge unaffected SSCG. frequencies 33.33 below controller supports synchronous mode operation. This accomplished strapping PPC405GPr synchronous mode connecting clock PPC405GPr SysClk input. 33.33 signalling, specification limitation amount frequency deviation modulation that applied clock. Therefore, PPC405GPr SSCG requirements stated above take precedence. frequencies above 33.33 MHz, controller must operated asynchronous mode. When asynchronous mode, clock must driven into PPC405GPr PCIClk input. this configuration controller supports 66.66 clock specification which specifies maximum frequency deviation modulation between kHz. Ethernet operation unaffected. operation unaffected. Caution: system designer ensure that SSCG used with PPC405GPr meets above requirements does adversely affect other aspects system.
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Revision 2.02 August 2005
Peripheral Interface Clock Timings
Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) Clock frequency (synchronous mode) Clock period (synchronous mode Note PCIClk input high time PCIClk input time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output time PHYTxClk input frequency PHYTxClk period PHYTxClk input high time PHYTxClk input time PHYRxClk input frequency PHYRxClk period PHYRxClk input high time PHYRxClk input time PerClk output frequency PerClk period PerClk output high time PerClk output time PerClk clock edge stability (phase jitter, cycle cycle) UARTSerClk input frequency (Note UARTSerClk period UARTSerClk input high time UARTSerClk input time TmrClk input frequency TmrClk period TmrClk input high time TmrClk input time Note:
405GPr Power 405GPr Embedded Processor
Note nominal period nominal period nominal period nominal period nominal period nominal period nominal period nominal period
66.66 Note 33.33 nominal period nominal period 66.66 nominal period nominal period 1000/(2TOPB+2ns) 66.66 nominal period nominal period
Units
2TOPB+2 TOPB+1 TOPB+1 nominal period nominal period
asynchronous mode minimum PCIClk frequency Clock. Refer PowerPC 405GPr Embedded Processor User's Manual more information. synchronous mode clock derived from SysClk PCIClk input unused. TOPB period clock. maximum clock frequency 66.66MHz.
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Input Setup Hold Waveform
Clock
Inputs Valid
Output Delay Float Timing Waveform
Clock
Outputs
High (Drive) Float (High-Z) (Drive) Valid Valid
AMCC
Revision 2.02 August 2005
405GPr Power 405GPr Embedded Processor
Notes: following Specifications tables timing values "na" means "not applicable" "dc" means "don't care." "Test Conditions" page output capacitive loading.
Specifications-Group
(Sheet Notes: timings operation 66.66MHz. output hold time requirement 66.66MHz 33.33MHz. synchronous mode, timing relative SysClk. asynchronous mode, timing relative PCIClk. Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI, specified 0.9OVDD specified 0.1OVDD. other interfaces, specified specified
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) settable clock period 10ns Hold Time (TOH min) clock period Output Current (mA) (min) 10.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 (min) PHYRX PHYRX PHYRX EMCMDClk PHYTX PHYTX PHYTX Clock Clock Clock Clock Clock Clock Clock Clock Clock Clock Clock Clock Clock async async async async async Clock Notes
Interface
PCIAD31:0 PCIC3:0[BE3:0] PCIClk PCIDevSel PCIFrame PCIGnt0[Req] PCIGnt1:5 PCIIDSel PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0[Gnt] PCIReq1:5 PCIReset PCISErr PCIStop PCITRDY Clock Clock async async
Ethernet Interface
EMCMDClk EMCMDIO[PHYMDIO] EMCTxD3:0 EMCTxEn EMCTxErr PHYCol PHYCrS PHYRxClk PHYRxD3:0 PHYRxDV PHYRxErr PHYTxClk
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Specifications-Group
(Sheet Notes: timings operation 66.66MHz. output hold time requirement 66.66MHz 33.33MHz. synchronous mode, timing relative SysClk. asynchronous mode, timing relative PCIClk. Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI, specified 0.9OVDD specified 0.1OVDD. other interfaces, specified specified
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (min) 15.3 15.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 (min) 10.2 10.2 async async async async async Clock Notes
Internal Peripheral Interface
IICSCL IICSDA UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_RTS/ UART1_DTR UART1_DSR/ UART1_CTS UART1_Rx UART1_Tx UARTSerClk
Interrupts Interface
IRQ0:6[GPIO17:23]
JTAG Interface
TRST
System Interface
GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO24 Halt SysClk SysErr SysReset TestEn TmrClk
10.3
10.3 10.3
async async async async async
AMCC
Revision 2.02 August 2005
Specifications-Group
405GPr Power 405GPr Embedded Processor
(Sheet Notes: timings operation 66.66MHz. output hold time requirement 66.66MHz 33.33MHz. synchronous mode, timing relative SysClk. asynchronous mode, timing relative PCIClk. Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI, specified 0.9OVDD specified 0.1OVDD. other interfaces, specified specified
Input (ns) Signal Trace [TS1E] [TS2E] [TS1O] [TS2O] [TS3] [TS4] [TS5] [TS6] Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (min) (min) Clock Notes
PTC/2+0.7
PTC/2-0.5
10.3
TrcClk
10pF load clk/data
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Specifications-Group
Notes: SDRAM command interface configurable through SDRAM0_TR[LDF] provide cycle delay before command used SDRAM. SDRAM timings specified relative MemClkOut terminated into lumped 10pF load. SDRAM interface hold times guaranteed PPC405GPr package pin. System designers must PPC405GPr IBIS model (available from www.amcc.com) ensure their clock distribution topology minimizes loading reflections, that relative delays clock wiring exceed delays other SDRAM signal wiring. PerClk timing specified with 10pF load package pin. indicated timing valid only PerClk feedback selected. Refer PowerPC 405GPr Embedded Processor User's Manual more information. Input timings specified 1.5V, assuming transition times between 2ns, when measured between points output voltage. specified specified
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) -0.5 Output Current (mA) (minimum) 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 10.3 10.3 15.3 10.3 10.3 15.3 10.3 15.3 10.3 10.3 10.3 10.3 15.3 10.3 15.3 (minimum) 10.2 10.2 10.2 19.3 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 Clock Notes
SDRAM Interface
BA1:0 BankSel3:0 ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:0 MemData0:31 DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 PerAddr0:31 PerBLast PerCS0 PerCS1:7[GPIO10:16] PerData0:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq PerClk PerErr MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk SysClk PerClk
External Slave Peripheral Interface
External Master Peripheral Interface
AMCC
Revision 2.02 August 2005
Strapping
405GPr Power 405GPr Embedded Processor
When SysReset input driven external device (system reset), state certain pins read enable default initial conditions prior PPC405GPr start-up. actual capture instant nearest SysClk edge before deassertion reset. These pins must strapped using external pull-up (logical pull-down (logical resistors select desired default conditions. recommended pull-up +3.3V +5V. recommended pull-down GND. These pins strap functions only during reset. They used other signals during normal operation. following tables list strapping pins along with their functions strapping options. signal names assigned pins normal operation follow number. PPC405GPr used replacement PPC405GP. When PPC405GPr used this purpose, should strapped operate PPC405GPr Legacy Mode. This option selected strapping ball (GPIO24) (0). Legacy Mode selected, "PPC405GPr Legacy Mode Strapping Assignments" table should used determine strapping options. operate chip PPC405GPr, strap (GPIO24) high "PPC405GPr Mode Strapping Assignments" page determine strapping options.
PPC405GPr Legacy Mode Strapping Assignments
Function Tuning
(Sheet
Ball Strapping UART0_Tx UART0_DTR DMAAck1 DMAAck3 EMCTxD2 AD16 UART0_RTS
Option
choice choice choice Choice TUNE[9:0] 1010111100 Choice TUNE[9:0] 0100111000 Choice TUNE[9:0] 0100110110 Choice TUNE[9:0] 0100111100 Choice TUNE[9:0] 0100111000 Choice TUNE[9:0] 1000111100 Choice TUNE[9:0] 1000111110 Choice TUNE[9:0] 1011111110 Forward Divider
DMAAck0
Bypass mode Divide Divide Divide Feedback Divider
DMAAck2
Divide Divide Divide Divide Divider from
EMCTxD3
Divide Divide Divide Divide
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
(Sheet
Ball Strapping EMCTxD1 EMCTxD0 GPIO2[TS2E] EMCTxEn UART1_RTS/ UART1_DTR
PPC405GPr Legacy Mode Strapping Assignments
Function Divider from Divide Divide Divide Divide Divider from Divide Divide Divide Divide External Divider from
Option
GPIO1[TS1E] EMCTxErr
Divide Divide Divide Divide Width
UART1_Tx
8-bit 16-bit 32-bit Reserved Location PPC405GPr Peripheral Attach PPC405GPr Attach Asynchronous Mode Enable Synchronous Mode Asynchronous Mode Arbiter Enable Internal Arbiter Disabled Internal Arbiter Enabled Note:
HoldAck ExtAck AF18 GPIO4[TS2O]
tune bits adjust parameters that control jitter. recommended values minimize jitter implemented PPC405GPr. These bits shown information only; require modification except special clocking circumstances such spread spectrum clocking. details Spread Spectrum Clock Generators (SSCGs) with PPC405GPr, visit technical documents area AMCC PowerPC site. combinations dividers produce valid operating configurations. Frequencies must within limits specified "Clocking Specifications" page Further requirements detailed Clocking chapter PowerPC 405GPr Embedded Processor User's Manual. Additional consideration must given pins that normally function Trace signals. Improved design margin gained using three-state buffers instead strapping resistors, minimizing trace lengths stubs.
AMCC
Revision 2.02 August 2005
405GPr Power 405GPr Embedded Processor
PPC405GPr Mode Strapping Assignments
Function Tuning PowerPC 405GPr Embedded Processor User's Manual details. Option
(Sheet
Ball Strapping UART0_DTR DMAAck1 EMCTxD2 AD16 UART0_RTS GPIO5[TS3] GPIO6[TS4]
UART0_Tx Choice TUNE[9:0] 1010111100 Choice TUNE[9:0] 0100111000 Choice TUNE[9:0] 0100110110 Choice TUNE[9:0] 0100111100 Choice TUNE[9:0] 0100111000 Choice TUNE[9:0] 1000111100 Choice TUNE[9:0] 1000111110 Choice TUNE[9:0] 1011111110 DMAAck0 Divide Divide Divide Divide Divide Divide Divide Divide EMCTxD3 Divide Divide Divide Divide Divide Divide Divide Divide
Forward Divider
Forward Divider
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
(Sheet
Ball Strapping DMAAck3 EMCTxD0 GPIO2[TS2E] EMCTxEn UART1_RTS/ UART1_DTR GPIO7[TS5] GPIO8[TS6]
PPC405GPr Mode Strapping Assignments
Function Feedback Divider Divide Divide Divide Divide Divide Divide Divide Divide Divide Divide Divide Divide Divide Divide Divide Divide Divider from
Option DMAAck2 EMCTxD1 Divide Divide Divide Divide
GPIO1[TS1E]
Divider from
Divide Divide Divide Divide External Divider from Divide Divide Divide Divide Width
EMCTxErr UART1_Tx
8-bit 16-bit 32-bit Reserved Location PPC405GPr Peripheral Attach PPC405GPr Attach
HoldAck
AMCC
Revision 2.02 August 2005
Function Asynchronous Mode Enable Option
405GPr Power 405GPr Embedded Processor
PPC405GPr Mode Strapping Assignments
(Sheet
Ball Strapping
ExtAck Synchronous Mode Asynchronous Mode GPIO3[TS1O] Asynchronous Mode Synchronous Mode AF18 GPIO4[TS2O] Internal Arbiter Disabled Internal Arbiter Enabled GPIO24 Legacy (PPC405GP) mode (PPC405GPr) mode4 GPIO9[TrcClk] Normal operation
External Synchronous Mode Enable
Arbiter Enable
Mode Enable Legacy mode PPC405GPr functions like PPC405GP. strapped, PPC405GPr defaults Legacy mode. Flip Circuit Disable (must strapped during initilization). Note:
tune bits adjust parameters that control jitter. recommended values minimize jitter implemented PPC405GPr. These bits shown information only; require modification except special clocking circumstances such spread spectrum clocking. details Spread Spectrum Clock Generators (SSCGs) with PPC405GPr, visit technical documents area AMCC PowerPC site. combinations dividers produce valid operating configurations. Frequencies must within limits specified "Clocking Specifications" page Further requirements detailed Clocking chapter PowerPC 405GPr Embedded Processor User's Manual. Additional consideration must given pins that normally function Trace signals. Improved design margin gained using three-state buffers instead strapping resistors, minimizing trace lengths stubs. pull-up initialization strapping resistor must rather than order overcome internal pull-down resistor.
Revision
Date 03/13/2003 08/28/2003 11/22/2004 12/02/2004 01/06/2005 08/29/2005 values 400MHz parts. Correct package drawings lead-free part numbers. +105°C temperature specification. voltage ramp-up restriction. Update AMCC format. Correct typographical error 27mm package drawing. dashes back into PNs. Contents Modification 400MHz part numbers power/current numbers
AMCC
405GPr Power 405GPr Embedded Processor
Revision 2.02 August 2005
Printed United States America, Monday, August 2005 following trademarks AMCC United States, other countries, both: AMCC
Other company, product, service names trademarks service marks others.
information contained this document subject change withdrawal time without notice being provided basis without warranty indemnity kind, whether express implied, including without limitation, implied warranties non-infringement, merchantability, fitness particular purpose. products, services, programs discussed this document sold licensed under AMCC's standard terms conditions, copies which obtained from your local AMCC representative. Nothing this document shall operate express implied license indemnity under intellectual property rights AMCC third parties. Without limiting generality foregoing, performance data contained this document determined specific controlled environment submitted formal AMCC test. Therefore, results obtained other operating environments vary significantly. Under circumstances will AMCC liable damages whatsoever arising resulting from document information contained herein.
AMCC
Revision 2.02 August 2005
405GPr Power 405GPr Embedded Processor
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AMCC reserves right make changes products, datasheets, related documentation, without notice warrants products solely pursuant terms conditions sale, only substantially comply with latest available datasheet. Please consult AMCC's Term Conditions Sale warranties other terms, conditions limitations. AMCC discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered Trademark Applied Micro Circuits Corporation. Copyright 2005 Applied Micro Circuits Corporation.
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405GPr Power 405GPr Embedded Processor PowerPC® 32-bit RISC

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