LC2MOS Complete, 12-Bit Analog System AD7868 LDAC TCLK CONTROL RC
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FEATURES Complete 12-Bit System, Comprising: 12-Bit with Track/Hold Amplifier Throughout Rate 12-Bit with Output Amplifier Settling Time On-Chip Voltage Reference Operates from Supplies Power Small 0.3" Wide APPLICATIONS Digital Signal Processing Speech Recognition Synthesis Spectrum Analysis High Speed Modems Servo Control
LC2MOS Complete, 12-Bit Analog System AD7868
LDAC TCLK CONTROL RCLK CONVST CLOCK
12-BIT REFERENCE REFERENCE SERIAL INTERFACE 12-BIT
VOUT
SERIAL INTERFACE
TRACK/HOLD
AD7868
GENERAL DESCRIPTION
DGND
AGND
AD7868 complete 12-bit system containing successive approximation type with track-and-hold amplifier having combined throughput rate kHz. output buffer amplifier with settling time bits. Temperature compensated buried Zener references provide precision references ADC. Interfacing both serial, minimizing count giving small 24-pin package size. Standard control signals allow serial interfacing most machines. Asynchronous conversion control updating made possible with CONVST LDAC logic inputs. AD7868 operates from power supplies, analog input/output range ADC/DAC part fully specified dynamic parameters such signal-to-noise ratio harmonic distortion well traditional specifications. part available 24-pin, 0.3" wide, plastic hermetic dual-in-line package (DIP) 28-pin, plastic SOIC package.
PRODUCT HIGHLIGHTS
Complete 12-Bit System. AD7868 contains 12-bit with track-and-hold amplifier 12-bit with output amplifier. Also included separate on-chip voltage references ADC. Dynamic Specifications Users. addition traditional specifications, AD7868 specified parameters including signal-to-noise ratio harmonic distortion. These parameters along with important timing parameters tested every device. Small Package. AD7868 available 24-pin 28-pin SOIC package.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Analog Devices, Inc., 1996 Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7868-SPECIFICATIONS AGND DGND
SECTION
external. specifications TMIN TMAX-
unless otherwise noted.)
Version1
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio3, (SNR) +25°C TMIN TMAX Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Track/Hold Acquisition Time ACCURACY Resolution Minimum Resolution Integral Nonlinearity Integral Nonlinearity Differential Nonlinearity Bipolar Zero Error Positive Gain Error5 Negative Gain Error5 ANALOG INPUT Input Voltage Range Input Current REFERENCE OUTPUT6 +25°C Reference Load Sensitivity
Version1
Version1
Units Bits Bits Volts min/V ppm/°C ppm/°C
Test Conditions/Comments Sine Wave, fSAMPLE Typically 71.5 41.5 Sine Wave, fSAMPLE Typically 71.5 41.5 Sine Wave, fSAMPLE Typically 71.5 41.5 kHz, kHz, fSAMPLE kHz, kHz, fSAMPLE
Missing Codes Guaranteed
2.99/3.01 2.99/3.01 2.99/3.01 -1.5 -1.5 -1.5
Reference Load Current Change µA-500 µA), Reference Load Should Changed During Conversion DGND
LOGIC INPUTS (CONVST, CLK, CONTROL) Input High Voltage, VINH Input Voltage, VINL Input Current, Input Current7 (CONTROL Input Only) Input Capacitance, CIN8 LOGIC OUTPUTS Outputs Output Voltage, RCLK Output Output Voltage, RFS, RCLK Outputs Floating-State Leakage Current Floating-State Output Capacitance8 CONVERSION TIME External Clock Internal Clock POWER REQUIREMENTS Total Power Dissipation
ISINK Pull-Up Resistor ISINK Pull-Up Resistor
Internal Clock Nominal Value Both Specified Performance Specified Performance Cumulative Current from Pins Cumulative Current from Pins Typically
NOTES Temperature ranges follows: Versions, -40°C +85°C; Version, -55°C +125°C. calculation includes distortion noise components. degradation asynchronous updating during conversion typ. Measured with respect internal reference. capacitive loads greater than series resistor required (see INTERNAL REFERENCE section). Tying CONTROL input places device factory test mode where normal operation exhibited. Sample tested +25°C ensure compliance. Specifications subject change without notice.
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AD7868 SECTION
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio3 (SNR) +25°C TMIN TMAX Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise ACCURACY Resolution Integral Nonlinearity Integral Nonlinearity Differential Nonlinearity Bipolar Zero Error Positive Full-Scale Error5 Negative Full-Scale Error5 REFERENCE OUTPUT6 +25°C Reference Load Change REFERENCE INPUT Input Range Input Current LOGIC INPUTS (LDAC, TFS, TCLK, Input High Voltage, VINH Input Voltage, VINL Input Current, Input Capacitance, CIN7 ANALOG INPUT Output Voltage Range Output Impedance Short-Circuit Current CHARACTERISTICS7 Voltage Output Settling-Time Positive Full-Scale Change Negative Full-Scale Change Digital-to-Analog Glitch Impulse Digital Feedthrough VOUT Isolation POWER REQUIREMENTS
(VDD AGND DGND decoupled shown Figure VOUT Load AGND; specifications TMIN TMAX unless otherwise noted.)
Version1 Version1 Version1 Units Test Conditions/Comments VOUT Sine Wave, fSAMPLE Typically 71.5 +25°C VOUT kHz4 VOUT Sine Wave, fSAMPLE Typically +25°C VOUT kHz4 VOUT Sine Wave, fSAMPLE Typically +25°C VOUT kHz4
Bits
Guaranteed Monotonic
2.99/3.01 2.99/3.01 2.99/3.01 -1.5 -1.5 -1.5 2.85/3.15 2.85/3.15 2.85/3.15
min/V ppm/°C ppm/°C Reference Load Current Change (0-500 min/V Settling Time Within Final Value Typically Typically Code Change 41.5 Sine Wave
secs secs
Section
NOTES Temperature ranges follows: Versions, -40°C +85°C; Version, -55°C +125°C. VOUT (pk-pk) calculation includes distortion noise components. Using external sample hold. Measured with respect includes bipolar offset error. capacitive loads greater than series resistor required (see INTERNAL REFERENCE section). Sample tested +25°C ensure compliance. Model Specifications subject change without notice.
ORDERING GUIDE
Temperature Range
-40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
Relative Accuracy (LSB)
Package Option*
N-24 Q-24 N-24 Q-24 R-28 R-28
AD7868AN AD7868AQ AD7868BN AD7868BQ AD7868AR AD7868BR
Plastic DIP; Cerdip; SOIC (Small Outline IC).
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AD7868 TIMING CHARACTERISTICS1,
Parameter TIMING t135 TIMING Limit TMIN, TMAX Versions) RCLK +200 RCLK
AGND DGND
Units Conditions/Comments CONVST Pulse Width RCLK Cycle Time, Internal Clock RCLK Falling Edge Setup Time RCLK Rising Edge RCLK Valid Data Delay, Relinquish Time after RCLK CONVST Delay
Limit TMIN, TMAX Version) RCLK +200 RCLK
TCLK Falling Edge TCLK Falling Edge TCLK Cycle Time Data Valid TCLK Setup Time Data Valid TCLK Hold Time LDAC Pulse Width
NOTES Timing specifications sample tested +25°C ensure compliance. input signals specified with (10% timed from voltage level Serial timing measured with pull-up resistor pull-up resistor RCLK capacitance three output When using internal clock, RCLK mark/space ratio (measured from voltage level range 40/60 60/40. external clock, RCLK mark/space ratio external clock mark/space ratio. will drive higher capacitance loads this will since increases external time constant (4.7 k/CL) hence time reach Time RCLK RCLK depends conversion start clock synchronization. TCLK mark/space ratio 40/60 60/40.
ABSOLUTE MAXIMUM RATINGS*
+25°C unless otherwise noted)
CONFIGURATIONS
CONVST RCLK DGND AGND VOUT CONTROL
CONVST RCLK
AGND -0.3 AGND +0.3 AGND DGND -0.3 +0.3 VOUT AGND AGND -0.3 AGND -0.3 AGND -0.3 AGND -0.3 Digital Inputs AGND -0.3 Digital Outputs AGND -0.3 Operating Temperature Range Versions -40°C +85°C Version -55°C +125°C Storage Temperature Range -65°C +150°C Lead Temperature (Soldering, secs) +300°C Power Dissipation (Any Package) +75°C Derates above +75°C mW/°C
*Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
SOIC
CONTROL AGND DGND TCLK LDAC
AD7868
VIEW (Not Scale)
AGND
DGND
AD7868
VIEW (Not Scale)
DGND
AGND
TCLK LDAC CONNECT
VOUT
CONNECT
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7868 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
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AD7868
FUNCTION DESCRIPTION
Number
Mnemonic
Function Positive Power Supply, Both pins must tied together. Negative Power Supply, Both pins must tied together. Analog Ground. Both AGND pins must tied together. Digital Ground. Both DGND pins must tied together.
POWER SUPPLY AGND DGND
ANALOG SIGNAL REFERENCE Analog Input. input range VOUT Analog Output Voltage from DAC. This output comes from buffer amplifier. range bipolar, with Voltage Reference Output. internal reference provided this pin. This output used reference connecting input. external load capability this reference Voltage Reference Output. This internal voltage references. operate with this internal reference, should connected DAC. external load capability reference Voltage Reference Input. voltage reference must applied this pin. internally buffered before being applied DAC. nominal reference voltage correct operation AD7868 INTERFACE CONTROL Clock Input. external TTL-compatible clock applied this input. Alternatively, tying enables internal laser-trimmed oscillator. Receive Frame Synchronization, Logic Output. This active open-drain output which provides framing pulse serial data. external pull-up resistor required RFS. RCLK Receive Clock, Logic Output. RCLK gated serial clock output which derived from internal external clock. CONTROL input clock runs continuously. With CONTROL input DGND RCLK output gated (three-stated) after serial transmission complete. RCLK open-drain output requires external pull-up resistor. Receive Data, Logic Output. This open-drain data output used conjunction with RCLK transmit data from ADC. Serial data valid falling edge RCLK when low. external resistor required output. CONVST Convert Start, Logic Input. high transition this input puts track-and-hold amplifier into hold mode starts conversion. This input asynchronous input. CONTROL Control, Logic Input. With this RCLK noncontinuous. With this RCLK continuous. Note, tying this places part factory test mode where normal operation exhibited. INTERFACE CONTROL Transmit Frame Synchronization, Logic Input. This frame synchronization signal with serial data expected after falling edge this signal. Transmit Data, Logic Input. This data input which used conjunction with TCLK transfer serial data input latch. TCLK Transmit Clock, Logic Input. Serial data bits latched falling edge TCLK when low. LDAC Load DAC, Logic Input. word transferred into latch from input latch falling edge this signal. Connect.
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AD7868
CONVERTER DETAILS
AD7868 complete 12-bit port, only external components required normal operation pull-up resistors data outputs power supply decoupling capacitors. comprised 12-bit successive approximation with track/hold amplifier, 12-bit with buffered output buried Zener references, clock oscillator control logic.
CLOCK
operation track/hold amplifier essentially transparent user. track/hold amplifier goes from track mode hold mode start conversion rising edge CONVST.
INTERNAL REFERENCES
AD7868 internal clock oscillator which used conversion procedure. oscillator enabled tying input VSS. oscillator laser trimmed factory give conversion time between mark/space ratio vary from 40/60 60/40. Alternatively, external compatible clock applied this input. allowable mark/space ratio external clock 40/60 60/40. RCLK clock output, used serial interface. This output derived directly from clock source switched conversion with CONTROL input.
CONVERSION TIMING
AD7868 on-chip temperature compensated buried Zener references which factory trimmed reference provides appropriate biasing ADC, while other available reference DAC. Both reference outputs available (labeled ADC) capable providing external load. input reference DAC) stored externally connected on-chip references. Applications requiring good full-scale error matching between should reference shown Figure maximum recommended capacitance either reference output pins normal operation either reference outputs required drive capacitive load greater than then resistor must placed series with capacitive load. addition decoupling capacitors, parallel with shown Figure improves noise performance. improvement noise performance seen from graph Figure Note, this applies output only; reference decoupling components affect performance. typical application will have just reference source decoupled with other open circuited.
ADC* LOAD GREATER THAN 50pF 10µF 0.1µF
conversion time both external clock continuous internal clock vary from rising clock edges depending conversion start clock synchronization. conversion initiated within prior rising edge clock, conversion time will consist rising clock edges, i.e., conversion time. noncontinuous internal clock, conversion time always rising clock edges.
TRACK-AND-HOLD AMPLIFIER
track-and-hold amplifier analog input AD7868 allows accurately convert input sine wave peak-peak amplitude 12-bit accuracy. input impedance typically equivalent circuit shown Figure input bandwidth track/hold amplifier much greater than Nyquist rate ADC, even when operated maximum throughput rate. cutoff frequency occurs typically kHz. track/hold amplifier acquires input signal 12-bit accuracy less than
DAC/RO LEFT OPEN CIRCUIT USED
Figure Reference Decoupling Circuitry
OUTPUT AMPLIFIER
TRACK/HOLD AMPLIFIER 4.5k INTERNAL COMPARATOR
4.5k
AD7868*
INTERNAL REFERENCE
output from voltage-mode buffered noninverting amplifier. buffer amplifier capable developing across load ground produce peak-to-peak sine wave signals frequency kHz. output updated falling edge LDAC input. output voltage settling time, within final value, typically less than small signal (200 p-p) bandwidth output buffer amplifier typically MHz. output noise from amplifier with figure nV/Hz frequency kHz. broadband noise from amplifier exhibits typical peakto-peak figure output bandwidth. Figure shows typical plot noise spectral density versus frequency output buffer amplifier either on-chip references.
*ADDITIONAL PINS OMITTED CLARITY
Figure Analog Input
overall throughput rate equal conversion time plus track/hold amplifier acquisition time. input clock throughput time max.
REV.
AD7868
+25°C
input signal within full dynamic range ADC. applications which require that input signal range match full analog input dynamic range ADC, offset full-scale errors have adjusted zero.
ADJUSTMENT
OUTPUT WITH LOADED DECOUPLED SHOWN FIGURE
100k
FREQUENCY
Figure signal conditioning input output AD7868 trimming points transfer functions both DAC. Offset error must adjusted before full-scale error. ADC, this achieved trimming offset while input voltage, below ground. trim procedure follows: apply voltage -0.73 (-1/2 LSB) Figure adjust offset voltage until output code flickers between 1111 1111 1111 (FFF HEX) 0000 0000 0000 (000 HEX). gain error adjusted either first code transition (ADC negative full scale) last code transition (ADC positive full scale). trim procedures both cases follows (see Figure
Positive Full-Scale Adjustment
Figure Noise Spectral Density Frequency
INPUT/OUTPUT TRANSFER FUNCTIONS
bipolar circuit AD7868 shown Figure analog input/output voltage range AD7868 designed code transitions occur midway between successive integer values (i.e., LSB, LSB, LSBs). input/output code complement binary with FS/4096 1.46 ideal transfer function shown Figure
AD7868*
ANALOG INPUT RANGE 10µF 0.1µF AGND VOUT
Apply voltage 2.9978 (FS/2 LSBs) Adjust until output code flickers between 0111 1111 1110 (7FE HEX) 0111 1111 1111 (7FF HEX).
Negative Full-Scale Adjustment
ANALOG OUTPUT RANGE
Apply voltage -2.9993 (-FS/2 LSB) adjust until output code flickers between 1000 0000 0000 (800 HEX) 1000 0000 0001 (801 HEX).
ADJUSTMENT
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7868 Basic Bipolar Operation Using Reference Input
OUTPUT CODE
included Figure transfer function adjustment. Again offset must adjusted before full scale. adjust offset: load with 0000 0000 0000 (000 HEX) trim offset with adjustment, gain error adjusted either first code transition (DAC negative full scale) last code transition (DAC positive full scale). trim procedures both cases follows:
Positive Full-Scale Adjustment
011.111 011.110
Load with 0111 1111 1111 (7FF HEX) adjust until output voltage equal 2.9985 (FS/2 LSB).
Negative Full-Scale Adjustment
000.010 000.001 000.000 111.111 111.110
Load with 1000 0000 0000 (800 HEX) adjust until output voltage equal (-FS/2).
-1LSB
INPUT VOLTAGE RANGE
1LSB 4096
100.001 100.000
VOUT OUTPUT VOLTAGE RANGE
INPUT VOLTAGE
AD7868*
Figure AD7868 Input/Output Transfer Function
OFFSET FULL-SCALE ADJUSTMENT
AGND
most digital signal processing (DSP) applications, offset full-scale errors have little effect system performance. Offset error always eliminated analog domain coupling. Full-scale errors cause problems long REV.
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7868 with Input/Output Adjustment
AD7868
TIMING CONTROL
Communication with AD7868 managed dedicated pins. These consist separate serial clocks, word framing strobe pulses data signals both receiving transmitting data. Conversion starts updating controlled digital inputs; CONVST LDAC. These inputs asserted independently microprocessor external timer when precise sampling intervals required. Alternatively, LDAC CONVST driven from decoded address allowing microprocessor control over conversion start updating well data communication AD7868.
Timing
serial clock which runs continuously. Both options available AD7868 ADC. With CONTROL input RCLK noncontinuous when RCLK continuous.
Timing
AD7868 contains latches, input latch latch. Data must loaded input latch under control TCLK, serial logic inputs. Data then transferred from input latch latch under control LDAC signal. Only data latch determines analog output AD7868. Data loaded input latch under control TCLK, AD7868 expects 16-bit stream serial data input. Data must valid falling edge TCLK. input provides frame synchronization signal which tells AD7868 that valid serial data will available next falling edges TCLK. Figure shows timing diagram serial data format. Although bits data clocked into input latch, only bits transferred into latch. Therefore, bits stream don't cares since their value does affect latch data. positions don't cares followed 12-bit data starting with MSB. LDAC signal controls transfer data latch. Normally, data loaded latch falling edge LDAC. However, LDAC held low, then serial data loaded latch sixteenth falling edge TCLK. LDAC goes during loading serial data input latch, latch update takes place falling edge LDAC. LDAC stays until serial transfer completed, then update takes place sixteenth falling edge TCLK. LDAC returns high before serial data transfer completed, latch update takes place.
Conversion control provided CONVST input. high transition CONVST input starts conversion drives track/hold amplifier into hold mode. Serial data then becomes available while conversion progress. corresponding timing diagram shown Figure word length bits; leading zeros, followed 12-bit conversion result starting with MSB. data synchronized serial clock output (RCLK) framed serial strobe (RFS). Data clocked high transition serial clock valid falling edge this clock while output low. goes start conversion first serial data (which first leading zero) valid first falling edge RCLK. serial lines open-drain outputs require external pull-up resistors. serial clock derived from master clock source which internal external. Normally, RCLK required during serial transmission only. these cases shut down (i.e., placed into high impedance) conversion allow multiple ADCs share common serial bus. However, some serial systems (e.g., TMS32020) require
CONVST
CONVERSION TIME
RCLK
DB10
DB11
NOTES 1EXTERNAL 4.7k PULL-UP RESISTOR
2EXTERNAL
PULL-UP RESISTOR
3CONTINUOUS
RCLK (DASHED LINE) WHEN CONTROL INPUT NONCONTINUOUS WHEN CONTROL INPUT
Figure Control Timing Diagram
TCLK
DON'T DON'T DON'T DON'T CARE CARE CARE CARE DB11 DB10
Figure Control Timing Diagram
REV.
AD7868
AD7868 DYNAMIC SPECIFICATIONS
AD7868 specified 100% tested dynamic performance specifications well traditional specifications such integral differential nonlinearity. These specifications required signal processing applications such speech recognition, spectrum analysis, high-speed modems. These applications require information converter's effect spectral content input signal. Hence, parameters which AD7868 specified include SNR, harmonic distortion peak harmonics. These terms discussed more detail following sections.
Signal-to-Noise Ratio (SNR)
Figure shows typical plot effective number bits versus frequency AD7868BQ with sampling frequency kHz. effective number bits typically falls between 11.7 11.85 corresponding figures 72.2 73.1
measured signal-to-noise ratio output DAC. signal magnitude fundamental. Noise nonfundamental signals half sampling frequency (fs/2) excluding dependent upon number levels used quantization process; more levels, smaller quantization noise. theoretical signal-to-noise ratio sine wave input given (6.02N 1.76) where number bits. Thus ideal 12-bit converter,
Effective Number Bits
Figure AD7868, Plot
1.76 6.02
EFFECTIVE NUMBER BITS
formula given Equation relates number bits. Rewriting formula, Equation possible measure performance expressed effective number bits (N).
11.5
effective number bits device calculated directly from measured SNR.
Harmonic Distortion
10.5
SAMPLE FREQUENCY 25°C
Harmonic distortion ratio harmonics fundamental. AD7868, total harmonic distortion (THD) defined
INPUT FREQUENCY 41.5
Figure Effective Number Bits Frequency
Testing
where amplitude fundamental amplitudes second through sixth harmonic. also derived from plot output spectrum.
Testing
output spectrum from evaluated applying sine-wave signal very distortion input which sampled sampling rate. Fast Fourier Transform (FFT) plot generated from which data obtained. Figure shows typical 2048 point plot AD7868BQ with input signal sampling frequency kHz. obtained from this graph should noted that harmonics taken into account when calculating SNR.
simplified diagram method used test dynamic performance specifications outlined Figure Data loaded under control microcontroller associated logic. output applied order low-pass filter whose cutoff frequency corresponds Nyquist limit. output filter turn applied 16-bit accurate digitizer. This digitizes signal microcontroller generates plot from which dynamic performance evaluated.
REV.
AD7868
MICROCONTROLLER AD7868 LOW-PASS FILTER 16-BIT DIGITIZER
quencies update rate kHz. plot Figure without sample-and-hold output while plot Figure generated with sample-and-hold output.
Figure AD7868 Dynamic Performance Test Circuit
ADG201HS
VOUT
330pF
digitizer sampling synchronized with update rate ease calculations. digitizer samples output after output settled value. Therefore, digitizer were sample output directly would effectively sampling value each time. result, dynamic performance would measured correctly. Using digitizer directly output would give better results than actual performance DAC. Using filter between digitizer means that digitizer samples continuously moving signal true dynamic performance AD7868 output measured. Figure shows typical 2048 point Fast Fourier Transform plot AD7868 with update rate output frequency kHz. obtained from graph dBs.
AD7868*
LDAC
AD711
LDAC
SHOT DELAY
*ADDITIONAL PINS OMITTED CLARITY
Figure Sample-and-Hold Circuit
+25°C
FREQUENCY
Figure Performance Frequency Sampleand-Hold)
Figure AD7868 Plot
Some applications will require improved performance versus frequency from AD7868 DAC. these applications, simple sample-and-hold circuit such that outlined Figure will extend very good performance kHz. Other applications will already have inherent sample-and-hold function following AD7868 output. example this type application driving switched-capacitor filter where updating synchronized with switched-capacitor filter. This inherent sample-and-hold function also extends frequency range performance.
Performance versus Frequency
+25°C
FREQUENCY
typical performance plots Figures show AD7868's performance over wide range input fre-
Figure Performance Frequency (Sample-andHold)
-10-
REV.
AD7868
MICROPROCESSOR INTERFACING
Microprocessor interfacing AD7868 serial that uses standard protocol compatible with machines. communication interface consists separate transmit (DAC) receive (ADC) sections whose operations either synchronous asynchronous with respect each other. Each section clock signal, data signal frame strobe pulse. Synchronous operation means that data transmitted from same time. this mode only interface clock needed this clock out, RCLK must connected TCLK. asynchronous operation, data transfers independent each other, provides receive clock (RCLK) while transmit clock (TCLK) provided processor some other external clock source. Another option considered with serial interfacing gated clock. gated clock means that device that sending data switches clock when data ready transmitted three states clock output when transmission complete. Only clock pulses transmitted with first data getting latched into receiving device first falling clock edge. Ideally, there need frame pulses, however, AD7868 frame input (TFS) driven high between data transmissions. easiest method drive only synchronous interfacing. This avoids interconnects between processor AD7868 frame signals. processors have gated clock facility, Figure shows example with DSP56000. Table below shows number interconnect lines between processor AD7868 different interfacing options. AD7868 facility different clocks transmitting receiving data. This option, however, only exists some processors normally just clock (ADC clock) used communication with AD7868. simplicity, interface examples this data sheet synchronous interfacing clock (RCLK) input clock (TCLK). better understanding each these interfaces, consult relevant processor data sheet.
Table Interconnect Lines Different Interfacing Options Interconnects Signals RCLK, (TCLK RCLK, RFS) RCLK, RFS, (TCLK RCLK serial CLK) RCLK, (TCLK RCLK, RFS)
DSP56000 internal serial control registers have configured 16-bit data word with valid data first falling clock edge. Conversion starts updating controlled external timer. Data transfers, which occur during conversions, between processor receive transmit shift registers AD7868's DAC. each 16-bit transfer DSP56000 receives internal interrupt indicating transmit register empty receive register full.
TIMER CONVST LDAC CONTROL
AD7868*
4.7k 4.7k
DSP56000
RCLK TCLK
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7868-DSP56000 Interface
AD7868-ADSP-2101/ADSP-2102 Interface
interface which suitable ADSP-2101 ADSP2102 shown Figure interface configured synchronous, continuous clock operation. LDAC tied gets updated sixteenth falling clock after goes low. Alternatively LDAC driven from timer shown Figure with previous interface processor receives interrupt after reading writing AD7868 updates internal registers preparation next data transfer.
TIMER CONVST
Configuration Synchronous Asynchronous*
CONTROL
ADSP-2101/ ADSP-2102
SCLK
AD7868*
4.7k 4.7k RCLK
Synchronous Gated Clock
TCLK
LINES INTERCONNECT WHEN TCLK RCLK LINES INTERCONNECT WHEN TCLK SERIAL
AD7868-DSP56000 Interface
Figure shows typical interface between AD7868 DSP56000. interface arrangement synchronous with gated clock requiring only three lines interconnect.
LDAC *ADDITIONAL PINS OMITTED CLARITY
Figure AD7868-ADSP-2101/ADSP-2102 Interface
REV.
-11-
AD7868
AD7868-TMS32020/TMS320C25 Interface
Figure shows interface which suitable TMS32020/TMS320C25 processors. This interface configured synchronous, continuous clock operation. Note, AD7868 will interface correctly these processors AD7868 configured noncontinuous clock. Conversion starts updating controlled external timer.
TIMER CONVST LDAC CONTROL
analog circuitry from digital noise. circuit layout Figures have both analog digital ground planes which kept separated only joined together AD7868 AGND pins.
NOISE
Keep input signal leads signal return leads from AGND short possible minimize input noise coupling. applications where this possible, shielded cable between source ADC. Reduce ground circuit impedance much possible since potential difference grounds between signal source appears error voltage series with input signal.
INPUT/OUTPUT BOARD
TMS32020 TMS320C25
CLKR
AD7868*
4.7k 4.7k RCLK
Figure shows analog board based AD7868. corresponding printed circuit board (PCB) layout silkscreen shown Figures analog input AD7868 buffered with AD711 amp. There component grid provided near analog input which used antialiasing filter reconstruction filter other conditioning circuitry. facilitate this option, there wire links (labeled LK2) required analog input output tracks. board contains circuit which used output AD7868 extend very good performance part over wider frequency range. increased performance from seen Figures this data sheet. wire link (labeled LK3) connects board output either output directly AD7868 output. There three LDAC link options board; LDAC driven from external source independent CONVST, LDAC tied CONVST LDAC tied GND. Choosing latter option tying LDAC disables operation, places permanently track mode. Microprocessor connections board made 9-way D-type connector. pinout shown Figure ADC's digital outputs buffered with 74HC4050s. These buffers provide higher current output capability high capacitance loads cables. Normally, these buffers required AD7868 will sitting same board processor.
POWER SUPPLY CONNECTIONS
CLKX
TCLK
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7868-TMS32020/TMS320C25 Interface
APPLICATION HINTS
Good printed circuit board (PCB) layout important circuit design itself achieving high speed performance. AD7868's comparator required make decisions size 1.465 achieve this, designer conscious noise both itself preceding analog circuitry. Switching mode power supplies recommended switching spikes will feed through comparator causing noisy code transitions. Other causes concern ground loops digital feedthrough from microprocessors. These factors which influence ADC, proper layout which minimizes these effects essential best performance.
LAYOUT HINTS
Ensure that layout printed circuit board digital analog signal lines separated much possible. Take care digital track alongside analog signal track. Guard (screen) analog input with AGND. Establish single point analog ground (star ground) separate from logic system ground close possible AD7868 AGND pins. Connect other grounds AD7868 DGND this single analog ground point. connect other digital grounds this analog ground point. impedance analog digital power supply common returns essential noise operation ADC, make foil width these tracks wide possible. ground planes minimizes impedance paths also guards
requires analog power supplies digital supply. Connections analog supply made directly shown silkscreen Figure connections labeled range both these supplies Connections digital supply made through D-type connector SKT6. analog supply required AD7868 generated from voltage regulators supplies.
-12-
REV.
AD7868
78L05 0.1µF 10µF 10µF ANALOG INPUT RANGE SKT1 0.1µF
COMPONENT GRID
AD711
10µF 0.1µF
0.1µF
10µF
AD7868
CONTROL COMPONENT GRID SKT2 ANALOG OUTPUT RANGE 0.1µF 10µF AGND DGND DGND
AGND SKT6 9-WAY D-TYPE CONNECTOR RCLK
RCLK
4.7k
4.7k
74HC4050
AD711
ADG201HS
VOUT
0.1µF 330pF
10µF
TCLK TCLK
DGND
LDAC 68pF CEXT 0.1µF 10µF REXT CONVST
74HC221
79L05
SKT3 LDAC
SKT4 CONVST
SKT5
Figure Input/Output Circuit Based AD7868
TCLK RCLK
WIRE LINK OPTIONS LK1, Analog Input Link
connects analog input component grid buffer amplifier which drives input.
LK2, Analog Output Link
DGND
connects analog output component grid either output (see LK3).
LK3, Select
CONNECT
Figure SKT6, D-Type Connector Pinout
analog output taken directly from from output DAC. -13-
REV.
AD7868
LK4, Reference Selection COMPONENT LIST
reference connected either reference output ADC) reference DAC).
LK5, Internal Clock Selection
This link configures continuous noncontinuous internal clock operation.
LK6, Updating
IC2, IC4, IC5, IC6, IC7, IC8, C11, C13, C17, C19, C10, C12, C14, C18, C20, LK1, LK2, LK3, LK4, LK5, LK6, LK7, SKT1, SKT2, SKT3, SKT4, SKT5 SKT6
AD7868 AD711 ADG201HS MC78L05 MC79L05 74HC4050 74HC221 Capacitor
DAC, LDAC input asserted independently CONVST signal tied CONVST tied GND.
LK7, Clock Source
Capacitor Capacitor Capacitor Resistor Resistor Resistor Resistor
This link provides option internal clock oscillator external compatible clock.
Frame Synchronous Option
provides option tying output input.
Transmit/Receive Clock Option
provides option connect RCLK TCLK.
Shorting Plugs
Sockets 9-Contact D-Type Connector
Figure Silkscreen Circuit Diagram Figure
-14-
REV.
AD7868
Figure Component Side Layout Circuit Diagram Figure
Figure Solder Side Layout Circuit Diagram Figure
REV.
-15-
AD7868
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
24-Pin Plastic (N-24)
24-Pin Cerdip (Q-24)
C1410-10-7/90
28-Pin Plastic SOIC (R-28)
-16-
REV.
PRINTED U.S.A.
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