µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
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INTEGRATED CIRCUIT
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456 members µPD789426, 789436, 789446, 789456 Subseries (for drive) 78K/0S Series. Flash memory versions, µPD78F9436, 78F9456, which operate same power supply voltage range mask versions, various development tools, available. Detailed function descriptions provided following user's manuals. sure read them before designing. µPD789426, 789436, 789446, 789456 Subseries User's Manual: U15075E 78K/0S Series User's Manual Instructions: U11047E
FEATURES
capacities
Item Part Number Program Memory (ROM) Data Memory Internal High-Speed bytes bytes Display bytes
µPD789425, 789435 µPD789426, 789436 µPD789445, 789455 µPD789446, 789456
Minimum instruction execution time changed from high-speed (0.4 operation with main system clock) ultra-low-speed (122 32.768 operation with subsystem clock). ports (µPD789425, 789426, 789435, 789436) (µPD789445, 789446, 789455, 789456) Timer: channels converter 8-bit resolution: channels (µPD789425, 789426, 789445, 789446) 10-bit resolution: channels (µPD789435, 789436, 789455, 789456) Serial interface: channel controller/driver Segment signals: common signals: (µPD789425, 789426, 789435, 789436) Segment signals: common signals: (µPD789445, 789446, 789455, 789456) Power supply voltage:
APPLICATIONS
Portable audio systems, cameras, healthcare equipment, etc.
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document U14493EJ1V0DS00 (1st edition) Date Published April 2001 CP(K) Printed Japan mark shows major revised points.
2000 1996, 1999
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
ORDERING INFORMATION
Part Number Package 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP
Remark
indicates code suffix.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
78K/0S SERIES LINEUP
products 78K/0S Series listed below. names enclosed boxes subseries names.
Products mass production Products under development Subseries products support SMB. Small-scale package, general-purpose applications 44-pin 42-/44-pin 30-pin 28-pin
PD789046 PD789026 µPD789074 PD789014
PD789074 with added subsystem clock PD789014 with enhanced timer increased ROM, capacity PD789026 with enhanced timer
On-chip UART capable voltage (1.8 operation
Small-scale package, general-purpose applications converter 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin
PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A
Inverter control
PD789177Y PD789167Y
PD789167 with enhanced converter PD789104A with enhanced timer PD789146 with enhanced converter PD789104A with added EEPROMµ PD789124A with enhanced converter oscillation version PD789104A PD789104A with enhanced converter PD789026 with added converter multiplier
44-pin
PD789842
On-chip inverter controller UART
drive 78K/0S Series 52-pin
PD789871
Total display outputs:
drive 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin
PD789488 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306
drive
converter on-chip voltage booster type PD789407A with enhanced converter converter resistance division type PD789446 with enhanced converter converter on-chip voltage booster type µPD789426 with enhanced converter on-chip voltage booster type oscillation version µPD789306 On-chip voltage booster type
144-pin 88-pin
PD789835 PD789830
Segment/common outputs: Segments: commons:
ASSP 80-pin 52-pin 52-pin 64-pin 44-pin 44-pin 20-pin 20-pin
PD789477 PD789467 PD789327 PD789803 µPD789800 PD789840 PD789861 PD789860
PD789488 with added remote control receiver resistance division type remote controller, with converter on-chip voltage booster type remote controller, with resistance division type
keyboard, on-chip function keyboard, on-chip function keypad, on-chip oscillation version µPD789860 keyless entry, on-chip return circuit
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
major functional differences among subseries listed below.
Function Capacity Subseries Name Small-scale package, generalpurpose applications Small-scale package, generalpurpose applications converter 8-Bit 16-Bit Watch 8-Bit 10-Bit Serial Interface (UART: MIN. Value Remarks
µPD789046 µPD789026 µPD789074 µPD789014 µPD789177 µPD789167 µPD789156 µPD789146 µPD789134A µPD789124A µPD789114A µPD789104A
(UART: RC-oscillation version (UART: (UART: (UART: (UART:
On-chip EEPROM RC-oscillation version
Inverter control drive drive
µPD789842 µPD789871 µPD789488 µPD789417A µPD789407A µPD789456 µPD789446 µPD789436 µPD789426 µPD789316 µPD789306
Note
drive
µPD789835 µPD789830
(UART:
ASSP
µPD789477 µPD789467 µPD789327 µPD789800 µPD789840 µPD789861
(UART: (USB:
On-chip
RC-oscillation version, on-chip EEPROM On-chip EEPROM
µPD789860
Note 10-bit timer: channel
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
OVERVIEW FUNCTIONS
Item Internal memory High-speed display Minimum instruction execution time General-purpose registers Instruction ports
µPD789425, 789435
bytes bytes
µPD789426, 789436
µPD789445, 789455
µPD789446, 789456
bytes
µs/1.6 operation with main system clock) 32.768 operation with subsystem clock) bits registers 16-bit operation manipulation (set, reset, test) Total: CMOS I/O: CMOS input: N-ch open drain: 16-bit timer: 8-bit timer: Watch timer: Watchdog timer: channel channels channel channel Total: CMOS I/O: CMOS input: N-ch open drain:
Timers
converter Serial interface controller/driver Vectored interrupt Maskable sources Non-maskable Power supply voltage Operating ambient temperature Package
8-bit resolution channels: 10-bit resolution channels:
µPD789425, 789426, 789445, 789446 µPD789435, 789436, 789455, 789456
Switchable between 3-wire serial mode UART mode: channel Segment signal outputs: (max.) Common signal outputs: (max.) Internal: External: Internal: +85°C 64-pin plastic TQFP Segment signal outputs: (max.) Common signal outputs: (max.)
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
CONTENTS
CONFIGURATION (Top View). Configuration µPD789425, 789426, 789435, 789436 (Top View) Configuration µPD789445, 789446, 789455, 789456 (Top View)
BLOCK DIAGRAM FUNCTIONS Port Pins Non-Port Pins Circuits Recommended Connection Unused Pins
MEMORY SPACE. PERIPHERAL HARDWARE FUNCTIONS Ports Clock Generator. Timer. Converter Serial Interface Controller/Driver.
INTERRUPT FUNCTIONS. STANDBY FUNCTION RESET FUNCTION. MASK OPTIONS
OVERVIEW INSTRUCTION 10.1 10.2 Conventions. List Operations.
ELECTRICAL SPECIFICATIONS CHARACTERISTICS CURVES CONTROLLER/DRIVER (REFRENCE VALUES) PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
CONFIGURATION (TOP VIEW)
Configuration µPD789425, 789426, 789435, 789436 (Top View) 64-pin plastic TQFP
RESET P00/KR0 P01/KR1 P02/KR2 P03/KR3
P21/BZO90 P22/SS20 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO90 P30/INTP0/CPT90 P31/INTP1/TO50/TMI60 P32/INTP2/TO60 P33/INTP3/TO61 AVSS P60/ANI0 P61/ANI1
P62/ANI2 P63/ANI3 P64/ANI4 P65/ANI5 AVDD
Cautions Connect (Internally Connected) directly VSS. Connect AVDD VDD. Connect AVSS VSS.
CAPH CAPL VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Configuration µPD789445, 789446, 789455, 789456 (Top View) 64-pin plastic TQFP
RESET P00/KR0 P01/KR1 P02/KR2 P03/KR3
P21/BZO90 P22/SS20 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO90 P30/INTP0/CPT90 P31/INTP1/TO50/TMI60 P32/INTP2/TO60 P33/INTP3/TO61 AVSS P60/ANI0 P61/ANI1
P62/ANI2 P63/ANI3 P64/ANI4 P65/ANI5 AVDD
Cautions Connect (Internally Connected) directly VSS. Connect AVDD VDD. Connect AVSS VSS.
CAPH CAPL VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
ANI0 ANI5: ASCK20: AVDD: AVSS: BZO90: CAPH, CAPL: COM0 COM3: CPT90: INTP0 INTP3: KR3: P03: P10, P11: P26: P33: P53: P63: P72: Analog input Asynchronous serial input Analog power supply Analog ground Buzzer output power supply capacitance control Common output Capture trigger input Internally connected External interrupt input return Port Port Port Port Port Port Port RESET: RxD20: SS20: S14: SCK20: SI20: SO20: TMI60: TO61: TxD20: VDD: VLC0 VLC2: VSS: XT1, XT2:
Note Note
Port Port Reset Receive data Serial chip select Segment output Serial clock Serial input Serial output Timer input Timer output Transmit data Power supply power supply Ground Crystal (Main system clock) Crystal (Subsystem clock)
TO90, TO50, TO60,
Note µPD789425, 789426, 789435, 789436 only
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
BLOCK DIAGRAM
TO50/TMI60 /INTP1/P31 TO60/INTP2/P32 TO61/INTP3/P33 TMI60/TO50 /INTP1/P31 TO90/P26 CPT90/INTP0/P30 BZO90/P21
Cascaded 16-bit timer/ 8-bit event timer/event counter counter 8-bit timer
Port
Port Port
P10, P80, P81Note P97Note RESET INTP0/CPT90/ INTP1/TO50/ TMI60/P31 INTP2/TO60/ INTP3/TO61/P33 KR0/P00 KR3/P03
16-bit timer Port
Watch timer
Port Port Port
Watchdog timer
78K/0S core
ANI0/P60 ANI5/P65 AVDD AVSS SCK20/ASCK20/P23 SO20/TxD20/P24 SI20/RxD20/P25 SS20/P22
converter space data
Port 8Note Port 9Note
Serial interface
System control
S14) COM0 COM3 VLC0 VLC2 CAPH CAPL controller driver Interrupt control
Note µPD789425, 789426, 789435, 789436 only Remarks Descriptions parentheses µPD789445, 789446, 789455, 789456. internal capacity varies depending product.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
FUNCTIONS
Port Pins (1/2)
Name Function Port 4-bit port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. Port 2-bit port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. Port 7-bit port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. After Reset Input Alternate Function
P10,
Input
Input BZO90 SS20
SCK20/ASCK20 SO20/TxD20 SI20/RxD20 TO90
Port 4-bit port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. Port 4-bit port. Input/output specified 1-bit units. on-chip pull-up resistor specified mask option. Port 6-bit input port. Port 3-bit port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. Port 2-bit port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software.
Input
INTP0/CPT90 INTP1/TO50/TMI60 INTP2/TO60 INTP3/TO61
Input
Input
Input Input
ANI0 ANI5
P80,
Note
Input
Note µPD789425, 789426, 789435, 789436 only
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Port Pins (2/2)
Name Note Function Port 8-bit port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. After Reset Input Alternate Function
Note µPD789425, 789426, 789435, 789436 only
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Non-Port Pins
Name INTP0 INTP1 INTP2 INTP3 SS20 SCK20 SI20 SO20 ASCK20 RxD20 TxD20 TO90 CPT90 TO50 TO60 TO61 TMI60 ANI0 ANI5
Note
Input
Function External interrupt input which valid edge (rising edge, falling edge, both rising falling edges) specified
After Reset Input
Alternate Function P30/CPT90 P31/TO50/TMI60 P32/TO60 P33/TO61
Input Input Input Output Input Output Output Input Output Output Output Input Input Output Output
return signal detection Serial interface (SIO20) chip select Serial interface (SIO20) serial clock input/output SIO20 serial interface serial data input SIO20 serial interface serial data output Asynchronous serial interface serial clock input Asynchronous serial interface serial data input Asynchronous serial interface serial data output 16-bit timer (TM90) output Capture edge input 8-bit timer (TM50) output 8-bit timer (TM60) output 8-bit timer (TM60) output External count clock input 8-bit timer (TM60) converter analog inputs Segment signal outputs controller/driver Segment signal outputs controller/driver Common signal outputs controller/driver drive voltage Connection driver's capacitor
Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output
P23/ASCK20 P25/RxD20 P24/TxD20 P23/SCK20 P25/SI20 P24/SO20 P30/INTP0 P31/INTP1/TMI60 P32/INTP2 P33/INTP3 P31/INTP1/TO50
COM0 COM3 Output VLC0 VLC2 CAPH CAPL RESET AVDD AVSS Input Input Input
Connecting crystal resonator main system clock oscillation
Connecting crystal resonator subsystem clock oscillation
System reset input Positive power supply ports Ground potential converter analog potential converter ground potential Internally connected. Connect directly VSS.
Input
Note µPD789445, 789446, 789455, 789456 only
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Circuits Recommended Connection Unused Pins input/output circuit type each recommended connection unused pins shown Table 3-1. input/output circuit configuration each type, refer Figure 3-1. Table 3-1. Types Input/Output Circuits Recommended Connection Unused Pins
Name Circuit Type Recommended Connection Unused Pins
P10, P21/BZO90 P22/SS20 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO90 P30/INTP0/CPT90 P31/INTP1/TO50/ TMI60 P32/INTP2/TO60 P33/INTP3/TO61 P60/ANI0 P65/ANI5 P80,
Note Note
Input: Independently connect resistor. Output: Leave open.
Input: Independently connect resistor. Output: Leave open.
13-W Input
Input: Independently connect resistor. Output: Leave open. Connect directly VSS. Input: Independently connect resistor. Output: Leave open.
Note
Output
Leave open.
COM0 COM3 VLC0 VLC2 CAPH, CAPL AVSS AVDD RESET
Input
Connect VSS. Leave open. Connect VSS. Connect VDD.
Input Connect directly VSS.
Notes µPD789425, 789426, 789435, 789436 only µPD789445, 789446, 789455, 789456 only
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Figure 3-1. Input/Output Circuits Type Type
P-ch N-ch AVSS
Comparator
VREF (Threshold voltage)
Schmitt-triggered input with hysteresis characteristics
Input enable
Type
Type 13-W
Pull-up enable Data P-ch
P-ch
Pull-up resistor (mask option) IN/OUT Output data Output disable
IN/OUT
N-ch
Output disable
N-ch
Input enable Middle-voltage input buffer
Input enable
Type
Type
VLC0
P-ch
Pull-up enable Data P-ch
P-ch
VLC1
P-ch N-ch P-ch
data
IN/OUT
N-ch P-ch N-ch N-ch
Output disable
N-ch
VLC2
Type
VLC0
P-ch P-ch N-ch P-ch N-ch
VLC1
data VLC2
N-ch P-ch N-ch
N-ch P-ch
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
MEMORY SPACE
Figure shows memory map. Figure 4-1. Memory
FFFFH Special function registers (SFRs) bits FF00H FEFFH Internal high-speed bits FD00H FCFFH Reserved mmmm mmmmH Data memory space display RAMNote FA00H F9FFH nnnnH+1 nnnnH Reserved nnnnH
Program area
Program memory space
Internal ROMNote
0080H 007FH CALLT table area 0040H 003FH Program area 0022H 0021H
0000H
0000H
Vector table area
Notes capacity display varies depending product (see following table).
Part Number Last Address display mmmmH FA04H FA0EH
µPD789425, 789426, 789435, 789436 µPD789445, 789446, 789455, 789456
internal capacity varies depending product (see following table).
Part Number Last Address Internal nnnnH 2FFFH 3FFFH
µPD789425, 789435, 789445, 789455 µPD789426, 789436, 789446, 789456
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
PERIPHERAL HARDWARE FUNCTIONS
Ports ports listed below. CMOS ports: CMOS input ports: N-ch open drain ports: (µPD789425, 789426, 789435, 789436) (µPD789445, 789446, 789455, 789456) Table 5-1. Port Functions
Port Name Port Name Function port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. port. Input/output specified 1-bit units. on-chip pull-up resistor specified mask option. Input-only port port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software.
Port
P10,
Port
Port
Port Port Port
Port
Note
P80,
Port
Note
Note µPD789425, 789426, 789435, 789436 only
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Clock Generator system clock generator incorporated. minimum instruction execution time changed. 0.4µs/1.6µs (@5.0 operation with main system clock) 122µs (@32.768 operation with subsystem clock) Figure 5-1. Clock Generator Block Diagram
Internal
oscillation mode register (SCKM)
Subsystem clock oscillator Prescaler
Watch timer controller/driver
Main system clock oscillator
Prescaler
Clock peripheral hardware
Selector
Standby controller
Wait controller
clock (fCPU)
STOP
PCC1 Processor clock control register (PCC)
CSS0 clock control register (CSS)
Internal
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Timer Five timer changed incorporated. 16-bit timer 8-bit timer Watch timer: Watchdog timer: channel channels channel channel Table 5-2. Timer Operation
16-Bit Timer 8-Bit timer 8-Bit Timer Watch Timer Watchdog Timer channel
Operation mode Function
Interval timer External event counter Timer output Square wave output Buzzer output Carrier generator output Output Capture input Interrupt request
output output input
channel output output
channel channel outputs output output output
channel
Data Sheet U14493EJ1V0DS
Figure 5-2. Block Diagram 16-Bit Timer
Internal
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
16-bit timer mode control register (TMC90) TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 output latch PM26
16-bit compare register (CR90)
TO90/P26 TOD90
Selector
Data Sheet U14493EJ1V0DS
Selector
fX/22 fX/26 fX/27
Match
INTTM90
Synchronizer
16-bit timer counter (TM90)
Selector
BZO90/P21
CTP90/INTP0 /TI81/P30 Edge detector 16-bit capture register (TCP90) 16-bit counter read buffer
output latch
PM21
BCS902 BCS901 BCS900 BZOE90 Write controller fX/2 Write controller clock Internal Buzzer output control register (BZC90)
fX/23 fX/27 Timer interrupt request signal (from Figure 5-4(B)) Timer output signal (from Figure 5-4(C))
Selector
Selector
8-bit timer mode control register (TMC50) Decoder
Figure 5-3. Timer Block Diagram
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Internal
TCE50 TEG50 TCL502 TCL501 TCL500 TMD501 TMD500 TOE50
output latch
PM31
8-bit compare register (CR50) Match Timer match signal Figure 5-4(F) cascade connection mode) INTTM50
Data Sheet U14493EJ1V0DS
TM60 (from Figure 5-4(A))
8-bit timer counter (TM50) Clear Selector
TO50/P31/ INTP1/TMI60
Cascade connection mode
mode
Timer match signal from Figure 5-4(E) cascade connection mode) Count operation start signal from Figure 5-4(E) (cascade connection)
Figure 5-4. Timer Block Diagram
Internal 8-bit timer mode control register (TMC60) TCE60 TCL602 TCL601 TCL600 TMD601 TMD600 TOE60 8-bit compare register (CRH60) 8-bit compare register (CR60) Carrier generator output control register (TCA60)
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
RMC60 NRZB60 NRZ60
Decoder Selector From Figure Timer counter match signal from timer carrier generator mode)
Match
Data Sheet U14493EJ1V0DS
TO60/INTP2/P32 Output control lerNote TO61/INTP3/P33 Figure Carrier clock (during carrier generator mode) timer output signal mode other than carrier generator mode)
fX/22
8-bit timer counter (TM60) fTMI/2 fTMI/22 fTMI/2
Prescaler
Selector
TMI60/TO50 /INTP1/P31
fTMI
Clear mode Reset Cascade connection mode
Figure TM60 cascade connection mode)
Figure Count operation start signal timer cascade connection mode) Figure TM60 timer counter match signal cascade connection mode)
INTTM60 Figure Timer interrupt request signal count clock input signal TM50
From Figure TM50 match signal cascade connection mode)
Note details, Figure 5-5.
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Figure 5-5. Output Controller Block Diagram
TOE60 TOE61
output latch output latch
PM32 PM33
TO60/P32/ INTP2 TO61/P33/ INTP3 Timer output signal
Figure 5-6. Watch Timer Block Diagram
Clear
Selector
fX/27
9-bit prescaler
5-bit counter Clear
INTWT
Selector
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer mode control register (WTM) Internal
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Table 5-10. Configuration Watchdog Timer
Item Control registers Configuration Watchdog timer clock selection register (WDCS) Watchdog timer mode register (WDTM)
Figure 5-7. Watchdog Timer Block Diagram
Internal
Prescaler
WDTMK
WDTIF 7-bit counter Clear
Controller
Selector
INTWDT maskable interrupt request RESET INTWDT non-maskable interrupt request
WDCS2 WDCS1 WDCS0 Watchdog timer clock selection register (WDCS)
WDTM4 WDTM3 Watchdog timer mode register (WDTM) Internal
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Converter conversion resolution converter differs depending product, shown below. 8-bit converter. µPD789425, 789426, 789445, 789446 10-bit converter. µPD789435, 789436, 789455, 789456 conversion operation only started software start. Figure 5-8. Converter Block Diagram
Series resistor string AVDD P-ch ANI0/P60 ANI1/P61 ANI2/P62 ANI3/P63 ANI4/P64 ANI5/P65 Sample hold circuit
Selector
Voltage comparator
selector
AVSS AVSS Successive approximation register (SAR)
Controller
INTAD0
ADS02 ADS01 ADS00 ADCS0 FR01 FR01 FR00 converter mode register (ADM0) Internal
conversion result register (ADCR0)
input selection register (ADS0)
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Serial Interface Serial interface following three modes. Operation stop mode Asynchronous serial interface (UART) mode 3-wire serial mode
Data Sheet U14493EJ1V0DS
Figure 5-9. Block Diagram Serial Interface
CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 SI20/P25 /RxD20
Data Sheet U14493EJ1V0DS
Internal Serial operating mode register (CSIM20) Receive buffer register (RXB20)
Asynchronous serial interface status register (ASIS20)
Asynchronous serial interface mode register (ASIM20)
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
PE20 FE20 OVE20
TXE20 RXE20 PS201 PS200 CL20 SL20
Switch first
Transmit shift register (TXS20) Receive shift register (RXS20) Port mode register (PM24)
Transmit shift clock CSIE20 DAP20
Receive shift clock Parity operation Addition stop Transmit data counter SL20, CL20, PS200, PS201
Selector Data phase control
SO20/P24 /TxD20
INTST20
Parity operation Addition stop Receive data counter
INTSR20/INTCSI20 Reception enable Transmit/receive clock control Baud rate generatorNote Receive detection
Receive clock Detection start Detection clock
CSIE20 CSCK20 fX/2 fX/28
SS20/P22 SCK20/P23 /ASCK20
CSIE20 Clock phase control CSCK20 Internal clock output External clock output Internal
TPS203 TPS202 TPS201 TPS200
Baud rate generator control register (BRGC20)
Note Figure 5-10 configuration baud rate generator.
Figure 5-10. Block Diagram Baud Rate Generator
Clock receive detection Transmit shift clock Transmit clock counter fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 SCK20/ASCK20/P23
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Selector
Receive clock counter
TXE20 RXE20 CSIE20 Receive detection
TPS203 TPS202 TPS201 TPS200 Baud rate generator control register (BRGC20) Internal
Selector
Receive shift clock
Selector
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Controller/Driver controller/driver following functions. Enables automatic output segment signals common signals automatically reading from display data memory. types display modes selected: duty (1/3 bias) duty (1/3 bias) Four frame frequency settings selected each display mode. Operation using subsystem clock also supported. number segment outputs varies depending product. Table lists number segment outputs each product maximum number pixels that displayed each mode. Table 5-3. Number Segment Outputs Maximum Number Displayed Pixels
Bias Method Time Division Common Signals Used Maximum Segment Outputs Maximum Number Displayed Pixels segments commons) segments commons) segments commons) segments commons)
µPD789425, 789426, 789435, 789436 789445, 789446, 789455, 789456
COM0 COM2 COM0 COM3 COM0 COM2 COM0 COM3
Data Sheet U14493EJ1V0DS
Figure 5-11. Block Diagram Controller/Driver
clock control register (LCDC0)
LCDC03 LCDC02 LCDC01 LCDC00
Internal voltage amplifier control register (LCDVA0) FA00H LCDON0 VAON0 LIPS0 LCDM02 LCDM01 LCDM00 GAIN 76543210 display mode register (LCDM0)
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Display data memory FA04H (FA14H)Note 76543210
fX/25 fX/26 fX/27
Selector
fCLK Prescaler fCLK fCLK fCLK fCLK fLCD clock select circuit Voltage amplifier 3210 Selector LCDON0 LCDON0 3210 Selector
Data Sheet U14493EJ1V0DS
Timing controller
drive voltage controller
Common driver
Segment driver
Segment driver
VLC2 VLC1 VLC0 COM0 COM1 COM2 COM3 (S14)
Note When used with µPD789445, 789446, 789455, 789456.
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
INTERRUPT FUNCTIONS
total interrupt sources divided into following types provided. Non-maskable: Maskable: Table 6-1. Interrupt Source List
Interrupt Type Priority
Note
Interrupt Source
Internal/ External
Vector Table Address
Name Nonmaskable Maskable INTWDT INTWDT INTP0 INTP1 INTP2 INTP3 INTSR20 INTCSI20 INTST20 INTWTI INTTM90 INTTM50 INTTM60 INTAD0 INTWT INTKR00
Trigger Watchdog timer overflow (with watchdog timer mode selected) Watchdog timer overflow (with interval timer mode selected) input edge detection External 0006H 0008H 000AH 000CH serial interface UART reception serial interface 3-wire transfer reception serial interface UART transmission Watch timer interval timer interrupt Generation match signal 16-bit timer Generation match signal 8-bit timer/event counter Generation match signal 8-bit timer/event counter conversion completion signal Watch timer interrupt return signal detection External 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H Internal 000EH Internal 0004H
Basic Configuration Type
Note Priority priority order when several maskable interrupts generated same time. highest lowest. Remark watchdog timer interrupt sources (INTWDT): non-maskable interrupt maskable interrupt (internal), available, either which selected.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
STANDBY FUNCTION
following standby functions available further reduction system current consumption. HALT mode: this mode, operation clock stopped. average current consumption reduced intermittent operation combining this mode with normal operation mode. STOP mode: this mode, oscillation main system clock stopped. operations performed main system clock suspended, resulting extremely small power consumption. Figure 7-1. Standby Function
CSS0Note Main system clock operation CSS0
Note
Subsystem clock operationNote HALT instruction Interrupt request HALT mode Clock supply stopped, oscillation maintained HALT mode Clock supply stopped, oscillation maintained HALT instruction
Interrupt request
STOP instruction Interrupt request
STOP mode Main system clock oscillation stopped
Notes sub-clock control register (CSS) current consumption reduced stopping main system clock. When operating subsystem clock, (MCC) processor clock control register (PCC) stop main system clock. STOP instruction cannot used. Caution When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
RESET FUNCTION
following reset methods available. External reset RESET signal input Internal reset watchdog timer inadvertent program loop time detection
MASK OPTIONS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456 have following mask options. Mask options on-chip pull-up resistor selected units. Specifies on-chip pull-up resistor. Does specify on-chip pull-up resistor.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
OVERVIEW INSTRUCTION
This section lists instruction µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456. 10.1 Conventions 10.1.1 Operand expressions description methods Operands described "Operand" column each instruction accordance with description method instruction operand expression (see assembler specifications details). When there more description methods, select them. Uppercase letters symbols, words described they are. meaning each symbol described below. Immediate data specification Absolute address specification Relative address specification Indirect address specification
immediate data, enter appropriate numeric value label. When using label, sure enter symbols. operand register expressions, either function names etc.) absolute names (names parenthesis table below, etc.) used description. Table 10-1. Operand Expressions Description Methods
Expression saddr saddrp addr16 addr5 word byte Description Method (R0), (R1), (R2), (R3), (R4), (R5), (R6), (R7) (RP0), (RP1), (RP2), (RP3) Special function register symbol FE20H FF1FH: immediate data label FE20H FF1FH: immediate data label (even addresses only) 0000H FFFFH: immediate data label (even addresses only 16-bit data transfer instruction) 0040H 007FH: immediate data label (even addresses only) 16-bit immediate data label 8-bit immediate data label 3-bit immediate data label
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
10.1.2 Description "Operation" column PSW: NMIS: addr16: jdisp8: register; 8-bit accumulator register register register register register register register register pair; 16-bit accumulator register pair register pair register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Flag indicating non-maskable interrupt servicing progress Memory contents indicated address register contents parenthesis Higher bits lower bits 16-bit register Logical product (AND) Logical (OR) Exclusive logical (exclusive Inverted data 16-bit immediate data label Signed 8-bit data (displacement value)
10.1.3 Description "Flag" column (Blank): Unchanged Cleared Set/cleared according result Previously saved value restored
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
10.2 List Operations
Mnemonic Operand Bytes Clocks Operation #byte saddr, #byte sfr, #byte saddr saddr, sfr, !addr16 !addr16, PSW, #byte PSW, [DE] [DE], [HL] [HL], byte] byte], saddr [DE] [HL] byte] MOVW #word saddrp saddrp, XCHW
Note Note Note Note Note Note
Flag
byte (saddr) byte byte (saddr) (saddr) (addr16) (addr16) byte (DE) (DE) (HL) (HL) byte) byte) (saddr) (sfr) (DE) (HL) byte) word (saddrp) (saddrp)
Notes Except Except Only when Remark instruction clock cycle clock cycle (fCPU) selected processor clock control register (PCC).
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Mnemonic
Operand
Bytes
Clocks
Operation
Flag
#byte saddr, #byte saddr !addr16 [HL] byte]
byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr) (saddr) byte (saddr) (addr16) (HL) byte)
ADDC
#byte saddr, #byte saddr !addr16 [HL] byte]
#byte saddr, #byte saddr !addr16 [HL] byte]
SUBC
#byte saddr, #byte saddr !addr16 [HL] byte]
#byte saddr, #byte saddr !addr16 [HL] byte]
Remark
instruction clock cycle clock cycle (fCPU) selected processor clock control register (PCC).
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Mnemonic
Operand
Bytes
Clocks
Operation
Flag
#byte saddr, #byte saddr !addr16 [HL] byte]
byte (saddr) (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr) (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr) byte (saddr) (addr16) (HL) byte) word word word rr+1 (saddr) (saddr) rr-1 (saddr) (saddr) (CY, time (CY, time time time
#byte saddr, #byte saddr !addr16 [HL] byte]
#byte saddr, #byte saddr !addr16 [HL] byte]
ADDW SUBW CMPW
#word #word #word saddr
saddr
INCW DECW RORC ROLC
Remark
instruction clock cycle clock cycle (fCPU) selected processor clock control register (PCC).
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Mnemonic
Operand
Bytes
Clocks
Operation
Flag
SET1
saddr. sfr. PSW. [HL].
(saddr. bit) sfr. PSW. (HL). (saddr. bit) sfr. PSW. (HL). 3)H, 3)L, addr16, 1)H, 1)L, (00000000, addr5 (00000000, addr5), (SP), (SP), NMIS PSW, rpH, rpL, (SP), (SP), addr16 jdisp8
CLR1
saddr. sfr. PSW. [HL].
SET1 CLR1 NOT1 CALL CALLT
!addr16 [addr5]
RETI
PUSH
MOVW
!addr16 $addr16
Remark
instruction clock cycle clock cycle (fCPU) selected processor clock control register (PCC).
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Mnemonic
Operand
Bytes
Clocks
Operation
Flag
$addr16 $addr16 $addr16 $addr16 saddr. bit, $addr16 sfr. bit, $addr16 bit, $addr16 PSW. bit, $addr16
jdisp8 jdisp8 jdisp8 jdisp8 jdisp8 (saddr. bit) jdisp8 sfr. jdisp8 jdisp8 PSW. jdisp8 (saddr. bit) jdisp8 sfr. jdisp8 jdisp8 PSW. then jdisp8 then jdisp8 (saddr) (saddr) then jdisp8 (saddr) Operation (Enable Interrupt) (Disable Interrupt) HALT Mode STOP Mode
saddr. bit, $addr16 sfr. bit, $addr16 bit, $addr16 PSW. bit, $addr16
DBNZ
$addr16 $addr16 saddr, $addr16
HALT STOP
Remark
instruction clock cycle clock cycle (fCPU) selected processor clock control register (PCC).
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Power supply voltage Symbol AVDD Input voltage P03, P10, P11, P26, Note P33, P65, P72, Note Note XT1, XT2, RESET N-ch open drain On-chip pull-up resistor Output voltage Output current, high Total pins Output current, Total pins Operating ambient temperature Storage temperature Tstg -0.3 -0.3 -0.3 +150
Note Note
Conditions AVDD
Ratings -0.3 +6.5
Unit
-0.3
Note
Notes µPD789425, 789426, 789435, 789436 less Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. Remark Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Main System Clock Oscillator Characteristics +85°C,
Resonator Ceramic resonator Recommended Circuit
Parameter Oscillation frequency (fX) Oscillation stabilization Note time
Note
Conditions
MIN.
TYP.
MAX.
Unit
After reaches oscillation voltage range MIN.
Note
Crystal resonator
Oscillation frequency(fX) Oscillation stabilization Note time
External clock
input frequency (fX)
Note
input high-/low-level width (tXH, tXL)
input frequency (fX)
Note
OPEN
input high-/low-level width (tXH, tXL)
Notes Indicates only oscillator characteristics. Refer Characteristics instruction execution time. Time required stabilize oscillation after reset STOP mode release. Cautions When using main system clock oscillator, wire follows area enclosed broken lines above figures avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock. Remark resonator selection oscillator constant, customers required either evaluate oscillation themselves apply resonator manufacturer evaluation.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Subsystem Clock Oscillator Characteristics +85°C,
Resonator Crystal resonator Recommended Circuit
Parameter Oscillation frequency Note (fXT) Oscillation stabilization Note time input frequency Note (fXT) input high-/low-level width (tXTH, tXTL)
Conditions
MIN.
TYP. 32.768
MAX.
Unit
External clock
14.3
15.6
Notes Indicates only oscillator characteristics. Refer Characteristics instruction execution time. Time required stabilize oscillation after reaches oscillation voltage range MIN. Cautions When using subsystem clock oscillator, wire follows area enclosed broken lines above figure avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. subsystem clock oscillator designed low-amplitude circuit reducing current consumption, more prone malfunction noise than main system clock oscillator. Particular care therefore required with wiring method when subsystem clock used. Remark resonator selection oscillator constant, customers required either evaluate oscillation themselves apply resonator manufacturer evaluation.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Characteristics +85°C,
Parameter Output current, Symbol pins Output current, high pins Input voltage, high VIH1 P10, P11, P65, Note P72, Note Note N-ch open drain 0.7VDD 0.9VDD 0.7VDD 0.9VDD 0.7VDD 0.9VDD 0.8VDD 0.9VDD Input voltage, VIL1 P10, P11, P65, Note P72, Note Note VIL3 RESET, P03, P26, XT1, Output voltage, high -100 Output voltage, VOL1 P03, P10, P11, P26, P33, P65, P72, Note Note Note XT1, VOL2 Conditions MIN. TYP. MAX. 0.3VDD 0.1VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD Unit
VIH2
On-chip pull- resistor VIH3 RESET, P03, P26, XT1,
VIH4
VIL2
VIL4
Note µPD789425, 789426, 789435, 789436 only Remark Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Characteristics +85°C,
Parameter Input leakage current, high Symbol ILIH1 Conditions P03, P10, P11, P26, P33, P65, P72, Note Note Note RESET XT1, (N-ch open drain) P03, P10, P11, P26, P33, P65, P72, Note Note Note RESET XT1, (N-ch open drain) P03, P10, P11, P26, P33, Note P72, Note Note MIN. TYP. MAX. Unit
ILIH2 ILIH3 Input leakage current, ILIL1
ILIL2 ILIL3 Output leakage current, ILOH high Output leakage current, ILOL Software pull-up resistor
Note
Mask option pull-up resistor
Notes µPD789425, 789426, 789435, 789436 only there on-chip pull-up resistor (specified mask option), have been input mode when read instruction executed read from P53, low-level input leakage current flows during only cycle. other times, maximum leakage current Remark Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Characteristics +85°C,
Parameter Power supply Note current Symbol IDD1 Conditions crystal oscillation ±10% operation mode Note ±10% Note ±10% crystal oscillation ±10% HALT mode Note ±10% Note ±10% 32.768 crystal oscillation operation Note mode 220k) 32.768 crystal oscillation HALT Note mode operating ±10% ±10% ±10%
Note Note
MIN.
TYP. 0.36 0.16 0.96 0.26
MAX. 0.45 1.92 0.76 0.34 14.5
Unit
IDD2
IDD3
IDD4
±10% ±10% ±10%
0.05 0.05
12.5 32.8 18.5 1.25
Note operating
±10% ±10% ±10%
IDD5
STOP mode
Note
±10% ±10% ±10%
IDD6
crystal oscillation ±10% Note operating mode Note ±10% Note ±10%
Note
Notes port current (including current that flows on-chip pull-up resistor) included. High-speed mode operation (when processor clock control register (PCC) 00H) Low-speed mode operation (when 02H) When main system clock stopped This current when controller/driver operating (LCDON0 VAON0 LIPS0 power supply current when operating (LCDON0 VAON0 LIPS0 included IDD2 (HALT mode). Remark When voltage amplifier stopped (LCDON0 VAON0 This total current that flows AVDD. Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Characteristics Basic operation +85°C,
Parameter Cycle time (minimum instruction execution time) Symbol Conditions Operating with main system clock MIN. TMI60 input high-/lowlevel width Interrupt input high/low-level width return input lowlevel width RESET low-level width tTIMH, tTIML tINTH, tINTL tKRL tRSL INTP0 INTP3 TYP. MAX. Unit
Operating with subsystem clock Capture input high-/low- tCPTH, level width tCPTL TMI60 input frequency fTMI CPT90
(main system clock)
Cycle time
Guaranteed operation range
Power supply voltage
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Serial interface (SIO20) +85°C, 3-wire serial mode (internal clock output)
Parameter SCK20 cycle time Symbol tKCY1 Conditions MIN. 3200 SCK20 high-/low-level width SI20 setup time SCK20) SI20 hold time (from SCK20) tKH1, tKL1 tSIK1
tKCY1/2-50 tKCY1/2-150
TYP.
MAX.
Unit
tSI1
SO20 output delay time tSO1 from SCK20
Note
1000
Note load resistance load capacitance SO20 output line. 3-wire serial mode (external clock input)
Parameter SCK20 cycle time Symbol tKCY2 Conditions MIN. 3200 SCK20 high-/low-level width SI20 setup time SCK20) SI20 hold time (from SCK20) tKH2, tKL2 tSIK2 1600 tSI2
Note
TYP.
MAX.
Unit
SO20 output delay time tSO2 from SCK20 SO20 setup time (with SS20, SCK20) tKAS2
1000
SO20 disable time (with tKDS2 SS20, from SCK20)
Note load resistance load capacitance SO20 output line. UART mode (dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 78125 19531 Unit
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
UART mode (external clock input)
Parameter ASCK20 cycle time Symbol tKCY3 Conditions MIN. 3200 ASCK20 high-/lowlevel width Transfer rate tKH3, tKL3 1600 39063 9766 ASCK20 rise/fall time TYP. MAX. Unit
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Timing Measurement Points (excluding inputs)
0.8VDD 0.2VDD 0.8VDD 0.2VDD
Point measurement
Clock Timing
1/fX VIH4 (MIN.) VIL4 (MAX.) 1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.)
input
input
Capture Input Timing
tCPTL tCPTH
CPT90
Timing
1/fTI tTIL tTIH
TMI60
Interrupt Input Timing
tINTL tINTH
INTP0 INTP3
Return Input Timing
tKRL
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
RESET Input Timing
tRSL
RESET
Serial Transfer Timing 3-wire serial mode:
tKCYm tKLm tKHm
SCK20
tSIKm SI20
tKSIm
Input data
tKSOm
SO20
Output data
Remark
3-wire serial mode (when using SS20):
SS20 tKAS2 tKDS2
SO20
Output data
UART mode (external clock input):
tKCY3 tKL3 ASCK20 tKH3
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
8-Bit Converter Characteristics (µPD789425, 789426, 789445, 789446) +85°C, AVDD AVSS
Parameter Resolution Overall error
Note
Symbol
Conditions
MIN.
TYP.
MAX. ±0.6 ±1.2
Unit %FSR %FSR
AVDD
Conversion time
tCONV
AVDD
AVDD
Analog input voltage
VIAN
Note Excludes quantization error (±0.2%) Remark FSR: Full scale range
10-Bit Converter Characteristics (µPD789435, 789436, 789455, 789456) +85°C, AVDD AVSS
Parameter Resolution Overall error
Note
Symbol
Conditions
MIN.
TYP. ±0.2 ±0.4 ±0.8
MAX. ±0.4 ±0.6 ±1.2 ±0.4 ±0.6 ±1.2 ±0.4 ±0.6 ±1.2 ±2.5 ±4.5 ±8.5 ±1.5 ±2.0 ±3.5
Unit %FSR %FSR %FSR
AVDD AVDD AVDD
Conversion time
tCONV
AVDD AVDD AVDD
%FSR %FSR %FSR %FSR %FSR %FSR
Zero-scale error
Note
AINL
AVDD AVDD AVDD
Full-scale error
Note
AINL
AVDD AVDD AVDD
Non-integral linearity
Note
AVDD AVDD AVDD
Non-differential Note linearity
AVDD AVDD AVDD
Analog input voltage
VIAN
AVDD
Note Excludes quantization error (±0.05%) Remark FSR: Full scale range
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Characteristics +85°C,
Parameter output voltage variation range Doubler output Tripler output Voltage amplification wait Note time Symbol VLCD2
Note
Conditions 0.47 GAIN GAIN
MIN. 0.84 1.26 2VLCD2 -0.1 3VLCD2 -0.15
TYP. 2.0VLCD2 3.0VLCD2
MAX. 1.165 1.74 2.0VLCD2 3.0VLCD2
Unit
VLCD1 VLCD0 tVAWAIT
Note Note
0.47 0.47
GAIN GAIN
±0.2 ±0.2
output voltage Note (common) differential output voltage Note (segment) differential
VODC VODS
Notes This capacitor that connected between voltage pins used drive LCD. capacitor connected between CAPH CAPL capacitor connected between VLC0 capacitor connected between VLC1 capacitor connected between VLC2 This wait time from when voltage amplification started (VAON0 until display enabled (LCDON0 voltage differential difference between segment common signal output's actual ideal output voltages. Data Memory STOP Mode Supply Voltage Data Retention Characteristics +85°C)
Parameter Data retention power supply voltage Release signal time Symbol VDDDR tSREL Conditions MIN. TYP. MAX. Unit
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Data Retention Timing (STOP Mode Release RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release Interrupt Request Signal)
HALT mode STOP mode Data retention mode Operation mode
VDDDR STOP instruction execution
tSREL
Standby release signal (interrupt request) tWAIT
Oscillation Stabilization Wait Time +85°C,
Parameter Oscillation stabilization wait Note time Symbol tWAIT Conditions Release RESET Release interrupt
MIN.
TYP. Note
MAX.
Unit
Notes resonator whose oscillation stabilizes within oscillation stabilization wait time. Selection /fX, /fX, possible with bits (OSTS0 OSTS2) oscillation stabilization time selection register (OSTS). Remark Main system clock oscillation frequency
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
CHARACTERISTICS CURVES CONTROLLER/DRIVER (REFRENCE VALUES)
Characteristics curves voltage amplification stabilization time following shows characteristics curves time from start voltage amplification (VAON0 changes output voltage (when GAIN (using display panel)).
output voltage/Voltage amplification time
VDD4.5 VDD5 VDD5.5
output voltage
VLCD2 VLCD1 VLCD0
1000
1500
2000
2500
3000
3500
4000
Voltage amplification time [ms]
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Temperature characteristics output voltage following shows temperature characteristics curves output voltage.
output voltage/ Temperature (When GAIN
VLCD2
VLCD1
VLCD0
output voltage
Temperature [°C]
output voltage/ Temperature (When GAIN
VLCD2
VLCD1
VLCD0
output voltage
Temperature [°C]
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
PACKAGE DRAWINGS
64-PIN PLASTIC TQFP (12x12)
detail lead
ITEM MILLIMETERS 14.0±0.2 12.0±0.2 12.0±0.2 14.0±0.2 1.125 1.125 0.32 +0.06 -0.10 0.13 0.65 (T.P.) 1.0±0.2 0.17 +0.03 -0.07 0.10 0.1±0.05 1.1±0.1 0.25 0.6±0.15 P64GK-65-9ET-2
NOTE Each lead centerline located within 0.13 true position (T.P.) maximum material condition.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
RECOMMENDED SOLDERING CONDITIONS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456 should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact your sales representative. Table 14-1. Surface Mounting Type Soldering Conditions
64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP 64-pin plastic TQFP
Soldering Method Soldering Conditions Recommended Condition Symbol Interface reflow Package peak temperature: 235°C, Time:30 seconds max. 210°C higher), Count: times less, Exposure limit: Note days (after that, prebake 125°C hours) Package peak temperature: 215°C, Time:40 seconds max. 200°C higher), Count: times less, Exposure limit: Note days (after that, prebake 125°C hours) temperature: 300°C max., Time: seconds max. (per row) IR35-107-2
VP15-107-2
Partial heating
Note After opening peak, store 25°C less less allowable storage period. Caution different soldering methods together (except partial heating).
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456. Language Processing Software
RA78K0S
Notes Notes Notes Notes
Assembler package common 78K/0S Series compiler package common 78K/0S Series Device file µPD789426, 789436, 789446, 789456 Subseries compiler library source file common 78K/0S Series
CC78K0S
DF789456
CC78K0S-L
Flash Memory Writing Tools
Flashpro Note (Part FL-PR3 PG-FP3) FA-64GK
Note
Flash programmer dedicated on-chip flash memory microcontroller Flash memory writing adapter 64-pin plastic TQFP (GK-9ET type)
Debugging Tools
IE-78K0S-NS In-circuit emulator This in-circuit emulator debugging hardware software application system using 78K/0S Series. supports integrated debugger (ID78K0S-NS). used with adapter, emulation probe, interface adapter connecting host machine. This adapter supplying power from AC-100 outlet. This adapter needed when PC-9800 series (except notebook type) used host machine IE-78K0S-NS (supports bus). This card interface cable needed when PC-9800 series notebook-type used host machine IE-78K0S-NS (supports PCMCIA socket). This adapter needed when PC/ATor compatible used host machine IE-78K0S-NS (supports bus). This adapter needed when that includes used host machine IE-78K0S-NS. This emulation board emulating peripheral hardware inherent µPD789426, 789436 Subseries devices. used with in-circuit emulator. This emulation board emulating peripheral hardware inherent µPD789446, 789456 Subseries devices. used with in-circuit emulator. This cable that used connect in-circuit emulator target system. 64-pin plastic TQFP (GK-9ET type). System simulator common 78K/0S Series Integrated debugger common 78K/0S Series Device file µPD789426, 789436, 789446, 789456 Subseries
IE-70000-MC-PS-B adapter IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF-A Interface adapter IE-789436-NS-EM1 Emulation board IE-789456-NS-EM1 Emulation board NP-64GK
Note
Emulator probe SM78K0S
Notes Notes
ID78K0S-NS DF789456
Notes
Real-Time
MX78K0S
Notes
78K/0S Series
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Notes Based PC-9800 Series (Japanese WindowsTM) Based PC/AT compatibles (Japanese/English Windows) Based HP9000 Series 700(HP-UXTM), SPARCstation(SunOSTM, SolarisTM), NEWS(NEWS-OSTM) This product manufactured Naito Densei Machida Mfg. Co., Ltd. (TEL +81-44-822-3813). Remark RA78K0S, CC78K0S, SM78K0S used combination with DF789456.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
APPENDIX RELATED DOCUMENTS
Documents Related Devices
Document Name Document This document prepared U15075E U11047E
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456 Data Sheet µPD78F9436, 78F9456 Data Sheet µPD789426, 789436, 789446, 789456 Subseries User's Manual
78K/0S Series User's Manual Instructions
Documents Related Development Tools (User's Manuals)
Document Name RA78K0S Assembler Package Operation Language Structured Assembly Language CC78K0S Compiler Operation Language SM78K0S, SM78K0, System Simulator Ver.2.10 later Windows Based SM78K Series System Simulator 2.10 Later ID78K0-NS, ID78K0S-NS Integrated Debugger Ver.2.20 later Windows Based IE-78K0S-NS In-circuit Emulator IE-789436-NS-EM1 Emulation Board IE-789456-NS-EM1 Emulation Board Operation External Part User Open Interface Specifications Operation Document U11622E U11599E U11623E U11816E U11817E U14611E U15006E U14910E U13549E prepared prepared
Documents Related Embedded Software (User's Manuals)
Document Name 78K/0S Series MX78K0S Fundamental Document U12938E
Other Related Documents
Document Name SEMICONDUCTOR SELECTION GUIDE Products Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Document X13769X C10535E C11531E C10983E C11892E
Caution related documents listed above subject change without notice. sure latest version each document designing.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
[MEMO]
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
related documents indicated this publication include preliminary versions. versions marked such. EEPROM trademark Corporation.
However, preliminary
Windows either registered trademark trademark Microsoft Corporation United States and/or other countries. PC/AT trademark International Business Machines Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. Solaris SunOS trademarks Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation.
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860
Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.2
Data Sheet U14493EJ1V0DS
µPD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
information this document current December, 2000. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).
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