µPD78095B, 78096B, 78098B 8-BIT SINGLE-CHIP MICROCONTROLLERS

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µPD78095B, 78096B, 78098B 8-BIT SINGLE-CHIP MICROCONTROLLERS

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INTEGRATED CIRCUIT
µPD78095B, 78096B, 78098B
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
µPD78095B, 78096B, 78098B members PD78098B Subseries 78K/0 Series microcontrollers. Compared µPD78094, 78095, 78098A, (Electro Magnetic Interference) noise reduced. Besides high-speed high-performance CPU, each microcontroller various on-chip peripheral hardware such ROM, RAM, ports, IEBus controller, 8-bit resolution converter, 8-bit resolution converter, timer, serial interface, real-time output port, interrupt control, etc. one-time PROM version PD78P098B) that operates same power supply voltage mask version various development tools also provided. details functions described following user's manuals. sure read them before starting design.
µPD78098B Subseries User's Manual: U12761E 78K/0 Series User's Manual Instructions: U12326E
FEATURES noise reduced version Internal high capacity
Item Part Number µPD78095B µPD78096B µPD78098B Program Memory (ROM) Kbytes Kbytes Kbytes High-Speed 1024 bytes Internal Data Memory Buffer Expanded bytes None 2048 bytes Package
80-pin plastic
External memory expansion space: Kbytes Minimum instruction execution time varied from high-speed (0.48 ultra-low-speed (122 ports: (N-ch open-drain: IEBus controller Effective transmission rate: kbps/17 kbps/ kbps 8-bit resolution converter: channels
8-bit resolution converter: channels Serial interface: channels 3-wire serial I/O/SBI/2-wire serial mode: channel 3-wire serial mode: channel 3-wire serial I/O/UART mode: channel Timer: channels Supply voltage:
APPLICATION FIELDS
audio, (compact disk) changer, etc.
information this document subject change without notice. Document U12735EJ1V0DS00 (1st edition) Date Published September 1997 Printed Japan
1997
µPD78095B, 78096B, 78098B
ORDERING INFORMATION
Part Number Package 80-pin plastic 80-pin plastic 80-pin plastic
Remark
indicates code suffix.
µPD78095B, 78096B, 78098B
78K/0 SERIES PRODUCT DEVELOPMENT
These products further development 78K/0 Series. designations appearing inside boxes subseries names.
Products mass production Products under development subseries products compatible with bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
µPD78075B µPD78078 µPD78070A µPD780058 µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083
Inverter control
PD78075BY µPD78078Y µPD78070AY µPD780018AYNote µPD780058YNote µPD78058FY µPD78054Y µPD780034Y µPD780024Y µPD78018FY µPD78014Y µPD78002Y
noise reduction version PD78078 timer added PD78054, external interface function enhanced ROM-less versions PD78078 Serial PD78078Y enhanced, only selected functions provided Serial PD78054 enhanced, noise reduction version noise reduction version PD78054 UART converter were added µPD78014, enhanced converter PD780024 enhanced Serial PD78018F enhanced, noise reduction version noise reduction version µPD78018F Low-voltage (1.8 operation versions PD78014 with several capacities available converter 16-bit timer were added µPD78002 converter added µPD78002 Basic subseries control On-chip UART, capable operating voltage (1.8
64-pin 64-pin
µPD780964 µPD780924
FIPdrive
converter PD780924 enhanced On-chip inverter control circuit UART, noise reduction version
78K/0 Series
100-pin 100-pin 80-pin 80-pin
µPD780208 PD780228 µPD78044H µPD78044F
PD78044F were enhanced, Display output total: PD78044H were enhanced, Display output total: N-ch open-drain input/output added PD78044F, Display output total: Basic subseries driving FIP, Display output total:
drive 100-pin 100-pin 100-pin
µPD780308 µPD78064B µPD78064
µPD780308Y µPD78064Y
µPD78064 enhanced, were expanded noise reduction version PD78064 Basic subseries driving LCDs, On-chip UART
IEBus supported 80-pin 80-pin
µPD78098B µPD78098
noise reduced version µPD78098 IEBus controller added µPD78054
Meter control 80-pin
µPD780973
On-chip controller/driver operating automobile meters
64-pin
µPD78P0914
On-chip output, digital code decoder, Hsync counter
Note Under planning
µPD78095B, 78096B, 78098B
following table shows differences among subseries functions.
Function Subseries name Control capacity Timer 8-bit 10-bit 8-bit Serial interface 8-bit 16-bit Watch (UART: value expansion Available MIN. External
µPD78075B µPD78078 µPD78070A µPD780058 µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083
(Time division UART: (UART:
(UART: Time division 3-wire:
Note (Time division UART: (UART: (UART: (UART: Available Available
Inverter control
µPD780964 µPD780924
driving µPD780208
µPD780228
µPD78044H µPD78044F
driving
µPD780308
µPD78064B µPD78064
IEBus supported Meter Control
µPD78098B µPD78098 µPD780973
(UART:
Available
(UART:
µPD78P0914
Available
Note 10-bit timer: channel
µPD78095B, 78096B, 78098B
Overview Function
Part number Item Internal memory High-speed Buffer Expanded Memory space General registers Minimum instruction cycle When main system clock selected When subsystem clock selected Instruction
µPD78095B
µPD78096B
µPD78098B
Kbytes Kbytes Kbytes 1024 bytes bytes None 2048 bytes Kbytes bits registers bits registers banks) On-chip minimum instruction execution time cycle variable function µs/1.0 µs/2.0 µs/4.0 µs/8.0 µs/16.0 6.0-MHz operation with main system clock) 32.768-kHz operation with subsystem clock) 16-bit operation Multiply/divide bits bits, bits bits) manipulate (set, reset, test, boolean operation) adjust, etc. Total CMOS input CMOS N-ch open-drain Effective transmission rate kbps/17 kbps/26 kbps 8-bit resolution channels 8-bit resolution channels 3-wire serial I/O/SBI/2-wire serial mode selectable channel 3-wire serial mode (on-chip max. bytes automatic data transmit/receive function) channel 3-wire serial /UART mode selectable channel 16-bit timer/event counter channel 8-bit timer/event counter channels Watch timer channel Watchdog timer channel (14-bit output 15.6 kHz, 31.3 kHz, 62.5 kHz, kHz, kHz, kHz, MHz, MHz, 6.0-MHz operation with main system clock) 32.768 32.768-kHz operation with subsystem clock) 1.95 kHz, kHz, 6.0-MHz operation with main system clock) Internal: External: Internal: Internal: External: 80-pin plastic
ports
IEBus controller converter converter Serial interface
Timer
Timer output Clock output
Buzzer output Vectored Maskable interrupt Non-maskable sources Software Test input Supply voltage Package
µPD78095B, 78096B, 78098B
CONTENTS
CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTIONS Port Pins Non-port Pins Circuits Recommended Connection Unused Pins
MEMORY SPACE PERIPHERAL HARDWARE FUNCTIONS Ports Clock Generator Timer/Event Counter Clock Output Control Circuit Buzzer Output Control Circuit Converter Converter Serial Interfaces Real-Time Output Port
5.10 IEBus Controller INTERRUPT FUNCTIONS TEST FUNCTIONS Interrupt Functions Test Functions
EXTERNAL DEVICE EXPANSION FUNCTIONS STANDBY FUNCTION RESET FUNCTION
INSTRUCTION ELECTRICAL SPECIFICATIONS CHARACTERISTIC CURVES (REFERENCE VALUES) PACKAGE DRAWING
µPD78095B, 78096B, 78098B
RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78095B, 78096B, 78098B
CONFIGURATION (TOP VIEW)
80-pin plastic
P15/ANI5 P16/ANI6 P17/ANI7 AVss P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P40/AD0 P41/AD1
P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVREF0 AVDD XT1/P07 P06/INTP6 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00
RESET P127/RTP7 P126/RTP6 P125/RTP5/RX P124/RTP4/TX P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
Cautions
Connect (Internally Connected) directly VSS. AVDD functions both converter power supply port. When µPD78095B, 78096B, 78098B used applications where noise generated inside microcontroller needs reduced, connect another power supply that same potential VDD. AVSS functions both converter converter port ground. When
µPD78095B, 78096B, 78098B used applications where noise generated inside microcontroller needs reduced, connect another ground line than VSS.
P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 P64/RD
µPD78095B, 78096B, 78098B
ANI0 ANI7 ANO0, ANO1 ASCK ASTB AVDD AVREF0, AVREF1 AVSS BUSY INTP0 INTP6 P120 P127 P130, P131
Address Address/Data Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected Interrupt from Peripherals Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port12 Port13 Programmable Clock
RESET RTP0 RTP7 SB0, SCK0 SCK2 TI00, TI01 TI1, WAIT XT1,
Read Strobe Reset Real-Time Output Port Receive Data (IEBus Controller) Receive Data (UART) Serial Serial Clock Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data (IEBus Controller) Transmit Data (UART) Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
µPD78095B, 78096B, 78098B
BLOCK DIAGRAM
P120 P127 P130, P131
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit TIMER/ EVENT COUNTER
PORT
PORT
8-bit TIMER/ EVENT COUNTER
PORT
8-bit TIMER/ EVENT COUNTER
PORT
WATCHDOG TIMER
PORT
WATCH TIMER
PORT
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 ANI0/P10 ANI7/P17
SERIAL INTERFACE
PORT 78K/0 CORE
PORT
SERIAL INTERFACE
PORT
PORT
SERIAL INTERFACE
CONVERTER
AVREF0 ANO0/P130, ANO1/P131 AVREF1 INTP0/P00 INTP6/P06 RTP0/P120 RTP7/P127 TX/P124/RTP4 RX/P125/RTP5 BUZ/P36 PCL/P35
INTERRUPT CONTROL REAL-TIME OUTPUT PORT IEBus CONTROLLER BUZZER OUTPUT CLOCK OUTPUT CONTROL
CONVERTER
EXTERNAL ACCESS
AD0/P40 AD7/P47 A8/P50 A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67
AVDD AVSS
SYSTEM CONTROL
RESET XT1/P07
Remark
Internal capacity varies depending products.
µPD78095B, 78096B, 78098B
FUNCTIONS
Port Pins (1/2)
Input Input/ Output Port 8-bit port Function Input only Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. After Reset Input Input Alternate Function INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 INTP6 ANI0 ANI7
Name P07Note
Input Input/ Output
Input/ Output
Input only Port 8-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.Note Port 8-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.
Input Input
Input
SCK1 BUSY SI0/SB0 SO0/SB1 SCK0
Input/ Output
Port 8-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.
Input
Input/ Output
Port Input 8-bit input/output port Input/output specified 8-bit units. When used input port, on-chip pull-up resistor used software. Test input flag (KRIF) falling edge detection.
Notes When using P07/XT1 pins input port, (FRG) processor clock control register (PCC). on-chip feedback resistor subsystem clock oscillator. When using P10/ANI0 P17/ANI7 pins converter analog input, internal pull-up resistor automatically disconnected.
µPD78095B, 78096B, 78098B
Port Pins (2/2)
Input/ Output Port 8-bit input/output port LEDs driven directly. Input/output specified bit-wise. When used input port, chip pull-up resistor used software. P120 P123 Input/ P124 P125 P126, P127 P130, P131 Input/ Output Output Input/ Output Port 3-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 8-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 2-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Input Input RTP0 RTP3 RTP4/TX RTP5/RX RTP6, RTP7 ANO0, ANO1 Input Input/ Output Port 8-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Input WAIT ASTB SI2/RxD SO2/TxD SCK2/ASCK N-ch open-drain input/output port. On-chip pull-up resistor specified mask option. driven directly. Input Function After Reset Input Alternate Function
Name
Caution
perform following operations pins that have alternate functions addition port during conversion. total error rating exceeded with following operations. Rewriting output latch port's output when used port. Changing output level used output when used port.
µPD78095B, 78096B, 78098B
Non-port Pins (1/2)
Input Function External interrupt request input which active edge (rising edge, falling edge, both rising falling edges) specified. After Reset Input Alternate Function P00/TI00 P01/TI01 Input Serial interface serial data input Input P25/SB0 P70/RxD Output Serial interface serial data output Input P26/SB1 P71/TxD Input/ Output Input/ Output Serial interface serial clock input/output Input Serial interface serial data input/output Input P25/SI0 P26/SO0 P72/ASCK Output Input Input Output Input Input Serial interface automatic transmit/receive strobe output Serial interface automatic transmit/receive busy input Asynchronous serial interface serial data input Asynchronous serial interface serial data output Asynchronous serial interface serial clock input External count clock input 16-bit timer (TM0) Capture trigger signal input capture register (CR00) External count clock input 8-bit timer (TM1) External count clock input 8-bit timer (TM2) Output 16-bit timer output (TM0) (also used 14-bit output) 8-bit timer output (TM1) 8-bit timer output (TM2) Output Output Clock output (for main system clock, subsystem clock trimming) Buzzer output Real-time output port which data output synchronization with trigger Input Input Input Input Input Input Input Input Input Input P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1 P120 P123 P124/TX P125/RX P126, P127 Output Input IEBus controller data output IEBus controller data input Input Input P124/RTP4 P125/RTP5
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 SCK0 SCK1 SCK2 BUSY ASCK TI00 TI01
RTP0 RTP3 Output RTP4 RTP5 RTP6, RTP7
µPD78095B, 78096B, 78098B
Non-port Pins (2/2)
Input/ Output WAIT ASTB Input Output Output Output High-order address external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output. Wait insertion external memory access. Strobe output which latches address data output ports access external memory. AN10 AN17 Input ANO0, ANO1 Output AVREF0 AVREF1 AVDD AVSS RESET Input Input Input Input Input Positive power supply. (Other than ports analog pins) Ground potential. (Other than ports analog pins) Internally connected. Connect directly VSS. Subsystem clock oscillation crystal connection. converter analog input. converter analog output. converter reference voltage input. converter reference voltage input. converter analog power supply. (Also used power supply ports) converter converter ground potential. (Also used ground potential ports) System reset input. Main system clock oscillation crystal connection. Input Input Input P130, P131 Input Input Input Input Function Low-order address/data external memory expansion. After Reset Input Alternate Function
Name
Cautions
AVDD functions both converter power supply port. When µPD78095B, 78096B, 78098B used applications where noise generated inside microcontroller needs reduced, connect another power supply that same potential VDD. AVSS functions both converter converter port ground. When µPD78095B, 78096B, 78098B used applications where noise generated inside microcontroller needs reduced, connect another ground line than VSS.
µPD78095B, 78096B, 78098B
Circuits Recommended Connection Unused Pins input/output circuit type each recommended connection unused pins shown Table 3-1. input/output circuit configuration each type, Figure 3-1. Table 3-1. Types Input/Output Circuits (1/2)
Name Input/Output Circuit Type P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 P07/XT1 P10/ANI0 P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7 P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB 13-I Independently connect resistor. Independently connect resistor. Independently connect resistor. Independently connect resistor. 11-C 10-C Input Input/output Connect VDD. Independently connect resistor. Input Input/output Connect VSS. Independently connect resistor. Recommended Connection Unused Pins
µPD78095B, 78096B, 78098B
Table 3-1. Types Input/Output Circuits (2/2)
Name Input/Output Circuit Type P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK Input/output Independently connect resistor. Recommended Connection Unused Pins
P120/RTP0 P123/RTP3 P124/RTP4/TX P125/RTP5/RX P126/RTP6, P127/RTP7 P130/ANO0, P131/ANO1 RESET REF0 REF1 Input Leave open. Connect VSS. Connect VDD. Connect other power supply that same potential VDD. Connect other ground that same potential VSS. Connect directly VSS. 12-B Independently connect resistor.
µPD78095B, 78096B, 78098B
Figure 3-1. Input/Output Circuits (1/2)
Type Type AVDD
pullup enable data AVDD P-ch
P-ch
IN/OUT Schmitt-triggered input with hysteresis characteristics output disable N-ch AVSS
Type pullup enable AVDD data
AVDD
Type 10-C
AVDD
P-ch
pullup enable AVDD data IN/OUT P-ch
P-ch
P-ch
IN/OUT open drain output disable N-ch AVSS
output disable AVSS input enable Type
N-ch
AVDD
Type 11-C pullup enable
AVDD
pullup enable AVDD data P-ch
P-ch
P-ch AVDD P-ch IN/OUT
data
IN/OUT output disable N-ch AVSS
output disable P-ch Comparator
N-ch AVSS
AVSS N-ch VREF (threshold voltage) input enable
µPD78095B, 78096B, 78098B
Figure 3-2. Input/Output Circuits (2/2)
Type 12-B pullup enable AVDD data P-ch IN/OUT output disable AVSS input enable P-ch Analog Output Voltage N-ch Type 13-J AVDD Mask Option IN/OUT data output disable N-ch AVSS AVDD AVSS N-ch AVDD
Type feedback cut-off P-ch
P-ch
P-ch
Middle-High Voltage Input Buffer
µPD78095B, 78096B, 78098B
MEMORY SPACE
memory µPD78095B, 78096B, 78098B shown Figure 4-1. Figure 4-1. Memory
FFFFH FF00H FEFFH FEE0H FEDFH Special Function Registers (SFR) bits General Registers bits Internal High-Speed 1024 bits F7FFH
Internal Expansion 2048 bits
Notes
FB00H FAFFH FAE0H FADFH FAC0H FABFH Data Memory Space F900H F8FFH F8E0H F8DFH F800H F7FFH F000H EFFFH nnnnH+1 nnnnH 0040H 003FH Vector Table Area 0000H 0000H Prohibited Buffer bits Prohibited IEBus Registers bits Prohibited Prohibited Program Area External Memory 0080H 007FH CALLT Table Area 1000H 0FFFH CALLF Entry Area 0800H 07FFH F000H
nnnnH Program Area
Program Memory Space
Internal ROMNote
Notes Only µPD78098B. When using external device expansion function with µPD78098B, internal capacity below Kbytes using memory size switching register (IMS). Internal capacity differs according product.
Target Part number Internal last address nnnnH 9FFFFH BFFFFH EFFFH
µPD78095B µPD78096B µPD78098B
µPD78095B, 78096B, 78098B
PERIPHERAL HARDWARE FUNCTIONS
Ports Input/output ports classified into three types. CMOS input (P00, P07) CMOS input/output (P01 P06, Ports P67, Port Port Port N-ch open-drain input/output (P60-P63) Total Table 5-1. Functions Ports
Port Name Port Name P00, Input only. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Port Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Input/output port. Input/output specified 8-bit units. When used input port, on-chip pull-up resistor connected software. test input flag (KRIF) falling edge detection. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. LEDs driven directly. Port N-ch open-drain input/output port. Input/output specified bit-wise. On-chip pull-up resistor connected mask option. LEDs driven directly. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Function
Port
Port
Port
Port
Port
Port
P120 P127
Port
P130, P131
µPD78095B, 78096B, 78098B
Clock Generator There kinds clock generators: main system subsystem clock generators. possible change minimum instruction execution time. µs/1.0 µs/2.0 µs/4.0 µs/8.0 µs/16.0 6.0-MHz operation with main system clock) 32.768 operation with subsystem clock) Figure 5-1. Clock Generator Block Diagram
XT1/P07 Subsystem Clock Oscillator Watch Timer, Clock Output Function Prescaler
Selector
Selector
Clock IEBus controller
Selector
Main System Clock Oscillator
Selector
Selector
Prescaler
Standby Control Circuit Wait Control Circuit
Clock Peripheral Hardware
STOP
Clock (fCPU)
INTP0 Sampling Clock
µPD78095B, 78096B, 78098B
Timer/Event Counter
There following five timer/event counter channels: 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer channel channels channel channel Table 5-2. Operations Timer/Event Counters
16-bit Timer/Event Counter Operation mode Function Interval timer External event counter Timer output output Pulse width measurement Square wave output One-shot pulse output Interrupt request Test input channel channel output output inputs output output outputs 8-bit Timer/Event Counter channels channels outputs Watch Timer Watchdog Timer
channel input
channel
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal INTP1
Selector
TI01/P01/ INTP1
16-Bit Capture/ Compare Register (CR00)
INTTM00
Match Watch Timer Output 2fXX fXX/2 fXX/2
Pulse Output Control Circuit
Output Control Circuit
TO0/P30
Selector
16-Bit Timer Register (TM0) Clear Selector INTTM01 INTP0 16-Bit Capture/ Compare Register (CR01)
TI00/P00/ INTP0
Edge Detector
Match
Internal
µPD78095B, 78096B, 78098B
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal
INTTM1 8-Bit Compare Register (CR10)
Selector
8-Bit Compare Register (CR20)
Match Match Selector TI1/P33
Output Control Circuit
TO2/P32 INTTM2
Selector
8-Bit Timer Register (TM1) Clear
8-Bit Timer Register (TM2) Clear
Selector
XX/2 TI2/P34
Selector
Output Control Circuit Internal
TO1/P31
Figure 5-4. Watch Timer Block Diagram
Selector
Prescaler
Selector
Selector
5-Bit Counter
INTWT
Selector
INTTM3
16-Bit Timer/ Event Counter
µPD78095B, 78096B, 78098B
Figure 5-5. Watchdog Timer Block Diagram
Prescaler INTWDT Maskable Interrupt Request 8-Bit Counter
Control Circuit
Selector
RESET INTWDT Non-maskable Interrupt Request
Clock Output Control Circuit This circuit output clocks following frequencies: 15.6 kHz/31.3 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1.0 MHz/2.0 MHz/4.0 6.0-MHz operation with main system clock) 32.768 32.768-kHz operation with subsystem clock Figure 5-6. Clock Output Control Circuit Block Diagram
fXX/2 fXX/22 fXX/24 fXX/25 fXX/26 fXX/27
Selector
fXX/23
Synchronization Circuit
Output Control Circuit
PCL/P35
µPD78095B, 78096B, 78098B
Buzzer Output Control Circuit This circuit output clocks following frequencies that used driving buzzers: Hz/1.95 kHz/3.9 kHz/7.8 6.0-MHz operation with main system clock) Figure 5-7. Buzzer Output Control Circuit Block Diagram
Selector
fXX/29 fXX/210 fXX/2
Output Control Circuit
BUZ/P36
Converter converter consists eight 8-bit resolution channels. conversion started following methods: Hardware starting Software starting Figure 5-8. Converter Block Diagram
Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 Sample Hold Circuit AVDD Connection Control AVREF0
ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17
Selector
Voltage Comparator
AVSS
Successive Approximation Register (SAR)
Selector
AVSS
INTP3/P03
Edge Detector
Control Circuit
INTAD INTP3
Conversion Result Register (ADCR)
Internal
µPD78095B, 78096B, 78098B
Converter converter consists 8-bit resolution channels. conversion method R-2R resistor ladder method. Figure 5-9. Converter Block Diagram
AVREF1
ANOn
Selector DACSn Write AVSS INTTMX
Conversion Value Register (DACSn)
DAMm Converter Mode Register
Internal
Serial Interfaces There following three on-chip serial interface channels synchronous with clock: Serial interface channel Serial interface channel Serial interface channel Table 5-3. Types Functions Serial Interfaces
Function 3-wire serial mode Serial Interface Channel (MSB/LSB first switching possible) Serial Interface Channel (MSB/LSB first switching possible) (MSB/LSB first switching possible) Serial Interface Channel (MSB/LSB first switching possible)
3-wire serial mode with automatic data transmit/receive function 2-wire serial mode (Serial interface) mode Asynchronous serial interface (UART) mode
(MSB first) (MSB first)
(On-chip dedicated baud rate generator)
µPD78095B, 78096B, 78098B
Figure 5-10. Serial Interface Channel Block Diagram
Internal
Selector
SI0/SB0/P25
Serial Shift Register (SIO0)
Output Latch
SO0/SB1/P26
Selector
Busy/Acknowledge Output Circuit Release/Command/ Acknowledge Detector Interrupt Request Signal Generator INTCSI0
SCK0/P27
Serial Clock Counter
Serial Clock Control Circuit
Selector
fXX/2-fXX/28
Figure 5-11. Serial Interface Channel Block Diagram
Internal
Automatic Data Transmit/ Receive Address Pointer (ADTP)
Buffer
Automatic Data Transmit/Receive Interval Specification Register (ADTI)
SI1/P20
Serial Shift Register (SIO1)
Match
SO1/P21 5-Bit Counter STB/P23 Handshake Control Circuit
BUSY/P24
SCK1/P22
Serial Clock Counter
Interrupt Request Signal Generator
INTCSI1
Serial Clock Control Circuit
Selector
fXX/2-fXX/28
µPD78095B, 78096B, 78098B
Figure 5-12. Serial Interface Channel Block Diagram
Internal
Receive Buffer Register (RXB/SIO2)
Direction Control Circuit
Direction Control Circuit
Transmit Shift Register (TXS/SIO2)
RXD/SI2/P70 TXD/SO2/P71
Receive Shift Register (RXS)
Transmit Control Circuit
INTST
Receive Control Circuit
INTSER INTSR/INTCSI2 Output Control Circuit
ASCK/SCK2/P72
Baud Rate Generator
fXX-fXX/210
Real-Time Output Port Data previously real-time output buffer transferred output latch hardware concurrently with timer interrupt request external interrupt request generation order output off-chip. This real-time output function. Pins used output off-chip called real-time output ports. using real-time output port, signal which jitter output. This most applicable control stepping motors, etc. Figure 5-13. Real-Time Output Port Block Diagram
Internal
INTP2 INTTM1 INTTM2
Output Trigger Control Circuit
Real-Time Output Real-Time Output Buffer Register Buffer Register Higher Bits Lower Bits (RTBH) (RTBL) Real-Time Output Port Mode Register (RTPM)
Output Latch
P127
P120
µPD78095B, 78096B, 78098B
5.10 IEBus Controller IEBus (Inter Equipment BusTM) small-scale digital data transmission system transmitting data between units. When configuring IEBus with µPD78098B Subseries, IEBus driver/receiver need connected externally they incorporated. Using IEBus controller incorporated µPD78098B Subseries, positive logic/negative logic selected software externally connected IEBus driver/receiver.
µPD78095B, 78096B, 78098B
INTERRUPT FUNCTIONS TEST FUNCTIONS
Interrupt Functions total interrupt sources functions provided, divided into following three types. Non-maskable Maskable Software Table 6-1. List Interrupt Factors
Interrupt Type Nonmaskable Maskable DefaultNote Priority Interrupt Factor Trigger Overflow watchdog timer (When watchdog timer mode selected) Overflow watchdog timer (When interval timer mode selected) input edge detection Internal/ External Internal Vector Table Address 0004H BasicNote Structure Type External 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 002AH
Name INTWDT INTWDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSI0 INTCSI1 INTSER
Completion serial interface channel transfer Internal Completion serial interface channel transfer Occurrence serial interface channel UART reception error INTSR Completion serial interface channel UART reception INTCSI2 Completion serial interface channel 3-wire transfer INTST Completion serial interface channel UART transmission INTTM3 Reference interval signal from watch timer INTTM00 Generation matching signal 16-bit timer register capture/compare register (CR00) INTTM01 Generation matching signal 16-bit timer register capture/compare register (CR01) INTTM1 Generation matching signal 8-bit timer/event counter INTTM2 Generation matching signal 8-bit timer/event counter INTAD Completion conversion INTIE Writing data from IEBus controller return code register (RCR) (including same value) detecting IEBus interface runaway. Execution instruction
Software
003EH
Notes Default priority priority order when several maskable interrupt requests generated same time. highest order lowest order. Basic structure types correspond Figure 6-1.
µPD78095B, 78096B, 78098B
Figure 6-1. Interrupt Function Basic Configuration (1/2) Internal non-maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Internal maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
External maskable interrupt (INTP0)
Internal
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
Interrupt Request
Sampling Clock
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
µPD78095B, 78096B, 78098B
Figure 6-1. Interrupt Function Basic Configuration (2/2) External maskable interrupt (except INTP0)
Internal
External Interrupt Mode Register (INTM0, INTM1)
Interrupt Request
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Software interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag
Priority specification flag
µPD78095B, 78096B, 78098B
Test Functions
Table shows test functions available. Table 6-2. Test Input Factors
Test Input Factor Name INTWT INTPT4 Trigger Overflow watch timer Detection falling edge port Internal/ External Internal External
Figure 6-2. Basic Configuration Test Function
Internal
Test Input Signal
Standby Release Signal
Test input flag
Test mask flag
µPD78095B, 78096B, 78098B
EXTERNAL DEVICE EXPANSION FUNCTIONS
external device expansion functions connect external devices areas other than internal ROM, RAM, SFR. Ports used connect external devices.
STANDBY FUNCTION
standby function designed reduce current consumption. following modes:
HALT mode this mode, operation clock stopped. average current consumption reduced intermittent operation combining this mode with normal operation mode. STOP mode this mode, oscillation main system clock stopped. operations performed main system clock suspended, only subsystem clock used extremely small power consumption. Figure 8-1. Standby Function
Main system clock operation STOP instruction Interrupt request STOP mode (Oscillation main system clock stopped.) Interrupt request HALT mode (Supply clock stopped although clock generated.) HALT instruction Interrupt request HALT modeNote (Supply clock stopped although clock generated.) HALT instruction Subsystem clock operationNote
Note Current consumption reduced shutting main system clock. operating subsystem clock, shut main system clock setting (MCC) processor clock control register (PCC). cannot STOP instruction. Caution When switching main system clock again after subsystem clock been used with main system clock stopped, sure provide oscillation stabilization time with program first.
RESET FUNCTION
There following reset methods. External reset input RESET Internal reset watchdog timer runaway time detection
µPD78095B, 78096B, 78098B
INSTRUCTION
8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Operand Operand #byte rNote saddr !addr16 [DE] [HL] byte] $addr16 None
ADDC SUBC
ADDC SUBC ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
RORC ROLC
saddr ADDC SUBC
DBNZ
DBNZ
!addr16
PUSH
[DE] [HL]
ROR4 ROL4
byte]
MULU DIVUW
Note Except
µPD78095B, 78096B, 78098B
16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Operand Operand ADDW SUBW CMPW MOVW MOVW MOVW MOVWNote MOVW MOVW MOVW MOVW MOVW MOVW XCHW MOVW MOVW MOVW MOVW #word rpNote sfrp saddrp !addr16 None
sfrp saddrp !addr16
INCW, DECW PUSH,
Note Only when manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
Operand Operand A.bit MOV1 BTCLR BTCLR BTCLR BTCLR BTCLR SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 A.bit sfr.bit saddr.bit PSW.bit [HL].bit $addr16 None
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
µPD78095B, 78096B, 78098B
Call instruction/Branch instructions CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DBNZ
Operand Operand Basic instruction CALL CALLF CALLT BNC, BTCLR DBNZ !addr16 !addr11 [addr5] $addr16
Compound instruction
Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT, STOP
µPD78095B, 78096B, 78098B
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol REF0 REF1 Input voltage P07, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, XT2, RESET Output voltage Analog input voltage Output current, high Total P06, P37, P56, P57, P67, P120 P127 Total P17, P27, P47, P55, P72, P130, P131 Output current, Note Total Total P56, P57, Total P17, P27, Total P06, P37, P67, P120 P127 Operating ambient temperature Storage temperature Power dissipation Tstg Peak value r.m.s. value Peak value r.m.s. value Peak value r.m.s. value Peak value Peak value r.m.s. value +150 P47, P72, P130, P131 r.m.s. value Analog input pins N-ch open-drain -0.3 -0.3 AVSS AVREF0 Test Conditions Ratings -0.3 +7.0 -0.3 -0.3 -0.3 -0.3 +0.3 -0.3 Unit
Note r.m.s. value should calculated follows: [r.m.s. value] [Peak value] Duty Caution Exposure Absolute Maximum Ratings extended periods affect device reliablity; exceeding ratings could cause permanent damage. parameters apply independently. Remark Unless otherwise specified, dual-function characteristics same port characteristics.
µPD78095B, 78096B, 78098B
Main System Clock Oscillator Characteristics +85°C,
Resonator Ceramic resonator Recommended Circuit
Parameter Oscillation frequency (fX)
Note
Test Conditions Oscillation voltage range After came MIN. oscillation voltage range
MIN.
TYP.
MAX. 6.29
Unit
Oscillation stabilization time
Note
Crystal resonator
Oscillation frequency (fX)
Note
6.29
Oscillation stabilization time External clock
Note
6.29
input frequency (fX)
Note
PD74HCU04
input high- low-level widths (tXH, tXL)
Using Other than above
Notes Only oscillator characteristics shown. instruction execution time, refer Characteristics. Time required oscillation stabilize after reset STOP mode been released. Cautions When using main system clock oscillator, wire portion enclosed dotted line figures follows avoid adverse influence wiring capacitance: Keep wiring length short possible. cross wiring over other signal lines. route wiring vicinity lines through which high fluctuating current flows. Always keep ground point capacitor oscillator circuit same potential connect power source pattern through which high current flows. extract signals from oscillation circuit. When switching main system clock again after subsystem clock been used with main system clock stopped, sure provide oscillation stabilization time with program first.
µPD78095B, 78096B, 78098B
Subsystem Clock Oscillator Characteristics +85°C,
Resonator Crystal resonator
Recommended Circuit
Parameter Oscillation frequency (fXT)
Note
Test Conditions
MIN.
TYP. 32.768
MAX.
Unit
Oscillation stabilization time Note
External clock
input frequency (fXT)
Note
input high-, low-level widths (tXTH, tXTL)
Notes Only oscillator characteristics shown. instruction execution time, refer Characteristics. Time required oscillation stabilize after power (VDD) turned Cautions When using subsystem clock oscillator, wire portion enclosed dotted line figures follows avoid adverse influence wiring capacitance: Keep wiring length short possible. cross wiring over other signal lines. route wiring vicinity lines through which high fluctuating current flows. Always keep ground point capacitor oscillator circuit same potential connect power source pattern through which high current flows. extract signals from oscillation circuit. amplification factor subsystem clock oscillator circuit designed reduce current consumption therefore, subsystem clock circuit influenced noise more easily than main system clock oscillator. When using subsystem clock, therefore, exercise utmost care wiring circuit.
Capacitance 25°C,
Parameter Input capacitance capacitance Symbol Unmeasured pins returned Test Conditions Unmeasured pins returned P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131 MIN. TYP. MAX. Unit
Remark
Unless otherwise specified, dual-function characteristics same port characteristics.
µPD78095B, 78096B, 78098B
Characteristics +85°C,
Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 Input voltage, VIL1 VIL2 VIL3 VIL4 VIL5 Output voltage, high Output voltage, VOH1 VOL1 Test Conditions P17, P21, P23, P32, P37, P47, P57, P67, P71, P120 P127, P130, P131 P06, P20, P22, P27, P130, P131 RESET XT1/P07, P17, P21, P23, P32, P37, P57, P67, P71, P120 P127, P130, P131 P06, P20, P22, P27, P33, P34, P70, RESET (N-ch open drain) XT1/P07, -100 P57, P06, P17, P27, P37, P47, P67, P72, P120 P127, P130, P131 VOL2 SB0, SB1, SCK0 Open-drain pulled-up VOL3 0.2VDD 0.3V 0.2V 0.2V 0.1V 0.2V N-ch open-drain 0.7VDD 0.8VDD 0.9VDD 0.3V 0.8VDD MIN. 0.7VDD TYP. MAX. Unit
Remark
Unless otherwise specified, dual-function characteristics same port characteristics.
µPD78095B, 78096B, 78098B
Characteristics +85°C,
Parameter Input leakage current, high Symbol ILIH1 Test Conditions P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, RESET ILIH2 ILIH3 Input leakage current, ILIL1 XT1/P07, P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, RESET ILIL2 ILIL3 Output leakage current, high Output leakage current, Mask option pull-up resistor Software pull-up resistor ILOH ILOL VOUT VOUT P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131 XT1/P07,
Note
MIN.
TYP.
MAX.
Unit
Note
When pull-up resistor incorporated P60-63 specified mask option), value -200 either following cases. When external device expansion function used low-level input pins. During clocks when read instruction executed port (P6) port mode register (PM6).
Remark
Unless otherwise specified, dual-function characteristics same port characteristics.
µPD78095B, 78096B, 78098B
Characteristics +85°C,
Parameter Supply current
Note
Symbol IDD1
Test Conditions 5.0-MHz crystal oscil- lation operating mode (fxx MHz)
Note Note Note Note Note
MIN.
TYP.
MAX. 22.5 14.5
Unit
5.0-MHz crystal oscil- lation operating mode (fxx MHz)
Note
6.29-MHz crystal oscil- lation operating mode (fxx MHz)
Note
Note
6.29-MHz crystal oscil- lation operating mode (fxx 4.19 MHz)
Note
Note
Notes This current flowing into pin. However, current flowing into converter, converter, on-chip pull-up resistors included. When (IECL10) clock switch selection register (IECL1) (IECL20) clock switch selection register (IECL2) oscillation mode selection register (OSMS) 00H. When IECL10 IECL20 OSMS 01H. When IECL10 IECL20 OSMS 00H. Only characteristics supply current indicated. Refer IEBus controller characteristics IEBus rating. When IECL10 IECL20 OSMS 01H. Only characteristics supply current indicated. Refer IEBus controller characteristics IEBus rating. High-speed mode operation (when processor clock control register (PCC) 00H) Low-speed mode operation (when 04H). Remark fxx: Main system clock frequency
µPD78095B, 78096B, 78098B
Characteristics +85°C,
Parameter Supply current
Note
Symbol IDD2
Test Conditions 5.0-MHz crystal oscil- ±10% lation HALT mode (fxx MHz)
Note Note Note Note Note
MIN.
TYP.
MAX.
Unit
±10%
5.0-MHz crystal oscil- ±10% lation HALT mode (fxx MHz)
Note
±10%
6.29-MHz crystal oscil- ±10% lation HALT mode (fxx MHz)
Note
Note
6.29-MHz crystal oscil- ±10% lation HALT mode (fxx 4.19 MHz) IDD3 32.768-kHz crystal oscillation operating mode IDD4 32.768-kHz crystal oscillation HALT mode IDD5 STOP mode, feedback resistor used IDD6 STOP mode, feedback resistor used
Note Note Note
Note
±10% ±10% ±10% ±10% ±10% ±10% ±10% ±10%
0.05
Notes This current flowing into AVDD pin. However, current flowing into converter, converter, on-chip pull-up resistors included. When (IECL10) clock switch selection register (IECL1) (IECL20) clock switch selection register (IECL2) oscillation mode selection register (OSMS) 00H. When IECL10 IECL20 OSMS 01H. When IECL10 IECL20 OSMS 00H. Only characteristics supply current indicated. Refer IEBus controller characteristics IEBus rating. When IECL10 IECL20 OSMS 01H. Only characteristics supply current indicated. Refer IEBus controller characteristics IEBus rating. When main system clock stopped. High-speed mode operation (when processor clock control register (PCC) 00H) Low-speed mode operation (when 04H). Remark fxx: Main system clock frequency
µPD78095B, 78096B, 78098B
Characteristics
Basic Operation +85°C,
Parameter Cycle time (minimum instruction execution time) Symbol Operating with main system clock (MCS
Note
Test Conditions fX/2 fX/3 fX/6 fX/9 Operating with main system clock (MCS
Note
MIN. 0.64 1.27 0.95 1.91 1.91 2.86
TYP.
MAX.
Unit
6.29 MHz)
0.64 1.27 0.48 1.91 1.91 1.43
Note
2fX/3 fX/3
6.29 MHz)
Operating with subsystem clock TI00 input frequency TI00 input high-/low-level width TI01, TI1, input frequency TI01, TI1, input high-/lowlevel width Interrupt request high-/lowlevel width RESET input high-/lowlevel width tTIH1 tTIL1 tINTH tINTL tRSL INTP0 INTP1 INTP6 fTI00 tTIH00 tTIL00 fTI1 fTI00 tTIH00 +tTIL00
1/tTI00
8/fsam Note 8/fsam
Note
Notes When oscillation mode selection register (OSMS) 00H. When OSMS 01H. When external clock used. When crystal resonator used, value (MIN.). fsam selected /2N, fxx/32, xx/64, fxx/128 bits (SCS0, SCS1) sampling clock selection register (SCS). Remarks Main system clock frequency Main system clock oscillation frequency
µPD78095B, 78096B, 78098B
(main system clock (IECL10 IECL20 operation)
(main system clock (IECL10 IECL20 operation)
Cycle Time
Operation Guaranteed Range
Cycle Time
Operation Guaranteed Range
Power Supply Voltage
Power Supply Voltage
(main system clock (IECL10 IECL20 operation)
main system clock (IECL10 IECL20 operation)
Cycle Time
Operation Guaranteed Range
Cycle Time
Operation Guaranteed Range
Power Supply Voltage
Power Supply Voltage
Remark
IECL10: clock selection register (IECL1) IECL20: clock selection register (IECL2) MCS: oscillation selection mode register (OSMS)
µPD78095B, 78096B, 78098B
(main system clock (IECL10 IECL20 operation)
(main system clock (IECL10 IECL20 operation)
Cycle Time
Operation Guaranteed Range
Cycle Time
Operation Guaranteed Range
Power Supply Voltage
Power Supply Voltage
(main system clock (IECL10 IECL20 operation)
(main system clock (IECL10 IECL20 operation)
Cycle Time
Cycle Time
Operation Guaranteed Range
Operation Guaranteed Range
Power Supply Voltage
Power Supply Voltage
Remark
IECL10: clock selection register (IECL1) IECL20: clock selection register (IECL2) MCS: oscillation selection mode register (OSMS)
µPD78095B, 78096B, 78098B
Read/Write Operation When PCC2-PCC0 000B +85°C,
Parameter ASTB high-level width Address setup time Address hold time Address data input time data input time Read data hold time low-level width WAIT input time WAIT input time WAIT low-level width Write data setup time Write data hold time low-level width ASTB delay time ASTB delay time external fetch ASTB delay time external fetch address hold time write data output time tRDWD write data output time address hold time WAIT delay time WAIT delay time tWRWD tWRADH tWTRD tWTWR 0.85tCY 1.15tCY 1.15tCY 1.15tCY 3.15tCY 3.15tCY tRDADH 0.85tCY 1.15tCY Symbol tASTH tADS tADH tADD1 tADD2 tRDD1 tRDD2 tRDH tRDL1 tRDL2 tRDWT1 tRDWT2 tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST (1.15 (2.85 (2.85 0.85tCY 0.85tCY 1.15tCY (2.85 0.85tCY 2tCY 2tCY Test Conditions MIN. 0.85tCY 0.85tCY (2.85 (2.85 MAX. Unit
Remarks MCS: oscillation mode selection register (OSMS) PCC2 PCC0: processor clock control register (PCC) TCY/4 indicates number waits
µPD78095B, 78096B, 78098B
Except when PCC2-PCC0 000B +85°C,
Parameter ASTB high-level width Address setup time Address hold time Address data input time data input time Read data hold time low-level width WAIT input time WAIT input time WAIT low-level width Write data setup time Write data hold time low-level width ASTB delay time ASTB delay time external fetch ASTB delay time external fetch address hold time write data output time tRDWD write data output time address hold time WAIT delay time WAIT delay time tWRWD tWRADH tWTRD tWTWR 0.4tCY 0.6tCY 0.6tCY 2.6t 2.6t tRDADH Symbol tASTH tADS tADH tADD1 tADD2 tRDD1 tRDD2 tRDH tRDL1 tRDL2 tRDWT1 tRDWT2 tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST (2.4 (2.4 0.4tCY 1.4t (1.4 (2.4 Test Conditions MIN. 0.4tCY (1.4 (2.4 MAX. Unit
Remarks MCS: oscillation mode selection register (OSMS) PCC2 PCC0: processor clock control register (PCC) indicates number waits
µPD78095B, 78096B, 78098B
Serial Interface Serial Interface Channel 3-wire serial mode (SCK0 internal clock output)
Parameter SCK0 cycle time SCK0 high-/low-level widths setup time SCK0 hold time (from SCK0 SCK0 output delay time tKSI1 tKSO1 pFNote Symbol tKCY1 tKH1, tKL1 tSIK1 Test Conditions MIN. 1600 tKCY1/2-50 tKCY1/2-100 TYP. MAX. Unit
Note output line load capacitance. (ii) 3-wire serial mode (SCK0 external clock input)
Parameter SCK0 cycle time SCK0 high-/low-level widths setup time SCK0 hold time (from SCK0 SCK0 output delay time SCK0 rise, fall time tR2, When using external device expansion function When using external device expansion function 1000 tKSI2 tKSO2 pFNote Symbol tKCY2 tKH2, tKL2 tSIK2 Test Conditions MIN. 1600 TYP. MAX. Unit
Note output line load capacitance.
µPD78095B, 78096B, 78098B
(iii) mode (SCK0 internal clock output)
Parameter SCK0 cycle time SCK0 high-/low-level widths SB0, setup time SCK0 SB0, hold time (from SCK0 SCK0 SB0, output delay time SCK0 SB0, SB0, SCK0 SB0, high-level width SB0, low-level width tKSB tSBK tSBH tSBL tKSO3 pFNote KCY3 KCY3 KCY3 KCY3 1000 tKSI3 Symbol tKCY3 tKH3, tKL3 tSIK3 Test Conditions MIN. 3200 tKCY3/2-50 tKCY3/2-150 tKCY3/2 TYP. MAX. Unit
Note output line load resistance load capacitance. (iv) mode (SCK0 external clock input)
Parameter SCK0 cycle time SCK0 high-/low-level widths SB0, setup time SCK0 SB0, hold time (from SCK0 SCK0 SB0, output delay time SCK0 SB0, SB0, SCK0 SB0, high-level width SB0, low-level width SCK0 rise, fall time tKSB tSBK tSBH tSBL tR4, When using external device expansion function When using external device expansion function 1000 tKSO4 pFNote KCY4 KCY4 KCY4 KCY4 1000 tKSI4 Symbol tKCY4 tKH4, tKL4 tSIK4 Test Conditions MIN. 3200 1600 tKCY4/2 TYP. MAX. Unit
Note output line load resistance load capacitance.
µPD78095B, 78096B, 78098B
2-wire serial mode (SCK0 internal clock input)
Parameter SCK0 cycle time SCK0 high-level widths SCK0 low-level width SB0, setup time SCK0 SB0, hold time (from SCK0 SCK0 SB0, output delay time tKSO5 tKSI5 Symbol tKCY5 tKH5 tKL5 tSIK5 Test Conditions
Note
MIN. 1600 3200 tKCY5/2-160 tKCY5 /2-50
TYP.
MAX.
Unit
Note SCK0, SB0, output line load resistance load capacitance. (vi) 2-wire serial mode (SCK0 external clock input)
Parameter SCK0 cycle time SCK0 high-level widths SCK0 low-level width SB0, setup time SCK0 SB0, hold time (from SCK0 SCK0 SB0, output delay time SCK0 rise, fall time tR6, When using external device expansion function When using external device expansion function 1000 tKSO6 Note tKSI6 tKCY6/2 Symbol tKCY6 tKH6 tKL6 tSIK6 Test Conditions MIN. 1600 3200 TYP. MAX. Unit
Note SCK0, SB0, output line load resistance load capacitance.
µPD78095B, 78096B, 78098B
Serial Interface Channel 3-wire serial mode (SCK1 internal clock output)
Parameter SCK1 cycle time SCK1 high-/low-level widths setup time SCK1 hold time (from SCK1 SCK1 output delay time tKSO7 pFNote tKSI7 Symbol tKCY7 tKH7 tKL7 tSIK7 Test Conditions MIN. 1600 tKCY7/2-50 tKCY7/2-100 TYP. MAX. Unit
Note output line load capacitance. (ii) 3-wire serial mode (SCK1 external clock input)
Parameter SCK1 cycle time SCK1 high-/low-level widths setup time SCK1 hold time (from SCK1 SCK1 output delay time SCK1 rise, fall time tR8, When using external device expansion function When using external device expansion function 1000 tKSO8 pFNote tKSI8 Symbol tKCY8 tKH8, tKL8 tSIK8 Test Conditions MIN. 1600 TYP. MAX. Unit
Note output line load capacitance.
µPD78095B, 78096B, 78098B
(iii) Automatic transmission/reception function 3-wire serial mode (SCK1 internal clock output)
Parameter SCK1 cycle time SCK1 high-/low-level widths setup time SCK1 hold time (from SCK1 SCK1 output delay time SCK1 Strobe signal high-level width Busy signal setup time busy signal detection timing) Busy signal hold time
(from busy signal detection timing)
Symbol tKCY9 tKH9, tKL9 tSIK9 tKSI9 tKSO9 tSBD tSBW tBYS tBYH tSPS
Test Conditions
MIN. 1600 tKCY9/2-50 tKCY9/2-100
TYP.
MAX.
Unit
pFNote tKCY9/2-100 KCY3-30
tKCY9/2+100 tKCY3
Busy inactivation SCK1
2tKCY9
Note output line load capacitance. (iv) Automatic transmission/reception function 3-wire serial mode (SCK1 external clock input)
Parameter SCK1 cycle time SCK1 high-/low-level widths setup time SCK1 hold time (from SCK1 SCK1 output delay time SCK1 rise, fall time tR10, tF10 When using external device expansion function When using external device expansion function 1000 Symbol tKCY10 tKH10, tKL10 tSIK10 tKSI10 tKSO10 Note Test Conditions MIN. 1600 TYP. MAX. Unit
Note output line load capacitance.
µPD78095B, 78096B, 78098B
Serial Interface Channel 3-wire serial mode (SCK2 internal clock output)
Parameter SCK2 cycle time SCK2 high-/low-level widths setup time SCK2 hold time (from SCK2 SCK2 output delay time tKSO11 pFNote tKSI11 Symbol tKCY11 tKH11, tKL11 tSIK11 Test Conditions MIN. 1600 tKCY11/2-50 tKCY11/2-100 TYP. MAX. Unit
Note output line load capacitance. (ii) 3-wire serial mode (SCK2 external clock input)
Parameter SCK2 cycle time SCK2 high-/low-level widths setup time SCK2 hold time (from SCK2 SCK2 output delay time SCK2 rise, fall time tR12, tF12 When using external device expansion function When using external device expansion function 1000 tKSO12 pFNote tKSI12 Symbol tKCY12 tKH12, tKL12 tSIK12 Test Conditions MIN. 1600 TYP. MAX. Unit
Note output line load capacitance.
µPD78095B, 78096B, 78098B
(iii) UART mode (dedicated baud rate generator output)
Parameter Transfer rate Symbol Test Conditions MIN. TYP. MAX. 78125 39063 Unit
(iv) UART mode (external clock input)
Parameter ASCK cycle time ASCK high-/low-level widths Transfer rate ASCK rise, fall time tR13, tF13 Symbol tKCY13 tKH13, tKL13 When using external device expansion function When using external device expansion function 1000 Test Conditions MIN. 1600 39063 19531 TYP. MAX. Unit
µPD78095B, 78096B, 78098B
Timing Test Point (Excluding Input)
0.8VDD 0.2VDD Test Points 0.8VDD 0.2VDD
Clock Timing
1/fx
Input
1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.)
Input
Timing
1/fTI00 tTIL00 tTIH00
TI00
1/fTI1 tTIL1 tTIH1
TI01, TI1,
µPD78095B, 78096B, 78098B
Read/Write Operations External fetch wait):
High-order 8-bit address tADD1 Hi-Z
tADS ASTB tASTH
Low-order 8-bit address
Instruction Code
tADH
tRDD1
tRDADH tRDAST
tASTRD tRDL1 tRDH
External fetch (wait insertion):
tADD1 tADS tASTH ASTB
Low-order 8-bit address
High-order 8-bit address
Hi-Z tRDD1
Instruction Code
tADH
tRDADH tRDAST
tASTRD WAIT tRDWT1 tWTL tWTRD tRDL1 tRDH
µPD78095B, 78096B, 78098B
External data access wait):
tADD2 Hi-Z Low-order
8-bit address
High-order 8-bit address
tADS tASTH ASTB
Read Data tRDD2 tRDH
Hi-Z
Write Data
Hi-Z
tADH
tASTRD tASTWR tRDL2
tRDWD tWRWD
tWDS
tWDH tWRADH
tWRL
External data access (wait insertion):
tADD2 tADS tASTH ASTB tASTRD tRDL2 tASTWR WAIT tRDWT2 tWTL
Low-order 8-bit address
High-order 8-bit address
Hi-Z tRDD2
Read Data tRDH
Hi-Z
Write Data
Hi-Z
tADH
tRDWD tWRWD
tWDS
tWDH tWRADH
tWRL tWTRD tWRWT tWTL tWTWR
µPD78095B, 78096B, 78098B
Serial Transfer Timing 3-wire serial mode:
tKCYm tKLm SCK0 SCK2 tKHm
tSIKm
tKSIm
tKSOm
Input Data
Output Data
Remark
mode (bus release signal transfer):
tKCY3,4 tKL3,4 SCK0 tKSB SB0, tSBL tSBH tSBK tSIK3,4 tKSI3,4 tKH3,4
tKSO3,4
mode (command signal transfer):
tKCY3,4 tKL3,4 SCK0 tKSB SB0, tSBK tSIK3,4 tKSI3,4 tKH3,4
tKSO3,4
µPD78095B, 78096B, 78098B
2-wire serial mode:
tKCY5, tKL5, SCK0 tKH5,
tKSO5,
tSIK5,
tKSI5,
SB0,1
Automatic transmission/reception function 3-wire serial mode:
tSIK9, tKSO9,
tKSI9, tKH9,
tF10 SCK1 tKL9, tKCY9, tR10 tSBD tSBW
Automatic transmission/reception function 3-wire serial mode (busy processing):
SCK1
9Note
10Note tBYS
10+nNote tBYH tSPS
BUSY (Active high)
Note signals actually here, represented this show timing convention.
µPD78095B, 78096B, 78098B
UART Mode (External Clock Input)
tKCY13 tKL13 tR13 ASCK tKH13 tF13
Converter Characteristics +85°C, AVDD
Parameter Resolution Total error
Note
Symbol
Test Conditions IEAD IEAD
MIN.
TYP.
MAX. AVREF0 AVDD
Unit
Conversion time Sampling time Analog input voltage Reference voltage AVREF0-AVSS resistance
tCONV tSAMP VIAN AVREF0 RAIREF0
19.1 12/f AVSS
Note
Excluding quantization error (±1/2 LSB). Shown percentage full scale value. Main system clock frequency IEAD current selection register
Remark
Converter Characteristics +85°C, AVSS
Parameter Resolution Total error Note1 Settling time Output resistor Analog reference voltage AVREF1 current AVREF1 IREF1 Note
Note1
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
MNote1 Note1 DACS0, DACS1 55HNote2
Notes converter output load resistance load capacitance. Value converter channel. Remark DACS0, DACS1 Conversion value register
µPD78095B, 78096B, 78098B
Data Memory STOP Mode Supply Voltage Data Retention Characteristics 85°C)
Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR DDDR Subsystem clock stopped, feedback resistor disconnected Release signal setup time Oscillation stabilization wait time tSREL tWAIT Release RESET Release interrupt request Note
Test Conditions
MIN.
TYP.
MAX.
Unit
Note 212/fxx, 214/fxx through 217/fxx selected bits (OSTS0 OSTS2) oscillation stabilization time selection register (OSTS). Remarks Main system clock frequency Main system clock oscillation frequency
Data Retention Timing (STOP mode released RESET)
Internal reset operation HALT mode STOP mode Data retention mode VDDDR STOP instruction execution RESET Operating mode
tSREL
tWAIT
Data Retention Timing (Standby released signal: STOP mode released interrupt request signal)
HALT mode STOP mode Data retention mode VDDDR STOP instruction execution Standby release signal (interrupt request) tWAIT tSREL Operating mode
µPD78095B, 78096B, 78098B
Interrupt Request Input Timing
tINTL INTP0 INTP6
tINTH
RESET Input Timing
tRSL
RESET
IEBus Controller Characteristics 85°C,
Parameter IEBus controller system clock frequency When using mode Driver delay time output line) Receiver delay time (Bus line input) Propagation delay time 6.00 6.29 6.00 6.29
Note1
Symbol
Test Conditions When using mode mode Note
MIN. 5.91 6.20 5.97 6.26
TYP. 6.00 6.29 6.00 6.29
MAX. 6.09 6.39 6.03 6.32 0.75 0.90 0.85
Unit
Note2 6.00 6.29
Notes Values lower line satisfy standard IEBus. output line load capacitance.
µPD78095B, 78096B, 78098B
CHARACTERISTIC CURVES (REFERENCE VALUES)
MHz, MHz) 25°C)
HALT oscillation, oscillation)
Supply Current [mA]
0.05
STOP stop, oscillation) HALT stop, oscillation)
0.01
32.768
0.005
0.001
Supply Voltage
µPD78095B, 78096B, 78098B
MHz, MHz) 25°C)
HALT oscillation, oscillation)
Supply Current [mA]
0.05
STOP stop, oscillation) HALT stop, oscillation)
0.01
32.768
0.005
0.001
Supply Voltage
µPD78095B, 78096B, 78098B
PACKAGE DRAWING
PLASTIC
detail lead
ITEM MILLIMETERS 17.2±0.4 14.0±0.2 14.0±0.2 17.2±0.4 0.825 0.825 0.30±0.10 0.13 0.65 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 0.1±0.1 5°±5° MAX. INCHES 0.677±0.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.004±0.004 5°±5° 0.119 MAX. S80GC-65-3B9-4
Remark Dimensions materials product same those mass-production products.
µPD78095B, 78096B, 78098B
RECOMMENDED SOLDERING CONDITIONS
These products should soldered mounted under conditions recommended below. details recommended soldering conditions, refer information document "Semiconductor Device Mounting Technology Manual" (C10535E). soldering methods conditions other than those recommended, please contact your sales representative. Table 14-1. Soldering Conditions Surface Mount Devices
80-pin plastic 80-pin plastic 80-pin plastic
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235°C, Reflow time: seconds less 210°C higher), Number reflow processes: less Package peak temperature: 215°C, Reflow time: seconds less 200°C higher), Number reflow processes: less Solder temperature: 260°C below, Flow time: seconds less, Number flow processes: Preheating temperature: 120°C max. (package surface temperature) temperature: 300°C below, Flow time: seconds less (per device side)
Symbol IR35-00-3
VP15-00-3
Wave soldering
WS60-00-1
Partial heating
Caution
Using more soldering methods together should avoided (except case partial heating).
µPD78095B, 78096B, 78098B
APPENDIX DEVELOPMENT TOOLS
following tools available system development using µPD78098 Subseries. Language Processing Software
RA78K/0Notes CC78K/0
Notes
Assembler package used common 78K/0 Series compiler package used common 78K/0 Series Device file used µPD78098 Subseries compiler library source file used common 78K/0 Series
DF78098 Notes CC78K/0-LNotes
PROM Writing Tools
PG-1500 PA-78P054GC PG-1500 Controller
Notes
PROM programmer Programmer adapter connected PG-1500 Control program PG-1500
Debugging Tools
IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78098-R-EMNote IE-780908-R-EM IE-78000-R-SV3 IE-70000-98-IF-B IE-70000-98N-IF IE-70000-PC-IF-B EP-78230GC-R EV-9200GC-80 SM78K0
Notes
In-circuit emulator used common among 78K/0 Series In-circuit emulator used common among 78K/0 Series (for integrated debugger) Break board used common among 78K/0 Series Emulation board used common µPD78098 Subseries Interface adapter cable (for IE-78000-R-A) when host machine Interface adapter (for IE-78000-R-A) when host machine PC-9800 Series (other than notebooks) Interface adapter cable (for IE-78000-R-A) when host machine PC-9800 Series notebook Interface adapter (for IE-78000-R-A) when host machine PC/ATEmulation probe used common µPD78234 Subseries Socket mount target system board that created 80-pin plastic (GC-3B9 type) System simulator used common 78K/0 Series Integrated debugger IE-78000-R-A Screen debugger IE-78000-R Device files used common µPD78098 Subseries
ID78K0Notes SD78K/0
Notes
DF78098 Notes
Real-Time
RX78K/0Notes MX78K0
Notes
Real-time used 78K/0 Series used 78K/0 Series
µPD78095B, 78096B, 78098B
Fuzzy Inference Development Support System
FE9000Note 1/FE9200Note FT9080Note 1/FT9085Note FI78K0Notes FD78K0
Notes
Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
Notes Based PC-9800 Series (MS-DOSTM) Based PC/ATand compatibles DOSTM/IBM DOSTM/MS-DOS) Based HP9000 Series 300(HP-UXTM), Based HP9000 Series 700(HP-UX), SPARCstation(SunOSTM), EWS-4800 Series (EWS-UX/V) Based PC-9800 Series (MS-DOS WindowsTM) Based PC/AT compatibles DOS/IBM DOS/MS Windows) Based NEWS (NEWS-OSTM)
Maintenance product Remark RA78K/0, CC78K/0, SM78K0, RX78K/0, ID78K/0, SD78K/0 combination with DF78098.
µPD78095B, 78096B, 78098B
APPENDIX RELATED DOCUMENTS
Documents Related Devices
Document Document English Japanese U12761J U12735J prepared U12326J U10903J U10904J prepared prepared prepared prepared U12326E
µPD78098B Subseries User's Manual µPD78095B, 78096B, 78098B Data Sheet µPD78P098B Data Sheet
78K/0 Series User's Manual Instruction 78K/0 Series Instruction Table 78K/0 Series Instruction
µPD78098B Subseries Special Function Register Table
Documents Related Development Tools (User's Manual) (1/2)
Document RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package Operation Assembly Structured Assembly Language CC78K Series Compiler CC78K0 Compiler CC78K/0 Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) Based PG-1500 Controller Series DOS) Based IE-78000-R IE-78000-R-A IE-78000-R-BK IE-780908-R-EM EP-78230 SM78K0 System Simulator Windows Based SM78K Series System Simulator Reference External Parts User Open Interface Specifications Operation Language Operation Language Programming know-how Operation Language EEU-1339 EEU-1404 EEU-1402 U11802E U11801E U11789E EEU-1280 EEU-1284 U11517E U11518E EEA-1208 EEU-1335 EEU-1291 U10540E U11376E U10057E EEU-1427 prepared EEU-1515 U10181E U10092E Document English Japanese EEU-809 EEU-815 U12323J U11802J U11801J U11789J EEU-656 EEU-655 U11517J U11518J EEA-618 U12322J U11940J EEU-704 EEU-5008 U11376J U10057J EEU-867 prepared EEU-985 U10181J U10092J
Caution
contents documents listed above subject change without prior notice. Make sure latest edition when starting design.
µPD78095B, 78096B, 78098B
Documents Related Development Tools (User's Manual) (2/2)
Document ID78K0 Integrated Debugger Based ID78K0 Integrated Debugger Based ID78K0 Integrated Debugger Windows Based SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based SD78K/0 Screen Debugger PC/AT DOS) Based Reference Reference Guide Introduction Reference Introduction Reference U11539E U11649E U10539E U11279E Document English Japanese U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J
Documents Related Embedded Software (User's Manual)
Document 78K/0 Series Real-Time 78K/0 Series MX78K0 Fuzzy Knowledge Data Input Tool 78K/0, 78K/II, 87AD Series Fuzzy Interface Development Support System Translator 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Knowledge Debugger Fundamental Installation Fundamental U11537E U11536E EEU-1438 EEU-1444 EEU-1441 EEU-1458 Document English Japanese U11537J U11536J U12257J EEU-829 EEU-862 EEU-858 EEU-921
Other Documents
Document PACKAGE MANUAL Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Guide Quality Assurance Semiconductor Devices C10943X C10535E C11531E C10983E MEI-1202 C10535J C11531J C10983J C11893J Document English Japanese
Caution
contents documents listed above subject change without prior notice. sure latest edition when starting design.
µPD78095B, 78096B, 78098B
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
FIP, IEBus, Inter Equipment trademarks Corporation. MS-DOS Windows either registered trademarks trademarks Microsoft Corporation United States and/or other countries. DOS, PC/AT trademarks International Business Machines Corporation. HP9000 Series 300, HP9000 Series 700, HP-UX trademarks Hewlett Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation.
µPD78095B, 78096B, 78098B
related documents indicated this publication include preliminary versions. However, preliminary versions marked such.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

µPD78095B, 78096B, 78098B 8-BIT SINGLE-CHIP MICROCONTROLLERS

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