µPD78070AY 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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µPD78070AY 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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INTEGRATED CIRCUIT
µPD78070AY
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
PD78070AY limited-function product from which on-chip µPD78078Y Subseries been removed. Through interchangeable external ROM, program maintenance performed easily. Besides highspeed, high-performance CPU, this microcontroller on-chip RAM, ports, 8-bit resolution converter, 8-bit resolution converter, timer, serial interface, real-time output port, interrupt control, various other peripheral hardware. Detailed information about product features specifications found following documents. sure read following documents before starting design.
µPD78070A, 78070AY User's Manual
U10200E
78K/0 Series User's Manual Instructions U12326E
FEATURES Internal large-capacity Internal high-speed 1024 bytes Internal buffer RAM: bytes External memory expansion space Kbytes Minimum instruction execution time
varied from high-speed (0.4 ultra-low-speed (122 ports: (N-ch open-drain
8-bit resolution converter channels 8-bit resolution converter channels Serial interface channels
3-wire serial I/O/2-wire serial I/O/I2C mode channel 3-wire serial mode channel 3-wire serial I/O/UART mode channel
Timer channels Power supply voltage
APPLICATIONS
Audio visual equipment (VCRs, audio equipment, etc.)
ORDERING INFORMATION
Part Number Package 100-pin plastic (Fine pitch) Resin thickness 1.45 100-pin plastic LQFP (Fine pitch) Resin thickness 1.40 100-pin plastic Resin thickness
PD78070AYGC-7EA PD78070AYGC-8EUNote PD78070AYGF-3BA
Note Under planning Caution
types packages provided PD78070AYGC (Refer PACKAGE DRAWINGS). Contact sales representative available packages.
information this document subject change without notice.
Document U10542EJ2V0DS00 (2nd edition) Date Published July 1997 Printed Japan
mark
shows major revised points.
1996 1995
µPD78070AY
78K/0 Series Development
following shows 78K/0 Series products development. Subseries names shown inside frames.
Under mass production Under development Controller 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin subseries provide interface function
PD78075B PD78078 PD78070A PD780018 PD780058 PD78058F PD78054 µPD780034 PD780024 PD78014H PD78018F µPD78014 µPD780001 PD78002 PD78083
Note
PD78075BY PD78078Y PD78070AY µPD780018Y µPD780058Y
Note
noise reduced version PD78078 Added timer enhanced external interface PD78054 Subseries ROM-less versions PD78078 Enhanced serial PD78078 with limited number functions Enhanced serial µPD78054, noise reduced version noise reduced version µPD78054 Added UART, PD78014 enhanced ports Enhanced PD780024 Enhanced serial PD78018F, noise reduced version noise reduced version µPD78018F
µPD78058FY PD78054Y µPD780034Y PD780024Y
PD78018FY µPD78014Y
voltage (1.8 operation version PD78014, enhanced variation Added 16-bit timer/event PD78002 Added µPD78002
PD78002Y
Basic subseries controller On-chip UART, operatable low-voltage (1.8
Inverter controller 64-pin 64-pin
PD780964 PD780924
driver
Enhanced PD780924 On-chip inverter control circuit UART, noise reduced version
78K/0 Series
100-pin 100-pin 80-pin 80-pin
PD780208 PD780228 PD78044H PD78044F
driver
Enhanced ports, controller/driver µPD78044F, Total display outputs: Enhanced ports, controller/driver PD78044H, Total display outputs: Added N-ch open-drain input/output PD78044F, Total display outputs: Basic subseries drive, Total display outputs:
100-pin 100-pin 100-pin
PD780308 µPD78064B PD78064
IEBus supported
PD780308Y
Enhanced µPD78064 expanded noise reduced version µPD78064
PD78064Y
Basic subseries driving, on-chip UART
80-pin 80-pin
µPD78098B PD78098
Meter controller
noise reduced version µPD78098 Added IEBus controller µPD78054
80-pin 100-pin
PD780973 µPD780805
automobile meter drive controller/driver PD780805 generalized Automobile meter drive controller/driver incorporated
64-pin
µPD78P0914
Incorporated output, digital code decorder, Hsync counter
Note
Under planning
µPD78070AY
following table shows differences among subseries functions.
Function Subseries name Controller Timer Serial Interface
MIN. Value
Capacity
8-bit 10-bit 8-bit
External Expansion
8-bit 16-bit Watch
PD78075B PD78078 PD78070A PD780018 PD780058 PD78058F PD78054 PD780034 PD780024 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083 PD780964 PD780924 PD780208 PD780228 PD78044H PD78044F PD780308 PD78064B PD78064
(UART:
Available
(Time division 3-wire: (UART: Time division 3-wire:
(Time division UART: (UART:
Note (Time division UART: (UART: 1ch) (UART: (UART: Available
Inverter controller driver
Available
(UART: 1ch) (UART: 1ch)
driver
IEBus PD78098B supported PD78098 Meter controller
Available
PD780973 PD780805
PD78P0914
Available
Note 10-bit timer: channel
µPD78070AY
FUNCTION DESCRIPTION
Item Internal memory High-speed Buffer Memory space General registers Minimum instruction execution time When main system clock selected When subsystem clock selected Instruction 16-bit operation Multiply/divide bits bits, bits bits) manipulation (set, reset, test, Boolean operation) adjust, etc. ports Total CMOS input CMOS N-ch open-drain converter converter Serial interface 8-bit resolution channels 8-bit resolution channels 3-wire serial I/O/2-wire serial I/O/I mode selectable: channel 3-wire serial mode (on-chip max. 32-byte automatic data transmit/receive function): channel 3-wire serial I/O/UART mode selectable: channel 16-bit timer/event counter: channel 8-bit timer/event counter: channels Watch timer: channel Watchdog timer: channel Timer output Clock output (14-bit output 8-bit output 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 MHz, MHz, (main system clock: 5.0-MHz operation) 32.768 (subsystem clock: 32.768-kHz operation) Buzzer output Vectored interrupt source Test input Power supply voltage Package Maskable Non-maskable Software kHz, kHz, kHz, (main system clock: 5.0-MHz operation) Internal external Internal Internal 100-pin plastic (Fine pitch) Resin thickness 1.45 100-pin plastic LQFP (Fine pitch) Resin thickness 1.40 under planning) 100-pin plastic Resin thickness 1024 bytes bytes Kbytes bits registers bits registers banks) On-chip minimum instruction execution time variable function s/0.8 µs/1.6 µs/3.2 s/6.4 µs/12.8 5.0-MHz operation) 32.768-kHz operation) Function
Timer
µPD78070AY
CONTENTS CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTIONS
Port Pins Non-port Pins Circuits Recommended Connection Unused Pins
MEMORY SPACE PERIPHERAL HARDWARE FUNCTIONS
Ports Clock Generator Timer/Event Counter Clock Output Control Circuit Buzzer Output Control Circuit Converter Converter Serial Interfaces Real-Time Output Port
INTERRUPT FUNCTIONS TEST FUNCTION
Interrupt Functions Test Function
EXTERNAL DEVICE EXPANSION FUNCTIONS STANDBY FUNCTION RESET FUNCTION
INSTRUCTION ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78070AY
CONFIGURATION (Top View)
100-pin plastic (Fine pitch) resin thickness: 1.45
µPD78070AYGC-7EA
100-pin plastic LQFP (Fine pitch) resin thickness: 1.40
µPD78070AYGC-8EUNote
P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL
98979695 9190 8887 8483 8281 7877 28293031 3334 3839 4243 4445 4849
P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVREF0 AVDD P06/INTP6 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00 RESET XT1/P07 P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3
P122/RTP2 P121/RTP1 P120/RTP0 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P103 P102 P101/TI6/TO6 P100/TI5/TO5 ASTB P66/WAIT
Note Under planning Cautions Connect (Internally Connected) directly VSS. Connect AVDD VDD. Connect AVSS VSS.
µPD78070AY
100-pin plastic
PD78070AYGF-3BA
P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P103 P102 P101/TI6/TO6 P100/TI5/TO5 ASTB P120/RTP0 P121/RTP1 P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 XT1/P07 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 AVDD AVREF0 P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5
P66/WAIT
Cautions
Connect (Internally Connected) directly Connect AVDD VDD. Connect AVSS
P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL
µPD78070AY
ANI0 ANI7 ANO0, ANO1 ASCK ASTB REF0, REF1 BUSY INTP0 INTP6 P63, P100 P103 P120 P127 P130, P131 Address Address/Data Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected Interrupt from Peripherals Port0 Port1 Port2 Port3 Port6 Port7 Port9 Port10 Port12 Port13 RESET RTP0 RTP7 SB0, SCK0 SCK2 SDA0, SDA1 TI00, TI01 TI1, TI2, TI5, WAIT XT1, Programmable Clock Read Strobe Reset Real-time Output Port Receive Data Serial Serial Clock Serial Clock Serial Data Serial Input Serial Output Strobe Timer Input Timer Input Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
TO2, TO5, Timer Output
µPD78070AY
BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 16-bit TIMER/ EVENT COUNTER PORT
TO1/P31 TI1/P33
8-bit TIMER/ EVENT COUNTER
PORT
TO2/P32 TI2/P34
8-bit TIMER/ EVENT COUNTER
PORT
TI5/TO5/P100
8-bit TIMER/ EVENT COUNTER
PORT
TI6/TO6/P101
8-bit TIMER/ EVENT COUNTER PORT WATCHDOG TIMER PORT WATCH TIMER P63,
SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SERIAL INTERFACE 78K/0 CORE SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24
PORT
PORT SERIAL INTERFACE PORT
P100 P103
P120 P127
SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 SERIAL INTERFACE PORT P130, P131
ANI0/P10 ANI7/P17 AVDD AVSS AVREF0 CONVERTER
REAL-TIME OUTPUT PORT
RTP0/P120 RTP7/P127
ANO0/P130, ANO1/P131 AVSS AVREF0 CONVERTER EXTERNAL ACCESS WAIT/P66
INTP0/P00 INTP6/P06
INTERRUPT CONTROL
BUZ/P36
RESET BUZZER OUTPUT SYSTEM CONTROL XT1/P07
PCL/P35
CLOCK OUTPUT CONTROL
µPD78070AY
FUNCTIONS
Port Pins (1/2)
Name
Note1
Input/Output Input Input/output Port 8-bit input/output port
Function Input only Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.
After Reset Input Input
Alternate Function INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 INTP6
Input Input/output
Input only Port 8-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.Note Port 8-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.
Input Input
ANI0 ANI7
Input/output
Input
SCK1 BUSY SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL
Input/output
Port 8-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.
Input
Notes When using P07/XT1 input port, (FRC) processor clock control register (PCC) on-chip feedback resistor subsystem clock oscillator. When using P10/ANI0 P17/ANI7 pins converter analog inputs, their on-chip pull-up resistors automatically disconnected.
µPD78070AY
Port Pins (2/2)
Name
Input/Output Input/output Port 5-bit input/output port Input/output specified bit-wise.
Function N-ch open-drain input/output port driven directly.
After Reset Input
Alternate Function
When used input port, on-chip pull-up resistor used software. Input/output Port 3-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Input/output Port 7-bit input/output port Input/output specified bit-wise. N-ch open-drain input/output port Input Input
WAIT
P100 P101 P102, P103
SI2/RXD SO2/TXD SCK2/ASCK
When used input port, on-chip pull-up resistor used software. Input/output Port 4-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 8-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 2-bit input/output port Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Input TI5/TO5 TI6/TO6 Input RTP0 RTP7
P120 P127 Input/output
P130, P131
Input/output
Input
ANO0, ANO1
µPD78070AY
Non-port Pins (1/2)
Input/Output Input Function External interrupt request input which active edge (rising edge, falling edge, both rising falling edges) specified. After Reset Input Alternate Function P00/TI00 P01/TI01 Input Serial interface serial data input Input P25/SB0/SDA0 P70/R Output Serial interface serial data output Input P26/SB1/SDA1 P71/TXD Input/Output Serial interface serial data input/output Input P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0/SB0 P26/SO0/SB1 Input/Output Serial interface serial clock input/output Input P27/SCL P72/ASCK P27/SCK0 Output Input Input Output Input Input Serial interface automatic transmit/receive strobe output Input Serial interface automatic transmit/receive busy input Asynchronous serial interface serial data input Asynchronous serial interface serial data output Asynchronous serial interface serial clock input External count clock input 16-bit timer (TM0) Capture trigger signal input capture register (CR00) External count clock input 8-bit timer (TM1) External count clock input 8-bit timer (TM2) External count clock input 8-bit timer (TM5) External count clock input 8-bit timer (TM6) Output 16-bit timer (TM0) output (also used 14-bit output) 8-bit timer (TM1) output 8-bit timer (TM2) output 8-bit timer (TM5) output (also used 8-bit output) 8-bit timer (TM6) output (also used 8-bit output) Output Clock output (for main system clock, subsystem clock trimming) Input Input Input Input Input Input Input P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1 P100/TO5 P101/TO6 P100/TI5 P101/TI6
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 SDA0 SDA1 SCK0 SCK1 SCK2 BUSY ASCK TI00 TI01
µPD78070AY
Non-port Pins (2/2)
Input/Output Output Output Input/Output Output Output Buzzer output Real-time output port which data output synchronization with trigger Data external memory Address external memory External memory read operation strobe signal output External memory write operation strobe signal output Input Input Output Input Input Input Input Input Positive power supply Ground potential Internal connection. Connected directly Subsystem clock oscillation crystal connection Input Wait insertion external memory access converter analog input converter analog output converter reference voltage input converter reference voltage input converter analog power supply. Connected converter converter ground potential Connected System reset input. Main system clock oscillation crystal connection Input Input Input P130, P131 Function After Reset Input Input Input Input Input Alternate Function P120 P127
Name RTP0 RTP7 WAIT ANI0 ANI7 ANO0, ANO1 AVREF0 AVREF1 AVDD AVSS RESET
µPD78070AY
Circuits Recommended Connection Unused Pins
input/output circuit type each recommended connection unused pins shown Table 3-1. input/output circuit configuration each type, Figure 3-1. Table 3-1. Types Input/Output Circuits (1/2)
Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 P07/XT1 P10/ANI0 P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P66/WAIT 13-C Input/Output Input/Output Independently connect resistor. Independently connect resistor. 10-A Input Input/Output Connect VDD. Independently connect resistor. Input/Output Circuit Type Input/Output Input Input/Output Recommended Connection Unused Pins Connect VSS. Independently connect resistor.
µPD78070AY
Table 3-1. Types Input/Output Circuits (2/2)
Name P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK P100/TI5/TO5 P101/TI6/TO6 P102, P103 P120/RTP0 P127/RTP7 P130/ANO0, P131/ANO1 12-A ASTB RESET AVREF0 AVREF1 AVDD AVSS Connect VSS. Connect directly Input Leave open. Connect VSS. Connect VDD. Input/Output Input/Output Output Independently connect resistor. Independently connect resistor. Leave open. Input/Output Circuit Type 13-C Input/Output Input/Output Independently connect resistor. Independently connect resistor. Input/Output Input/Output Recommended Connection Unused Pins Independently connect resistor.
µPD78070AY
Figure 3-1. Input/Output Circuits (1/2)
Type
Type
pullup enable data P-ch
P-ch
IN/OUT Schmitt-Triggered Input with Hysteresis Characteristic output disable N-ch
Type pullup enable data
Type 10-A
P-ch
pullup enable data IN/OUT P-ch
P-ch
P-ch
IN/OUT open drain output disable N-ch
output disable
N-ch
input enable Type Type pullup enable data P-ch IN/OUT IN/OUT output disable N-ch output disable P-ch Comparator N-ch VREF (threshold voltage) input enable N-ch
pullup enable data P-ch
P-ch
P-ch
µPD78070AY
Figure 3-1. Input/Output Circuits (2/2)
Type 12-A pullup enable data
Type feedback cut-off P-ch
P-ch
P-ch IN/OUT
output disable input enable
N-ch
P-ch Analog Output Voltage N-ch
Type 13-C
IN/OUT data output disable N-ch
µPD78070AY
MEMORY SPACE
memory PD78070AY shown Figure 4-1. Figure 4-1. Memory
FFFFH Special Function Registers (SFR) bits FF00H FEFFH FEE0H FEDFH General Registers bits
Internal High-Speed 1024 bits FB00H FAFFH Prohibited Data Memory Space FAE0H FADFH Buffer bits FAC0H FABFH Prohibited FA80H FA7FH 0FFFH CALLF Entry Area 0800H 07FFH Program Memory Space External Memory 64128 bits Program Area 0080H 007FH 0040H 003FH 0000H 0000H CALLT Table Area
Vector Table Area
µPD78070AY
PERIPHERAL HARDWARE FUNCTIONS
Ports CMOS inputs (P00, P07) CMOS input/outputs (P01 P06, Port P66, Port P96, Port Port Port N-ch open-drain input/outputs (P60 P63, P93) Total Table 5-1. Functions Ports
Port Name Port Name P00, Port Port Port Port Port Port Port Port Port P100 P103 P120 P127 P130, P131 Function Input only Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. N-ch open-drain input/output port. Input/output specified bit-wise. driven directly. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. N-ch open-drain input/output port. Input/output specified bit-wise. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software. Input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor connected software.
Input/output ports classified into three types.
µPD78070AY
Clock Generator
There kinds clock generators: main system subsystem clock generators. possible change minimum instruction execution time. µs/0.8 s/1.6 µs/3.2 µs/6.4 s/12.8 main system clock frequency MHz) subsystem clock frequency 32.768 kHz) Figure 5-1. Clock Generator Block Diagram
XT1/P07
Subsystem Clock Oscillator
Watch Timer, Clock Output Function Prescaler
Main System Clock Oscillator
Selector
Prescaler
Division Circuit
Clock Peripheral Hardware
Selector Standby Control Circuit Wait Control Circuit
STOP
Clock (fCPU)
INTP0 Sampling Clock
µPD78070AY
Timer/Event Counter channel channels channel channel Table 5-2. Types Functions Timer/Event Counters
16-bit Timer/ Event Counter Type Interval timer External event counter Function Timer output output channel channel output output 8-bit Timer/ 8-bit Timer/ Watch Timer Watchdog Timer channel input channel
There following seven timer/event counter channels: 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer
Event Counter Event Counter channels channels outputs outputs channels channels outputs outputs outputs
Pulse width measurement inputs Square wave output One-shot pulse output Interrupt source Test input output output
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal INTP1 Selector TI01/P01/ INTP1 16-Bit Capture/ Compare Register (CR00)
INTTM00
Match Watch Timer Output 2fXX fXX/2 fXX/22 TI00/P00/ INTP0 Edge Detector Match Selector 16-Bit Timer Register (TM0) Clear
Pulse Output Control Circuit
Output Control Circuit
TO0/P30
Selector INTTM01 INTP0
16-Bit Capture/ Compare Register (CR01)
Internal
µPD78070AY
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal
INTTM1 8-Bit Compare Register (CR10)
Selector
8-Bit Compare Register (CR20)
Match Match Selector fXX/2 fXX/29 fXX/211 TI1/P33
Output Control Circuit
TO2/P32 INTTM2
Selector
8-Bit Timer Register (TM1) Clear
8-Bit Timer Register (TM2) Clear
Selector
fXX/2 fXX/29 fXX/211 TI2/P34
Selector
Output Control Circuit Internal
TO1/P31
Figure 5-4. 8-Bit Timer/Event Counter Block Diagram
Internal
8-Bit Compare Register (CRn0)
Match
INTTMn TO5/P100/TI5, TO6/P101/TI6
Selector
2fXX fXX/29 fXX/211 TI5/P100/TO5, TI6/P101/TO6
8-Bit Timer Register (TMn)
Output Control Circuit
Clear
Internal
µPD78070AY
Figure 5-5. Watch Timer Block Diagram
Selector
Selector
Prescaler
Selector
fXX/27
5-Bit Counter
INTWT
Selector
INTTM3
16-Bit Timer/ Event Counter
Figure 5-6. Watchdog Timer Block Diagram
Prescaler INTWDT Maskable Interrupt Request Control Circuit 8-Bit Counter RESET INTWDT Non-maskable Interrupt Request
Clock Output Control Circuit 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 main system clock frequency MHz) 32.768 subsystem clock frequency 32.768 kHz) Figure 5-7. Clock Output Control Circuit Block Diagram
This circuit output clocks following frequencies:
fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 Selector
Synchronization Circuit
Selector
Output Control Circuit
PCL/P35
µPD78070AY
Buzzer Output Control Circuit
This circuit output clocks following frequencies that used driving buzzers: kHz/2.4 kHz/4.9 kHz/9.8 main system clock frequency MHz) Figure 5-8. Buzzer Output Control Circuit Block Diagram
Selector
fXX/29 fXX/210 fXX/211
Output Control Circuit
BUZ/P36
Converter
converter consists eight 8-bit resolution channels. conversion started following methods: Hardware starting Software starting Figure 5-9. Converter Block Diagram
Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 AVSS Successive Approximation Register (SAR) Selector Sample Hold Circuit Voltage Comparator Selector AVDD AVREF0
INTP3/P03
Edge Detector
Control Circuit
INTAD INTP3
Conversion Result Register (ADCR)
Internal
Converter
converter consists 8-bit resolution channels. conversion method R-2R resistor ladder method.
µPD78070AY
Figure 5-10. Converter Block Diagram
AVREF1
ANOn
Selector DACSn Write AVSS INTTMX
Conversion Value Register (DACSn)
DAMm Converter Mode Register
Internal
Serial Interfaces
There following three on-chip serial interface channels synchronous with clock: Serial interface channel Serial interface channel Serial interface channel Table 5-3.
Function 3-wire serial mode 3-wire serial mode with automatic data transmit/receive function 2-wire serial mode mode Asynchronous serial interface (UART) mode
Types Functions Serial Interfaces
Serial Interface Channel (MSB/LSB first switching possible) (MSB/LSB first switching possible) Serial Interface Channel (MSB/LSB first switching possible)
Serial Interface Channel (MSB/LSB first switching possible)
(MSB first) (MSB first)
(On-chip dedicated baud rate generator)
µPD78070AY
Figure 5-11. Serial Interface Channel Block Diagram
Internal
Selector
SI0/SB0/SDA0/P25
Serial Shift Register (SIO0)
Output Latch
SO0/SB1/SDA1/P26
Selector
Start Condition/ Stop Condition/ Acknowledge detector Interrupt Request Signal Generator
Acknowledge Output Circuit
SCK0/SCL/P27
Serial Clock Counter
INTCSI0
Serial Clock Control Circuit
Selector
fXX/2 fXX/28
Figure 5-12. Serial Interface Channel Block Diagram
Internal
Automatic Data Transmit/ Receive Address Pointer (ADTP)
Buffer
Automatic Data Transmit/Receive Interval Specification Register (ADTI)
SI1/P20
Serial Shift Register (SIO1)
Match
SO1/P21 5-Bit Counter STB/P23 Handshake Control Circuit
BUSY/P24
SCK1/P22
Serial Clock Counter
Interrupt Request Signal Generator
INTCSI1
Serial Clock Control Circuit
Selector
fXX/2 fXX/28
µPD78070AY
Figure 5-13. Serial Interface Channel Block Diagram
Internal
Receive Buffer Register (RXB/SIO2)
Direction Control Circuit
Direction Control Circuit
Transmit Shift Register (TXS/SIO2)
RXD/SI2/P70 TXD/SO2/P71
Receive Shift Register (RXS)
Transmit Control Circuit
INTST
Receive Control Circuit
INTSER INTSR/INTCSI2 Output Control Circuit
ASCK/SCK2/P72
Baud Rate Generator
fXX/210
Real-Time Output Port
Data previously real-time output buffer transferred output latch hardware concurrently with timer interrupt external interrupt generation order output off-chip. This real-time output function. Pins used output off-chip called real-time output ports. using real-time output port, signal which jitter output. This most applicable control stepping motors, etc. Figure 5-14. Real-Time Output Port Block Diagram
Internal
INTP2 INTTM1 INTTM2
Output Trigger Control Circuit
Real-Time Output Buffer Register Higher Bits (RTBH)
Real-Time Output Buffer Register Lower Bits (RTBL) Real-Time Output Port Mode Register (RTPM)
Output Latch
P127
P120
µPD78070AY
INTERRUPT FUNCTIONS TEST FUNCTION
Interrupt Functions total interrupt soources provided, divided into following three types. Non-maskable Maskable Software
µPD78070AY
Table 6-1. List Interrupt Sources
Interrupt Type Nonmaskable Maskable
DefaultNote1 Priority
Interrupt Source Name INTWDT INTWDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSI0 INTCSI1 INTSER INTSR INTCSI2 Completion serial interface channel transfer Completion serial interface channel transfer Occurrence serial interface channel UART reception error Completion serial interface channel UART reception Completion serial interface channel 3-wire transfer Completion serial interface channel UART transmission Reference time interval signal from watch timer Generation matching signal 16-bit timer register capture/compare register (CR00) Generation matching signal 16-bit timer register capture/compare register (CR01) Generation matching signal 8-bit timer/event counter Generation matching signal 8-bit timer/event counter Completion conversion Generation matching signal 8-bit timer/event counter Generation matching signal 8-bit timer/event counter Execution instruction Trigger Overflow watchdog timer (When watchdog timer mode selected) Overflow watchdog timer (When interval timer mode selected) input edge detection Internal/ External
Vector
Basic
Table Structure Address TypeNote2
Internal 0004H
External 0006H 0008H 000AH 000CH 000EH 0010H 0012H Internal 0014H 0016H 0018H 001AH
Software
INTST INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD INTTM5 INTTM6
001CH 001EH 0020H 0022H 0024H 0026H 0028H 002AH 002CH 003EH
Notes Default priority priority order when several maskable interrupt requests generated same time. highest priority lowest priority. Basic structure types correspond Figure 6-1.
µPD78070AY
Figure 6-1. Basic Configuration Interrupt Function (1/2) Internal non-maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Internal maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
External maskable interrupt (INTP0)
Internal
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
Interrupt Request
Sampling Clock
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
µPD78070AY
Figure 6-1. Basic Configuration Interrupt Function (2/2) External maskable interrupt (except INTP0)
Internal
External Interrupt Mode Register (INTM0, INTM1)
Interrupt Request
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Software interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
µPD78070AY
Test Function
Table shows test function available. Table 6-2. Test Input Source
Test Input Source Name INTWT Trigger Overflow watch timer
Internal/ External Internal
Figure 6-2. Basic Configuration Test Function
Internal
Test Input Signal
Standby Release Signal
Test input flag Test mask flag
µPD78070AY
EXTERNAL DEVICE EXPANSION FUNCTIONS
external device expansion functions connect external devices areas other than SFR.
µPD78070AY ROM-less product, therefore requires connection external ROM. Connect external
devices using independent address data bus.
STANDBY FUNCTION
standby function designed reduce current consumption. following modes:
HALT mode this mode, operation clock stopped. average current consumption reduced intermittent operation combining this mode with normal operation mode. STOP mode this mode, oscillation main system clock stopped. operations performed main system clock suspended, only subsystem clock used extremely small power consumption. Figure 8-1. Standby Function
Main system clock operation STOP instruction Interrupt request STOP mode (Oscillation main system clock stopped.) Interrupt request HALT mode (Supply clock stopped although clock generated.) HALT instruction Interrupt request HALT modeNote (Supply clock stopped although clock generated.) HALT instruction Subsystem clock operationNote
Note Current consumption reduced shutting main system clock. operating subsystem clock, shut main system clock setting (MCC) processor clock control register (PCC). cannot STOP instruction. Caution When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock.
RESET FUNCTION
There following reset methods. External reset input RESET Internal reset watchdog timer runaway time detection
µPD78070AY
INSTRUCTION
8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Operand
#byte
rNote
saddr
!addr16
[DE]
[HL]
byte] $addr16
None
Operand
ADDC SUBC
ADDC SUBC ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
RORC ROLC
saddr ADDC SUBC
DBNZ
DBNZ
!addr16 [DE]
PUSH
Note Except
µPD78070AY
Operand
#byte
saddr
!addr16
[DE]
[HL]
byte] $addr16
None
Operand
[HL] byte]
ROR4 ROL4
MULU DIVUW
16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Operand Operand #word ADDW SUBW CMPW sfrp saddrp !addr16 MOVW MOVW MOVW MOVW MOVWNote MOVW MOVW MOVW MOVW INCW, DECW PUSH, Note MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW MOVW None
Note Only when
µPD78070AY
manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
Operand Operand A.bit A.bit sfr.bit saddr.bit PSW.bit [HL].bit MOV1 $addr16 BTCLR BTCLR saddr.bit MOV1 BTCLR BTCLR BTCLR MOV1 AND1 XOR1 MOV1 AND1 XOR1 MOV1 AND1 XOR1 MOV1 AND1 XOR1 MOV1 AND1 XOR1 SET1 CLR1 NOT1 SET1 CLR1 SET1 CLR1 SET1 CLR1 None SET1 CLR1 SET1 CLR1
sfr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
Call instruction/Branch instructions CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DBNZ
Operand Operand Basic instruction !addr16 CALL !addr11 CALLF [addr5] CALLT $addr16 BNC, BTCLR DBNZ
Compound instruction
Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT, STOP
µPD78070AY
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS 25°C)
Parameter Supply voltage Symbol AVDD AVREF0 AVREF1 AVSS Input voltage P07, P17, P27, P37, P66, P72, P96, P100 P103, P120 P127, P130, P131, AD7, XT2, RESET P63, N-ch open-drain Test Conditions Ratings -0.3 +7.0 -0.3 -0.3 -0.3 -0.3 +0.3 -0.3 Unit
Output voltage Analog input voltage Output current, high
-0.3 -0.3
Analog input pins
AVSS AVREF0 +150
Total P37, P63, P66, P96, P100 P103, P120 P127, A14, A15, ASTB Total P06, P17, P27, P72, P130, P131, AD7, Output current, Note Peak value r.m.s. value Total Peak value r.m.s. value Total P63, A14, Peak value r.m.s. value Total P37, P66, P96, P100 P103, P120 P127, ASTB Total P27, AD7, Total P06, P17, P72, P130, P131 Operating ambient temperature Storage temperature Tstg Peak value r.m.s. value Peak value r.m.s. value Peak value r.m.s. value
Note r.m.s. value should calculated follows: [r.m.s. value] [Peak value] Duty Caution Exposure Absolute Maximum Ratings extended periods affect device reliability; exceeding ratings could cause permanent damage. parameters apply independently. device should operated within limits specified under Characteristics. Remark Unless otherwise specified, dual-function characteristics same port characteristics.
µPD78070AY
CAPACITANCE 25°C,
Parameter Input capacitance Symbol Test Conditions MHz, Unmeasured pins returned MIN. TYP. MAX. Unit
Output capacitance COUT capacitance
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS
Resonator Ceramic resonator Recommended Circuit
Parameter Oscillation frequency Note Oscillation stabilization time Note Oscillation frequency Note Oscillation stabilization time Note
Test Conditions Oscillation voltage range After came MIN. oscillation voltage range
MIN.
TYP.
MAX.
Unit
Crystal resonator
External clock
input frequency Note input high- low-level widths
PD74HCU04
Notes Only oscillator characteristics shown. instruction execution time, refer Characteristics. Time required oscillation stabilize after reset STOP mode been released. Cautions When using oscillation circuit main system clock, wire portion enclosed dotted lines figures follows avoid adverse influences wiring capacitance: Keep wiring length short possible. cross wiring over other signal lines. route wiring vicinity lines through which high fluctuating current flows. Always keep ground point capacitor oscillation circuit same potential connect power source ground pattern through which high current flows. extract signals from oscillation circuit. When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock.
µPD78070AY
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS +85°C,
Resonator Crystal resonator Recommended Circuit
Parameter Oscillation frequency Note Oscillation stabilization time Note
Test Conditions
MIN.
TYP. 32.768
MAX.
Unit
External clock
input frequency Note input high-, low-level widths (tXTH tXTL)
PD74HCU04
Notes Only oscillator characteristics shown. instruction execution time, refer Characteristics. Time required oscillation stabilize after reaches minimum value oscillation voltage range. Cautions When using oscillation circuit subsystem clock, wire portion enclosed dotted lines figures follows avoid adverse influences wiring capacitance: Keep wiring length short possible. cross wiring over other signal lines. route wiring vicinity lines through which high fluctuating current flows. Always keep ground point capacitor oscillation circuit same potential connect power source pattern through which high current flows. extract signals from oscillation circuit. amplification factor subsystem clock oscillator designed reduce current consumption therefore, subsystem clock oscillator influenced noise more easily than main system clock oscillator. When using subsystem clock, therefore, exercise utmost care wiring circuit.
µPD78070AY
CHARACTERISTICS +85°C,
Parameter Input voltage, high Symbol VIH1 Test Conditions P17, P21, P23, P32, P37, P66, P71, P96, P102, P103, P120 P127, P130, P131, P06, P20, P22, P27, P33, P34, P70, P72, P100, P101, RESET P63, (N-ch open-drain) XT1/P07, MIN. 0.7VDD TYP. MAX. Unit
VIH2 VIH3 VIH4 VIH5
0.8VDD 0.7VDD 0.8VDD 0.9VDD
0.3VDD
Input voltage,
VIL1
P17, P21, P23, P32, P37, P66, P71, P96, P102, P103, P120 P127, P130, P131, P06, P20, P22, P27, P33, P34, P70, P72, P100, P101, RESET P63, (N-ch open-drain) XT1/P07,
VIL2 VIL3
0.2VDD 0.3VDD 0.2VDD 0.2VDD 0.1VDD
VIL4 VIL5
Output voltage, high
-100
Output voltage,
VOL1
P06, P17, P27, P37, P66, P72, P96, P100 P103, P120 P127, P130, P131, AD7, A15, ASTB
VOL2
SB0, SB1, SCK0
Open-drain, pulled
0.2VDD
VOL3
Remark Unless otherwise specified, dual-function characteristics same port characteristics.
µPD78070AY
CHARACTERISTICS +85°C,
Parameter Input leakage current, high Symbol LIH1 Test Conditions P06, P17, P27, P37, P63, P66, P72, P96, P100 P103, P120 P127, P130, P131, AD7, RESET XT1/P07, P06, P17, P27, P37, P63, P66, P72, P96, P100 P103, P120 P127, P130, P131, AD7, RESET XT1/P07, VOUT VOUT MIN. TYP. MAX. Unit
LIH2 Input leakage current, LIL1
LIL2 Output leakage current, high Output leakage current, ILOL
Remark Unless otherwise specified, dual-function characteristics same port characteristics.
µPD78070AY
CHARACTERISTICS +85°C,
Parameter Software pull-up resistor Symbol Test Conditions P06, P17, P27, P37, P66, P72, P96, P100 P103, P120 P127, P130, P131 Supply currentNote 5.0-MHz crystal oscillation operating mode (fXX MHz)Note 5.0-MHz crystal oscillation operating mode (fXX MHz)Note 5.0-MHz crystal oscillation HALT mode (fXX MHz)Note 5.0-MHz crystal oscillation HALT mode (fXX MHz)Note ±10% Note ±10% Note ±10% Note ±10% Note ±10% Note ±10% Note ±10% Note ±10% Note 0.65 0.05 13.5 24.0 1.95 MIN. TYP. MAX. Unit
32.768-kHz crystal oscillation ±10% operating modeNote ±10% 32.768-kHz crystal oscillation ±10% operating modeNote ±10% STOP mode Feedback resistor used STOP mode Feedback resistor used ±10% ±10% ±10% ±10%
Notes Current flowing into pin. including current flowing into converter, converter, on-chip pull-up resistor. fX/2 operation (when oscillation mode selection register (OSMS) 00H). operation (when OSMS 01H). When main system clock stopped. High-speed mode operation (when processor clock control register (PCC) 00H). Low-speed mode operation (when 04H). Remarks Unless otherwise specified, dual-function characteristics same port characteristics. Main system clock frequency fX/2) Main system clock oscillation frequency
µPD78070AY
CHARACTERISTICS Basic Operation +85°C,
Parameter Cycle time (minimum instruction execution time) Symbol Operating main system clock Test Conditions
Note1
MIN.
TYP.
MAX.
Unit
Note2
2/fsam 2/fsam
Note Note
Operating subsystem clock TI00 input high-/lowlevel widths TI01 input high-/lowlevel widths TI1, TI2, TI5, input frequency TI1, TI2, TI5, input high-/low-level widths Interrupt request input high-/low-level widths tTIH00, tTIL00 tTIH01, tTIL01 fTI1
tTIH1 tTIL1 tINTH, tINTL
INTP0
2/fsam Note 2/fsam
Note
INTP1 INTP6 RESET low-level width tRSL
Notes When oscillation mode selection register (OSMS) When OSMS fsam selected fXX/2 /32, fXX/128 bits (SCS0, SCS1) sampling clock selection register. Remark Main system clock frequency fX/2) Main system clock oscillation frequency
µPD78070AY
(Main System Clock fX/2 Operation) (Main System Clock Operation)
Cycle Time
Operation Guaranteed Range
Cycle Time
Operation Guaranteed Range
Power Supply Voltage
Power Supply Voltage
µPD78070AY
Read/Write Operation When PCC2 PCC0 000B
Parameter ASTB high-level width Address setup time Address hold time Address Data input time Data input time Symbol ASTH ADD1 ADD2 RDD1 RDD2 Read data hold time low-level width RDL1 RDL2 WAIT input time WAIT input time WAIT low-level width Write data setup time Write data hold time low-level width ASTB delay time ASTB delay time external fetch ASTB delay time external fetch address hold time write data output time write data output time address hold time WAIT delay time WAIT delay time RDADH RDWD WRWD WRADH WTRD WTWR 0.85tCY 0.85tCY 1.15tCY 1.15tCY 1.15t 3.15t 3.15t 1.15t RDWT1 RDWT2 WRWT ASTRD ASTWR RDAST (1.15 (2.85 (2.85 0.85tCY 0.85tCY 1.15t (2.85 0.85t 2tCY 2tCY Test Conditions MIN. 0.85tCY 0.85tCY (2.85 (2.85 MAX. Unit
Remarks MCS: oscillation mode selection register (OSMS) PCC2 PCC0: processor clock control register (PCC) CY/4 indicates number waits.
µPD78070AY
Except When PCC2 PCC0 000B +85°C,
Parameter ASTB high-level width Address setup time Address hold time Address Data input time Data input time Symbol ASTH ADD1 ADD2 RDD1 RDD2 Read data hold time low-level width WAIT input time WAIT input time WAIT low-level width Write data setup time Write data hold time low-level width ASTB delay time ASTB delay time external fetch ASTB delay time external fetch address hold time write data output time write data output time address hold time WAIT delay time WAIT delay time RDWD WRWD WRADH WTRD WTWR 0.4t 0.6tCY 0.6tCY 2.6t 2.6t RDL1 RDL2 RDWT1 RDWT2 WRWT ASTRD ASTWR RDAST RDADH (2.4 (2.4 0.4t 1.4t (1.4 (2.4 2tCY 2tCY Test Conditions MIN. 0.4t (1.4 (2.4 MAX. Unit
Remarks
MCS: oscillation mode selection register (OSMS) PCC2-PCC0: processor clock control register (PCC) CY/4 indicates number waits.
µPD78070AY
Serial Interface Serial Interface Channel 3-wire serial mode (SCK0 internal clock output)
Parameter SCK0 cycle time Symbol KCY1 Test Conditions MIN. 1600 SCK0 high-/low-level width setup time SCK0 hold time (from SCK0 SCK0 output delay time KH1, SIK1 KCY1/2 KCY1/2 KSI1 KSO1
Note
TYP.
MAX.
Unit
Note SCK0, output line load capacitance. (ii) 3-wire serial mode (SCK0 external clock input)
Parameter SCK0 cycle time Symbol KCY2 Test Conditions MIN. 1600 SCK0 high-/low-level width setup time SCK0 hold time (from SCK0 SCK0 output delay time SCK0 rise, fall time KH2, SIK2 KSI2 KSO2 pFNote TYP. MAX. Unit
Note output line load capacitance.
µPD78070AY
(iii) 2-wire serial mode (SCK0 internal clock output)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width Symbol tKCY3 tKH3 tKL3 Test Conditions pFNote MIN. 1600 tKCY3/2 KCY3/2 tKCY3/2 SB0, setup time SCK0 SB0, hold time (from SCK0 SCK0 SB0, output delay time tKSO3 tSIK3 tKSI3 TYP. MAX. Unit
Note SCK0, SB0, output line load resistance load capacitance. (iv) 2-wire serial mode (SCK0 external clock input)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, setup time SCK0 SB0, hold time (from SCK0 SCK0 SB0, output delay time SCK0 rise, fall time tKSO4 pFNote Symbol tKCY4 tKH4 tKL4 tSIK4 tKSI4 Test Conditions MIN. 1600 KCY4/2 TYP. MAX. Unit
tR4,
Note SB0, output line load resistance load capacitance.
µPD78070AY
mode (SCL internal clock output)
Parameter cycle time high-level width low-level width Symbol KCY5 Test Conditions Note MIN. KCY5/2 KCY5/2 KCY5/2 SDA0, SDA1 setup time SDA0, SDA1 hold time (from SDA0, SDA1 output delay time SDA0, SDA1 SDA0, SDA1 SDA0, SDA1 SDA0, SDA1 high-level width SIK5 KSI5 KSO5 TYP. MAX. Unit
Note SCL, SDA0, SDA1 output line load resistance load capacitance. (vi) mode (SCL external clock input)
Parameter cycle time high-/low-level width SDA0, SDA1 setup time SDA0, SDA1 hold time (from SDA0, SDA1 output delay time SDA0, SDA1 SDA0, SDA1 SDA0, SDA1 SDA0, SDA1 high-level width rise, fall time Symbol KCY6 KH6, SIK6 KSI6 KSO6 pFNote 1000 Test Conditions MIN. 1000 TYP. MAX. Unit
Note SDA0, SDA1 output line load resistance load capacitance.
µPD78070AY
Serial Interface Channel 3-wire serial mode (SCK1 internal clock output)
Parameter SCK1 cycle time Symbol tKCY7 Test Conditions MIN. 1600 SCK1 high-/low-level width tKH7, tKL7 setup time SCK1 hold time (from SCK1 SCK1 output delay time tSIK7 KCY7/2 tKCY7/2 tKSI7 tKSO7 pFNote TYP. MAX. Unit
Note SCK1, output line load capacitance. (ii) 3-wire serial mode (SCK1 external clock input)
Parameter SCK1 cycle time Symbol KCY8 Test Conditions MIN. 1600 SCK1 high-/low-level width setup time SCK1 hold time (from SCK1 SCK1 output delay time SCK1 rise, fall time KH8, SIK8 KSI8 KSO8 pFNote TYP. MAX. Unit
Note output line load capacitance.
µPD78070AY
(iii) 3-wire serial mode with automatic transmission/reception function (SCK1 internal clock output)
Parameter SCK1 cycle time Symbol KCY9 Test Conditions MIN. 1600 SCK1 high-/low-level width setup time SCK1 hold time (from SCK1 SCK1 output delay time SCK1 Strobe signal high-level width KH9, SIK7 KCY9/2 KCY9/2 KSI7 KSO7
Note
TYP.
MAX.
Unit
KCY9/2 tKCY9 2tKCY9 KCY9/2 tKCY9
Busy signal setup time busy signal detection timing) Busy signal hold time (from busy signal detection timing) Busy inactive SCK1
Note SCK1, output line load capacitance. (iv) 3-wire serial mode with automatic transmission/reception function (SCK1 external clock input)
Parameter SCK1 cycle time Symbol KCY10 Test Conditions MIN. 1600 SCK1 high-/low-level width KH10 KL10 SIK10 KSI10 KSO10 R10, tF10 pFNote TYP. MAX. Unit
setup time SCK1 hold time (from SCK1 SCK1 output delay time SCK1 rise, fall time
Note output line load capacitance.
µPD78070AY
Serial Interface Channel 3-wire serial mode (SCK2 internal clock output)
Parameter SCK2 cycle time Symbol tKCY11 Test Conditions MIN. 1600 SCK2 high-/low-level width tKH11 tKL11 tSIK11 KCY11/2 KCY11/2 hold time (from SCK2 SCK2 output delay time tKSI11 tKSO11
Note
TYP.
MAX.
Unit
setup time SCK2
Note SCK2, output line load capacitance. (ii) 3-wire serial mode (SCK2 external clock input)
Parameter SCK2 cycle time Symbol tKCY12 Test Conditions MIN. 1600 SCK2 high-/low-level width setup time SCK2 hold time (from SCK2 SCK2 output delay time SCK2 rise, fall time tKH12 tKL12 tSIK12 tKSI12 tKSO12 tR12,
Note
TYP.
MAX.
Unit
Note output line load capacitance.
µPD78070AY
(iii) UART mode (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Test Conditions MIN. TYP. MAX. 78125 39063 Unit
(iv) UART mode (External clock input)
Parameter ASCK cycle time Symbol tKCY13 Test Conditions MIN. 1600 ASCK high-/low-level width tKH13 tKL13 39063 19531 ASCK rise, fall time tR13, tF13 TYP. MAX. Unit
Transfer rate
µPD78070AY
Timing Test Point (Excluding Input)
Test Points
Clock Timing
1/fx VIH4 (MIN.) VIL4 (MAX.)
Input
1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.)
Input
Timing
tTIL00 ,tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1 tTIL1 tTIH1
TI1, TI2, TI5,
µPD78070AY
Read/Write Operation External fetch wait):
tADD1 Hi-Z
Address
tADS ASTB
Low-order 8-bit address
Instruction code
tASTH
tADH
tRDD1
tRDADH tRDAST
tASTRD tRDL1 tRDH
External fetch (wait insertion):
tADD1 tADS tASTH ASTB
Low-order 8-bit address
Address
Hi-Z tRDD1
Instruction code
tADH
tRDADH tRDAST
tASTRD WAIT tRDWT1 tWTL tWTRD tRDL1 tRDH
µPD78070AY
External data access wait):
Low-order 8-bit address
Address tADD2 Hi-Z Hi-Z Hi-Z
tADS tASTH ASTB
Read Data tRDD2 tRDH
Write Data
tADH
tASTRD tASTWR tWRL tRDL2 tRDWD tWRWD tWDS tWDH tWRADH
External data access (wait insertion):
Low-order 8-bit address
Address tADD2 Hi-Z Hi-Z Hi-Z
tADS tASTH ASTB
Read Data tRDH
Write Data
tADH tRDD2 tASTRD
tRDL2 tASTWR WAIT tRDWT2 tWTL tWTRD
tRDWD tWRWD
tWDS
tWDH tWRADH
tWRL tWTL tWRWT tWTWR
µPD78070AY
Serial Transfer Timing 3-wire serial mode:
tKCYm tKLm SCK0 SCK2 tKHm
tSIKm
tKSIm
tKSOm
Input Data
Output Data
Remark 2-wire serial mode:
tKCY3, tKL3, SCK0 tKH3,
tKSO3,
tSIK3,
tKSI3,
SB0,
mode:
tKL5, SDA0, SDA1 tSBH tSBK tKH5, tKSI5, tSIK5, tKSO5, tKCY5, tKSB tSBK tKSB
µPD78070AY
3-wire serial mode with automatic transmission/reception function:
tSIK9, tKSO9,
tKSI9, tKH9,
tF10 SCK1 tKL9, tKCY9, tR10 tSBD tSBW
3-wire serial mode with automatic transmission/reception function (busy processing):
SCK1
9Note
10Note tBYS
10+nNote tBYH tSPS
BUSY (Active high)
Note signal actually here, represented this show timing. UART mode (external clock input):
tKCY13 tKL13 tR13 ASCK tKH13 tF13
µPD78070AY
CONVERTER CHARACTERISTICS +85°C, AVDD
Parameter Resolution Total error
Note
Symbol
Test Conditions AVREF0 AVDD
MIN.
TYP.
MAX.
Unit
Conversion time Sampling time Analog input voltage Reference voltage AVREF0-AVSS resistance
tCONV tSAMP VIAN AVREF0 RAIREF0
19.1 12/fXX AVSS
AVREF0 AVDD
Note Excluding quantization error (±1/2 LSB). Shown percentage full scale value. Remark Main system clock frequency fx/2) Main system clock oscillation frequency CONVERTER CHARACTERISTICS +85°C,
Parameter Resolution Total error MNote
Note Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Settling time
pFNote
AVREF1 AVREF1
Output resistor Analog reference voltage AVREF0-AVSS resistance
AVREF1 RAIREF1
Note
DACS0, DACS1 Note
Notes converter output load resistance load capacitance. Value converter channel. Remark DACS0, DACS1: conversion value setting registers
µPD78070AY
DATA MEMORY STOP MODE SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS +85°C)
Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR VDDDR When subsystem clock stopped feedback resistor disconnected Release RESET Release interrupt request 217/fX Note Test Conditions MIN. TYP. MAX. Unit
Release signal setup time Oscillation stabilization wait time
tSREL tWAIT
Note 212/fXX 214/f 17/fXX selected (OSTS0 OSTS2) oscillation stabilization time selection register (OSTS). Remark fXX: Main system clock frequency X/2) Main system clock oscillation frequency Data Retention Timing (STOP mode released RESET)
Internal reset operation HALT mode STOP mode Data retention mode VDDDR STOP instruction execution RESET tSREL Operating mode
tWAIT
Data Retention Timing (Standby release signal: STOP mode released interrupt signal)
HALT mode STOP mode Data retention mode VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT Operating mode
µPD78070AY
Interrupt Request Input Timing
tINTL INTP0 INTP6 tINTH
RESET Input Timing
tRSL
RESET
µPD78070AY
PACKAGE DRAWINGS
PLASTIC (FINE PITCH)
detail lead
NOTE
ITEM MILLIMETERS 16.0±0.2 14.0±0.2 14.0±0.2 16.0±0.2 0.22 +0.05 -0.04 0.10 (T.P.) 1.0±0.2 0.5±0.2 0.17 +0.03 -0.07 0.10 1.45 0.125±0.075 5°±5° MAX. INCHES 0.630±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.630±0.008 0.039 0.039 0.009±0.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.004 0.057 0.005±0.003 5°±5° 0.067 MAX. P100GC-50-7EA-2
Each lead centerline located within 0.10 (0.004 inch) true position (T.P.) maximum material condition.
Remark shape material versions same those mass-produced versions.
µPD78070AY
PLASTIC LQFP (FINE PITCH)
detail lead
NOTE Each lead centerline located within 0.08 (0.003 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 16.00±0.20 14.00±0.20 14.00±0.20 16.00±0.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.00±0.20 0.50±0.20 0.17 +0.03 -0.07 0.08 1.40±0.05 0.10±0.05 1.60 MAX. INCHES 0.630±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.630±0.008 0.039 0.039 0.009±0.002 0.003 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.003 0.055±0.002 0.004±0.002 0.063 MAX. S100GC-50-8EU
µPD78070AY
PLASTIC
detail lead
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition. ITEM
P100GF-65-3BA1-2 MILLIMETERS 23.6 20.0 14.0 17.6 0.30 0.10 0.15 0.65 (T.P.) 0.15+0.10 -0.05 0.10 MAX. INCHES 0.929 0.016 0.795 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.031 0.024 0.012+0.004 -0.005 0.006 0.026 (T.P.) 0.071+0.008 -0.009 0.031+0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
Remark shape material versions same those mass-produced versions.
5°±5°
µPD78070AY
RECOMMENDED SOLDERING CONDITIONS
recommended that µPD78070AY soldered under following conditions. details recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended, please contact your sales representative. Table 13-1. Soldering Conditions Surface Mount Devices PD78070AYGC-7EA: 100-pin plastic (Fine pitch) resin thickness 1.45
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Reflow time: seconds less 210°C higher), Number reflow processes: less, Exposure limit: daysNote hours pre-baking required 125°C afterwards) Package peak temperature: 215°C, Reflow time: seconds less 200°C higher), Number reflow processes: less, Exposure limit: daysNote hours pre-baking required 125°C afterwards) Partial heating temperature: 300°C below, Flow time: seconds less (per device side) Symbol IR35-107-2
VP15-107-2
Note Exposure limit before soldering after pack package opened. Storage conditions: 25°C relative humidity less. µPD78070AYGF-3BA: 100-pin plastic resin thickness
Soldering Method Infrared reflow Wave soldering Soldering Conditions Package peak temperature: 235°C, Reflow time: seconds less 210°C higher), Number reflow processes: less Package peak temperature: 215°C, Reflow time: seconds less 200°C higher), Number reflow processes: less Solder temperature: 260°C below, Flow time: seconds less, Number flow processes: Preheating temperature: 120°C max. (package surface temperature) Partial heating temperature: 300°C below, Flow time: seconds less (per device side) Symbol IR35-00-3 VP15-00-3 WS60-00-1
Cautions
different soldering methods together (except partial heating method). Since µPD78070AYGC-8EU under planning, soldering conditions determined.
µPD78070AY
APPENDIX DEVELOPMENT TOOLS
following dvelopment tools available support development systems using PD78070AY. Language Processing Software
RA78K/0Notes CC78K/0
Notes
Assembler package common 78K/0 Series compiler package common 78K/0 Series Device file common µPD78078 Subseries compiler library source file common 78K/0 Series
DF78078Notes CC78K/0-L
Notes
Debugging Tools
IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78078-R-EM EP-78064GC-R EP-78064GF-R TGC-100SDW In-circuit emulator common 78K/0 Series In-circuit emulator common 78K/0 Series (for Integrated debugger) Break board common 78K/0 Series Emulation board common µPD78078 Subseries Emulation probe common µPD78064 Subseries Adapter mounted target system board prepared 100-pin plastic (GC-7EA, GC-8EU type) Manufactured TOKYO ELETECH Corporation Contact representative purchase. EV-9200GF-100 SM78K0Notes ID78K0
Notes Notes
Socket mounted target system board prepared 100-pin plastic (GF-3BA type) System simulator common 78K/0 Series Integrated debugger IE-78000-R-A Screen debugger IE-78000-R Device file common µPD78078 Subseries
SD78K/0
DF78078Notes
Real-Time
RX78K/0Notes MX78K0Notes Real-time used 78K/0 Series used 78K/0 Series
µPD78070AY
Fuzzy Inference Development Support System
FE9000 Note 1/FE9200Note FT9080 FI78K0
Note
Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
/FT9085
Note
Notes
FD78K0Notes
Notes Based PC-9800 Series (MS-DOSTM) Based PC/ATand compatibles DOS/IBM DOSTM/MS-DOS) Based HP9000 Series 300(HP-UXTM) Based HP9000 Series 700(HP-UX), SPARCstation(SunOS), EWS4800 Series (EWS-UX/V) Based PC-9800 Series (MS-DOS WindowsTM) Based PC/AT compatibles DOS/IBM DOS/MS-DOS Windows) Based NEWS(NEWS-OSTM) Remarks Please refer 78K/0 Series Selection Guide (U11126E) information third party development tools. RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, RX78K/0 combination with DF78078.
µPD78070AY
APPENDIX RELATED DOCUMENTS
Documents Related Devices
Document Name Document Japanese English U10200E This document U10605E U12326E
µPD78070A, 78070AY User's Manual µPD78070AY Data Sheet µPD78P078Y Data Sheet
78K/0 Series User's Manual-Instructions 78K/0 Series Instruction Table 78K/0 Series Instruction
IEU-907 U10542J U10605J U12326J U10903J U10904J U10134J
µPD78070AY Special Function Register Table
Documents Related Development Tools (1/2)
Document Name Document Japanese RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package Operation Assembly language Structured assembly language CC78K Series Compiler Operation Language CC78K0 Compiler Operation Language CC78K/0 Compiler Application Note CC78K Series Library Source File IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78078-R-EM EP-78064 Programming know-how EEU-809 EEU-815 EEU-817 U11802J U11801J U11789J EEU-656 EEU-655 U11517J U11518J EEA-618 U12322J EEU-810 U10057J EEU-867 EEU-978 EEU-934 English EEU-1399 EEU-1404 EEU-1402 U11802E U11801E U11789E EEU-1280 EEU-1284 U11517E U11518E EEA-1208 EEU-1398 U10057E EEU-1427 EEU-1504 EEU-1522
Caution
contents documents listed above subject change without prior notice. sure latest edition when starting design.
µPD78070AY
Documents Related Development Tools (2/2)
Document Name Document Japanese SM78K0 System Simulator Windows Based SM78K Series System Simulator ID78K0 Integrated Debugger Based ID78K0 Integrated Debugger Based ID78K0 Integrated Debugger Windows Based SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based SD78K/0 Screen Debugger PC/AT DOS) Based Reference External parts user open interface specification Reference Reference Guide Introduction Reference Introduction Reference U10181J U10092J U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J English U10181E U10092E U11539E U11649E U10539E EEU-1414 U11279E
Documents Related Embedded Software (User's Manual)
Document Name Document Japanese 78K/0 Series Real-time Basic Installation 78K/0 Series MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger Basic U11537J U11536J U12257J EEU-829 EEU-862 EEU-858 EEU-921 English EEU-1438 EEU-1444 EEU-1441 EEU-1458
Other Documents
Document Name Document Japanese Package Manual Semiconductor Device Mounting Technology Manual Semiconductor Device Quality Grades Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Semiconductor Device Quality Assurance Guide Microcontroller-Related Product Guide Third Party Products C10943X C10535J C10531J C10983J MEM-539 C11893J U11416J C10535E C10531E C10983E MEI-1202 English
Caution
contents documents listed above subject change without prior notice. sure latest edition when starting design.
µPD78070AY
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78070AY
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290
Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics Taiwan Ltd. Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96.
µPD78070AY
Note: Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
IEBus trademarks Corporation. MS-DOS Windows either registered trademarks trademarks Microsoft Corporation United States and/or other countries. DOS, PC/AT trademarks International Business Machines Corporation. HP9000 series 300, HP9000 series 700, HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks SONY CORPORATION. related documents indicated this publication include preliminary versions. However, preliminary versions marked such. part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

µPD78070AY 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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