Integrated High Speed ADC/Quad System AD7339 DVDD1 ADCPDB ADCCLK

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Integrated High Speed ADC/Quad System AD7339 DVDD1 ADCPDB ADCCLK

Datasheet Thumbnail

Top Searches for this datasheet

FEATURES 8-Bit Converter 8-Bit Converters 8-Bit Serial Converters Single Supply Operation On-Chip Reference Power-Down Mode 52-Lead PQFP Package
Integrated High Speed ADC/Quad System AD7339
DVDD1 ADCPDB ADCCLK DACCLK DACPDB SDATA SCLK SERIAL CONTROL LOGIC REGISTER REGISTER SERIAL SERIAL REGISTER PARALLEL DACB REGISTER PARALLEL DGND1 AGND1
DACA
SDAC0F SDAC0S SDAC1F SDAC1S VREF
LATCH SDACPDB
GENERAL DESCRIPTION
2.5V REFERENCE AVDD
AD7339 composite that contains both functions. device includes 8-bit parallel A-to-D converter. 8-bit parallel DACs also included serial control DACs. These serial DACs 8-bit DACs. AD7339, which operates with single power supply, bandgap reference board with nominal value reduce power consumption part, each section, except reference, individually powered down when use. AD7339 available 52-lead PQFP package.
VREFA
AD7339
VREFB
DVDD2
DVDD3
DGND2
DGND3
AGND2
AGND3
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1997
DVDD AD7339-SPECIFICATIONS1 (AVDDnoted) wise
Parameter Resolution Differential Nonlinearity Integral Nonlinearity Zero Input Offset Error Signal Range Version Units Bits
10%, AGND DGND TMIN TMAX, unless otherTest Conditions/Comments ADCCLK 2.048 Bits Monotonic
input must biased about Therefore, coupling with capacitor needed bias voltage does equal input should driven with maximum source impedance
Full Power Input Bandwidth Conversion Rate Signal (Noise Distortion) Effective Bits (ENOB) Intermodulation Distortion Error Rate Input Capacitance Coding PARALLEL DACS Resolution Differential Nonlinearity Integral Nonlinearity Output Signal Range VSWING VBIAS Update Rate Bipolar Zero Offset Error Gain Error Output Harmonic Content Band 1.152 Gain Matching Between DACs Crosstalk Channel from Channel Channel from Channel VREFB from Channel VREFA from Channel Load Resistance Load Capacitance Full-Scale Settling Time Coding SERIAL DACS Resolution Differential Nonlinearity Integral Nonlinearity Output Range Update Rate Load Resistance Load Capacitance ISINK ISOURCE Full-Scale Settling Time Coding
1.024 2.048 42.7 1011 Offset Binary VBIAS VSWING 14/25 VREFA/B VREFA/B 2.304
MSPS Bits
Terminology
with DACCLK 2.304 Bits Bits Monotonic
VREFA/B means VREFA DACA VREFB DACB.
Factory Trim. Does Include Gain Error Full-Scale Digital Sine Wave Band 76.8 Full-Scale Digital Sine Wave Band Amplitudes Which Equal Full Scale Load Between DACA VREFA, Between DACB VREFB Channel full-scale output frequency kHz. Channel full-scale output frequency kHz. Channel full-scale output frequency kHz. Channel full-scale output frequency kHz. Connected Between DACA/B VREFA/B
Offset Binary AVDD 0.247 SCLK/10 Straight Binary
with Bias Voltage SCLK gated clock. Bits Bits Monotonic With Respect Full Scale Figure When AVDD 5.247 analog output will equal VREF.
REV.
AD7339
Parameter Version Units Test Conditions/Comments
REFERENCE VREF Voltage VREFA/VREFB Voltage Load Capacitance ISINK ISOURCE LOGIC INPUTS VINH, Input High Voltage VINL, Input Voltage IINH, Input Leakage Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Voltage COUT, Output Capacitance POWER SUPPLIES AVDD, DVDD Power-Down Current
DVDD DVDD 4.5/5.5
min/max min/max Each reference output must have load capacitance minimum compensation purposes. |IOUT| |IOUT|
min/max Active Mode +25°C. Load VREF -40°C +85°C. Load VREF
NOTES Operating temperature range follows: Version; -40°C +85°C. Specifications subject change without notice.
2VREF +5.5V POWER SUPPLY OUTPUT VOLTAGE Volts 4.753 POWER SUPPLY
4.253 +4.5V POWER SUPPLY
ANALOG OUTPUT VOLTAGE
Figure Analog Output Voltage from Serial DACs Power Supply
REV.
AD7339 TIMING CHARACTERISTICS
Parameter PARALLEL DACS SERIAL DACS
(AVDD
Units
10%; AGND DGND TMlN TMAX, unless otherwise noted)
Description Figure ADCCLK Period ADCCLK Width ADCCLK Width High Data Valid After Falling Edge ADCCLK Data Valid Before Subsequent Falling Edge ADCCLK Figure DACCLK Period DACCLK Width DACCLK Width High Data Setup Before DACCLK Rising Edge Time Data Hold After DACCLK Rising Edge Time Propagation Delay Settling Time (from 90%) Figure SCLK Period SCLK Width SCLK Width High Data Setup Before SCLK Rising Edge Latch Enable Setup Time After SCLK Falling Edge LATCH Pulsewidth Conversion Delay
Limit 1.94 1.94
OUTPUT
+2.1V 15pF
Figure Load Circuit Timing Specifications
REV.
AD7339
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
ADCCLK
Figure Timing
DACCLK
DATA DATA
DACA DACB
Figure Parallel DACs Timing
SCLK
D9(MSB)
SDATA
LATCH
SDAC0S SDAC1S
Figure Serial DACs Timing
REV.
AD7339
ABSOLUTE MAXIMUM RATINGS
+25°C unless otherwise noted)
AVDD, DVDD -0.3 AGND DGND -0.3 +0.3 Digital Voltage DGND -0.3 Analog Input Voltage Input/Output Current Except Supplies2 Operating Temperature Range Industrial Version) -40°C +85°C Storage Temperature Range -65°C +150°C Maximum Junction Temperature +150°C PQFP, Thermal Impedance 90°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared sec) +220°C
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Transient currents will cause latchup.
ORDERING GUIDE
Model AD7339BS
Temperature Range -40°C +85°C
Package Description Plastic Quad Flatpack (PQFP)
Package Option S-52
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this device features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD7339
CONFIGURATION
VREFA VREFB DACA DACB SDAC1S
IDENTIFIER
DACCLK DVDD1 DACPDB DGND1 SDACPDB
SDAC1F SDAC0S SDAC0F AGND1 VREF AGND3 AVDD AGND2 ADCPDB DVDD3 DGND3 ADCCLK
AD7339
VIEW (Not Scale)
SCLK
SDATA
FUNCTION DESCRIPTIONS
Number Power Supply ADCs 26-23, 20-17 Parallel DACs 45-52 3-10
Mnemonic AVDD DVDD1 DGND1 AGND1 DVDD2 DVDD3 DGND2 DGND3 AGND2 AGND3 ADCCLK D0-D7 ADCPDB
Function Analog power supply connection. Digital power supply parallel DACs. Digital ground connection parallel DACs. Analog ground connection parallel DACs. Digital power supply ADC. Digital power supply ADC. Digital ground connection ADC. Digital ground connection ADC. Analog ground connection ADC. Analog ground connection reference. Analog input ADC. analog input must appropriately coupled. AD7339 accept analog input maximum. Input Clock, CMOS Logic Input. analog input sampled rising edge ADCCLK. ADCCLK nominally 2.048 MHz. Digital Output from ADC. 8-bit digital word from offset binary. digital output uses CMOS logic. Digital Input. When ADCPDB low, powered down. While this mode, ADCCLK should tied low. powered taking ADCPDB high. Digital input parallel DAC. digital input uses CMOS logic word presented offset binary format. Digital input parallel DAC. digital input uses CMOS logic word presented offset binary format. Input clock parallel DACs. digital words registers loaded into DACs rising edge DACCLK. DACCLK nominal frequency 2.304 uses CMOS logic. Analog outputs from DACs. Both DACs have analog output VREFA/ VREFB volts where VREFA VREFB nominal
DA0-DA7 DB0-DB7 DACCLK
DACA, DACB
REV.
DGND2
LATCH
DVDD2
AD7339
Number Mnemonic DACPDB Function Digital Input. parallel DACs, VREFA VREFB, powered down using DACPDB. When DACPDB low, both parallel DACs VREFA/VREFB outputs placed standby mode, drawing minimal current. reference, which available VREF pin, powered down. Serial Input Data. Serial data latched into AD7339 registers rising edge SCLK. digital data uses CMOS logic. Data loaded into latches 10-bit bursts (MSB first), MSBs word indicating which digital word being loaded while LSBs contain digital word being loaded into DAC. serial DACs offset binary. Serial Input Clock. Data latched into registers rising edge SCLK, which nominally kHz. SCLK gated clock-the clock should active only when data being loaded into latches. clock should idle between conversions. Latch Enable Input. LATCH used load digital data from latch into begin conversion. Both DACs loaded with digital data their respective latches. LATCH pulsed high load DACs, DACs being loaded rising edge LATCH. Analog Output from Serial DAC0. analog output from this will have value AVDD 0.247 Feedback Analog Input. connecting resistor between SDAC0F SDAC0S, gain DAC0 buffer altered magnitude analog output adjusted accordingly. Analog Output from Serial DAC1. analog output from this will have value AVDD 0.247 Feedback Analog Input. connecting resistor between SDAC1F SDAC1S, gain DAC1 buffer altered magnitude analog output adjusted accordingly. Digital Input. serial DACs powered down using SDACPDB. When this tied low, serial DACs placed standby mode. onboard bandgap reference available VREF pin. reference value nominal. bypass capacitor required between VREF AGND. This output cannot powered down. buffered version reference available VREFA/VREFB. analog outputs from parallel DACs biased about reference voltage. DACA biased about VREFA while DACB biased about VREFB. VREFA VREFB used with DACA DACB provide differential analog inputs circuitry connected DACs. These outputs powered down using DACPDB. These outputs should decoupled using capacitance minimum.
Serial DACs
SDATA
SCLK
LATCH
SDAC0S SDAC0F
SDAC1S SDAC1F
Reference
SDACPDB
VREF
VREFA/VREFB
REV.
AD7339
FUNCTIONAL DESCRIPTION A-to-D Converter Parallel DACs
conversion circuitry consists track-and-hold amplifier followed flash A-to-D converter. Figure shows architecture ADC.
AD7339
HOLD COMPARATOR NETWORK DECODE LOGIC OUTPUT REGISTER OUTPUT DRIVERS
circuitry each parallel consists current source followed buffer that converts current voltage. Figure shows functional block diagram parallel DACs. loading both controlled DACCLK signal, which nominally 2.304 MHz. digital input each latched rising edge DACCLK signal that both DACs simultaneously perform D-to-A conversion.
AD7339
REGISTER DACA
REFERENCE
RESISTOR LADDER
TIMING CONTROL LOGIC
DACCLK REGISTER
DACB
ADCCLK ADCPDB
REFERENCE VREFA
Figure Architecture
Track-and-Hold Amplifier
track-and-hold amplifier analog input AD7339's allows accurately convert input frequencies 8-bit accuracy. input bandwidth track-and-hold amplifier much greater than Nyquist rate ADC. operation track-and-hold essentially transparent user. track-and-hold amplifier goes from tracking mode hold mode rising edge ADCCLK.
Analog Input
CONTROL LOGIC
VREFB
DACPDB
Figure Parallel DACs Functional Block Diagram
accepts analog input p-p. analog input biased about internally. signal applied biased about then coupling used. coupling needed analog input biased about voltage other than capacitor suitable coupling. Figure shows ideal input/output transfer function ADC. designed code transitions occur midway between successive integer values (1/2 LSB, LSB, with FS/256 V/256
OUTPUT CODE 11111111 11111110
analog output from each biased about reference voltage VREFA (DAC VREFB (DAC analog output about reference voltage. Since analog outputs biased about reference voltage, reference outputs used with analog outputs form differential signal circuitry that follows DACs. AD7339 includes calibration feature that reduces offset between output bias voltage VREFA/ VREFB voltage. 4-bit offset nulling feature used factory trim offset. device also 4-bit offset register that user controlled; i.e., user disable factory trimmed offset 4-bit register instead. This allows user calibrate system offset; however, user also responsible calibrating AD7339 offset. 4-bit offset register accessed serial interface that used Table gives addresses accessing these registers. 10-bit data word enables user write 4-bit offset register. When this factory trimmed value used offset value, while user programmed value used when equals When offset user controlled, used inform AD7339 reduce increase output voltage. When equals output reduced, while output increased when equals When user trimming being used, 4-bit word loaded into register contained LSBs 10-bit word being written serial port.
AD7339
10000010 10000001 10000000 01111111 01111110 1LSB
00000001 00000000 ANALOG INPUT VOLTAGE
Figure Transfer Function
REV.
AD7339
4-bit offset nulling feature size thereby, allowing user vary output
Table Writing Parallel DACs Offset Registers
Address Factory/ User Offset
Decr/ Incr
Data Word
8-bit word loaded into from register using LATCH. Data loaded into DACs falling edge LATCH. When D-to-A conversion performed, analog output altered accordingly. analog output will remain valid until next falling edge LATCH, which stage next digital word register converted. LATCH normally low, input being pulsed load DACs, DACs being loaded falling edge LATCH. analog output available SDAC0S/SDAC1S pin. Each analog output AVDD 0.247 input generating analog output while digital input produces analog output AVDD 0.247 i.e., serial DACs straight binary coding. analog output generated board reference. Therefore, when AVDD greater than 5.247 VOUT VREF when digital word equals However, when AVDD less than 5.247 output limited 0.247 below AVDD amplifier clips output. output from current source converted voltage using operational amplifier. amplifier configured gain signal two; however, gain amplifier adjusted tying resistor between SDAC0F/SDAC1F SDAC0S/SDAC1S. resistors board AD7339 have value
Power-Down
DACs offset binary coding with FS/256 2.8/256 10.94 Table shows ideal input code output voltage relationship.
Table Ideal Input/Output Code Table
Latch Contents Analog Output, VOUT* -1.4 -1.38906 -0.01094 +0.01094 +1.37812 +1.38906
00000000 00000001 01111111 10000000 10000001 11111110 11111111
Serial DACs
*These nominal output voltages with
AD7339 serial DACs board. serial DACs have architecture similar parallel DACs. 8-bit digital word each serially loaded. serial DACs have common serial port. distinguish between DACs, 10-bit bursts transferred DACs, MSBs identifying which 8-bit word loaded. Table shows truth table MSBs. serial word loaded into serial register using SDATA SCLK. SCLK gated clock nominal value kHz, which should active only when 10-bit word being loaded into register; i.e., SCLK should consist pulses. SCLK continuous, consists more than pulses, data shifted into serial register will shifted serial register register will contain valid data. When serial register being written SCLK should idle low. serial data bits read into serial register rising edge SCLK, MSBs word identifying which word being written, eight LSBs 10-bit word containing 8-bit word converted, 8-bit word being transferred first. SDATA idles low.
Table III. Serial DACs Truth Table
Each section AD7339 individually powered down. ADC, parallel DACs serial DACs have individual power-down pins, which allows each section powered down when being used, thus minimizing current consumption AD7339. ADCPDB used place sleep mode. When this taken low, powered down. normal operation, ADCPDB high. When parallel DACs being used, they placed power-down mode using DACPDB. When DACPDB low, both DACs powered down. reference outputs VREFA VREFB also powered down. During power-down, analog outputs DACA DACB, well reference outputs, pulled down ground. When DACs powered analog outputs settle bias voltage VREFA/VREFB. serial DACs powered down using SDACPDB. When this tied low, serial DACs placed sleep mode. When converter powered required analog digital circuitry settle. Conversions commence when circuitry settled. reference board AD7339 permanently powered While outputs VREFA VREFB powered down, reference voltage, which available VREF, always available.
Written Offset Register Loaded Register Loaded Register Loaded Offset Register Loaded
-10-
REV.
AD7339
TERMINOLOGY Differential Nonlinearity
difference between measured ideal change between adjacent codes DACs. specified Differential Nonlinearity over operating temperature range ensures monotonicity.
Integral Nonlinearity
maximum deviation code from straight line passing through endpoints transfer function. endpoints transfer function zero scale, point below first code transition (000 full scale, point above last code transition (111 11). error expressed LSBs.
Signal (Noise Distortion)
products, order difference frequencies nfb, where Intermodulation terms those which equal zero. AD7339, Intermodulation Distortion level which second third intermodulation terms suppressed below full scale output signal level, second order terms being while third order terms (2fa fb), (2fa fb), 2fb) 2fb).
Error Rate
rate which A-to-D conversion errors occur.
DACS Bipolar Zero Offset Error
Signal (Noise Distortion) measured signal-to-noise output ADC. signal magnitude fundamental. Noise nonfundamental signals half sampling frequency (FS/2) excluding Signal (Noise Distortion) dependent number quantization levels used digitization process; more levels, smaller quantization noise. theoretical signal (Noise Distortion) ratio sine wave signal given Signal (Noise Distortion) (6.02N 1.76) where number bits. Thus ideal 8-bit converter, Signal (Noise Distortion) 49.92
Effective Number Bits (ENOB)
deviation between measured output voltage bias voltage (VREFA VREFB, depending which being tested) when loaded with code after gain error been adjusted out.
Gain Error
measure output error between ideal actual device output with loaded after offset error been adjusted out.
Update Rate
rate which DACs loaded with data. parallel DACs have update rate 2.304 while serial DACs have update rate 256/10 maximum.
Gain Matching Between DACs
Signal (Noise Distortion) expressed dBs; rewriting Signal (Noise Distortion) formula, possible measure performance expressed effective number bits. effective number bits device calculated directly from measured Signal (Noise Distortion) value. ENOB (SNR 1.76)/6.02 where Signal (Noise Distortion).
Zero Input Offset Error
matching between analog output amplitudes parallel DACs when same digital word written each DAC.
Crosstalk
ratio amplitude full-scale signal appearing channel amplitude same signal which couples onto another channel. Crosstalk expressed dBs.
Output Harmonic Content
This offset error when analog input zero. Ideally, digital output should equal offset error deviation from ideal output code. offset error expressed LSBs.
Intermodulation Distortion
With inputs consisting sine waves frequencies, active device with nonlinearities will create distortion
When digital word converted analog form, harmonics will also generated. Output Harmonic Content specifies amount which these harmonics attenuated relative fundamental frequency. With parallel DACs, full sine wave frequency input. resulting analog output evaluated amount which harmonics frequency band 1.1152 attenuated measured relative magnitude fundamental output signal.
REV.
-11-
AD7339
GROUNDING LAYOUT
Digital analog ground planes should joined only place. AD7339 only device requiring AGND-toDGND connection, ground planes should connected AGND DGND pins AD7339. AD7339 system where multiple devices require AGND-to-DGND connections, connection should made point only, star point that should established close possible AD7339. Avoid running digital lines under device these will couple noise onto die. analog ground plane should allowed under AD7339 avoid noise coupling. power supply lines AD7339 should large track possible provide impedance paths reduce effects glitches power supply line. Fast switching signals such clocks should shielded with digital ground avoid radiating noise other sections board. Avoid
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
52-Lead Plastic Quad Flatpack (PQFP) (S-52)
0.094 (2.39) 0.084 (2.13) 0.037 (0.95) 0.026 (0.65) SEATING PLANE 0.557 (14.15) 0.537 (13.65) 0.398 (10.11) 0.390 (9.91)
VIEW
(PINS DOWN)
0.008 (0.20) 0.006 (0.15) 0.082 (2.09) 0.078 (1.97)
0.0256 (0.65)
0.014 (0.35) 0.010 (0.25)
-12-
REV.
PRINTED U.S.A.
0.012 (0.30) 0.006 (0.15)
0.398 (10.11) 0.390 (9.91) 0.557 (14.15) 0.537 (13.65)
C3049-8-10/97
printed circuit board that houses AD7339 should designed that analog digital sections separated confined certain areas board. This facilitates ground planes that easily separated. minimum etch technique generally best ground planes gives best shielding.
crossover digital analog signals. Traces opposite sides board should right angles each other. This will reduce effects feedthrough through board. microstrip technique best, always possible with double-sided board. this technique, component side board dedicated ground planes while signals placed other side. Good decoupling important. analog digital supplies AD7339 independent separately pinned minimize coupling between analog digital sections device. analog digital supplies should decoupled AGND DGND respectively using ceramic capacitors parallel with tantalum capacitors. achieve best from decoupling capacitors, they should placed close possible device, ideally right against device. systems where common supply used drive both AVDD DVDD AD7339, recommended that system's AVDD supply used. This supply should have recommended analog supply decoupling between AVDD pins AD7339 AGND recommended digital supply decoupling capacitors between DVDD pins DGND.

Integrated High Speed ADC/Quad System AD7339 DVDD1 ADCPDB ADCCLK

Top Searches for this datasheet

Other recent searches