Standard Definition Video Reconstruction Filters Buffers MAX7428/

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Standard Definition Video Reconstruction Filters Buffers MAX7428/

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19-2119; 9/02
Standard Definition Video Reconstruction Filters Buffers
MAX7428/MAX7430/MAX7432 filters low-cost, high-performance replacements standard discrete filter buffer solutions. MAX7428/MAX7430/ MAX7432 ideal anti-aliasing smoothing video applications, when analog video reconstructed from digital data stream. These devices require single supply filters have cutoff frequency optimized NTSC, PAL, standard definition digital (SDTV) video signals. MAX7428/MAX7430/ MAX7432 feature Maxim's Single (MSPBTM) interface digitally control channel selection (IN_A IN_B), adjust high-frequency boost, bypass filter, configure luma chroma operation, control output disable. MAX7428 single-channel filter ideal composite (CVBS) video signals. MAX7430 dual filter optimized S-Video (Y/C) applications. MAX7432 triple filter optimized component (YPbPr embedded synchronous RGB) video signals. MAX7428 available tiny 8-pin SOT23 package, MAX7430 available miniature 10-pin µMAX package, MAX7432 available 14-pin TSSOP package. MAX7428/MAX7430/MAX7432 fully specified over -40°C +85°C extended temperature range. 6th-Order Lowpass Filter Drives Video Loads Four Levels Passband High-Frequency Boost Control Input Multiplexer Output Disable Filter Bypassing Single-Supply Voltage Tiny 8-Pin SOT23 Package (MAX7428), 10-Pin µMAX Package (MAX7430), 14-Pin TSSOP Package (MAX7432)
Features
Ideal CVBS, (S-Video), Outputs NTSC, PAL, SDTV
MAX7428/MAX7430/MAX7432
Ordering Information
PART MAX7428EKA-T MAX7430EUB MAX7432EUD TEMP RANGE -40°C +85°C -40°C +85°C -40°C +85°C PINPACKAGE SOT23-8 µMAX TSSOP MARK AAIU
Applications
Set-Top Boxes Players Hard-Disk Recorders Camcorders
MSPB trademark Maxim Integrated Products, Inc. Configurations appear data sheet.
Functional Diagrams
SYNCIO SERIAL INTERFACE CONTROL DATA
SYNC
MAX7428
6TH-ORDER FILTER +6dB
ENCODER INPUT *OPTIONAL LEVEL SHIFT BIAS GENERATOR REXT
Functional Diagrams continued data sheet. Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
ABSOLUTE MAXIMUM RATINGS
.+6V Other Pins .-0.3V (VCC 0.3V) Maximum Current Into .±50mA Continuous Power Dissipation +70°C) 8-Pin SOT23 (derate 9.71mW/°C above +70°C).777mW 10-Pin µMAX (derate 6.94mW/°C above +70°C) .555.5mW 14-Pin TSSOP (derate 9.1mW/°C above +70°C) .727mW Operating Temperature Range .-40°C +85°C Storage Temperature Range .-65°C +150°C Junction Temperature .+150°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC ±10%, RREXT 300k ±1%, 0.1µF, CREXT (1nF 1µF) ±1%, CLOAD 20pF; BOOST0_, BOOST1_ TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Note
PARAMETER Passband Response Stopband Attenuation Boost Relative Step Size, Levels Differential Gain Differential Phase Harmonic Distortion Signal-to-Noise Ratio Group Delay Deviation Line-Time Distortion Field-Time Distortion Clamp Settling Time Output Clamp Level Low-Frequency Gain Group Delay Matching Low-Frequency Gain Matching Channel-to-Channel Crosstalk Output Short-Circuit Current Input Leakage Current Input Dynamic Swing Supply Range tg(MATCH) AV(MATCH) XTALK YINp-p CINp-p CLEVEL CLEVEL Hdist Vdist tclamp SYMBOL CONDITIONS 100kHz 4.2MHz relative 100kHz 100kHz 5MHz relative 100kHz 27MHz 4.2MHz 5MHz 5-step modulated staircase 5-step modulated staircase 100kHz 5MHz Peak signal (2Vp-p) noise, 100Hz 50MHz Deviation from 100kHz 3.58 (4.43)MHz 18µs, lines, 18µs, (Note CLEVEL CLEVEL Gain 100kHz frequency channel-to-channel matching 100kHz Channel-to-channel gain matching, 100kHz Channel-to-channel crosstalk, 100kHz 5.5MHz OUT_ shorted ground 1.35 1.975 1.85 2.05 -0.5 -1.0 +0.5 +1.0 UNITS degrees Lines Vp-p
Standard Definition Video Reconstruction Filters Buffers
ELECTRICAL CHARACTERISTICS (continued)
(VCC ±10%, RREXT 300k ±1%, 0.1µF, CREXT (1nF 1µF) ±1%, CLOAD 20pF; BOOST0_, BOOST1_ TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Note
PARAMETER Supply Current Power-Supply Rejection Ratio IN_A/IN_B Crosstalk LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Voltage Logic Input Current Logic Output High Voltage Logic Output Voltage IIH/IIL (source), (sink) I(SOURCE) 500µA I(SINK) 500µA SYMBOL PSRR load CONDITIONS MAX7428 MAX7430 MAX7432 100mVp-p, 5.5MHz 100mVp-p, 100kHz 5.5MHz UNITS
MAX7428/MAX7430/MAX7432
MSPB INTERFACE TIMING SPECIFICATIONS
(VCC ±10%, RREXT 300k ±1%, CREXT (1nF 1µF) ±1%, CLOAD 20pF, TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Figures through
PARAMETER MSPB TIMING Logic-Zero/Prompt Pulse Width Logic-One Pulse Width Transaction Pulse Width Separation Between Pulses Release Time Host After Prompt Pulse Reclaim Time Host After Prompt Pulse Read Back Data Valid Window After Prompt Pulse tWAIT tRELEASE tRECLAIM tREAD SYMBOL CONDITIONS UNITS
Note horizontal line 63.5µs. Note MAX7428 devices 100% production tested +25°C guaranteed design from TMIN TMAX.
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
Typical Operating Characteristics
(VCC +5V, RREXT 300k; BOOST0_, BOOST1_ VIN_ 1Vp-p, +25°C, unless otherwise noted.)
AMPLITUDE FREQUENCY
MAX7428/30/32 toc01
PASSBAND AMPLITUDE FREQUENCY
MAX7428/30/32 toc02
PHASE RESPONSE FREQUENCY
MAX7428/30/32 toc03
AMPLITUDE (dB)
AMPLITUDE (dB)
PHASE (DEGREES) -120 -180
BOOST1, BOOST0 BOOST1, BOOST0 BOOST1, BOOST0 BOOST1, BOOST0 FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
GROUP DELAY FREQUENCY
MAX7428/30/32 toc04
RESPONSE (1IRE 7.14mV)
MAX7428/30/32 toc05
MODULATED 12.5T RESPONSE (1IRE 7.14mV)
MAX7428/30/32 toc06
GROUP DELAY (ns) FREQUENCY (MHz)
INA_ 200mV/div
INA_ 200mV/div
OUT_ 200mV/div
OUT_ 200mV/div
200ns/div
400ns/div
SUPPLY CURRENT TEMPERATURE
MAX7428/30/32 toc07
DIFFERENTIAL GAIN
MAX7428/30/32 toc08
DIFFERENTIAL PHASE
-0.06 DIFFERENTIAL PHASE (DEGREES) 0.20 0.15 0.10 0.05 0.04 0.06 0.06 0.04 0.02
MAX7428/30/32 toc09
SUPPLY CURRENT (mA) LOAD
-0.01
-0.04
-0.08
-0.10
DIFFERENTIAL GAIN
-0.1 -0.2 -0.3
-0.05 1st. 2nd. 3rd. 4th. 5th. 6th. 1st. 2nd. 3rd. 4th. 5th. 6th.
TEMPERATURE (°C)
Standard Definition Video Reconstruction Filters Buffers
Typical Operating Characteristics (continued)
(VCC +5V, RREXT 300k; BOOST0_, BOOST1_ 1Vp-p, +25°C, unless otherwise noted.)
OUTPUT TRANSIENT INPUT SWITCHING
MAX7428/30/32 toc11
MAX7428/MAX7430/MAX7432
OUTPUT IMPEDANCE FREQUENCY
IMPEDANCE OUT_ 500mV/div
MAX7428/30/32 toc10
PASSBAND CHANNEL-TO-CHANNEL CROSSTALK FREQUENCY
MAX7428/30/32 toc12
CROSSTALK (dB)
BOOST CODE
FREQUENCY (MHz) 200ns/div
FREQUENCY (MHz)
Description
MAX7432 MAX7430 MAX7428 NAME IN1A IN2A IN3A IN1B IN2B IN3B DATA OUT3 OUT2 REXT FUNCTION Video Input Master channel, sync signal required. 0.1µF series input capacitor proper operation. Video Input Slave channel, clamping controlled master channel sync. 0.1µF series input capacitor proper operation. Video Input Slave channel, clamping controlled master channel sync. 0.1µF series input capacitor proper operation. Ground Video Input Master channel, sync signal required. 0.1µF series input capacitor proper operation. Video Input Slave channel, clamping controlled master channel sync. 0.1µF series input capacitor proper operation. Video Input Slave channel, clamping controlled master channel sync. 0.1µF series input capacitor proper operation. Serial Data Interface Buffer Output Buffer Output External Resistor. Connect 300k resistor from REXT internal biasing. Connect capacitor from REXT chip-address programming (see Table
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
Description (continued)
MAX7432 MAX7430 MAX7428 NAME OUT1 SYNCIO Buffer Output Supply Voltage Video Input 0.1µF series input capacitor proper operation. Video Input 0.1µF series input capacitor proper operation. Sync Pulse Input Output Buffer Output FUNCTION
**220µF
0.1µF **220µF
MAX7428
REXT DATA
300k
0.1µF ENCODER
SERIAL SYNC PULSE (SEE TABLE *NEEDED ONLY FILTER BYPASS MODE **OPTIONAL CAPACITOR ***ONLY PULLUP RESISTOR NEEDED
SYNCIO
Figure MAX7428 Typical Application Circuit
Detailed Description
MAX7428/MAX7430/MAX7432 filter buffer outputs encoder chipsets that process digital video information applications such set-top boxes, hard-disk recorders, players, recorders, digital VCRs. These devices also filter "clean-up" analog video signals. Each channel MAX7428/ MAX7430/MAX7432 includes input select input channel, 6th-order Sallen-Key filter with four adjustable high-frequency boost levels, output buffer with gain, sync detector clamp, external resistor internal bias levels. Output disable adds additional multiplexing wired-OR configuration. Filter bypass, conjunction with inputs, used provide filtered unfiltered video signal processing. Maxim's Single
(MSPB) interface controls above features. external capacitor used assign each device unique address that allows control devices same bus. Typical application circuits MAX7428/MAX7430/MAX7432 shown Figures
Input Considerations
0.1µF ceramic capacitor AC-couple input MAX7428/MAX7430/MAX7432. This input capacitor stores level level-shift input signal optimal point between GND. ABSEL Control Register sets which channel (IN_A IN_B) selected (Control Register section). IN_A IN_B inputs have typical input resistance 50k.
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
200µF**
0.1µF DATA 0.1µF ENCODER IN1B IN1A OUT1 SERIAL 200µF** 200µF**
MAX7430
0.1µF 300k 0.1µF ENCODER (SEE TABLE *NEEDED ONLY FILTER BYPASS MODE **OPTIONAL OUTPUT CAPACITOR ***ONLY PULLUP RESISTOR NEEDED IN2B REXT IN2A OUT2 200µF**
Figure MAX7430 Typical Application Circuit
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
220µF**
0.1µF 0.1µF ENCODER 0.1µF 0.1µF ENCODER 0.1µF OUT3 0.1µF ENCODER IN3B REXT IN3A IN2B IN2A IN1B IN1A DATA OUT1
220µF**
SERIAL
220µF**
MAX7432
OUT2 220µF**
220µF**
220µF**
300k (SEE TABLE *NEEDED ONLY FILTER BYPASS MODE **OPTIONAL OUTPUT CAPACITOR ***ONLY PULLUP RESISTOR NEEDED
Figure MAX7432 Typical Application Circuit
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
Table MAX7428 Control Register
(MSB) NAME DEFAULT SYNCIO ABSEL BYPASS CLEVEL BOOST1 BOOST0 OUTDISABLE FIRST (LSB)
Filter
Filter Response reconstruction filter consists 6th-order Butterworth filter three second-order stages. Butterworth filter features maximally flat passband NTSC bandwidths. stopband offers typically 50dB attenuation sampling frequencies 25MHz above (see Typical Operating Characteristics). corner frequency critical since response filter meets both stopband passband specifications. MAX7428/MAX7430/MAX7432 incorporate autotrimming feature that reduces corner frequency variation digitally. possible, although likely, that discrete shift corner frequency occur external environmental change. autotrimming operates continuously that corner frequency remains centered over full operating temperature range. High-Frequency Boost high-frequency boost compensates signal degradation roll-off signal path prior MAX7428/ MAX7430/MAX7432. High-frequency boost programmable four steps increase image sharpness.
Serial Interface
Maxim's Single (MSPB) interface uses DATA transfer data from microprocessor (µP) MAX7428/MAX7430/MAX7432. This negative logic protocol uses three different pulse widths represent logic "1", logic "0", control commands. MSPB allows devices connected same assigning unique 4-bit identification address each device. communicate each device individually sending "broadcast" message devices. unique address each device means time constant external capacitor connected parallel with external 300k resistor (see Initializing MAX7428/ MAX7430/MAX7432 section).
MAX7428 Control Register
Table defines structure MAX7428 8-bit control register programmed MSPB. This register controls selection INB, SYNCIO functionality, filter bypassing, clamp-level selection, high-frequency boost control, output disable. Maxim's Single Interface (MSPB) section detailed programming instructions. SYNCIO: SYNCIO Select bit. logic sets SYNCIO function output while logic sets SYNCIO function input. ABSEL: Channel Select bit. logic selects input processed while logic selects input processed. BYPASS: Filter Bypass Select bit. logic selects filter while logic bypasses filter.
Output Buffer
output buffer able drive video loads with 2Vp-p signal. +6dB gain output buffer independent filter bypass input selection. output buffer drives backmatch resistors series capacitor (typically 220µF). MAX7428/ MAX7430/MAX7432 able drive video load directly without using 220µF capacitor. This feature common SCART applications. OUTDISABLE control register disables output (mute) (see Control Register section).
Table Boost Level Programming
BOOST1 BOOST0 RELATIVE HIGH-FREQUENCY BOOST 0.45dB 0.90dB 1.35dB
Filter Bypass
MAX7428/MAX7430/MAX7432 offer selectable filter bypassing that allows either video inputs filtered unfiltered. optional input resistors needed only filter bypass mode provide discharge path input coupling capacitors.
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
Table MAX7430 Control Register
(MSB) NAME DEFAULT ABSEL2 BYPASS2 CLEVEL2 BOOST1(2) BOOST0(2) DISABLE2
NAME DEFAULT
ABSEL1
BYPASS1
CLEVEL1
BOOST1(1)
BOOST0(1)
DISABLE1
FIRST (LSB)
CLEVEL: Clamp Level bit. logic selects clamp level while logic selects clamp level 1.5V output. [BOOST1, BOOST0]: High-Frequency Boost Control bits. adjust bits select amount high-frequency boost filter. Table defines four levels adjustment. OUTDISABLE: Output Disable bit. logic selects normal operation while logic places output high-impedance state.
Table Boost Level Programming
BOOST1_ BOOST0_ RELATIVE HIGHFREQUENCY BOOST 0.45dB 0.90dB 1.35dB
MAX7430 Control Register
Table defines structure MAX7430 16-bit control register programmed MSPB. This register controls selection IN_A IN_B, selection filter filter bypassing, clamp-level selection, high-frequency boost control, output disable. Maxim's Single Interface (MSPB) section detailed programming instructions. ABSEL_: Channel Select bit. logic zero selects input IN_B processed while logic selects input IN_A processed. BYPASS_: Filter Bypass Select bit. logic selects channel filter while logic bypasses channel filter. CLEVEL_: Clamp Level bit. logic selects channel clamp level while logic selects channel clamp level 1.5V output. [BOOST1_, BOOST0_]: High-Frequency Boost Control bits. adjust bits select amount high-frequency boost channel filter. Table defines four levels adjustment. OUTDISABLE_: Output Disable bit. logic selects normal channel output operation while logic puts channel output high-impedance state.
MAX7432 Control Register
Table defines structure MAX7432 24-bit control register programmed MSPB. This register controls selection IN_A IN_B, selection filter filter bypassing, clamp-level selection, highfrequency boost control, output disable. Maxim's Single Interface (MSPB) section detailed programming instructions. ABSEL_: Channel Select bit. logic zero selects input IN_B processed while logic selects input IN_A processed. BYPASS_: Filter Bypass Select bit. logic selects channel filter while logic bypasses channel filter. CLEVEL_: Clamp Level bit. logic selects channel clamp level while logic selects channel clamp level 1.5V output. [BOOST1_, BOOST0_]: High-Frequency Boost Control bits. adjust bits select amount high-frequency boost channel filter. Table defines four levels adjustment. OUTDISABLE_: Output Disable Bit. logic selects normal channel output operation while logic puts channel output high-impedance state.
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
Table MAX7432 Control Register
(MSB) NAME DEFAULT ABSEL3 BYPASS3 CLEVEL3 BOOST1(3) BOOST0(3) DISABLE3 DISABLE2 DISABLE1
NAME DEFAULT
ABSEL2
BYPASS2
CLEVEL2
BOOST1(2)
BOOST0(2)
NAME DEFAULT
ABSEL1
BYPASS1
CLEVEL1
BOOST1(1)
BOOST0(1)
FIRST (LSB)
Applications Information
Maxim's Single (MSPB) Serial Interface
MSPB interface uses three pulses different widths represent commands data bits. Figure shows pulses that single interface uses communicate with device. combination pulse (t1), zero pulse (t0), transaction pulse (tT), prompt pulse (tP), writes reads back from, sends broadcast data devices bus. Note: zero pulse prompt pulse same. Initialization pulses significantly longer used only power-up software reset.
Table Boost Level Programming
BOOST1_ BOOST0_ RELATIVE HIGHFREQUENCY BOOST 0.45dB 0.90dB 1.35dB
Initializing MAX7428/MAX7430/MAX7432
Initialization performed only after power-up software reset. assigns unique address each device bus. time constant capacitor connected REXT parallel with 300k resistor determines order which devices initialized (address assigned). device with largest time constant initialized first descending order. Table shows "Initialize Wait" "Initialize Time" pulse widths needed specific capacitor value tolerance. Program each device with this command sequence starting with device with biggest capacitor. reinitialize device, cycle power software reset. following command sequence timing diagram (Figure initialization shown below. Chip entered first. Note: there only device bus, initialization needed. Communicate device using broadcast command described page
ZERO/PROMPT PULSE
PULSE
30µs
TRANSACTION PULSE
100µs
Figure MSPB Interface Pulses
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
Table Initialization Capacitor Values Pulse Widths (CREXT ±10% Tolerance, RREXT Tolerance)
CAPACITOR VALUE (nF) 1000 INITIALIZING WAIT PERIOD (ms) (tINTWAIT) 20.000 13.600 9.400 4.400 3.000 2.000 1.360 0.940 0.440 0.300 0.200 0.136 0.094 0.044 0.030 0.020 INITIALIZING TIME PERIOD (ms) WITH RREXT 300k (tINT) (136.8) 52.6 (44.1) 35.90 23.90 (13.7) 16.25 11.21 (4.4) 5.26 3.59 2.39 1.625 (1.37) 1.121 0.526 (0.441) 0.359 0.239 0.162 (0.137) (144) 55.4 (46.4) 37.80 25.20 (14.4) 17.10 11.80 (4.64) 5.54 3.78 2.52 1.710 (1.44) 1.180 0.554 (0.464) 0.378 0.252 0.171 (0.144) (151.2) 58.2 (48.72) 39.70 26.50 (15.1) 17.95 12.39 (4.9) 5.82 3.97 2.65 1.795 (1.51) 1.239 0.582 (0.487) 0.397 0.265 0.179 (0.151)
Note: Indicates time periods associated with capacitors. This limits maximum number devices seven.
Initialization Command Sequence: Initialize wait T011 Initialize Time Address 4-bits T111
than 8/16/24 bits loaded into register. following command sequence timing diagram (Figure write sequence.
Write Command Sequence: Data 8-bits (MAX7428, Table Data 16-bits (MAX7430, Table Data 24-bits (MAX7432, Table
Programming MAX7428/MAX7430/MAX7432
address sequence precedes write read operation determine with which device communicate. address transmitted this mode matches with device's address, device initiate data transfer. When entering four address bits, ensure that entered first. following command sequence timing diagram (Figure address sequence.
Address Command Sequence: T010 Address 4-bits T111
T001
T111
write sequence load data into data register device. must follow address sequence. Transmit minimum eight data bits MAX7428, data bits MAX7430, data bits MAX7432 make this transaction valid starting with first. last 8/16/24 data bits used more
During read sequence, sends prompt pulse causing device output data word first. Similar write transaction, read transaction must preceded address sequence. more than prompts (MAX7428), prompts (MAX7430), prompts (MAX7432) available, device outputs same data starting with again. following command sequence timing diagram (Figure read sequence.
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
Read Command Sequence: T101 Prompts (MAX7428) Prompts (MAX7430) Prompts (MAX7432) T111 Software Reset Command Sequence: T000 more (MAX7428) more (MAX7430) more (MAX7432) T010 T001 Address 4-bits more (MAX7428) more (MAX7430) more (MAX7432) T111 T111 T111
broadcast sequence writes data control registers devices same time. Write data with first. following command sequence timing diagram (Figure broadcast transaction. address sequence required. broadcast command when there only device bus.
Broadcast Command Sequence: T000 Data 8-bits (MAX7428) Data 16-bits (MAX7430) Data 24-bits (MAX7432) T111
more ones MAX7430, more ones MAX7432 that device register.
Composite Video Filtering
MAX7428 ideally suited filtering composite video signals. Program SYNCIO output when processing composite video signals. rare occasion that external sync pulse needed process composite video, program SYNCIO input.
Executing software reset serves same function power-on reset achieved transmitting data bits (eight more) MAX7428, sixteen
tWAIT tINTWAIT tINT
ADDRESS: 0001
Figure Initialization Timing Diagram
tWAIT
ADDRESS: 0001
Figure Address Timing Diagram
tWAIT
DATA: 1***000
Figure Write Timing Diagram
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
tWAIT
HIGH-Z
READS (LSB) WILL RELEASE TIME
READS
REPEAT READ MORE BITS
UNTIL TIME FINISH READING DEVICE WILL RELEASE TIME
START READING TIME
NOTE: TIME REFERENCED
Figure Read Timing Diagram
tWAIT
DATA: 1***000
Figure Broadcast Timing Diagram
When processing composite video clamp level (CLEVEL MAX7430 process synchronous composite signals simultaneously. MAX7432 process three synchronous composite signals simultaneously.
Video Filtering
MAX7430 ideally suited processing S-Video (Y/C) signals (Figure 10). Ensure that IN1_ filters signal that contains sync information since clamping IN2_ internally controlled master channel (IN1_) sync. clamp level IN1_ (CLEVEL1 clamp level IN2_ +1.5V (CLEVEL2 MAX7428s video filtering. Since only signal contains sync, typical video-filtering application requires master-slave configuration SYNCIO. MAX7428 processing signal should have SYNCIO configured output, which turn drives SYNCIO second MAX7428, processing signal that SYNCIO configured input (Figure 11). Clamping level signal should (CLEVEL clamping level signal should +1.5V (CLEVEL MAX7432 filter composite video signal that synchronous.
Component video consists three separate signals. Typically three signals separate red, green, blue (RGB) signals (luma) color difference signals: (Pb) which blue minus luma (Pr), which minus luma. Sync information included with signal component video, case RGB, sync usually carried separate sync line. MAX7432 ideally suited filtering component video signals. Ensure that sync signal signals usually signals) filtered IN1_ since IN2_ IN3_ internally synced IN1_. clamp level IN1_ (CLEVEL1 clamp levels IN2_ IN3_ +1.5V (CLEVEL2, filtering (Figure clamp levels (CLEVEL_ filtering (Figure 13). component video-filter application requires three MAX7428s with SYNCIO master-slave configuration. MAX7428 processing signal SYNCIO configured output, which turn drives SYNCIO inputs other MAX7428s (Figure 14). video signal filtering with separate horizontal sync signal, configure MAX7428s SYNCIO input (Figure 15).
Component Video (RGB Filtering
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
(LUMA) SYNCIO
MAX7430
(LUMA) IN1A [CLEVEL OUT1
(CLEVEL
MAX7248
(CHROMA) (CHROMA) IN2A [CLEVEL OUT2
SYNCIO (CLEVEL
MAX7248
Figure MAX7430 Video Filter Application
Figure Video Filter Application
MAX7432
(LUMA) (INCLUDES SYNC SIGNAL) IN1A [CLEVEL OUT1 (MUST CONTAIN SYNC SIGNAL) IN1A
MAX7432
[CLEVEL OUT1
IN2A
[CLEVEL
OUT2
IN2A
[CLEVEL
OUT2
IN3A
[CLEVEL
OUT2
IN3A
[CLEVEL
OUT3
Figure MAX7432 Video Filter Application
Figure MAX7432 Video Filter with Embedded Sync Application
clamping levels component video MAX7428 processing clamps (CLEVEL remaining MAX7428s should have clamp levels +1.5V (CLEVEL video with external sync (H), three MAX7428s should have clamp levels (CLEVEL
Power-Supply Bypassing Layout
MAX7428/MAX7430/MAX7432 operate from single supply. Bypass with 0.1µF capacitor. Place external components close devices possible. Refer MAX7428EVKIT proven board layout example.
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
(LUMA) (INCLUDES SYNC SIGNAL) SYNCIO (CLEVEL
SYNCIO (CLEVEL
MAX7248
MAX7248
SYNCIO (CLEVEL
SYNCIO (CLEVEL
MAX7248
MAX7248
SYNCIO (CLEVEL
SYNCIO (CLEVEL
MAX7248
EXTERNAL SYNC
MAX7248
Figure Video Filter Application
Figure Video Filter with External Sync Application
Chip Information
TRANSISTOR COUNT: MAX7428 4955 MAX7430 7413 MAX7432 9873 PROCESS: BiCMOS
Standard Definition Video Reconstruction Filters Buffers
Configurations
VIEW
MAX7428/MAX7430/MAX7432
REXT DATA SYNCIO
IN1A IN2A REXT IN1B
OUT1 OUT2 DATA
IN1A IN2A IN3A
OUT1 REXT
MAX7428
MAX7430
IN1B IN2B IN3B
MAX7432
OUT2 OUT3 DATA
IN2B
SOT23
µMAX
TSSOP
Functional Diagrams (continued)
IN1A 6TH-ORDER FILTER IN1B LEVEL SHIFT INPUT SYNC +6dB OUT1
SERIAL INTERFACE CONTROL
DATA
ENCODER
IN2A 6TH-ORDER FILTER IN2B LEVEL SHIFT INPUT MAX7430 BIAS GENERATOR REXT +6dB OUT2
*OPTIONAL OUTPUT CAPACITOR
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
Functional Diagrams (continued)
IN1A 6TH-ORDER FILTER IN1B LEVEL SHIFT INPUT SYNC SERIAL INTERFACE CONTROL DATA +6dB OUT1
IN2A 6TH-ORDER FILTER IN2B LEVEL SHIFT INPUT +6dB OUT2
IN3A 6TH-ORDER FILTER +6dB OUT3
ENCODER
IN3B LEVEL SHIFT INPUT MAX7432 BIAS GENERATOR REXT
*OPTIONAL OUTPUT CAPACITOR
Standard Definition Video Reconstruction Filters Buffers
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
SOT23, 8L.EPS
MAX7428/MAX7430/MAX7432
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
Package Information (continued)
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
10LUMAX.EPS
INCHES 0.043 0.002 0.006 0.030 0.037 0.116 0.120 0.114 0.118 0.116 0.120 0.118 0.114 0.199 0.187 0.0157 0.0275 0.037 0.007 0.0106 0.0197 0.0035 0.0078 0.0196
MILLIMETERS 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 0.177 0.270 0.500 0.090 0.200 0.498
0.50±0.1 0.6±0.1
0.6±0.1
VIEW
BOTTOM VIEW
GAGE PLANE
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, uMAX/uSOP
APPROVAL DOCUMENT CONTROL REV.
21-0061
Standard Definition Video Reconstruction Filters Buffers MAX7428/MAX7430/MAX7432
Package Information (continued)
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
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Standard Definition Video Reconstruction Filters Buffers MAX7428/

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