HM512200B Series 1,048,576-word 2-bit Dynamic Random Access Memor

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HM512200B Series 1,048,576-word 2-bit Dynamic Random Access Memor

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ADE-203-352A
HM512200B Series
1,048,576-word 2-bit Dynamic Random Access Memory
Rev. Jan. 1995
Hitachi HM512200B CMOS dynamic organized 1,048,576-word 2-bit. HM512200B realized higher density, higher performance various functions employing CMOS process technology some CMOS circuit design technologies. HM512200B offers Fast Page Mode high speed access mode. Multiplexed address input permits HM512200B packaged standard 300-mil 26-pin plastic SOJ.
Ordering Information
Type HM512200BS-6 HM512200BS-7 HM512200BS-8 Access time Package 300-mil 26-pin plastic (CP-26/20D)
Features
Single (±10%) High speed Access time ns/70 ns/80 (max) power dissipation Active mode mW/385 mW/330 (max) Standby mode (max) Fast page mode capability 1024 refresh cycles variations refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Test function Battery back operation
HM512200B Series
Arrangement
HM512200BS Series
I/O1 I/O2
CAS1 CAS2
(Top view)
Description
name I/O1 I/O2 CAS1, CAS2 Function Address input Refresh address input Data-in/Data-out address strobe Column address strobe Read/Write enable Output enable Power Ground connection
HM512200B Series
Block Diagram
Control Circuit
CAS1 CAS1 Control Circuit
CAS2 CAS2 Control Circuit
Control Circuit
Control Circuit
I/O1
I/O2
I/O1 Buffer
I/O2 Buffer
Column Decoder
Column Decoder
Column Decoder
Column Decoder
Memory Array
Memory Array
Memory Array
Memory Array
Memory Array
Memory Array
Memory Array
Driver
Driver
Driver
Driver
Driver
Driver
Driver
Driver
Decoder Peripheral Circuit
Address Buffer
Column Address Buffer
Address A0-A9
Memory Array
HM512200B Series
Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature Symbol Iout Topr Tstg Value -1.0 +7.0 -1.0 +7.0 +125 Unit
Recommended Operating Conditions +70°C)
Parameter Supply voltage Symbol Input high voltage Input voltage Note: -1.0 Unit Note
voltage referred VSS.
Characteristics +70°C, 10%,
HM512200B Parameter Operating current Standby current Symbol ICC1 ICC2 Notes RAS, CAS1, CAS2 cycling, interface RAS, CAS1, CAS2 Dout High-Z CMOS interface RAS, CAS1, CAS2 Dout High-Z
Unit Test conditions
RAS-only refresh current
ICC3
HM512200B Series
Characteristics (cont)
HM512200B Parameter Standby current Symbol ICC5 Notes CAS1, CAS2 Dout enable Vout Dout disable High Iout Iout
Unit Test conditions
CAS-before-RAS refresh current Fast page mode current Input leakage current Output leakage current Output high voltage Output voltage
ICC6 ICC7
Notes: depends output load condition when device selected. specified output open condition. Address changed twice less while VIL. Address changed once less while CAS1, CAS2 VIH.
Capacitance 25°C, 10%)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI/O Unit Notes
Notes: Capacitance measured with Boonton Meter effective capacitance measuring method. CAS1, CAS2 disable Dout.
HM512200B Series
Characteristics +70°C, 10%, *14, *15,
Test Conditions Input rise fall times Input timing reference levels Output load gate (100 (Including scope jig) Read, Write, Read-Modify-Write Refresh Cycles (Common parameters)
HM512200B Parameter Random read write cycle time precharge time pulse width pulse width address setup time address hold time Column address setup time Column address hold time delay time column address delay time hold time hold time precharge time delay time delay time from setup time from Transition time (rise fall) Refresh period Symbol tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tREF Unit Notes
10000 10000
10000 10000
10000 10000
HM512200B Series
Read Cycle
HM512200B Parameter Access time from Access time from Access time from address Access time from Read command setup time Read command hold time Read command hold time Column address lead time Output buffer turn-off time Output buffer turn-off time delay time pulse width Symbol tRAC tCAC tOAC tRCS tRCH tRRH tRAL tOFF1 tOFF2 tCDD tOEP Unit Notes
Write Cycle
HM512200B Parameter Write command setup time Write command hold time Write command pulse width Write command lead time Write command lead time Data-in setup time Data-in hold time Symbol tWCS tWCH tRWL tCWL Unit Notes
HM512200B Series
Read-Modify-Write Cycle
HM512200B Parameter Read-modify-write cycle time delay time delay time Column address delay time hold time from Symbol tRWC tRWD tCWD tAWD tOEH Unit Notes
Refresh Cycle
HM512200B Parameter setup time (CBR refresh cycle) hold time (CBR refresh cycle) precharge hold time precharge time normal mode Symbol tCSR tCHR tRPC tCPN Unit Notes
Fast Page Mode Cycle
HM512200B Parameter Fast page mode cycle time Fast page mode pulse width Access time from precharge hold time from precharge Symbol tRASC tACP tRHCP Unit Notes
Fast page mode precharge time
100000
100000
100000
HM512200B Series
Fast Page Mode Read-Modify-Write Cycle
HM512200B Parameter Fast page mode read-modify-write cycle time Fast page mode read-modify-write cycle precharge delay time Symbol tPCM tCPW Unit Notes
Test Mode Cycle
HM512200B Parameter Test mode setup time Test mode hold time Symbol Unit Notes
Counter Test Cycle
HM512200B Parameter precharge time counter test cycle Symbol tCPT Unit Notes
HM512200B Series
Notes: measurements assume Assumes that tRCD tRCD (max) tRAD tRAD (max). tRCD tRAD greater than maximum recommended value shown this table, tRAC exceeds value shown. Measured with load circuit equivalent loads Assumes that tRCD tRCD (max) tRAD tRAD (max). Assumes that tRCD tRCD (max) tRAD tRAD (max). tOFF (max) defines time which output achieves open circuit condition referred output voltage levels. (min) (max) reference levels measuring timing input signals. Also, transition times measured between VIL. Operation with tRCD (max) limit insures that tRAC (max) met, tRCD (max) specified reference point only, tRCD greater than specified tRCD (max) limit, then access time controlled exclusively tCAC. Operation with tRAD (max) limit insures that tRAC (max) met, tRAD (max) specified reference point only, tRAD greater than specified tRAD (max) limit, then access time controlled exclusively tAA. tWCS, tRWD, tCWD, tCPW tAWD restrictive operating parameters. They included data sheet electrical characteristics only; tWCS tWCS (min), cycle early write cycle data will remain open circuit (high impedance) throughout entire cycle; tRWD tRWD (min), tCWD tCWD (min), tCPW tCPW (min) tAWD tAWD (min), cycle read-modify-write data output will contain data read from selected cell; neither above sets conditions satisfied, condition data access time) indeterminate. These parameters referred leading edge early write cycle leading edge delayed write read-modify-write cycle. tRASC defines pulse width fast page mode cycles. Access time determined longer tCAC tACP. initial pause required after power followed minimum eight initialization cycles (RAS-only refresh cycle CAS-before-RAS refresh cycle). internal refresh counter used, minimum eight CAS-before-RAS refresh cycles required. delayed write read-modify-write cycles, must disable output buffer prior applying data device. Test mode operation specified this data sheet 2-bit test function controlled control address bits CA0. This test mode operation performed WE-and-CAS-before-RAS (WCBR) refresh cycle. Refresh during test mode operation will performed normal read cycles WCBR refresh cycles. When state test bits accord each other, condition output data high level. When state test bits accord, condition output data level. order this test mode operation, perform RAS-only refresh cycle CAS-before-RAS refresh cycle. test mode read cycle, value tRAC, tAA, tCAC, tOAC tACP delayed specified value. These parameters should specified test mode cycles adding above value specified value this data sheet. Either tRCH tRRH must satisfied tRAS (min) tRWD (min) tRWL (min) read-modify-write cycle. tCAS (min) tCWD (min) tCWL (min) read-modify-write cycle. When both CAS1 CAS2 same time, bits data written into device. CAS1 CAS2 cannot staggered within same write/read cycles.
HM512200B Series
Notes 2CAS control
mermory cycle, activate both 2CASs CAS1 CAS2 only them neither them. activate both 2CASs early write cycle fast page mode early write cycle, please keep tSKW (skew between CAS1 CAS2) less.
CAS1 (CAS2)
CAS2 (CAS1)
different activated consecutive fast page cycles, tUL, period
Example.
that both CASs high, should keep spec (tCP tUL).
CAS1
CAS2
cycle
cycle
HM512200B Series
Timing Waveforms*22
Read Cycle
CAS1 CAS2
Address
Column
Dout High-Z OFF1
Dout OFF2
Notes:
(min) (max), (min) (max))
Invalid Dout
HM512200B Series
Early Write Cycle
CAS1 CAS2
Address
Column
Dout
High-Z*
(min)
HM512200B Series
Delayed Write Cycle
CAS1 CAS2 Column
Address
Dout
Invalid Dout*
High-Z
OFF2
Invalid Dout comes out, when level.
HM512200B Series
Read-Modify-Write Cycle
CAS1 CAS2 tCAH
Address
Column
High-Z
Dout
Dout
OFF2
HM512200B Series
RAS-Only Refresh Cycle
tRPC tCRP
CAS1 CAS2
Address
Dout
High-Z
Refresh address (AX0 AX9)
HM512200B Series
CAS-Before-RAS Refresh Cycle
CAS1 CAS2
Address
OFF1 High-Z
Dout
HM512200B Series
Hidden Refresh Cycle
(Read)
(Refresh)
(Refresh)
CAS1 CAS2
Column
Address
Dout
OFF1 Dout OFF2 High-Z tDZO
HM512200B Series
Fast Page Mode Read Cycle
RASC RHCP
CAS1 CAS2 Address tASC Column Column Column
High-Z High-Z tCAC OFF1 Dout OFF2 Dout Dout
High-Z OFF1 Dout OFF2 OFF2 OFF1
HM512200B Series
Fast Page Mode Early Write Cycle
RASC
CAS1 CAS2
Address
Column
Column
Column
Dout
High-Z**
HM512200B Series
Fast Page Mode Delayed Write Cycle
RASC
tRCD CAS1 CAS2 Column
Address
Column
Column
Dout
High-Z
HM512200B Series
Fast Page Mode Read-Modify-Write Cycle
RASC
CAS1 CAS2
Address
Column
Column
Column
High-Z tOAC Dout Dout OFF2 Dout OFF2 High-Z Dout OFF2
High-Z
tOEP
HM512200B Series
Test Mode Cycle
*,** Reset Cycle
Cycle**
Test Mode Cycle
Normal Mode
CAS1 CAS2
RAS-only refresh Address, Din,
Test Mode Cycle WE-and-CAS-Before RAS-Refresh Cycle
CAS1 CAS2 CPN@
Address OFF1 High-Z
Dout
HM512200B Series
CAS-Before-RAS Refresh Counter Check Cycle (Read)
CAS1 CAS2
tCRP
Address
Column
High-Z
OFF1
Dout
Dout OFF2
HM512200B Series
CAS-Before-RAS Refresh Counter Check Cycle (Write)
CAS1 CAS2
Address
Column
Dout
High-Z

HM512200B Series 1,048,576-word 2-bit Dynamic Random Access Memor

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