COM/SEG Driver SEP. 2004 Version SPLC562C Table Content

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COM/SEG Driver SEP. 2004 Version SPLC562C Table Content

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SPLC562C
COM/SEG Driver
SEP. 2004 Version
SPLC562C
Table Contents
PAGE
GENERAL DESCRIPTION FEATURES BLOCK DIAGRAM 3.1. BLOCK FUNCTION 3.2. INPUT/OUTPUT CIRCUITS SIGNAL DESCRIPTIONS.
4.1. CONNECTION FUNCATIONAL DESCRIPTIONS
5.1. FUNCTIONS. 5.2. FUNCTION OPERATIONS
5.3. RELATIONSHIP BETWEEN DISPLAY DATA DRIVER OUTPUT PINS 5.4. PRECAUTIONS ELECTRICAL SPECIFICATIONS 6.1. ABSOLUTE MAXIMUM RATINGS 6.2. RECOMMENDED OPERATING CONDITIONS 6.3. CHARACTERISTICS 6.4. CHARACTERISTICS APPLICATION CIRCUIT PACKAGE/PAD LOCATIONS 8.1. ASSIGNMENT LOCATIONS 8.2. ORDERING INFORMATION DISCLAIMER. REVISION HISTORY
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COM/SEG DRIVER
GENERAL DESCRIPTION
SPLC562C 240-output segment/common driver suitable driving large/medium scale matrix panels, used personal computers/work-stations. Through (Super Slim TCP) technology, ideal substantially decreasing size frame section module. SPLC562C good both segment driver common driver, create power consuming, high-resolution LCD. Common Mode Built-in bits bi-directional shift register (divisible into 120-bits Shift clock frequency: 4.0MHz (Max.) (VDD +2.5V +5.5V) Available single mode(240 bits shift register) dual mode (120 bits shift register Y240 Y240
FEATURES
Both Segment Mode Common Mode Number drive outputs:
Y120, Y121 Y240 Y240 Y121, Y120
Supply voltage drive: +15V +30V power consumption output impedance
Supply voltage logic system: +2.5V +5.5V
CMOS silicon gate process (P-type silicon substrate) Package: 278-pin (Tape Carrier Package) bump chip Segment Mode
Shift clock frequency:
20MHz (Max.) (VDD +5.0V 10%)
15MHz (Max.) (VDD +3.0V +4.5V) 12MHz (Max.) (VDD +2.5V +3.0V) Adopts data system
4-bit 8-bit parallel input modes selectable with mode (MD) Automatic transfer function enable signal
Automatic counting function which, chip select mode, causes internal clock stopped automatically counting input data Line latch circuits reset when DISPOFF active
BLOCK DIAGRAM
V12R V43R LEVEL SHIFTER
DISPOFF
above shift directions pin-selectable
Shift register circuit reset function when DISPOFF active
Single mode Single mode
Dual mode Dual mode
Y239 Y240
V43L V12L
4-LEVEL DRIVER
EIO1 EIO2
ACTIVE CONTROL
LEVEL SHIFTER
LINE LATCH/SHIFTER REGISTER
CONTROL LOGIC
8BITS*2 DATA LATCH
DATA CONTROL
CONVERSION DATA CONTROL
TEST CIRCUIT
TEST1
TEST1
Remark: TCP's external shape customized.
order your TCP's external shape, please contact SUNPLUS salesperson.
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3.1. Block Function 3.1.1. Active control
case segment mode, controls selection non-selection chip. Following signal, after chip select signal Once data input been completed, input, select signal generated internally until bits data have been read non-selected. select signal cascade connection output, chip case common mode, controls input/output
3.1.5. Data latch
case segment mode, latches data data bus. latched state each driver output controlled control logic data latch control, bits data read sets bits.
3.1.6. Test circuit
circuit test. During normal operation, doesn't act.!
data bidirectional pins.
3.1.2. Conversion Data Control
case segment mode, keep input data which clocks 4-bit parallel mode into latch circuit, keep input data which clock 8-bits parallel mode into latch circuit, after that they internal data bits time.
3.1.7. Line latch/shift register
case segment mode, bits which have been read into signal, output level shifter block. edge signal.
data latch simultaneously latched falling edge
3.1.3. Data latch control
case segment mode, selects state data latch which reads data signals. shift direction controlled
control logic, every bits data read selection signal shifts based state control circuit.
3.1.4. Control logic
Controls operation each block.
when signal been input, blocks reset control block.
control logic waits selection signal output from active Once selection signal been output, operation data latch data transmission controlled, bits data read chip non-selected. case common mode, controls direction data shift.
3.2. Input/Output Circuits
3.1.8. Level shifter
level, output driver block.
common mode, shifts data from data input falling
case
logic voltage signal level-shifted driver voltage
3.1.9. 4-level driver
case segment mode,
Drives driver output pins from line latch/shift register data, selecting levels (V0, V12, V43, based S/C,
DISPOFF signals.
Internal Circuit Applicable L/R, S/C, DI6-0, DISPOFF,
Figure1: Input Circuit
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Control Signal
Internal Circuit
Figure2: Input Circuit
Control Signal VSS(0 Output Signal Control Signal
Figure3: Input/Output Circuit
Applicable DI7,
Internal Circuit
Applicable
Control Signal
Control Signal
Control Signal
Internal Circuit
Control Signal
Applicable
Y240 VSS(0
Figure4: Drive Output Circuit
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SIGNAL DESCRIPTIONS
Mnemonic Y240 V12L, V12R V43L, V43R V5L, EIO1 EIO2 #32, #31, #30, #29, Power supply driver Power supply driver Power supply driver Input selecting reading direction display data segment mode/Input Power supply logic system (+2.5V +5.5V) selecting shift direction shift register common mode Type driver output Power supply driver Description
DISPOFF
4.1. Connection
Note: Doesn't prescribe outline.
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V12R V43R EIO1 DISPOFF EIO2 V43L V12L
Segment mode/common mode selection Input/output chip selection segment mode/Shift clock input/output shift register Display data input segment mode common mode Display data input segment mode/Dual mode data input common mode Clock input taking display data segment mode Control input output non-select level Latch pulse input display data segment mode/Shift clock input shift register AC-converting signal input driver waveform common mode Mode selection input Ground (0V)
CHIP SURFACE
Y238 Y239 Y240
SEP. 2004 Version:
SPLC562C
FUNCATIONAL DESCRIPTIONS
5.1. Functions 5.1.1. Segment mode
Mnemonic V0R, V0L, V12R, V12L, V43R, V43L, V5L, Description Logic system power supply connects +2.5V +5.5V Ground connects Bias Power supply driver voltage Normally, bias voltage used resistor divider. Ensure that voltage such that <V43<V12<V0.
must connect external power supply, supply regular voltage which assigned specification each power pin. should shorted directly panel. connect-pin. Input pins display data applications, even though have same voltage level, layout That should have individual path
DISPOFF
4-bit parallel input mode, input data into pins, DI0. 8-bit parallel input mode, input data into pins, DI7-DI0. Operations. Clock input taking display data Data read falling edge clock pulse. Latch pulse input display data Data latched falling edge clock pulse. Input selecting reading direction display data When level "L", data read sequentially from Y240 When level "H", data read sequentially from Y240. Operations. Control input output non-select level drive circuit. When level "L", drive output pins (Y240 level output reading data correctly. Table truth values shown "5.2.1 Truth table" Function Operations. Segment mode/common mode selection When level "H", segment mode set. signal input driving waveform circuit. Normally, inputs frame inversion signal.
Connect VDD.
Refer "5.3 Relationship between Display Data Driver Output PINs" Functional
Refer "5.3 Relationship between Display Data Driver Output PINs" Functional
input signal level-shifted from logic voltage level drive voltage level, controls
While "L", contents line latch reset, display data read data latch regardless condition DISPOFF When DISPOFF function canceled, driver outputs non-select level (V12 V43), then outputs contents data latch next falling edge
that time, DISPOFF removal time does correspond what shown characteristics,
input signal level-shifted from logic voltage level drive voltage level, controls drive
driver output pin's output voltage level using line latch output signal signal. Table truth values shown "5.2.1 Truth table" Function Operations.
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Mnemonic Mode selection When level "L", 8-bit parallel input mode set. When level "H", 4-bit parallel input mode set. Refer "5.3 Relationship between Display Data Driver Output PINs" Functional Operations. EIO1, EIO2 Input/output pins chip selection When input Level "L", EIO1 output EIO2 input. When input Level "H", EIO1 input EIO2 output. During output, while Description
after bits data have been read,
cycle (from falling edge falling edge XCK), after which returns "H". non-selected after bits data have been read. Y240 driver output pins output.
During input, chip selected while after signal input. chip
5.1.2. Common mode
Mnemonic
V0R, V0L, V12R, V12L, V43R, V43L, V5L,
EIO1
Table truth values shown "5.2.1 Truth table" Function Operations. Description Logic system power supply connects +2.5V +5.5V. Ground connects Bias Power supply driver voltage Normally, bias voltage used resistor divider. Ensure that voltage such that <V43<V12<V0. assigned specification each power pin. Shift clock pulse input bi-directional shift register Data shifted falling edge clock pulse. Shift data input/output bi-directional shift register Output when level "L", input when level "H". When EIO1 used input pin, will pull-down. When EIO1 used output pin, won't pull-down. Operations. Input selecting shift direction bi-directional shift register level "H". Operations. Shift data input/output bi-directional shift register Input when level "L", output when level "H". When EIO2 used input pin, will pull-down. When EIO2 used output pin, won't pull-down.
Corresponding directly each shift register, level (V0, V12, V43, selected
(I=0, must connect external power supply, supply regular voltage which
Refer "5.3 Relationship between Display Data Driver Output PINs" Functional
Data shifted from Y240 when level "L", data shifted from Y240 when
Refer "5.3 Relationship between Display Data Driver Output PINs" Functional EIO2
Refer "5.3 Relationship between Display Data Driver Output PINs" Functional Operations. Segment mode common mode selection When level "L", common mode set.
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Mnemonic signal input driving waveform input signal level-shifted from logic voltage level drive voltage level, controls drive circuit. Normally, input frame inversion signal. driver output pin's output voltage level using shift register output signal signal. Table truth values shown "5.2.1 Truth table" Functional Operations. Control input output non-select level drive circuit. Description
DISPOFF
input signal level-shifted from logic voltage level drive voltage level, controls When level "L", drive output pins (Y240 level
While "L", contents shift register reset reading data.
function canceled, driver outputs non-select level (V12 V43), shift data reading
Y240
characteristics, shift data reading correctly. Table truth values shown "5.2.1 Truth table" Functional Operations. Mode selection operation selected. Operations. used Connect VDD, avoiding floating. used pull-down common mode, connect open. Dual mode data input bit. When chip used dual mode, will pull-down. When chip used single mode, won't pull-down. Operations. driver output pins output. Table truth values shown "5.2.1 Truth table" Functional Operations.
falling edge that time, DISPOFF removal time does correspond what shown
When DISPOFF
When level "L", single mode operation selected, when level "H", dual mode Refer "5.3 Relationship between Display Data Driver Output PINs" Functional
According data shift direction data shift register, data input starting from 121st
Refer "5.3 Relationship between Display Data Driver Output PINs" Functional
Corresponding directly each shift register, level (V0, V12, V43, selected
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5.2. Function Operations 5.2.1. Truth table 5.2.1.1. Segment mode
Latch data DISPOFF Driver output voltage level (Y240
5.2.1.2. Common mode
Latch data DISPOFF Driver output voltage level (Y240
Note1:
Don't care
Note2: "Don't care" should fixed "L", avoiding floating. drive voltage) driver. power pin.
There kinds power supply (logic level voltage
5.3. Relationship between Display Data Driver Output PINs 5.3.1. Segment mode
5.3.1.1. 4-bit parallel mode
EIO1
EIO2 Data Figure clock Input Clock Clock Clock Clock Y229 Y230 Y231 Y232 Output Input Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233 Y232 Y231 Y230 Y229 Input Output
Supply regular voltage which assigned specification each
(0V), (+2.5V +5.5V),
Y233 Y234 Y235 Y236
Clock
Clock Y237 Y238 Y239 Y240
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5.3.1.2. 8-bit parallel mode
EIO1 EIO2 Data Input Output Input Input Output Clock Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233 Clock Y232 Y231 Y230 Y229 Y228 Y227 Y226 Y225 Figure clock Clock Y224 Y223 Clock Y217 Y218 Y219 Y220 Y221 Clock Y225 Y226 Y227 Y228 Y229 Y230 Y231 Y232 Clock Y233 Y234 Y235 Y236 Y237 Y238
5.3.2. Common mode
(Single)
(Dual)
Note1: (0V), (+2.5V +5.5V), Don't care
Note2: "Don't care" should fixed "L", avoiding floating.
Y219 Y218 Y217 Data transfer direction Y240 Y240 EIO1 L(shift left) Output Input H(shift right) L(shift left) Y240 Y121 Y120 Output H(shift right) Y120 Y121 Y240 Input
Y221 Y220
Y222
Y222 Y223 Y224
EIO2 Input Output Input
Y239 Y240
Input
Output
Input
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5.3.3. Connection examples plural segment drivers
CASE data Data flow Y240 EIO2 EIO1 Y240 EIO2 EIO1 Y240 EIO2 EIO1 Last data
CASE
EIO2
EIO1
EIO2
EIO2 Y240 Last data
EIO1
Y240
Y240
Data flow
data
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5.3.4. Timing chart 4-device casecade connection segment drivers
DATA
LAST DATA
(device (device
(device
(device
n=60 4-bit parallel input mode. n=30 8-bit parallel input mode.
device
device
device
device
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5.3.5. Connection examples plural common drivers
Single MODE (L/R "L")
First
Last
Y240
Y240
Y240
DISPOFF
DISPOFF
VSS(VDD)
DISPOFF
Single Mode (L/R "H") DISPOFF
VSS(VDD)
DISPOFF DISPOFF
Y240
DISPOFF
EIO2
EIO1
EIO2
EIO1
EIO2
EIO1
DISPOFF
Y240
EIO1
Y240
Y120 Y121
First
Last
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Dual MODE (L/R "L")
First
Last First
Last
Y240
Y240 Y121 Y120
Y240
DISPOFF
DISPOFF
VSS(VDD)
DISPOFF
Dual MODE (L/R "H")
DISPOFF
VSS(VDD)
DISPOFF
EIO2
EIO1
EIO2
EIO1
EIO2
EIO1
DISPOFF
DISPOFF
DISPOFF
EIO1
Y240
Y120 Y121
Y240
Y240
First
Last First
Last
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5.4. Precautions 5.4.1. Precaution when connecting disconnecting power
This high-voltage driver, permanently damaged high current which flow voltage supplied driver power supply while logic system power supply floating. detail follows. When connecting power supply, connect drive power after connecting logic system power. Furthermore, when disconnecting power, disconnect logic system power after disconnecting driver power. recommend connecting serial resistor (50~100: fuse drive power system current limited. suitable value resistor consideration display grade. when connecting logic power supply, logic condition this inside insecurity. Therefore connect driver power supply after resetting logic condition this inside
DISPOFF function.
After that, cancel DISPOFF function
after driver power supply become stable. Furthermore, when disconnecting power, drive output pins level DISPOFF function.
disconnect logic system power after disconnecting drive power.
When connecting power supply, follow recommended sequence shown here.
DISPOFF
After that,
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ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Parameter Supply voltage Symbol Supply voltage Input voltage Storage temperature
Note1: +25: Note2: maximum applicable voltage with respect (0V). conditions AC/DC Electrical Characteristics.
Conditions
Applicable Pins V0L,
Ratings -0.3 +6.5 -0.3 -0.3 V0+0.3 -0.3 V0+0.3
Unit
Referenced VSS(0V)
V12L, V12R V43L, V43R V5L, XCK, L/R, S/C, EIO1, EIO2, DISPOFF
TSTG
Note3: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device.
6.2. Recommended Operating Conditions
Parameter Symbol
Supply voltage
Supply voltage
Operating temperature
Note1: applicable voltage with respect (0V). Note2: Ensure that voltage such that
6.3. Characteristics 6.3.1. Segment mode
Parameter Input voltage
Output voltage
Input leakage current
Output resistance Stand-by current
Conditions Applicable Pins Min. +2.5 Referenced (0V) V0L, TOPR Symbol Conditions Applicable Pins Min. XCK, L/R, S/C, EIO1, EIO2, DISPOFF EIO1, EIO2 0.8VDD ILIH ILIL -0.4mA VDD-0.4 +0.4mA XCK, L/R, S/C, EIO1, EIO2, DISPOFF Y240 V0L, ISTB IDD1 IDD2 VON| 0.5V +30V +20V
-0.3 V0+0.3
-0.3 VDD+0.3 +125
normal operational
Unit
Typ.
Max. +5.5
(VSS +2.5V +5.5V, +15V +30V, +25: Typ. Max. 0.2VDD +0.4 Unit
Supply current (Non-selection) Supply current (Selection) Supply current
Note1: +5.0V, +30V, Note2: +5.0V, +30V, fXCK 20MHz, No-load, VDD. Note3: +5.0V, +30V, fXCK 20MHz, No-load, VSS. mode) input data turned over data taking clock (4-bit parallel input mode) input data turned over data taking clock (4-bit parallel input mode) input data turned over data taking clock (4-bit parallel input
Note4: +5.0V, +30V, fXCK 20MHz, 41.6KHz, 80Hz, no-load.
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6.3.2. Common mode
(VSS +2.5V +5.5V, +15V +30V, +25: Parameter Input voltage Symbol ILIH ILIL ISTB Conditions -0.4mA +0.4mA VON| 0.5V +30V +20V Applicable Pins XCK, L/R, S/C, EIO1, EIO2, DISPOFF EIO1, EIO2 XCK, L/R, S/C, EIO1, EIO2, DISPOFF Y240 XCK, EIO1, EIO2, Min. 0.8VDD VDD-0.4 Typ. Max. 0.2VDD +0.4 Unit
Output voltage
Input leakage current
Output resistance Input pull-down current Stand-by current Supply current Supply current
Note1: +5.0V, +30V,
Note2: +5.0V, +30V, 41.6KHz, 80Hz case 1/480 duty operation, no-load.
6.4. Characteristics
6.4.1. Segment mode
Parameter Shift clock period
Shift clock pulse width Shift clock pulse width Data setup time Data hold time
Latch pulse pulse width
Shift clock rise latch pulse rise time Shift clock fall latch pulse fall time
Latch pulse rise shift clock rise time Latch pulse fall shift clock fall time Input signal rise time Input signal fall time Enable setup time
Symbol TWCK Conditions Min. 10ns TWCKH TWCKL 15pF 15pF 15pF TWLPH TWDL TPD1, TPD2 TPD3
Max.
Unit
(VSS +4.5V +5.5V, +15V +30V, +25: Typ.
DISPOFF removal time DISPOFF pulse width
Output delay time Output delay time Output delay time
Note1: Take cascade connection into consideration.
Note2: (TWCK TWCKH TWCKL) maximum case high speed operation.
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6.4.2. Segment mode
(VSS +3.0V +4.5V, +15V +30V, +25: Parameter Shift clock period Shift clock pulse width Shift clock pulse width Data setup time Data hold time Latch pulse pulse width Shift clock rise latch pulse rise time Shift clock fall latch pulse fall time Latch pulse rise shift clock rise time Latch pulse fall shift clock fall time Input signal rise time Input signal fall time Enable setup time Symbol TWCK TWCKH TWCKL TWLPH Conditions 10ns Min. Typ. Max. Unit
DISPOFF removal time
DISPOFF pulse width
Output delay time Output delay time Output delay time
Note1: Take cascade connection into consideration.
Note2: (TWCK TWCKH TWCKL) maximum case high speed operation.
6.4.3. Segment mode
Parameter Shift clock period
Shift clock pulse width Shift clock pulse width Data setup time Data hold time
Latch pulse pulse width
Shift clock rise latch pulse rise time Shift clock fall latch pulse fall time
Latch pulse rise shift clock rise time Latch pulse fall shift clock fall time Input signal rise time Input signal fall time Enable setup time
TWDL 15pF 15pF 15pF TPD1, TPD2 TPD3 Symbol TWCK Conditions Min. Typ. 10ns TWCKH TWCKL TWDL TPD1, TPD2 TPD3 15pF 15pF 15pF TWLPH
(VSS +2.5V +3.0V, +15V +30V, +25: Max. Unit
DISPOFF removal time DISPOFF pulse width
Output delay time Output delay time Output delay time
Note1: Take cascade connection into consideration.
Note2: (TWCK TWCKH TWCKL) maximum case high speed operation.
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6.4.3.1. Timing characteristics segment mode
TWLPH
TWCKH TWCKL
TWCK DATA
LAST DATA
TWDL
DISPOFF
4-bit parallel input mode. 8-bit parallel input mode.
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*Note: Recommand TPD4 10ns application which reduce power noise.
6.4.4. Common mode
Parameter Shift clock period
Shift pulse width Data setup time Data hold time
Input signal rise time Input signal fall time
DISPOFF removal time
DISPOFF pulse width
Output delay time Output delay time
Output delay time
Symbol TWLP Conditions Min. Typ. 20ns TWLPH +5.0V +2.5V +4.5V TWDL 15pF 15pF 15pF TPD1, TPD2 TPD3
Max.
Unit
(VSS +2.5V +5.5V, +15V +30V, +25:
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6.4.4.1. Timing chart common mode
TWLP
TWLPH EIO2 (DI7) EIO1
DISPOFF
*Note Recommand TPD4 10ns application which reduce power noise.
TWDL
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APPLICATION CIRCUIT
(Case bias)
Controller DISPOFF XD7-0 EIO2 DI7-0 DISP EIO1 EIO2 DI7-0 DISP
DI7DI0 DI7DI0 SEG1 SEG2 EIO1 EIO2 DI7-0 EIO1 EIO2 DI7-0 EIO1 DISP DISP SEG1919 SEG1920 EIO2 EIO1 EIO2 EIO1 DISP DISP COM479 COM480 COM1 COM2 Y240-1 Y240-1
50-100
SPLC562
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SPLC562
1920 MATRIX PANEL
Y240-1 Y240-1
SEP. 2004 Version:
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PACKAGE/PAD LOCATIONS
8.1. Assignment Locations
Please contact Sunplus sales representatives more information.
8.2. Ordering Information
Product Number SPLC562C SPLC562C Package Type Chip form with Bump Package form
Note: *The TCP's external shape customized. order your TCP's external shape, please contact SUNPLUS salesperson.
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DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHER, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications. Please note that application circuits
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. illustrated this document reference purposes only.
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REVISION HISTORY
Date SEP. 2004 DEC. 2003 FEB. 2003 SEP. 2002 APR. 2002
Revision Correct Timing diagram Note
Description
Page
Remove PACKAGE/PAD LOCATIONS" Remove "Preliminary" Correct pitch "8.1 Assignment" Correct type error Original Modify: pitch: "8.1 Assignment" "8.3 Align Coordinate"
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COM/SEG Driver SEP. 2004 Version SPLC562C Table Content

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