High-Voltage Durable 240-Channel Common Driver Dot-Matrix MAY. 20

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High-Voltage Durable 240-Channel Common Driver Dot-Matrix MAY. 20

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SPLC564A
High-Voltage Durable 240-Channel Common Driver Dot-Matrix
MAY. 2005 Version:
patent other rights third parties which result from use. addition, Sunplus products authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product reasonably expected result significant injury user, without express written approval Sunplus.
SPLC564A
Table Contents
PAGE
GENERAL DESCRIPTION FEATURES BLOCK DIAGRAM 3.1. INTERNAL BLOCK DIAGRAM 3.1.1. drive circuit.
3.1.2. Level shifter.
3.1.3. Shift register. 3.1.4. Alternating signal generating circuit
SIGNAL DESCRIPTIONS.
4.1. FUNCTIONS (CONT) ELECTRICAL SPECIFICATIONS 5.1. ABSOLUTE MAXIMUM RATINGS 5.1.1. Power 5.1.2. Shut down 5.2. CHARACTERISTICS 5.3. CHARACTERISTICS 5.4. CHARACTERISTICS 5.5. CHARACTERISTICS 5.6. TERMINAL CONFIGURATION 5.6.1. Terminal configuration 5.6.2. Terminal Configuration (2). APPLICATION CIRCUIT 6.1. APPLICATION EXAMPLE 6.2. POWER SUPPLY CIRCUIT EXAMPLE PACKAGE/PAD LOCATIONS 7.1. PACKAGE/PAD LOCATIONS. 7.2. ORDERING INFORMATION DISCLAIMER. REVISION HISTORY
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2005 Version:
SPLC564A
HIGH-VOLTAGE DURABLE 240-CHANNEL COMMON DRIVER DOT-MATRIX
GENERAL DESCRIPTION
SPLC564A 240-channel common driver which drives matrix panel. changing mode, this Through applied 240- 200- 160-channel output.
FEATURES
Display duty: 1/240 drive voltage: Built-in switching circuit generate -21.5V) Number drive circuit: Operating voltage: 2.5V 5.5V Intermediate voltage
high-voltage CMOS process technology, high-voltage drive +21.5V -21.5V, centering possible. used. -21.5V generated from +21.5V with built-in switching logic-drive voltage (3.0V) circuit external capacity. SPLC563A.
Built-in alternating signal generation circuit programmable Output mode change: 240-output mode 160-output mode
This device used together with segment driver
BLOCK DIAGRAM
VLCDL, VEEL,
Built-in display-off function Flex
200-output mode
X240
Drive Circuit
Level shifter
Level Shifter
Shift register
Shift register
Shift register
Shift register
Shift register
Logic
DISPOFF
SR20
SR21 SR40
SR41 SR200
SR201
SR220
SR221
SR240
Logic
Logic
Logic
Logic
Logic
Switch circuit
Logic
Alternating signal generating circuit
MODE1 DIO1 DIO2 MODE0
RESET
Logic
VLCDL VLCDR, VEEL VEER internally connected. VHR, VLR, internally connected.
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SPLC564A
3.1. Internal Block Diagram 3.1.1. drive circuit
This circuit selects outputs three level signals drive. circuit. combination data shift register either selected transmitted output
3.1.4. Alternating signal generating circuit
This circuit generates alternating signal signal) display. suppress cross-talk, signal alternated unit connecting MWS0 from several lines several tens lines. alternated.
MWS4 pins GND, desired number signals When alternating signals externally input, pins (MWS0 MWS4) connected GND.
3.1.2. Level shifter
This boosts 2.5V 5.5V signal high-voltage signal drive.
3.1.3. Shift register
This 240-bit bidirectional shift register circuit. sequentially shifted shift clock determined pin. first line marker signal output from DIO1, DIO2
shift direction
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SPLC564A
SIGNAL DESCRIPTIONS
Classification Power supply Symbol VLCDL VLCDR VEEL VEER VCC, 240, 284, 244, VEEL, Output Power supply Input Power supply drive level VHL, VHR: Selected level (Set same voltage VLCDL, VLCDR.) VEER.) VLL, VLR: Selected level (Set same voltage VEEL, VML, VMR: Non-selected level connect VEEL, VEER pins. between VLCD Connected Power supply Functions VLCDL, VLCDR-VEEL, VEER: Power supply drive VLCDL, VLCDR: Power supply switch circuit -GND: Power supply logic circuit
When built-in switching circuit generate VEE, reversed output voltage input voltage
Control signal
don't connect lines this pin. 246, 248, Capacitance switch circuit generate VEE. this pin. Input Shift clock input. clock shift register. Extension driver MWS0 Input MWS1 MWS2 MWS3 MWS4 unit number lines. specify number lines zero.
Number lines MWS4 MWS3 MWS2 MWS1 MWS0
voltage point reference
built-in switching circuit used,
External capacitance should connected here when using built-in switching circuit used, don't connect lines Data shifted falling edge shift
Inputs outputs alternating current drive output. This specifies cycle alternating signal signal) number lines, which integer from specified follows. Usually, specify number lines within range from When SPLC564A driven external alternating signal,
Line alternating waveform Prohibited lines alternated lines alternated lines alternated
M-pin status Input
Output
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4.1. Functions (cont)
Class Control signal Symbol MODE0 MODE1 Connected Type Input Functions
Switch terminals number drive output pins
MODE0 MODE1 Shift direction 240-output (X1, X3.X238, X239, X240) 200-output (X21, X22, X23.X218, X219, X220) 160-output (X41, X42, X43.X198, X199, X200) Prohibited
DIO1 DIO2
Extension driver
Serial data input output
level level DIO1 Serial output Serial iutput
DISPOFF
GND. Input Built-in switching circuit on-off control. VCC. fixex GND.
Input
Built-in switching circuit clock input.
switching circuit generate VEE, this connect pin. built-in switching circuit used, must fixed
DIO2
Serial iutput Serial output
When built-in
When built-in switching circuit, this must fixed built-in switching circuit used, this must
RESET
Input
Setting this sets initializes alternating signal signal) circuit. level RESET normally used. Setting this sets drive output X240 level. Controls display-off function, display-off signal output
Input
Input
from pin.
Output
level
When DISPOFF level, output level When DISPOFF high level, output high level
level
DISPOFF
Until serial data input times output level from
DIO1,
When using level, should connect Dispoff control pin.
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SPLC564A
Class Symbol Connected Type Input Functions This switches shift directions.
MODE0 MODE1 Shift direction Right shift level DIO2->SR1->.->SR240->DIO1 DIO2->SR21->.->SR220->DIO1 DIO2->SR41->.->SR200->DIO1 Left shift level DIO1->SR240->.->SR1->DIO2 DIO1->SR220->.->SR21->DIO2 DIO1->SR200->.->SR41->DIO2
SR1, correspond
Note: pins invalidated 200-output 160-output mode output non- selected level synchronized every time;
drive output
x220
X221 X234 X235 X240
Note1: Configuring panel using SPLC564A when using selected SEGMENT driver.
release these pins.
Output
drive output
combination display data signal, when
DISPOFF VCC, either selected
transmitted output circuit.
Output level
Note:
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2005 Version:
SPLC564A
ELECTRICAL SPECIFICATIONS
5.1. Absolute Maximum Ratings
Item Power supply voltage logic circuits Power supply voltage drive circuits Input voltage Input voltage Input voltage Input voltage Operating temperature Storage temperature Symbol VLCD TOPR TSTG Rating -0.3 -0.3 -0.3 -0.3 VLCD -0.3 +110 Unit Notes
Notes: used beyond above maximum ratings, permanently damaged. Note: Voltage from
should always used within specified operating range normal operation prevent malfunction degraded reliability.
Applicable DIO1, DISPOFF SHL, NWS0, NWS1, NWS2, NWS3, NWS4, RESET MODE0, MODE1, AMP, CCL, DIO2 Applicable VLCDL, pins. Applicable VEEL pins. Applicable VHL, pins. Applicable VLL, pins. (Caution)
Applicable VML, pins.
Operating excess absolute maximum rating will result permanent damage. reliability.
observing electrical characteristic conditions normal operation. Exceeding conditions will cause malfunctions will affect Observe sequence activation inactivation following power supplies signals. this sequence apply built-in switching circuit.
sequence observed, cause malfunction, permanent damage, adverse effects.
2.5V 2.5V VLCD, VEE, DISPOFF Input signal, clock, data Undefined Initialization (Longer than frame)
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SPLC564A
5.1.1. Power
Turn power supply order VCC, -VLCD (VH), input DISPOFF pin. level forcibly outputs level DISPOFF function. DISPOFF function priority even input signal distortion occurs immediately after input. Then input predetermined signals initialize driver registers. Preparation normal display thus completed. this case, assure period more than frame. this point, Cancel DISPOFF function setting DISPOFF VCC. VM-VEE generated automatically. this case,
levels (VL), VLCD (VH) must reached predetermined respective voltage.
5.1.2. Shut down
rule, shut down order opposite that used power DISPOFF GND.
first shut power supply GND-VLCD (VH), same time GND-VEE (VL) input signal GND. this point, (VL), VLCD (VH) input must completely drop Therefore, incorrect display appear shut down power
Since DISPOFF function inactivated when level drops GND, output output level other than
5.2. Characteristics
Item
Input high voltage
Input voltage
Output high-level voltage Output low-level voltage resistance between Input leakage current
Symbol PINs Min. Typ. Max. Unit DIO1, DISPOFF SHL, MWS0-4,
Next shut
Notes
(VCC 2.5V 5.5V, VLCD 43V, +75) Test Condition
RESET
MODE0, MODE1,
AMP, CCL, DIO2
DIO1, DIO2
-0.4mA 0.4mA 150A
DIO1, DIO2 X240,
IIL1
DIO1, DISPOFF SHL, MWS0-4,
-5.0
RESET MODE0,
MODE1, AMP, CCL, DIO2 Input leakage current Input leakage consumption ICC1 3.3V, VLCD 40V, 19.2KHz, 1.5KHz Sunplus Technology Co., Ltd. Proprietary Confidential MAY. 2005 Version: IIL2
SPLC564A
Item Current consumption Symbol ICC2 PINs Min. Typ. Max. Unit Test Condition 5.0V, VLCD 40V, 19.2KHz, 1.5KHz Current consumption ILCD VLCD 3.3V, VLCD 40V, 19.2KHz, 1.5KHz
Note1: This resistance value between pins (either when load current applied X240 pins. These values regulated under conditions VLCD 21.75V, -18.5V, 1.75V, range VLCD VMVH-VM 21.5 7.5V, VMVL -21.5 -7.5V, with relation Note2: current applied between input output excluded. When input CMOS gate intermediate level, through current flows between power supplies power supply current increases. Therefore, GND. Note3: voltage relationship each signal follows:
Segment Voltage
Notes
(5.0V)
(3.3V) (3.0V)
(1.0V) (0.0V)
Segment wavform Common wavform Normal display period Display-off period Normal display period Display-off period
Common Voltage (23.0V)
(3.3V) (3.0V)
(0.0V)
(-17.0V)
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5.3. Characteristics
(VCC 2.5V 5.5V, VLCD 43V, -30°C +75°C) Item Clock cycle time Clock high-level width Clock low-level width rising time falling time Data setup time Data hold time Data output delay time output delay time setup time hold time Symbol tCYC tCWH tCWL PINs DIO1, DIO2, DIO1, DIO2, DIO1, DIO2, Min. Max. Unit Note
delay time delay time
5.4. Characteristics
Item
Output delay time
5.5. Characteristics
Item
Output delay time
Notes: following timing regulated with circuit right connected.
tDOC1 tDOC2
DISPOFF
Max.
Note
DIO1, DIO2,
(VCC 2.5V 4.5V, VLCD 43V, -30°C +75°C) Min. Unit
Symbol tpd1
PINs
(n),
(VCC 4.5V 5.5V, VLCD 43V, -30°C +75°C) Min. Max. Unit Note
Symbol tpd1
PINs
(n),
Test Point
30pF 100pF
Figure Load circuit
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SPLC564A
tCWL
tCWH
tCYC
DIO1 DIO2
DIO1 DIO2
(During output)
X(n)
(During input)
tpd1
DISPOFF
DIO1 DIO2 (During input) tDOC1
tDOC2
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5.6. Terminal Configuration 5.6.1. Terminal configuration
Input Data
Input Terminal Applicable terminals: CCL, SHL, MODE0, DISPOFF, RESET, MWS0-4,
Input Terminal Applicable terminals:
Level Input Terminal
Level
*VHR terminal connect with terminal LSI.
Level
Input Terminal
Applicable terminals: VMR, *VMR terminal connect with terminal LSI.
Applicable terminals: VMR, *VMR terminal connect with terminal LSI.
Output Terminal Applicable terminals:
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5.6.2. Terminal Configuration
Input Data
Terminal Applicable terminals: DIO1, DIO2, VLCD VLCD
Data
Output enable
Terminal Applicable terminals:
Terminal Applicable terminals:
drive Output Terminal Applicable terminals: X240
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SPLC564A
APPLICATION CIRCUIT
6.1. Application Example
Figure shows application example (collar) Half Size color panel. This panel configured SPLC564A piece SPLC563 pieces. SPLC564A generates signal signal. connected pin. signal connected signal SPLC563A. SPLC564A able generates voltage external capacitor.
Note1: When designing board, connect capacitor near stabilize power supply. capacitors about 0.1F each (between GND, GND, VLCD GND, GND) Note2: addition, power supply circuit, connect capacitor several several tens between liquid-crystal power supply GND. evaluation, confirm that there inversion liquid-crystal drive power supply level power supply turned when turned off. Note3: When using external capacitor generate VEE, must connect capacitor several several tens between GND.
RESET DISPOFF NWS4-0 VHL, VML, VLL,
COM1 COM2 COM3
panel (collar) 1/240 duty
VLCD
Y320
Y320
Y320
EIO2 MODE
SPLC563A (No.
EIO1
EIO2 MODE
SPLC563A (No.
EIO1
EIO2 MODE
SPLC563A (No.
EIO1
Controller
Figure Application Example
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SEG958 SEG959 SEG960
SEG1 SEG2 SEG3
COM238 COM239 COM240
V0L,
DIO1 VLCDL.R VEEL,R SPLC564A DIO2 Power supply circuit
X240
D11-0 DISPOFF VML,
D11-0 DISPOFF VML,
D11-0 DISPOFF VML,
V0L,
V1L,
V0L,
V1L,
V1L,
MWS4
DISP
D11-0
MAY. 2005 Version:
SPLC564A
6.2. Power Supply Circuit Example
+21V
VLCD
DC-DC CONVERTER
+3.0V 5.0V
+2.7V 5.5V
Driver
External Capacitor (2.2~4.7F)
Driver SPLC564A
External Capacitor (2.2~4.7F)
Figure Power Supply Circuit Example
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MAY. 2005 Version:
SPLC564A
PACKAGE/PAD LOCATIONS
7.1. Package/PAD Locations
Please contact Sunplus sales representatives more information.
7.2. Ordering Information
Product Number SPLC564A-C SPLC564A-PT112 SPLC564A-PJ061 Package Type Chip form Package form 5SP, Package form 5SP,
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2005 Version:
SPLC564A
DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHERMORE, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications. Please note that application circuits
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. illustrated this document reference purposes only.
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2005 Version:
SPLC564A
REVISION HISTORY
Date MAY. 2005 Revision Description package information "SPLC564A-PJ061" Modify Terminal configuration Modify Terminal Configuration Correct Delete SPLC564A-PC011 ordering information FEB. 2004 package information Remove "Preliminary" JUN. 2003 Correct "4.2 Ordering Information" Remove PACKAGE/PAD LOCATIONS" JAN. 2003 Correct type error Correct "Bumped height": Original Page
JUL. 2001
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High-Voltage Durable 240-Channel Common Driver Dot-Matrix MAY. 20

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