Development Software Warp® IEEE 1076/1164 VHDL IEEE 1364 Verilog
|
|
|
Top Searches for this datasheet
Delta39KISRCPLD Family CPLDs FPGA DensitiesHigh density 200K usable gates 3072 macrocells maximum pins Twelve dedicated inputs including four clock pins, four global control signal pins four JTAG interface pins boundary scan reconfigurability Embedded memory 480K bits embedded SRAM 384K bits (single-port) cluster memory bits (dual-port) channel memory High speed 233-MHz in-system operation AnyVoltinterface 3.3V, 2.5V, 1.8V versions available 3.3V, 2.5V,1.8V, 1.5V capability versions Low-power operation 0.18-mm six-layer metal SRAM-based logic process Full-CMOS implementation product term array Standby current 1.8V Simple timing model penalty using full product terms/macrocell delay single product term steering sharing Flexible clocking Spread AwarePLL drives four clock networks Allows 0.6% spread spectrum input clocks Several multiply, divide phase shift options Offered with 3.3/2.5V versions only Four synchronous clock networks device Locally generated product term clock Clock polarity control each register Carry-chain logic fast efficient arithmetic operations Multiple standards supported LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), GTL+ Compatible with NOBLTM, ZBTTM, QDRSRAMs Programmable slew rate control each User-programmable Hold capability each Fully 3.3V compliant 64-bit spec, rev. 2.2) CompactPCI swap ready Multiple package/pinout offering across densities pins PQFP, BGA, FBGA packages Same pinout 3.3V/2.5V 1.8V devices Simplifies design migration across density Self-Bootsolution FBGA packages In-System Reprogrammable(ISRTM) JTAG-compliant on-board programming Design changes cause pinout changes IEEE1149.1 JTAG boundary scan
Development Software
Warp® IEEE 1076/1164 VHDL IEEE 1364 Verilog context sensitive editing Active-HDL graphical finite state machine editor Active-HDL post-synthesis timing simulator Architecture Explorer detailed design analysis Static Timing Analyzer critical path analysis Available Windows 95/98/2000/XPand Windows NTfor Supports Cypress programmable logic products
Delta39KISR CPLD Family Members
Typical Gates[1] 144K 241K 288K Cluster memory (Kbits) Channel memory (Kbits) Maximum Pins fMAX2 (MHz) Speed Pin-to-Pin (ns) Standby ICC[2] 25°C 3.3/2.5V 1.8V
Device 39K30 39K50 39K100 39K165 39K200
Macrocells 1536 2560 3072
Notes: Upper limit typical gates calculated assuming only channel memory used. Standby values with utilized, output load stable inputs.
Cypress Semiconductor Corporation Document 38-03039 Rev.
3901 North First Street
Jose
95134 408-943-2600 Revised December 2002
Delta39KISRCPLD Family
Delta39K Speed Bins[3]
Device 39K30 39K50 39K100 39K165 39K200 3.3/2.5V 1.8V 3.3/2.5V 1.8V 3.3/2.5V 1.8V 3.3/2.5V 3.3/2.5V 1.8V
Device Package Offering Count Including Dedicated Clock Control Inputs
Self-Boot Solution[4] EQFP 0.5-mm pitch FBGA 1.0-mm pitch 484-FBGA 1.0-mm pitch 256-FBGA 1.0-mm pitch 388-BGA 1.27-mm pitch 484-FBGA 1.0-mm pitch 676-FBGA 1.0-mm pitch
Device 39K30 39K50 39K100 39K165 39K200
Notes: Speed bins shown here commercial operating range. Please refer Delta39K ordering information industrial-range speed bins page Self-boot solution integrates boot PROM (flash memory) with Delta39K inside same package. This flash memory endure least 10,000 programming/erase cycles retain data least years.
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
GCLK[3:0]
Clock
GCTL[3:0]
GCLK[3:0]
Bank
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
GCLK[3:0]
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
GCLK[3:0]
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Bank
Bank
Figure Delta39K100 Block Diagram (Three Rows Four Columns) with Bank Structure
General Description
Delta39K family, based 0.18-mm, six-layer metal CMOS logic process, offers wide range high-density solutions unparalleled system performance. Delta39K family designed combine high speed, predictable timing, ease CPLDs with high densities power FPGAs. With devices ranging from 30,000 200,000 usable gates, family features devices times size previously available CPLDs. Even these large
densities, Delta39K family fast enough implement fully synthesizable 64-bit, 66-MHz core. architecture based Logic Block Clusters (LBC) that connected Horizontal Vertical routing channels. Each features eight individual Logic Blocks (LB) cluster memory blocks. Adjacent each channel memory block, which accessed directly from pins. Both types memory blocks highly configurable cascaded width depth. Figure block diagram Delta39K architecture.
Document 38-03039 Rev.
Page
Bank
Bank
Delta39KISRCPLD Family
members Delta39K family have Cypress's highly regarded In-System Reprogrammability (ISR) feature, which simplifies both design manufacturing flows, thereby reducing costs. feature provides ability reconfigure devices without having design changes cause pinout timing changes most cases. Cypress function implemented through JTAG-compliant serial interface. Data shifted through pins respectively. Superior routability, simple timing, allows users change existing logic designs while simultaneously fixing pinout assignments maintaining system performance. entire family features JTAG boundary scan, compatible with Local specification, meeting electrical timing requirements. Delta39K family also features user programmable bus-hold slew rate control capabilities each pin. AnyVolt Interface Delta39KV devices feature on-chip regulator, which accepts 3.3V 2.5V supply pins steps down 1.8V internally, voltage level which core operates. Delta39KZ devices accept 1.8V supply pins directly. With Delta39K's AnyVolt technology, pins connected either 1.8V, 2.5V, 3.3V. Delta39K devices 3.3V tolerant regardless VCCIO settings. Table Device 39KV 39KZ 3.3V 2.5V 1.8V VCCIO 3.3V 2.5V 1.8V 1.5V[5] 3.3V 2.5V 1.8V 1.5V[5]
Block
Global Routing Description routing architecture Delta39K made horizontal vertical routing channels. These routing channels allow signals from each Delta39K architectural components communicate with another. addition horizontal vertical routing channels that interconnect banks, channel memory blocks, logic block clusters, each contains Programmable Interconnect Matrix (PIMTM), which used route signals among logic blocks cluster memory blocks. Figure block diagram routing channels that interface within Delta39K architecture. exactly same every member Delta39K CPLD family. Logic Block Cluster (LBC) Delta39K architecture consists several logic block clusters, each which have eight Logic Blocks (LB) cluster memory blocks connected Programmable Interconnect Matrix (PIM) shown Figure Each cluster memory block consists 8-Kbit single-port RAM, which configurable synchronous asynchronous. cluster memory blocks cascaded with other cluster memory blocks within same well other LBCs implement larger memory functions. cluster memory block specifically utilized designer, Cypress's Warp software automatically implement large blocks logic. LBCs interface with each other horizontal vertical routing channels.
Cluster Memory Block
Cluster
Cluster Memory Block
Channel Memory Block
Channel memory outputs drive dedicated tracks horizontal vertical routing channels
Block
H-to-V V-to-H
inputs from cells drive dedicated tracks horizontal vertical routing channels
Figure Delta39K Routing Interface
Note: HSTL only.
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Clock Inputs GCLK[3:0]
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Cluster Memory
Cluster Memory
Carry Chain
Inputs From Horizontal Routing Channel
Inputs From Vertical Routing Channel
Outputs Horizontal Vertical cluster-to-channel PIMs
Figure Delta39K Logic Block Cluster Diagram Logic Block (LB) logic block basic building block Delta39K architecture. consists product term array, intelligent product-term allocator, macrocells. Product Term Array Each logic block features programmable product term array. This array accepts inputs from PIM. These inputs originate from device pins macrocell feedbacks well cluster memory channel memory feedbacks. Active active HIGH versions each these inputs generated create full 72-input field. product terms array created from inputs. product terms, general-purpose macrocells logic block. remaining three product terms logic block used asynchronous asynchronous reset product terms. final product term Product Term clock (PTCLK) shared macrocells within logic block. Product Term Allocator Through product term allocator, Warp software automatically distributes product terms needed among macrocells logic block. product term allocator provides important capabilities without affecting performance: product term steering product term sharing. Product Term Steering Product term steering process assigning product terms macrocells needed. example, macrocell requires product terms while another needs just three, product term allocator will "steer" product terms macrocell three other. Delta39K devices, product terms steered individual basis. number between product terms steered macrocell. Product Term Sharing Product term sharing process using same product term among multiple macrocells. example, more than function more product terms equation that common other functions, those product terms only programmed once. Delta39K product term allocator allows sharing across groups four macrocells variable fashion. software automatically takes advantage this capability that user does have intervene. Note that neither product term sharing product term steering have effect speed product. steering sharing configurations have been incorporated timing specifications Delta39K devices.
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Macrocell Within each logic block there macrocells. Each macrocell accepts product terms from product term array. these product terms output either registered combinatorial mode. Figure displays block diagram macrocell. register asynchronously preset asynchronously reset macrocell level with separate preset reset product terms. Each these product terms features programmable polarity. This allows registers preset reset based expression expression. gate Delta39K macrocell allows many different types equations realized. used polarity implement true complement form equation product term array toggle turn flip-flop into flip-flop. carry-chain input allows additional flexibility implementation different types logic. macrocell utilize carry chain logic implement adders, subtractors, magnitude comparators, parity tree, even generic logic. output macrocell either registered combinatorial. Carry Chain Logic Delta39K macrocell features carry chain logic which used fast efficient implementation arithmetic operations. carry logic connects macrocells four logic blocks total macrocells. Effective data path operaCarry (from macrocell n-1)
tions implemented through carry-in arithmetic, which drives through circuit quickly. Figure shows that carry chain logic within macrocell consists product terms (CPT0 CPT1) from input carry-in carry logic. inputs carry chain connected directly product terms PTA. output carry chain generates carry-out next macrocell logic block well local carry input that connected input input mux. Carry-in configuration inputs gate. This gate provides method segmenting carry chain macrocell logic block. Macrocell Clocks Clocking register highly flexible. Four global synchronous clocks (GCLK[3:0]) Product Term clock (PTCLK) available each macrocell register. Furthermore, clock polarity within each macrocell allows register clocked rising falling edge (see macrocell diagram Figure PRESET/RESET Configurations macrocell register asynchronously preset reset using PRESET RESET mux. Both signals active high controlled either Preset/Reset product terms (PRC[1:0] Figure GND. situations where PRESET RESET active same time, RESET takes priority over PRESET.
PRESET
Carry Chain CPT0 CPT1
Input
Output
PSET
FROM Clock GCLK[3:0] PTCLK Clock Polarity
PRC[1:0]
Carry macrocell n+1)
RESET
Figure Delta39K Macrocell
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Embedded Memory Each member Delta39K family contains types embedded memory blocks. channel memory block placed intersection horizontal vertical routing channels. Each channel memory block 4096 bits size configured asynchronous synchronous Dual-Port RAM, Single-Port RAM, Read-Only memory (ROM), synchronous FIFO memory. memory organization configurable 512K second type memory block located within each referred cluster memory block. Each contains cluster memory blocks that 8192 bits size. Similar channel memory blocks, cluster memory blocks configured asynchronous synchronous Single-Port ROM. Cluster Memory Each logic block cluster Delta39K contains 8192-bit cluster memory blocks. Figure block diagram cluster memory block interface cluster memory block cluster PIM. output cluster memory block optionally registered perform synchronous pipelining register asynchronous Read Write operations. output registers contain asynchronous RESET which used type sequential logic circuits (e.g., state machines). There four global clocks (GCLK[3:0]) local clock available input output registers. local clock input registers independent used output registers. local clock generated user design macrocell comes from pin. Cluster Memory Initialization cluster memory powers undefined state, user-defined known state during configuration. facilitate look-up-table (LUT) logic applications, cluster memory blocks initialized with given data when device configured power applications, user cannot write memory blocks. Channel Memory Delta39K architecture includes embedded memory block each crossing point horizontal vertical routing channels. channel memory 4096-bit embedded memory block that configured asynchronous synchronous single-port RAM, dual-port RAM, ROM, synchronous FIFO memory. Data, address, control inputs channel memory driven from horizontal vertical routing channels. data FIFO logic outputs drive dedicated tracks horizontal vertical routing channels. clocks channel memory block selected from four global clocks inputs from horizontal vertical channels. clock muxes also include polarity each clock that user choose inverted clock. Dual-Port (Channel Memory) Configuration Each port distinct address inputs, well separate data control inputs that accessed simultaneously. inputs Dual-Port memory driven from horizontal vertical routing channels. data outputs drive dedicated tracks routing channels. interface routing such that Port Dual-Port interfaces primarily with horizontal routing channel Port interfaces primarily with vertical routing channel.
Write Control Logic ADDR[12:0]
DIN[7:0]
Decode (1024 Rows)
Write Pulse
Cluster
GCLK[3:0] Local DOUT[7:0]
1024x8 Asynchronous SRAM
Read Control Logic
RESET
GCLK[3:0] Local
Figure Block Diagram Cluster Memory Block
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
clocks each port Dual-Port configuration selected from four global clocks local clocks. local clock sourced from horizontal channel other from vertical channel. data outputs dualport memory also registered. Clocks output registers also selected from four global clocks local clocks. clock polarity port allows true complement polarity input output clocking purposes. Arbitration Dual-Port configuration Channel Memory Block provides arbitration when both ports access same address same time. Depending memory operation being attempted, port always gets priority. Table details which port gets priority Read Write operations. active-LOW "Address Match" signal generated when address collision occurs. Table Arbitration Result: Address Match Signal Becomes Active Result Port Port Arbitration Read Write Read Read arbitration required Port gets priority Comment Both ports read same time Port requests first then will read current data. output will then change newly written data Port Port requests first then will read current data. output will then change newly written data Port Port blocked until Port finished writing FIFO block contains necessary FIFO flag logic, including Read Write address pointers. FIFO flags include empty/full flag (EF), half-full flag (HF), programmable almost-empty/full (PAEF) flag output. FIFO configuration ability perform simultaneous Read Write operations using separate clocks. These clocks tied together single operation independently asynchronous Read/Write (with regard each other) applications. data control inputs FIFO block driven from horizontal vertical routing channels. data flag outputs driven onto dedicated routing tracks both horizontal vertical routing channels. This allows FIFO blocks expanded using multiple FIFO blocks same horizontal vertical routing channel without speed penalty. FIFO mode, Write Read ports controlled separate clock enable signals. clocks each port selected from four global clocks local clocks. local clock sourced from horizontal channel other from vertical channel. data outputs from Read port FIFO also registered. clock polarity port allows using true complement polarity Read Write operations. Write operation controlled clock Write enable pin. Read operation controlled clock Read enable pin. enable pins sourced from horizontal vertical channels. Channel Memory Initialization channel memory powers undefined state, user-defined known state during configuration. facilitate look-up-table (LUT) logic applications, channel memory blocks initialized with given data when device configured power applications, user cannot write memory blocks. Channel Memory Routing Interface Similar outputs, channel memory blocks feature dedicated tracks horizontal vertical routing channels data outputs flag outputs, shown Figure This allows channel memory blocks expanded easily. These dedicated lines routed pins chip outputs other logic block clusters used logic equations.
Read
Write
Port gets priority
Write
Write
Port gets priority
FIFO (Channel Memory) Configuration channel memory blocks also configurable synchronous FIFO RAM. FIFO mode operation, channel memory block supports normal FIFO operations without general-purpose logic resources device.
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
channel memory inputs driven from routing channels
4096-bit Dual-Port Array
Configurable Async/Sync Dual-Port Sync FIFO
Global Clock Signals
Configurable block sizes
GCLK[3:0]
Vertical Channel
channel memory outputs drive dedicated tracks routing channels
Horizontal Channel
Figure Block Diagram Channel Memory Block Banks Delta39K interfaces horizontal vertical routing channels pins through banks. There eight banks device shown Figure I/Os from bank located same section package layout convenience. Delta39K devices support True Vertical Migration(i.e., each package type, Delta39K devices different densities keep given pins same banks). This allows easy simple implementation multiple standards during design prototyping phase, before final density been determined. Please refer application note titled "Family, Package Density Migration Delta Quantum38K CPLDs." Each bank contains several cells, each cell contains input/output register, output enable register, programmable slew rate control programmable hold control logic. Each cell drives output device; cell also supplies input device that connects dedicated track associated routing channel. Each bank supported standard supplying appropriate VREF VCCIO voltages configuring through Warp software. VREF VCCIO pins bank must connected same VREF VCCIO voltage respectively. This requirement restricts number standards supported bank given time. number I/Os which used each bank depend type standards number VCCIO pins being used. This restriction derived from electromigration limit VCCIO bussing chip. Please refer note page application note titled "Delta39K Family Device Standards Configurations" details. Cell Figure block diagram Delta39K cell. cell contains three-state input buffer, output buffer, register that configured input output register. output buffer slew rate control option that used configure output slower slew rate. input device output each configured registered combinatorial; however, only path configured registered given design. output enable cell selected from four global control signals from Output Control Channel (OCC) signals. output enable configured always enabled always disabled controlled remaining inputs mux. selection done that includes inputs.
bank bank bank
bank bank bank
Page
Delta39K Delta39K
bank
bank
Figure Delta39K Bank Block Diagram
Document 38-03039 Rev.
Delta39KISRCPLD Family
Registered
From Output
Input
Routing Channel
Output Control Channel
Global Clock Signals
Global Control Signals
Register Input
Output
Register Enable Clock Polarity
Hold
Clock
Slew Rate Control
Register Reset
Figure Block Diagram Cell Signals There four dedicated inputs (GCTL[3:0]) that used Global Control Signals available every cell. These global control signals used output enables, register resets register clock enables shown Figure These global control signals, driven from four dedicated pins, only used active-high signals available only cells thereby implementing fast resets, register output enables. addition, there signals available each cell. These control signals used output enables, register resets register clock enables shown Figure Unlike global control signals, these signal driven from internal logic pin. four global clocks selected clock cell register. clock output input clock polarity that allows input/output register clocked either edge clock Slew Rate Control output buffer slew rate control option. This allows output buffer slew fast rate V/ns) slow rate V/ns). I/Os default fast slew rate. designs concerned with meeting emissions standards slow edge provides lower system noise. designs requiring very high performance fast edge rate provides maximum system performance. Table Standards Standard LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V GTL+ SSTL3 SSTL3 SSTL2 SSTL2 HSTL HSTL HSTL HSTL 1.15 1.15 0.68 0.68 0.68 0.68 1.35 1.35 VREF Min. Max. 3.3V 3.3V 3.0V 2.5V 1.8V 3.3V 3.3V 3.3V 2.5V 2.5V 1.5V 1.5V 1.5V 1.5V 1.25 1.25 0.75 0.75 VCCIO Termination Voltage (VTT)
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Programmable Hold each pin, user-programmable-bus-hold included. Bus-hold, which improved version popular internal pull-up resistor, weak latch connected that does degrade device's performance. latch, bus-hold maintains last state when placed high-impedance state, thus reducing system noise businterface applications. Bus-hold additionally allows unused device pins remain unconnected board, which particularly useful during prototyping designers route signals device without cutting trace connections GND. more information, application note titled "Understanding Bus-Hold-A Feature Cypress CPLDs." Clocks Delta39K four dedicated clock input pins (GCLK[3:0]) accept system clocks. these clocks (GCLK[0]) selected drive on-chip phase-locked loop (PLL) frequency modulation (see Figure details). global clock tree Delta39K device driven combination dedicated clock pins and/or PLLderived clocks. global clock tree consists four global clocks that every macrocell, memory block, cell. Clock Tree Distribution global clock tree performs primary functions. First, clock tree generates four global clocks multiplexing four dedicated clocks from package pins four driven clocks. Second, clock tree distributes four global clocks every cluster, channel memory, block die. global clock tree designed such that clock skew minimized while maintaining acceptable clock delay. Spread AwarePLL Each device Delta39K family features on-chip designed using Spread Aware technology applications. general, PLLs used implement time-divisionoff-chip signal (external feedback) INTCLK0, INTCLK1, INTCLK2, INTCLK3 Register (TFF) Send global clock chip GCLK1 Normal signal path Lock Detect/IO
multiplex circuits achieve higher performance with fewer device resources. example, system that operates 32-bit data path that runs implemented with 16-bit circuitry that runs internally MHz. PLLs also used take advantage positioning internally generated clock edges shift performance towards improved setup, hold clock-to-out times. There several frequency multiply (X1, X16) divide (/1, /16) options available create wide range clock frequencies from single clock input (GCLK[0]). increased flexibility, there seven phase shifting options which allow clock skew/de-skew 45°, 90°, 135°, 180°, 225°, 270°, 315°. Spread Aware feature refers ability track spread-spectrum input clock such that spread seen output clock with staying locked. total amount spread input clock should limited 0.6% fundamental frequency. Spread Aware feature supported only with multiply options. Voltage Controlled Oscillator (VCO), core Delta39K designed operate within frequency range MHz. Hence, multiply option combined with input (GCLK[0]) frequency should selected such that this operating frequency requirement met. This demonstrated Table (columns Another feature this ability drive output clock (INTCLK) Delta39K chip clock other devices board, shown Figure above. This off-chip clock half frequency output clock through register (I/O register macrocell register). This also used board de-skewing purpose driving output clock off-chip, routing other devices board feeding back PLL's external feedback input (GCLK[1]). When this feature used, only limited multiply, divide phase shift options used.
Clock Tree Delay
Phase selection Divide
1-6,8,16 INTCLK0 GCLK0 Lock Phase selection Divide 1-6,8,16 INTCLK1 GCLK1 Phase selection Divide 1-6,8,16 INTCLK2 GCLK2 Phase selection Divide 1-6,8,16 INTCLK3 GCLK3
GCLK0
Source Clock
GCLK[3:0]
Figure Block Diagram Spread Aware Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table describes valid multiply divide options that used without external feedback. Table describes valid multiply divide options that used with external feedback. Table describes valid phase shift options that used with without external feedback. clock. Note that duty cycle 50-50 when output divided even number. Also note that phase shift applies output divided output. Spread Aware operates specified Delta39KV devices (2.5V/3.3V), Delta39KZ devices (1.8V). more details architecture operation this please refer application note entitled "Delta39K Clock Tree".
Table example effect available divide phase shift options output MHz. also shows effect division duty cycle resultant Table Valid Multiply Divide Options-without External Feedback Input Frequency (GCLK[0]) fPLLI (MHz) DC-12.5 100-133 50-133 33.3-88.7 25-66 20-53.2 16.6-44.3 12.5-33 12.5-16.625 Valid Multiply Options Value Output Frequency (MHz) 100-133 100-266 100-266 100-266 100-266 100-266 100-266 200-266 Value 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6,
Valid Divide Options Output Frequency (INTCLK[3:0]) fPLLO (MHz) DC-12.5 6.25-133 6.25-266 6.25-266 6.25-266 6.25-266 6.25-266 6.25-266 6.25-266 Off-chip Clock Frequency DC-6.25 3.125-66 3.125-133 3.1-266 3.125-133 3.1-133 3.1-133 3.125-133 3.125-133
Table Valid Multiply Divide Options-with External Feedback Valid Multiply Options Input (GCLK) Frequency fPLLI (MHz) 50-133 25-66.5 16.67-44.33 12.5-33.25 12.5-26.6 12.5-22.17 12.5-16.63 Value Output Frequency (MHz) 100-266 100-266 100-266 100-266 125-266 150-266 200-266 Value Valid Divide Options Output (INTCLK) Frequency fPLLO (MHz) 100-266 50-133 33.33-88.66 25-66.5 25-53.2 25-44.34 25-33.25 Off-chip Clock Frequency 50-133 25-66.5 16.67-44.33 12.5-33.25 12.5-26.6 12.5-22.17 12.5-16.63
Table Recommended Phase Shift Options without External Feedback 0°,45°, 90°, 135°, 180°, 225°, 270°, 315° with External Feedback
Table Timing Clock Phases Divide Options Output Frequency Divide Factor Period (ns) Duty Cycle% 40-60 33-67 40-60 (ns) (ns) (ns) 135° (ns) 180° (ns) 225° (ns) 270° (ns) 315° (ns)
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
CompactPCI Swap CompactPCI Swap specification allows removal insertion cards into CompactPCI sockets without switching-off bus. Delta39K CPLDs used CompactPCI host target these cards. This feature useful telecommunication networking applications allows implementation high availability systems, where repairs upgrades done without downtime. Delta39K CPLDs CompactPCI Swap Ready CompactPCI Swap specification R2.0, with following exception: cells provide bias voltage support. External resistors used achieve this, section 3.1.3.1 CompactPCI Swap specification R2.0. simple board level solution provided application note titled "Hot-Swapping Delta39K Quantum38K CPLDs." Timing Model important feature Delta39K family simplicity timing. combinatorial registered/synchronous delays worst case system performance static shown specs section) long data routed through same horizontal vertical channels. Figure illustrates true timing model 200-MHz devices. synchronous clocking macrocells, delay incurred from macrocell clock macrocell clock separate Logic Blocks within same cluster, well separate Logic Blocks within different clusters. This respectively shown tSCS tSCS2 Figure combinatorial paths, input output (from corner corner device), incurs worstcase delay 39K100 regardless amount logic which horizontal vertical channels used. This shown Figure synchronous systems, input setup time output macrocell register clock output time shown parameters tMCS tMCCO shown Figure These measurements output synchronous clock, regardless logic placement. Delta39K features: dedicated delays penalty using product terms added delay steering product terms added delay sharing product terms output bypass delays. simple timing model Delta39K family eliminates unexpected performance penalties. Family, Package, Density Migration Delta39K CPLDs Delta39K CPLDs combine dense logic, embedded memory configurable standards. Further design flexibility added easy migration options available between different packages, densities even between Quantum38K Delta39K CPLD families. (For details Quantum38K CPLD family refer Quantum38K CPLD family data sheet). This migration flexibility makes changes additions designs simple even after layout. also provides ability experimental designs used production PCBs. Please refer application note titled "Family, Package, Density Migration Delta39K CPLDs."
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
tSCS
GCLK[3:0] Channel Channel Channel Channel
Cluster Cluster
Cluster Cluster
SRAM SRAM
tMCS
Cluster
Cluster
GCLK[3:0] Channel Channel Channel Channel
tSCS2
Cluster Cluster
Cluster Cluster
Cluster Cluster
Cluster
Cluster
GCLK[3:0] Channel Channel Channel Channel
Cluster Cluster
Cluster Cluster
Cluster Cluster
Cluster Cluster
tMCCO
Figure Timing Model 39K100 Device IEEE 1149.1-compliant JTAG Operation Delta39K family IEEE 1149.1 JTAG interface both Boundary Scan operations. Four dedicated pins reserved each device Test Access Port (TAP). Boundary Scan Delta39K family supports Bypass, Sample/Preload, Extest, Intest, Idcode Usercode boundary scan instructions. JTAG interface shown Figure In-System Reprogramming (ISR) In-System Reprogramming combination capability program reprogram device on-board, ability support design changes without changing system timing device pinout. This combination means design changes during debug field upgrades cause board respins. Document 38-03039 Rev. Delta39K family implements providing JTAG compliant interface on-board programming, robust routing resources pinout flexibility, simple timing model consistent system performance. Configuration Each device Delta39K family available volatile Self-Boot package. Cypress's CPLD boot EEPROM used store configuration data volatile solution embedded on-chip FLASH memory device used SelfBoot solution. volatile Delta39K packages, programming defined loading user's design into external CPLD boot EEPROM. Self-Boot Delta39K packages, programming defined loading user's design into on-chip FLASH internal Delta39K package. Configuration defined loading user's design into Delta39K die. Page
Delta39KISRCPLD Family
Instruction Register
Bypass Reg. Boundary Scan idcode Usercode Prog.
Delta39K devices complete desired reconfiguration diagnostic operations. Contact your local sales office information availability this option. Programming
TCLK
JTAG CONTROLLER
on-chip FLASH device Delta39K Self-Boot package programmed issuing appropriate IEEE 1149.1 JTAG instruction internal FLASH memory JTAG interface. This done automatically using ISR/STAPL software. configuration bits sent from through JTAG port into Delta39K C3ISR programming cable. data then internally passed from Delta39K on-chip FLASH. more information program Delta39K through ISR/STAPL, please refer ISR/STAPL User Guide. external CPLD boot EEPROM used store configuration data Delta39K volatile package programmed through Cypress's CYDH2200E CPLD Boot PROM Programming two-wire interface. more information program CPLD boot EEPROM, please refer data sheet titled "CYDH2200E CPLD Boot PROM Programming Kit." more information architecture timing specification boot EEPROM, refer data sheet titled "512K/1Mb CPLD Boot EEPROM" "2-Mbit CPLD Boot EEPROM." Third-Party Programmers Cypress support available wide variety third-party programmers. major programmers (including Micro, System General, Hi-Lo) support Delta39K family.
Data Registers Figure JTAG Interface Configuration begin ways. initiated toggling Reconfig from HIGH, issuing appropriate IEEE 1149.1 JTAG instruction Delta39K device JTAG interface. There IEEE 1149.1 JTAG instructions that initiate configuration Delta39K. Self Config instruction causes Delta39K (re)configure with data stored serial boot PROM embedded FLASH memory. Load Config instruction causes Delta39K (re)configure according data provided other sources such automatic test equipment (ATE), embedded micro-controller/processor JTAG interface. more information configuring Delta39K devices, refer application note titled "Configuring Delta39K/Quantum38K" http://www.cypress.com. There configuration options available issuing IEEE 1149.1 JTAG instructions Delta39K. first method with C3ISR programming cable software. With this method, pins Delta39K devices system routed connector edge printed circuit board. C3ISR programming cable then connected between this connector. simple configuration file instructs software programming operations performed Delta39K devices system. software then automatically completes necessary data manipulations required accomplish configuration, reading, verifying, other functions. more information Cypress interface, Programming data sheet (CY3900i). second configuration option Delta39K utilize embedded controller processor that already exists system. Delta39K software assists this method converting device file into serial stream that contains instruction information addresses data locations configured. embedded controller then simply directs this stream chain
Development Software Support
Warp Warp state-of-the-art design environment designing with Cypress programmable logic. Warp utilizes subset IEEE 1076/1164 VHDL IEEE 1364 Hardware Description Language (HDL) design entry. Warp accepts VHDL Verilog input, synthesizes optimizes entered design, outputs configuration bitstream desired Delta39K device. simulation, Warp provides graphical waveform simulator well VHDL Verilog Timing Models. VHDL Verilog open, powerful, non-proprietary Hardware Description Languages (HDLs) that standards behavioral design entry simulation. allows designers learn single language that useful facets design process. Third-Party Software Cypress products supported number third-party design entry simulation tools. Refer third-party software data sheet contact your local sales office list currently supported third party vendors.
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature (39k200, EQFP) -45°C +125°C Storage Temperature (all other densities packages). -65°C +150°C Soldering Temperature. 220°C Ambient Temperature with Power Applied. -40°C +85°C Junction Temperature 135°C Ground Potential (39KZ device) .-0.5V 2.5V Ground Potential (39KV device) .-0.5V 4.6V VCCIO Ground Potential. .-0.5V 4.6V Voltage Applied Outputs High-Z state -0.5V 4.5V Input voltage. .-0.5V 4.5V Current into Outputs. mA[6] Static Discharge Voltage (per JEDEC EIA./ JESD22-A114A). >2001V Latch-up Current >200
Operating Range
Range Ambient Temperature +70°C Commercial Junction Temperature +85°C Output Condition 3.3V 2.5V 1.8V 1.5V -40°C +85°C Industrial -40°C +100°C 3.3V 2.5V 1.8V 1.5V VCCIO 3.3V 0.3V 2.5V 0.2V 1.8V 0.15V 1.5V 0.1V[5] 3.3V 0.3V 2.5V 0.2V 1.8V 0.15V 1.5V 0.1V[5] VCCJTAG/ VCCCNFG VCCPLL VCCPRG 3.3V 0.3V
3.3V 0.3V Same Same 2.5V 0.2V VCCIO (39KV) 1.8V 0.15V (39KZ)
Characteristics
Parameter VDRINT VDRIO IIX[7] IOS[8] IBHL IBHH IBHLO IBHHO ICC0 Description Data Retention Voltage (config data lost below this) Data Retention VCCIO Voltage (config data lost below this) Input Leakage Current Output Leakage Current Output Short Circuit Current 3.6V VCCIO VCCIO Max. VOUT 0.5V +250 -250
bins
Test Conditions
VCCIO 3.3V VCCIO 2.5V Min. -160 +200 -200
bins
VCCIO 1.8V Max. Unit -160 +150 -150
-125
Max.
Min.
Max. Min. -160
Input Hold Sustaining Current Min. VPIN Input Hold HIGH Sustaining Current Min. VPIN Input Hold Overdrive Current Input Hold HIGH Overdrive Current Standby Current 39K30 39K50 39K100 39K165 39K200 Max. Max.
Notes: current into outputs with HSTL III, with HSTL with GTL+ (with pull-up resistor 1.5).
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Input Leakage current ±10µA pins Delta39K package except following pins Delta39K100 packages: input leakage current spec these pins ±200µA
Delta39K100 Package 388-BGA 484-FBGA 676-FBGA Pins F11,
more than output should tested time. Duration short circuit should exceed second. VOUT 0.5V been chosen avoid test problems caused tester-ground degradation. Tested initially after design process changes that affect these parameters.
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Capacitance
Parameter CI/O CCLK CPCI Description Input/Output Capacitance Clock Signal Capacitance Compliant[9] Capacitance Test Conditions VCCIO 25°C VCCIO 25°C VCCIO 25°C Min. Max. Unit
Characteristics (I/O)[10]
VREF VCCIO Standards LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V GTL+ SSTL3 SSTL3 SSTL2 SSTL2 HSTL HSTL HSTL HSTL 1.25 1.25 0.75 0.75
[11]
mA[12] (max.) 0.45 0.1VCCIO 0.54 0.35 Min. 2.0V 2.0V 2.0V 2.0V 2.0V 2.0V 2.0V 2.0V 2.0V 1.7V
Max. Min.
Max. 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.7V
-0.1 -0.1 -0.1 -1.0 -2.0 -0.5
(min.) VCCIO 0.2V VCCIO 0.2V VCCIO 0.45V 0.9VCCIO VCCIO 1.1V VCCIO 0.9V
VCCIO -0.3V VCCIO -0.3V VCCIO -0.3V VCCIO -0.3V VCCIO -0.3V VCCIO -0.3V VCCIO -0.3V VCCIO -0.3V VCCIO -0.3V VCCIO -0.3V
0.65VCCIO 0.5VCCIO VREF
VCCIO -0.3V VCCIO -0.5V
0.35VCCIO 0.3VCCIO VREF
VREF VCCIO -0.3V VREF VREF VCCIO -0.3V VREF VREF 0.18 VCCIO -0.3V VREF 0.18 VREF 0.18 VCCIO -0.3V VREF 0.18 VREF VCCIO -0.3V VREF VREF VCCIO -0.3V VREF VREF VCCIO -0.3V VREF VREF VCCIO -0.3V VREF
-7.6 VCCIO 0.62V VCCIO 0.4V VCCIO 0.4V VCCIO 0.4V VCCIO 0.4V
-15.2 VCCIO 0.43V 15.2
Notes: spec (rev 2.2) requires IDSEL have capacitance less than equal Delta39K Tables starting from page identify pins given package, which used IDSEL design. other pins meet requirement capacitance less than equal number I/Os which used each bank depends type standards number VCCIO pins being used. Please refer application note titled "Delta39K Quantum38K Standards Configurations" details. source current limit bank Vccio sink current limit bank "Power-up Sequence Requirements" below VCCIO requirement. resistor terminated termination voltage 1.5V.
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Configuration Parameters
Parameter tRECONFIG Description Reconfig time before goes HIGH Min. Unit
Power-up Sequence Requirements
Upon power-up, outputs remain three-stated until pins have powered-up nominal voltage part completed configuration. part will start configuration until VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL VCCPRG have reached nominal voltage. pins powered order. This includes VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL VCCPRG. VCCIOs bank should tied same potential powered together. VCCIOs (even unused banks) need powered least 1.5V before configuration completed. Maximum ramp time VCCs should nominal voltage
Switching Characteristics Parameter Descriptions Over Operating Range[13]
Parameter Combinatorial Mode Parameters tPRR tPRO tPRW Delay from input, through cluster channel associated with that input, output horizontal vertical channel associated with that cluster Global control output enable Global control output disable Asynchronous macrocell RESET PRESET recovery time from input horizontal vertical channel associated with cluster macrocell Asynchronous macrocell RESET PRESET from input horizontal vertical channel associated with cluster that macrocell output those same channels Asynchronous macrocell RESET PRESET minimum pulse width, from input macrocell farthest cluster horizontal vertical channel associated with Set-up time input macrocell cluster channel associated with that input pin, relative global clock Hold time input macrocell cluster channel associated with that input pin, relative global clock Global clock output macrocell output horizontal vertical channel associated with cluster that macrocell Set-up time input cell register associated with that pin, relative global clock Hold time input cell register associated with that pin, relative global clock Clock output cell register output associated with that register Macrocell clock macrocell clock through array logic within same cluster Macrocell clock macrocell clock through array logic different clusters same channel register clock macrocell clock cluster channel register associated with Macrocell clock register clock horizontal vertical channel associated with cluster that macrocell Clock output disable (high-impedance) Clock output enable (low-impedance) Maximum frequency with internal feedback-within same cluster Maximum frequency with internal feedback-within different clusters opposite ends horizontal vertical channel Description
Synchronous Clocking Parameters tMCS tMCH tMCCO tIOS tIOH tIOCO tSCS tSCS2 tICS tOCS tCHZ tCLZ fMAX fMAX2
Note: tCHSW signals making horizontal vertical channel switch vice-versa.
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Characteristics Parameter Descriptions Over Operating Range[13] (continued)
Parameter Product Term Clock tMCSPT tMCHPT tMCCOPT tSCS2PT Set-up time macrocell used input register, from input product term clock Hold time macrocell used input register Product term clock output delay from input Register register delay through array logic different clusters same channel using product term clock Adder signal switch from horizontal vertical channel vice-versa Cluster-to-cluster delay adder (through channels channel PIM) Delay from input cluster PIM, through macrocell cluster, back cluster input. This parameter added tSCS parameters each extra pass through AND/OR array required given signal path Adder carry chain logic macrocell Delay from input output buffer Delay from input channel buffer Delay from clock input clock driver Delay from input register
[14]
Description
Channel Interconnect Parameters tCHSW tCL2CL
Miscellaneous Delays tCPLD tMCCD tIOD tIOIN tCKIN tIOREGPIN Parameters tMCCJ tDWSA tDWOSA tLOCK tINDUTY fPLLI fPLLO fPLLVCO PSAPLLI fMPLLI JTAG Parameters tJCKH tJCKL tJCP tJSU tJCO tJXZ tJZX TCLK HIGH time TCLK time TCLK clock period JTAG port set-up time (TDI/TMS inputs) JTAG port hold time (TDI/TMS inputs) JTAG port clock output time (TDO) JTAG port valid output high impedance (TDO) JTAG port high impedance valid output (TDO)
Maximum cycle cycle jitter time zero phase delay with clock tree deskewed zero phase delay without clock tree deskewed Lock time Input duty cycle Input frequency Output frequency frequency operation Percentage modulation allowed (spread awareness) input clock Frequency modulation allowed input clock. This specifies fast fPLLI sweeps between fPLLI* PSAPLLI/100) fPLLI* PSAPLLI/100)
Note: offered with Delta39K 3.3/2.5V versions only.
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Cluster Memory Timing Parameter Descriptions Over Operating Range
Parameter Asynchronous Mode Parameters tCLMAA tCLMPWE tCLMSA tCLMHA tCLMSD tCLMHD Cluster memory access time. Delay from address change Read data Write Enable pulse width Address set-up beginning Write Enable with both signals from same block Address hold after Write Enable with both signals from same block Data set-up Write Enable Data hold after Write Enable Clock cycle time flow through Read Write operations (from macrocell register through cluster memory back macrocell register same cluster) Clock cycle time pipelined Read Write operations (from cluster memory input register through memory cluster memory output register) Address, data, set-up time inputs, relative global clock Address, data, hold time inputs, relative global clock Global clock data valid output pins flow through data Global clock data valid output pins pipelined data Cluster memory input clock macrocell clock same cluster Cluster memory output clock macrocell clock same cluster Macrocell clock cluster memory input clock same cluster Macrocell clock cluster memory output clock same cluster Asynchronous cluster memory access time from input cluster memory output cluster memory Description
Synchronous Mode Parameters tCLMCYC1 tCLMCYC2 tCLMS tCLMH tCLMDV1 tCLMDV2 tCLMMACS1 tCLMMACS2 tMACCLMS1 tMACCLMS2 tCLMCLAA
Internal Parameters
Channel Memory Timing Parameter Descriptions Over Operating Range
Parameter Dual Port Asynchronous Mode Parameters tCHMAA tCHMPWE tCHMSA tCHMHA tCHMSD tCHMHD tCHMBA Channel memory access time. Delay from address change Read data Write enable pulse width Address set-up beginning Write enable with both signals from same block Address hold after Write enable with both signals from same block Data set-up Write enable Data hold after Write enable Channel memory asynchronous dual port address match (busy access time) Clock cycle time flow through Read Write operations (from macrocell register through channel memory back macrocell register same cluster) Clock cycle time pipelined Read Write operations (from channel memory input register through memory channel memory output register) Address, data, set-up time inputs, relative global clock Address, data, hold time inputs, relative global clock Global clock data valid output pins flow through data Global clock data valid output pins pipelined data. Channel memory synchronous dual-port address match (busy, clock data valid) Page Description
Dual Port Synchronous Mode Parameters tCHMCYC1 tCHMCYC2 tCHMS tCHMH tCHMDV1 tCHMDV2 tCHMBDV
Document 38-03039 Rev.
Delta39KISRCPLD Family
Channel Memory Timing Parameter Descriptions Over Operating Range (continued)
Parameter tCHMMACS1 tCHMMACS2 tMACCHMS1 tMACCHMS2 tCHMCLK tCHMFS tCHMFH tCHMFRDV tCHMMACS tMACCHMS tCHMFO tCHMMACF tCHMFRS tCHMFRSR tCHMFRSF tCHMSKEW1 tCHMSKEW2 tCHMSKEW3 tCHMCHAA Description Channel memory input clock macrocell clock same cluster Channel memory output clock macrocell clock same cluster Macrocell clock channel memory input clock same cluster Macrocell clock channel memory output clock same cluster Read Write minimum clock cycle time Data, Read enable, Write enable set-up time relative inputs Data, Read enable, Write enable hold time relative inputs Data access time output pins from rising edge Read clock (Read clock data valid) Channel memory FIFO Read clock macrocell clock Read data Macrocell clock channel memory FIFO Write clock Write data Read Write clock respective flag output output pins Read Write clock macrocell clock with FIFO flag Master Reset Pulse Width Master Reset Recovery Time Master Reset Flag Data Output Time Read/Write Clock Skew Time Full Flag Read/Write Clock Skew Time Empty Flag Read/Write Clock Skew Time Boundary Flags Asynchronous channel memory access time from input channel memory output channel memory
Synchronous FIFO Data Parameters
Synchronous FIFO Flag Parameters
Internal Parameters
Switching Characteristics Parameter Values Over Operating Range
Parameter tPRR tPRO tPRW tMCS tMCH tMCCO tIOS tIOH tIOCO tSCS tSCS2 tICS Min. Max. Min. Combinatorial Mode Parameters 10.5 Page
Max. Min.
Max. Min.
Max. Min.
Max. Unit
Synchronous Clocking Parameters
Document 38-03039 Rev.
Delta39KISRCPLD Family
Switching Characteristics Parameter Values Over Operating Range (continued)
Parameter tOCS tCHZ tCLZ fMAX fMAX2 tMCSPT tMCHPT tMCCOPT tSCS2PT tCHSW tCL2CL Miscellaneous Parameters tCPLD tMCCD Parameters tMCCJ tDWSA tDWOSA tLOCK tINDUTY fPLLO fPLLI
[15] [15]
Max. Min. Max. Min.
Max. Min.
Max. Min.
Max. Unit
Min.
Product Term Clocking Parameters
0.22 -150 -1.35 -150 12.5 -0.3 -0.85 +0.3
0.25 -150 -1.35 -150 12.5 -0.3 -0.85 +0.3
0.28 -150 -1.35 -150 12.5 -0.3 -0.85 +0.3
11.0 10.0
0.35 -180 -2.0 -180 12.5 -0.3 -1.5 +0.3
15.0 15.0
0.38 -200 -2.9 -200 12.5 -0.3 -2.4 +0.3
Channel Interconnect Parameters
fPLLVCO PSAPLLI fMPLLI JTAG Parameters tJCKH tJCKL tJCP tJSU tJCO tJXZ tJZX
Note: Refer page application note titled "Delta39K Clock Tree" details operation.
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Input Output Standard Timing Delay Adjustments
timing specifications this data sheet specified based LVCMOS compliant inputs outputs (fast slew rates).[16] Apply following adjustments inputs outputs configured operate other standards.
Output Delay Adjustments Fast Slew Rate Standard LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V GTL+ SSTL3 SSTL3 SSTL2 SSTL2 HSTL HSTL HSTL HSTL tIOD 2.75 0.16 0.14 0.41 -0.14 0.02
[17]
Slow Slew Rate (additional delay fast slew rate) tIODSLOW tEASLOW tERSLOW
Input Delay Adjustments tIOIN tCKIN tIOREGPIN
0.05 0.6[17]
0.9[17]
-0.15 -0.4 -0.02 -0.22 0.94 0.79 0.77 0.44
Notes: "slow slew rate" output delay adjustments, refer Warp software's static timing analyzer results. These delays based falling edge output. rising edge delay depends size pull-up resistor termination voltage.
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Cluster Memory Timing Parameter Values Over Operating Range
Parameter tCLMAA tCLMPWE tCLMSA tCLMHA tCLMSD tCLMHD tCLMCYC1 tCLMCYC2 tCLMS tCLMH tCLMDV1 tCLMDV2 tCLMMACS1 tCLMMACS2 tMACCLMS1 tMACCLMS2 tCLMCLAA Min. Max. 10.2 Min. Asynchronous Mode Parameters 10.5 10.0
Max. Min.
Max. Min.
Max. Min.
Max. Unit
Synchronous Mode Parameters
Internal Parameters
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Channel Memory Timing Parameter Values Over Operating Range
Parameter tCHMAA tCHMPWE tCHMSA tCHMHA tCHMSD tCHMHD tCHMBA tCHMCYC1 tCHMCYC2 tCHMS tCHMH tCHMDV1 tCHMDV2 tCHMBDV tCHMMACS1 tCHMMACS2 tMACCHMS1 tMACCHMS2 tCHMCLK tCHMFS tCHMFH tCHMFRDV tCHMMACS tMACCHMS tCHMFO tCHMMACF tCHMFRS tCHMFRSR tCHMFRSF tCHMSKEW1 tCHMSKEW2 tCHMSKEW3 Internal Parameters tCHMCHAA 10.0 13.0 10.5 10.0 11.0 11.5 15.0 10.0 18.0 10.6 Min. Max. 10.0 14.0 10.0 10.0 10.6 10.6 Min. Dual-Port Asynchronous Mode Parameters 10.0 14.0 16.0 13.0 10.6 13.0 14.0 10.6 16.0 16.0
Max. Min.
Max. Min.
Max. Min.
Max. Unit
Dual-Port Synchronous Mode Parameters
Synchronous FIFO Data Parameters
Synchronous FIFO Flag Parameters
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Waveforms
Combinatorial Output
INPUT
COMBINATORIAL OUTPUT
Registered Output with Synchronous Clocking (Macrocell)
INPUT tMCS tMCH
SYNCHRONOUS CLOCK
REGISTERED OUTPUT tMCCO
Registered Input Cell
DATA INPUT tIOS tIOH
INPUT REGISTER CLOCK
tIOCO
REGISTERED OUTPUT
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Waveforms (continued)
Clock Clock
INPUT REGISTER CLOCK
tICS
tSCS
MACROCELL REGISTER CLOCK
Clock Clock
DATA INPUT tMCSPT tSCS2PT
CLOCK
Asynchronous Reset/Preset
RESET/PRESET INPUT tPRO REGISTERED OUTPUT
tPRW
tPRR
CLOCK
Output Enable/Disable
GLOBAL CONTROL INPUT OUTPUTS
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Waveforms (continued)
Cluster Memory Asynchronous Timing
READ ADDRESS CLUSTER INPUT)
WRITE
READ
WRITE ENABLE tCLMPWE
INPUT
tCLMCLAA OUTPUT
tCLMCLAA
Cluster Memory Asynchronous Timing
READ ADDRESS PIN) WRITE READ
tCLMSA
tCLMHA
WRITE ENABLE tCLMPWE
INPUT tCLMSD tCLMAA tCLMHD tCLMAA
OUTPUT
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Waveforms (continued)
Cluster Memory Synchronous Flow-Through Timing
READ GLOBAL CLOCK tCLMS tCLMH tCLMCYC1 WRITE READ
ADDRESS tCLMS tCLMH tCLMS tCLMH
WRITE ENABLE
REGISTERED INPUT tCLMDV1
tCLMDV1 REGISTERED OUTPUT
tCLMDV1
Cluster Memory Internal Clocking
MACROCELL INPUT CLOCK tCLMMACS1 CLUSTER MEMORY INPUT CLOCK tCLMMACS2 tMACCLMS2 tMACCLMS1
CLUSTER MEMORY OUTPUT CLOCK
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Waveforms (continued)
Cluster Memory Output Register Timing (Asynchronous Inputs)
ADDRESS
WRITE ENABLE
INPUT
tCLMCYC2
GLOBAL CLOCK (OUTPUT REGISTER) tCLMDV2
REGISTERED OUTPUT
Cluster Memory Output Register Timing (Synchronous Inputs)
ADDRESS
WRITE ENABLE
INPUT tCLMCYC2 GLOBAL CLOCK (INPUT REGISTER) tCLMS tCLMH
GLOBAL CLOCK (OUTPUT REGISTER) tCLMDV2
REGISTERED OUTPUT
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Waveforms (continued)
Channel Memory Asynchronous Timing
ADDRESS
An-1
An+1
An+2
tCHMSA
tCHMPWE
tCHMHA
WRITE ENABLE
tCHMSD
tCHMHD
DATA INPUT
tCHMAA
tCHMAA
OUTPUT
Dn-1
Dn+1
Channel Memory Internal Clocking
MACROCELL INPUT CLOCK tMACCHMS1
tCHMMACS1 CHANNEL MEMORY INPUT CLOCK
tCHMMACS2
tMACCHMS2
CHANNEL MEMORY OUTPUT CLOCK
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Waveforms (continued)
Channel Memory Internal Clocking
MACROCELL INPUT CLOCK tCHMMACS FIFO READ CLOCK
tMACCHMS
FIFO WRITE CLOCK tCHMMACF FIFO READ WRITE CLOCK
Channel Memory SRAM Flow-Through Timing
CLOCK tCHMCYC1 tCHMS tCHMH
ADDRESS
An-1
An+1
An+2
An+3
WRITE ENABLE
tCHMS
tCHMH
DATA INPUT
Dn-1
Dn+1
Dn+3
tCHMDV1
tCHMDV1
tCHMDV1
tCHMDV1
OUTPUT
Dn-1
Dn+1
Dn+2
Dn+3
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Waveforms (continued)
Channel Memory SRAM Pipeline Timing
CLOCK tCHMCYC2 tCHMS
tCHMH
ADDRESS
An-1
tCHMH
An+1
An+2
An+3
tCHMS WRITE ENABLE
tCHMS
tCHMH
DATA INPUT
Dn-1
Dn+1
Dn+3
tCHMDV2
tCHMDV2
tCHMDV2
OUTPUT
Dn-1
Dn+1
Dn+2
Dual-Port Asynchronous Address Match Busy Signal
ADDRESS
ADDRESS
An-1
An+1
tCHMBA tCHMBA ADDRESS MATCH
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Waveforms (continued)
Dual-Port Synchronous Address Match Busy Signal
CLOCK
ADDRESS
An-1
ADDRESS
Bn-1 tCHMS
tCHMS
Bn+1
ADDRESS MATCH
tCHMBDV tCHMBDV
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Empty/Write Timing
PORT CLOCK tCHMCLK tCHMFS tCHMFH
WRITE ENABLE
REGISTERED INPUT
Dn+1
EMPTY FLAG (Active LOW)
tCHMSKEW2
tCHMFO
tCHMFO
PORT CLOCK
READ ENABLE
tCHMFRDV
REGISTERED OUTPUT
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Full/Read Timing
PORT CLOCK tCHMCLK tCHMFS tCHMFH
READ ENABLE
tCHMFRDV
REGISTERED OUTPUT
FULL FLAG (Active LOW)
tCHMSKEW1
tCHMFO
tCHMFO
PORT CLOCK
WRITE ENABLE
tCHMS
tCHMH
REGISTERED INPUT
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Programmable Flag Timing
PORT CLOCK tCHMCLK tCHMFH
tCHMFS
WRITE ENABLE
PROGRAMMABLE ALMOST EMPTY FLAG (active LOW) tCHMSKEW3 tCHMFO tCHMFO
PORT CLOCK
tCHMFS READ ENABLE
tCHMFH
PORT CLOCK tCHMCLK
WRITE ENABLE tCHMFO PROGRAMMABLE ALMOST FULL FLAG (Active LOW) tCHMSKEW3 tCHMFO
PORT CLOCK
READ ENABLE
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Master Reset Timing
tCHMFRS MASTER RESET INPUT
tCHMFRSR
READ ENABLE WRITE ENABLE tCHMFRSF EMPTY/FULL PROGRAMMABLE ALMOST EMPTY FLAGS tCHMFRSF
HALF-FULL/ PROGRAMMABLE ALMOST FULL FLAGS tCHMFRSF
REGISTERED OUTPUT
Cypress Semiconductor Family Type Delta39K Family Gate Density 30=30k Usable Gates 50=50k Usable Gates 100=100k Usable Gates Operating Conditions Commercial +70°C Industrial -40°C +85°C 165k Usable Gates 200k Usable Gates
Operating Reference Voltage 3.3V 2.5V Supply Voltage 1.8V Supply Voltage Count Leads Balls Balls Balls Balls
Package Type Plastic Quad Flat Pack (PQFP) Thermally Enhanced Quad Flat Pack (EQFP) Ball Grid Array (BGA) Fine-pitch Ball Grid Array (FBGA) 1.0-mm Lead Pitch Self-Boot Solution Ball Grid Array Self-Boot Solution Fine Pitch Ball Grid Array 1.0-mm Lead Pitch Speed
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Delta39K Part Numbers (Ordering Information)
Device 39K30 Speed (MHz) Ordering Code CY39030V208-233NTC CY39030V256-233BBC CY39030V256-233MBC CY39030V208-125NTC CY39030V256-125BBC CY39030V256-125MBC CY39030Z208-125NC CY39030Z256-125BBC CY39030Z256-125MBC CY39030V208-125NTI CY39030V256-125BBI CY39030Z256-125BBI CY39030Z208-125NI CY39030V208-83NTC CY39030V256-83BBC CY39030V256-83MBC CY39030Z256-83MBC CY39030Z208-83NC CY39030Z256-83BBC CY39030V208-83NTI CY39030V256-83BBI CY39030Z256-83BBI CY39030Z208-83NI 39K50 CY39050V208-233NTC CY39050V256-233BBC CY39050V388-233MGC CY39050V484-233MBC CY39050V208-125NTC CY39050V256-125BBC CY39050V388-125MGC CY39050V484-125MBC CY39050Z484-125MBC CY39050Z256-125BBC CY39050Z208-125NC CY39050Z388-125MGC Package Name NT208 BB256 MB256 NT208 BB256 MB256 N208 BB256 MB256 NT208 BB256 BB256 N208 NT208 BB256 MB256 MB256 N208 BB256 NT208 BB256 BB256 N208 NT208 BB256 MG388 MB484 NT208 BB256 MG388 MB484 MB484 BB256 N208 MG388 Package Type 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 388-Lead Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 388-Lead Pitch Ball Grid Array Commercial Industrial Commercial Industrial SelfBoot Solution Operating Range Commercial
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Delta39K Part Numbers (Ordering Information) (continued)
Device 39K50 Speed (MHz) Ordering Code CY39050V208-125NTI CY39050V256-125BBI CY39050Z256-125BBI CY39050Z208-125NI CY39050V208-83NTC CY39050V256-83BBC CY39050V388-83MGC CY39050V484-83MBC CY39050Z208-83NC CY39050Z484-83MBC CY39050Z256-83BBC CY39050Z388-83MGC CY39050V208-83NTI CY39050V256-83BBI CY39050Z256-83BBI CY39050Z208-83NI 39K100 CY39100V208B-200NTC CY39100V256B-200BBC CY39100V484B-200BBC CY39100V388B-200MGC CY39100V676B-200MBC Package Name NT208 BB256 BB256 N208 NT208 BB256 MG388 MB484 N208 MB484 BB256 MG388 NT208 BB256 BB256 N208 NT208 BB256 BB484 MG388 MB676 Package Type 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array Commercial Industrial Commercial SelfBoot Solution Operating Range Industrial
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Delta39K Part Numbers (Ordering Information) (continued)
Device 39K100 Speed (MHz) Ordering Code CY39100V208B-125NTC CY39100V256B-125BBC CY39100V484B-125BBC CY39100V388B-125MGC CY39100V676B-125MBC CY39100Z208-125NC CY39100Z256-125BBC CY39100Z484-125BBC CY39100Z388-125MGC CY39100Z676-125MBC CY39100V208B-125NTI CY39100V256B-125BBI CY39100V484B-125BBI CY39100V208B-83NTC CY39100V256B-83BBC CY39100V484B-83BBC CY39100V388B-83MGC CY39100V676B-83MBC CY39100Z208-83NC CY39100Z256-83BBC CY39100Z484-83BBC CY39100Z388-83MGC CY39100Z676-83MBC CY39100V208B-83NTI CY39100V256B-83BBI CY39100V484B-83BBI CY39100Z208-83NI CY39100Z256-83BBI CY39100Z484-83BBI Package Name NT208 BB256 BB484 MG388 MB676 N208 BB256 BB484 MG388 MB676 NT208 BB256 BB484 NT208 BB256 BB484 MG388 MB676 N208 BB256 BB484 MG388 MB676 NT208 BB256 BB484 N208 BB256 BB484 Package Type 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array Industrial Commercial Industrial SelfBoot Solution Operating Range Commercial
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Delta39K Part Numbers (Ordering Information) (continued)
Device 39K165 Speed (MHz) Ordering Code CY39165V208-181NTC CY39165V484-181BBC CY39165V388-181MGC CY39165V676-181MBC CY39165V208-125NTC CY39165V484-125BBC CY39165V388-125MGC CY39165V676-125MBC CY39165V208-125NTI CY39165V484-125BBI CY39165V208-83NTC CY39165V484-83BBC CY39165V388-83MGC CY39165V676-83MBC CY39165V208-83NTI CY39165V484-83BBI Package Name NT208 BB484 MG388 MB676 NT208 BB484 MG388 MB676 NT208 BB484 NT208 BB484 MG388 MB676 NT208 BB484 Package Type 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array Industrial Commercial Industrial Commercial SelfBoot Solution Operating Range Commercial
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Delta39K Part Numbers (Ordering Information) (continued)
Device 39K200 Speed (MHz) Ordering Code CY39200V208-181NTC CY39200V484-181BBC CY39200V388-181MGC CY39200V676-181MBC CY39200V208-125NTC CY39200V484-125BBC CY39200V388-125MGC CY39200V676-125MBC CY39200Z208-125NTC CY39200Z484-125BBC CY39200Z388-125MGC CY39200Z676-125MBC CY39200V208-125NTI CY39200V484-125BBI CY39200Z208-125NTI CY39200Z484-125BBI CY39200V208-83NTC CY39200V484-83BBC CY39200V388-83MGC CY39200V676-83MBC CY39200Z208-83NTC CY39200Z484-83BBC CY39200Z388-83MGC CY39200Z676-83MBC CY39200V208-83NTI CY39200V484-83BBI CY39200Z208-83NTI CY39200Z484-83BBI Package Name NT208 BB484 MG388 MB676 NT208 BB484 MG388 MB676 NT208 BB484 MG388 MB676 NT208 BB484 NT208 BB484 NT208 BB484 MG388 MB676 NT208 BB484 MG388 MB676 NT208 BB484 NT208 BB484 Package Type 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array Industrial Commercial Industrial Commercial SelfBoot Solution Operating Range Commercial
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
CPLD Boot EEPROM[18] Part Numbers (Ordering Information)
Device 2Mbit 1Mbit 512Kbit Speed (MHz) Ordering Code CY3LV002-10JC CY3LV002-10JC CY3LV010-10JC CY3LV010-10JI CY3LV512-10JC CY3LV512-10JI Package Name Package Type 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier Operating Range Commercial Industrial Commercial Industrial Commercial Industrial
Recommended CPLD Boot EEPROM corresponding Delta39K CPLDs
CPLD Device 39K30 39K50 39K100 39K165 39K200
Note: data sheet titled "CPLD Boot EEPROM" detailed architectural timing information.
Recommended boot EEPROM CY3LV512 CY3LV512 CY3LV010 CY3LV002 CY3LV002
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Package Diagrams
208-Lead Enhanced Quad Flat Pack (EQFP) NT208
51-85069-*B
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Package Diagrams (continued)
388-Lead Ball Grid Array MG388
51-85103-*C
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Package Diagrams (continued)
256-Ball FBGA BB256/MB256
51-85108-*C
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Package Diagrams (continued)
484-Ball FBGA BB484/MB484
51-85124-*B
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Package Diagrams (continued)
676-Ball FBGA BB676/MB676
51-85125-*B
Tables
Table Definition Table Name GCLK0-3 GCTL0-3 IO/VREF0 IO/VREF1 IO/VREF2 IO/VREF3 IO/VREF4 IO/VREF5 IO/VREF6 Function Input Input Ground Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Description Global Clock signals through Global Control signals through Ground Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table Definition Table Name IO/VREF7 IO6/Lock MSEL Reconfig TCLK VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCJTAG VCCCNFG VCCPLL[19] VCCPRG Config_Done CCLK Data Reset Function Input/Output Input/Output Input/Output Input Input Input Input Output Input Power Power Power Power Power Power Power Power Power Power Power Power Power Output Output Output Input Output Description Dual function pin: Reference Voltage Bank Input Output Dual function pin: Bank lock output signal Mode Select (see Table start configuration Delta39K JTAG Test Clock JTAG Test Data JTAG Test Data JTAG Test Mode Select Operating Voltage bank bank bank bank bank bank bank bank JTAG pins Configuration port programming Self-Bootsolution embedded boot PROM Flag indicating that configuration complete Configuration Clock serial interface with external boot PROM Chip select external boot PROM (active low) receive configuration data from external boot PROM Reset signal interface with external boot PROM
Notes: available Delta39K devices (2.5V/3.3V) Delta39K devices (1.8V). Delta39K devices, connect VCCPLL VCC.
Table Mode Select (MSEL) Connectivity Table VCCCNFG Delta39K Self-BootSolution Delta39K with external boot PROM
Table Banks Global Clock Global Control Pins densities packages) GCLK[0] GCTL[0] Bank Number GCLK[1] GCTL[1] GCLK[2] GCTL[2] GCLK[3] GCTL[3]
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Table EQFP/PQFP Table 21[20] 22[20] 27[20] 30[20] 31[20] 32[20] CY39030 GCTL0 GCLK0 IO/VREF0 VCCIO0 IO/VREF0 VCCIO0 IO/VREF0 VCCIO0 VCCIO1 IO/VREF1 VCCIO1 IO/VREF1 CY39050 GCTL0 GCLK0 IO/VREF0 VCCIO0 IO/VREF0 VCCIO0 IO/VREF0 VCCIO0 VCCIO1 IO/VREF1 VCCIO1 IO/VREF1 CY39100 GCTL0 GCLK0 IO/VREF0 VCCIO0 IO/VREF0 VCCIO0 IO/VREF0 VCCIO0 VCCIO1 IO/VREF1 VCCIO1 IO/VREF1 CY39165 GCTL0 GCLK0 IO/VREF0 VCCIO0 IO/VREF0 VCCIO0 IO/VREF0 VCCIO0 VCCIO1 IO/VREF1 VCCIO1 IO/VREF1 CY39200 GCTL0 GCLK0 IO/VREF0 VCCIO0 IO/VREF0 VCCIO0 IO/VREF0 VCCIO0 VCCIO1 IO/VREF1 VCCIO1 IO/VREF1
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Table EQFP/PQFP Table (continued) 81[20] 82[20] 83[20] 86[20] 87[20] CY39030 VCCPRG VCCIO1 IO/VREF1 VCCCNFG Data Config_Done Reset Reconfig CCLK VCCCNFG MSEL IO/VREF2 VCCIO2 IO/VREF2 VCCIO2 IO/VREF2 VCCIO2 VCCIO3 CY39050 VCCPRG VCCIO1 IO/VREF1 VCCCNFG Data Config_Done Reset Reconfig CCLK VCCCNFG MSEL IO/VREF2 VCCIO2 IO/VREF2 VCCIO2 IO/VREF2 VCCIO2 VCCIO3 CY39100 VCCPRG VCCIO1 IO/VREF1 VCCCNFG Data Config_Done Reset Reconfig CCLK VCCCNFG MSEL IO/VREF2 VCCIO2 IO/VREF2 VCCIO2 IO/VREF2 VCCIO2 VCCIO3 CY39165 VCCPRG VCCIO1 IO/VREF1 VCCCNFG Data Config_Done Reset Reconfig CCLK VCCCNFG MSEL IO/VREF2 VCCIO2 IO/VREF2 VCCIO2 IO/VREF2 VCCIO2 VCCIO3 CY39200 VCCPRG VCCIO1 IO/VREF1 VCCCNFG Data Config_Done Reset Reconfig CCLK VCCCNFG MSEL IO/VREF2 VCCIO2 IO/VREF2 VCCIO2 IO/VREF2 VCCIO2 VCCIO3 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table EQFP/PQFP Table (continued) 88[20] 122[20] 123[20] 126[20] CY39030 IO/VREF3 VCCIO3 IO/VREF3 VCCIO3 IO/VREF3 IO/VREF4 VCCIO4 VCCPRG IO/VREF4 IO/VREF4 VCCIO4 VCCIO4 CY39050 IO/VREF3 VCCIO3 IO/VREF3 VCCIO3 IO/VREF3 IO/VREF4 VCCIO4 VCCPRG IO/VREF4 IO/VREF4 VCCIO4 VCCIO4 CY39100 IO/VREF3 VCCIO3 IO/VREF3 VCCIO3 IO/VREF3 IO/VREF4 VCCIO4 VCCPRG IO/VREF4 IO/VREF4 VCCIO4 VCCIO4 CY39165 IO/VREF3 VCCIO3 IO/VREF3 VCCIO3 IO/VREF3 IO/VREF4 VCCIO4 VCCPRG IO/VREF4 IO/VREF4 VCCIO4 VCCIO4 CY39200 IO/VREF3 VCCIO3 IO/VREF3 VCCIO3 IO/VREF3 IO/VREF4 VCCIO4 VCCPRG IO/VREF4 IO/VREF4 VCCIO4 VCCIO4 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table EQFP/PQFP Table (continued)
[20]
CY39030 VCCIO5 IO/VREF5 VCCIO5 IO/VREF5 VCCIO5 IO/VREF5 GCLK1 GCTL1 TCLK VCCJTAG GCLK2 GCTL2 IO/VREF6 VCCIO6 IO/VREF6
CY39050 VCCIO5 IO/VREF5 VCCIO5 IO/VREF5 VCCIO5 IO/VREF5 GCLK1 GCTL1 TCLK VCCJTAG GCLK2 GCTL2 IO/VREF6 VCCIO6 IO/VREF6
CY39100 VCCIO5 IO/VREF5 VCCIO5 IO/VREF5 VCCIO5 IO/VREF5 GCLK1 GCTL1 TCLK VCCJTAG GCLK2 GCTL2 IO/VREF6 VCCIO6 IO/VREF6
CY39165 VCCIO5 IO/VREF5 VCCIO5 IO/VREF5 VCCIO5 IO/VREF5 GCLK1 GCTL1 TCLK VCCJTAG GCLK2 GCTL2 IO/VREF6 VCCIO6 IO/VREF6
CY39200 VCCIO5 IO/VREF5 VCCIO5 IO/VREF5 VCCIO5 IO/VREF5 GCLK1 GCTL1 TCLK VCCJTAG GCLK2 GCTL2 IO/VREF6 VCCIO6 IO/VREF6 Page
134[20]
[20]
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table EQFP/PQFP Table (continued) 183[20] 184[20]
[20]
CY39030 VCCIO6 VCCPLL IO/VREF6 IO6/Lock VCCIO6 VCCIO7 IO/VREF7 VCCIO7 IO/VREF7 VCCIO7 IO/VREF7 GCLK3 GCTL3
CY39050 VCCIO6 VCCPLL IO/VREF6 IO6/Lock VCCIO6 VCCIO7 IO/VREF7 VCCIO7 IO/VREF7 VCCIO7 IO/VREF7 GCLK3 GCTL3
CY39100 VCCIO6 VCCPLL IO/VREF6 IO6/Lock VCCIO6 VCCIO7 IO/VREF7 VCCIO7 IO/VREF7 VCCIO7 IO/VREF7 GCLK3 GCTL3
CY39165 VCCIO6 VCCPLL IO/VREF6 IO6/Lock VCCIO6 VCCIO7 IO/VREF7 VCCIO7 IO/VREF7 VCCIO7 IO/VREF7 GCLK3 GCTL3
CY39200 VCCIO6 VCCPLL IO/VREF6 IO6/Lock VCCIO6 VCCIO7 IO/VREF7 VCCIO7 IO/VREF7 VCCIO7 IO/VREF7 GCLK3 GCTL3
188[20] 189[20] 190[20]
Note: Capacitance these pins meets spec (rev. 2.2), which requires IDSEL design have capacitance less than equal 8pf. document titled "Delta39K CPLD Family data sheet", this spec defined CPCI. other pins have capacitance less than equal 10pf.
Table Table CY39050 CY39100 CY39165 CY39200 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table Table (continued) A13[20] A14[20] B13[20] B14[20] CY39050 IO/VREF7 IO/VREF6 IO/VREF7 IO/VREF7 IO6/Lock IO/VREF6 CY39100 IO/VREF7 IO/VREF7 IO/VREF6 IO/VREF7 IO/VREF7 IO/VREF7 IO6/Lock IO/VREF6 CY39165 IO/VREF7 IO/VREF7 IO/VREF6 IO/VREF7 IO/VREF7 IO/VREF7 IO6/Lock IO/VREF6 CY39200 IO/VREF7 IO/VREF7 IO/VREF6 IO/VREF7 IO/VREF7 IO/VREF7 IO6/Lock IO/VREF6 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table Table (continued) C13[20] C14[20] CY39050 IO/VREF7 IO/VREF6 IO/VREF6 IO/VREF0 GCTL3 GCLK3 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 CY39100 IO/VREF7 IO/VREF6 IO/VREF6 IO/VREF6 IO/VREF0 GCTL3 GCLK3 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 CY39165 IO/VREF7 IO/VREF6 IO/VREF6 IO/VREF6 IO/VREF0 GCTL3 GCLK3 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 CY39200 IO/VREF7 IO/VREF6 IO/VREF6 IO/VREF6 IO/VREF0 GCTL3 GCLK3 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table Table (continued) CY39050 VCCPLL VCCIO6 VCCIO6 GCLK2 GCTL2 TCLK GCTL0 GCLK1 IO/VREF0 GCLK0 GCTL1 IO/VREF5 VCCIO0 VCCJTAG CY39100 VCCPLL VCCIO6 VCCIO6 GCLK2 IO/VREF6 GCTL2 TCLK GCTL0 GCLK1 IO/VREF0 GCLK0 GCTL1 IO/VREF5 VCCIO0 VCCJTAG CY39165 VCCPLL VCCIO6 VCCIO6 GCLK2 IO/VREF6 GCTL2 TCLK GCTL0 GCLK1 IO/VREF0 GCLK0 GCTL1 IO/VREF5 VCCIO0 VCCJTAG CY39200 VCCPLL VCCIO6 VCCIO6 GCLK2 IO/VREF6 GCTL2 TCLK GCTL0 GCLK1 IO/VREF0 GCLK0 GCTL1 IO/VREF5 VCCIO0 VCCJTAG Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table Table (continued) M2[20] M3[20] CY39050 VCCIO0 VCCIO5 VCCIO5 IO/VREF5 VCCIO0 VCCIO5 CY39100 IO/VREF0 VCCIO0 VCCIO5 IO/VREF5 VCCIO5 IO/VREF5 VCCIO0 VCCIO5 CY39165 IO/VREF0 VCCIO0 VCCIO5 IO/VREF5 VCCIO5 IO/VREF5 VCCIO0 VCCIO5 CY39200 IO/VREF0 VCCIO0 VCCIO5 IO/VREF5 VCCIO5 IO/VREF5 VCCIO0 VCCIO5 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table Table (continued)
[20]
CY39050 IO/VREF0 IO/VREF5 IO/VREF1 VCCIO1 VCCIO4
CY39100 IO/VREF0 IO/VREF5 IO/VREF1 VCCIO1 VCCIO4 IO/VREF1
CY39165 IO/VREF0 IO/VREF5 IO/VREF1 VCCIO1 VCCIO4 IO/VREF1
CY39200 IO/VREF0 IO/VREF5 IO/VREF1 VCCIO1 VCCIO4 IO/VREF1 Page
N4[20]
[20]
P3[20] P4[20] P24[20] P25[20] R24[20] R25[20]
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table Table (continued)
[20]
CY39050 IO/VREF4 VCCPRG VCCPRG VCCIO1 VCCIO4 IO/VREF1 VCCIO1 VCCIO4
CY39100 IO/VREF4 VCCPRG VCCPRG VCCIO1 VCCIO4 IO/VREF1 VCCIO1 VCCIO4 IO/VREF4
CY39165 IO/VREF4 VCCPRG VCCPRG VCCIO1 VCCIO4 IO/VREF1 VCCIO1 VCCIO4 IO/VREF4
CY39200 IO/VREF4 VCCPRG VCCPRG VCCIO1 VCCIO4 IO/VREF1 VCCIO1 VCCIO4 IO/VREF4 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table Table (continued) AA23 AA24 AA25 AA26 AB23 AB24 AB25 AB26 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 CY39050 IO/VREF1 IO/VREF4 VCCCNFG Config_Done Data Reconfig VCCIO2 VCCIO2 VCCCNFG VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 IO/VREF4 Reset CCLK IO/VREF2 CY39100 IO/VREF1 IO/VREF4 VCCCNFG Config_Done Data Reconfig VCCIO2 VCCIO2 VCCCNFG VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 IO/VREF4 Reset CCLK IO/VREF2 CY39165 IO/VREF1 IO/VREF4 VCCCNFG Config_Done Data Reconfig VCCIO2 VCCIO2 VCCCNFG VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 IO/VREF4 Reset CCLK IO/VREF2 CY39200 IO/VREF1 IO/VREF4 VCCCNFG Config_Done Data Reconfig VCCIO2 VCCIO2 VCCCNFG VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 IO/VREF4 Reset CCLK IO/VREF2 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table Table (continued) AD10 AD11 AD12 AD13 AD14[20] AD15
[20]
CY39050 IO/VREF2 IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 MSEL IO/VREF3 IO/VREF3
CY39100 IO/VREF2 IO/VREF2 IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 MSEL IO/VREF2 IO/VREF3 IO/VREF3
CY39165 IO/VREF2 IO/VREF2 IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 MSEL IO/VREF2 IO/VREF3 IO/VREF3
CY39200 IO/VREF2 IO/VREF2 IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 MSEL IO/VREF2 IO/VREF3 IO/VREF3 Page
AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE10 AE11 AE12 AE13[20] AE14[20] AE15 AE16 AE17 AE18 AE19 AE20 AE21
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table Table (continued) AE22 AE23 AE24 AE25 AE26 AF10 AF11 AF12 AF13 AF14[20] AF15[20] AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 CY39050 CY39100 IO/VREF3 IO/VREF3 CY39165 IO/VREF3 IO/VREF3 CY39200 IO/VREF3 IO/VREF3
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Table FBGA Table C8[20]
[20]
CY39030 IO/VREF7 IO6/Lock IO/VREF6 IO/VREF6 VCCIO7 IO/VREF7 VCCPLL VCCIO6 VCCIO7 VCCIO7 VCCIO6 VCCIO6
CY39050 IO/VREF7 IO/VREF7 IO6/Lock IO/VREF6 IO/VREF6 VCCIO7 IO/VREF7 IO/VREF6 VCCPLL VCCIO6 VCCIO7 VCCIO7 VCCIO6 VCCIO6
CY39100 IO/VREF7 IO/VREF7 IO6/Lock IO/VREF6 IO/VREF6 VCCIO7 IO/VREF7 IO/VREF6 VCCPLL VCCIO6 VCCIO7 VCCIO7 VCCIO6 VCCIO6 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued)
[20]
CY39030 IO/VREF7 IO/VREF6 TCLK VCCIO0 IO/VREF0 GCTL3 GCLK3
CY39050 IO/VREF7 IO/VREF6 TCLK VCCIO0 IO/VREF0 GCTL3 GCLK3
CY39100 IO/VREF7 IO/VREF6 TCLK VCCIO0 IO/VREF0 GCTL3 GCLK3 Page
D9[20]
[20]
E9[20] Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued) H1[20] H2[20] H3[20] H14[20] H15[20] H16[20] J3[20] J4[20] Document 38-03039 Rev. CY39030 GCTL2 GCLK2 IO/VREF5 VCCIO5 VCCJTAG VCCIO0 IO/VREF0 GCTL0 GCTL1 IO/VREF5 VCCIO5 IO/VREF0 GCLK0 GCLK1 IO/VREF5 CY39050 GCTL2 GCLK2 IO/VREF5 VCCIO5 VCCJTAG VCCIO0 IO/VREF0 GCTL0 GCTL1 IO/VREF5 VCCIO5 IO/VREF0 GCLK0 GCLK1 IO/VREF5 CY39100 GCTL2 GCLK2 IO/VREF5 VCCIO5 VCCJTAG VCCIO0 IO/VREF0 GCTL0 GCTL1 IO/VREF5 VCCIO5 IO/VREF0 GCLK0 GCLK1 IO/VREF5 Page
Delta39KISRCPLD Family
Table FBGA Table (continued) J5[20]
[20]
CY39030 VCCPRG VCCIO1 IO/VREF1 IO/VREF4 VCCIO4 VCCPRG VCCIO1 IO/VREF1 VCCCNFG Config_Done IO/VREF4 VCCIO4
CY39050 VCCPRG VCCIO1 IO/VREF1 IO/VREF4 VCCIO4 VCCPRG VCCIO1 IO/VREF1 VCCCNFG Config_Done IO/VREF4 VCCIO4
CY39100 VCCPRG VCCIO1 IO/VREF1 IO/VREF4 VCCIO4 VCCPRG VCCIO1 IO/VREF1 VCCCNFG Config_Done IO/VREF4 VCCIO4 Page
J13[20]
[20]
[20]
L9[20] Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued)
[20]
CY39030 Data Reconfig IO/VREF1 MSEL IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 IO/VREF4 VCCIO2 VCCIO2 VCCIO3 VCCIO3
CY39050 Data Reconfig IO/VREF1 MSEL IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 IO/VREF4 VCCIO2 VCCIO2 VCCIO3 VCCIO3
CY39100 Data Reconfig IO/VREF1 MSEL IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 IO/VREF4 VCCIO2 VCCIO2 VCCIO3 VCCIO3 Page
M9[20]
[20]
N9[20] Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued) Table FBGA Table CY39050 CY39100 CY39165 IO/VREF7 IO/VREF7 CY39200 IO/VREF7 IO/VREF7 Page CY39030 CCLK VCCCNFG VCCIO2 VCCIO3 Reset IO/VREF2 IO/VREF3 CY39050 CCLK VCCCNFG VCCIO2 VCCIO3 Reset IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 CY39100 CCLK VCCCNFG VCCIO2 VCCIO3 Reset IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued) CY39050 VCCIO7 IO/VREF7 IO/VREF6 VCCIO6 CY39100 VCCIO7 IO/VREF7 IO/VREF6 VCCIO6 CY39165 VCCIO7 IO/VREF7 VCCIO7 VCCIO6 IO/VREF6 IO6[21] VCCIO6 CY39200 IO/VREF6 VCCIO7 IO/VREF7 VCCIO7 VCCIO6 IO/VREF6 VCCIO6 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued) CY39050 IO/VREF7 VCCIO0 IO/VREF7 IO6/Lock IO/VREF6 IO/VREF6 VCCIO5 CY39100 IO/VREF7 IO/VREF6 VCCIO0 IO/VREF7 IO/VREF7 IO6/Lock IO/VREF6 IO/VREF6 VCCIO5 CY39165 IO/VREF7 IO/VREF6
[21]
CY39200 IO/VREF7 IO/VREF6 IO/VREF0 VCCIO0 IO/VREF7 IO/VREF7 IO6/Lock IO/VREF6 IO/VREF6 VCCIO5 IO/VREF5 Page
IO/VREF0 VCCIO0 IO/VREF7 IO/VREF7 IO6/Lock IO/VREF6 IO/VREF6 VCCIO5 IO/VREF5
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued) F11[20] F12[20] CY39050 VCCIO7 IO/VREF7 VCCPLL VCCIO6 VCCIO7 VCCIO7 VCCIO6 VCCIO6 CY39100 VCCIO7 IO/VREF7 IO/VREF6 VCCPLL VCCIO6 VCCIO7 VCCIO7 VCCIO6 VCCIO6 CY39165 VCCIO7 IO/VREF7 IO/VREF6 VCCPLL VCCIO6 IO6[19] VCCIO7 VCCIO7 VCCIO6 VCCIO6 CY39200 VCCIO7 IO/VREF7 IO/VREF6 VCCPLL VCCIO6 VCCIO7 VCCIO7 VCCIO6 VCCIO6 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued)
[20]
CY39050 IO/VREF6 TCLK
CY39100 IO/VREF7 IO/VREF6 TCLK IO/VREF0
CY39165 IO/VREF7 IO6[21] IO/VREF6 TCLK IO/VREF0 VCCIO0 IO/VREF0
CY39200 IO/VREF7 IO/VREF6 TCLK IO/VREF0 VCCIO0 IO/VREF0 Page
G12[20] H11[20] H12[20]
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued) L4[20] L5[20] CY39050 VCCIO0 IO/VREF0 GCTL3 GCLK3 GCTL2 GCLK2 IO/VREF5 VCCIO5 VCCJTAG VCCIO0 IO/VREF0 GCTL0 GCTL1 IO/VREF5 VCCIO5 CY39100 VCCIO0 IO/VREF0 GCTL3 GCLK3 GCTL2 GCLK2 IO/VREF5 VCCIO5 VCCJTAG IO/VREF5 VCCIO0 IO/VREF0 GCTL0 GCTL1 IO/VREF5 VCCIO5 CY39165 VCCIO0 IO/VREF0 GCTL3 GCLK3 GCTL2 GCLK2 IO/VREF5 VCCIO5 VCCJTAG IO/VREF5 VCCIO5 IO/VREF5 VCCIO0 IO/VREF0 GCTL0 GCTL1 IO/VREF5 VCCIO5 CY39200 VCCIO0 IO/VREF0 GCTL3 GCLK3 GCTL2 GCLK2 IO/VREF5 VCCIO5 VCCJTAG IO/VREF5 VCCIO5 IO/VREF5 VCCIO0 IO/VREF0 GCTL0 GCTL1 IO/VREF5 VCCIO5 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued) L6[20] L17[20] L18[20] L19[20] M6[20]
[20]
CY39050 IO/VREF0 GCLK0 GCLK1 IO/VREF5 VCCPRG
CY39100 IO/VREF0 GCLK0 GCLK1 IO/VREF5 VCCPRG
CY39165 IO/VREF0 GCLK0 GCLK1 IO/VREF5 VCCPRG
CY39200 IO/VREF0 GCLK0 GCLK1 IO/VREF5 VCCPRG Page
M8[20]
[20]
M16[20] M17[20]
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued)
[20]
CY39050 VCCIO1 IO/VREF1 IO/VREF4 VCCIO4 VCCPRG IO/VREF1 VCCIO1 VCCCNFG Config_Done IO/VREF4 VCCIO4
CY39100 VCCIO1 IO/VREF1 IO/VREF4 VCCIO4 VCCPRG IO/VREF1 VCCIO1 IO/VREF1 VCCCNFG Config_Done IO/VREF4 VCCIO4 IO/VREF4
CY39165 VCCIO1 IO/VREF1 IO/VREF4 VCCIO4 VCCPRG IO/VREF1 VCCIO1 IO/VREF1 VCCIO1 IO/VREF1 VCCCNFG Config_Done IO/VREF4 VCCIO4 IO/VREF4 VCCIO4 IO/VREF4
CY39200 VCCIO1 IO/VREF1 IO/VREF4 VCCIO4 VCCPRG IO/VREF1 VCCIO1 IO/VREF1 VCCIO1 IO/VREF1 VCCCNFG Config_Done IO/VREF4 VCCIO4 IO/VREF4 VCCIO4 IO/VREF4 Page
P12[20]
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued) R11[20] R12[20] T11[20] T12[20] CY39050 Data Reconfig IO/VREF1 MSEL IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 IO/VREF4 CY39100 Data Reconfig IO/VREF1 MSEL IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 IO/VREF4 CY39165 Data Reconfig IO/VREF1 MSEL IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF4
[21]
CY39200 Data Reconfig IO/VREF1 MSEL IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 IO/VREF4 Page
IO/VREF3
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued) CY39050 VCCIO2 VCCIO2 VCCIO3 VCCIO3 CCLK VCCCNFG VCCIO2 VCCIO3 VCCIO1 Reset CY39100 VCCIO2 VCCIO2 VCCIO3 VCCIO3 CCLK VCCCNFG VCCIO2 VCCIO3 VCCIO1 Reset CY39165 VCCIO2 VCCIO2 VCCIO3 VCCIO3 IO3[21] CCLK VCCCNFG VCCIO2 VCCIO3 IO/VREF1 VCCIO1 Reset CY39200 VCCIO2 VCCIO2 VCCIO3 VCCIO3 CCLK VCCCNFG VCCIO2 VCCIO3 IO/VREF1 VCCIO1 Reset Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued) CY39050 VCCIO4 IO/VREF2 IO/VREF3 VCCIO2 IO/VREF2 CY39100 IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 VCCIO4 IO/VREF2 IO/VREF3 VCCIO2 IO/VREF2 CY39165 IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 VCCIO4 IO/VREF4 IO/VREF2 IO/VREF3 VCCIO2 IO/VREF2 CY39200 IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 VCCIO4 IO/VREF4 IO/VREF2 IO/VREF3 VCCIO2 IO/VREF2 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table (continued) AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 CY39050 IO/VREF3 VCCIO3 CY39100 IO/VREF3 VCCIO3 CY39165 VCCIO2 VCCIO3 IO3[21]
[21]
CY39200 VCCIO2 VCCIO3 IO/VREF3 VCCIO3 IO/VREF2 IO/VREF2 IO/VREF3
IO/VREF3 VCCIO3 IO/VREF2 IO/VREF2
Note: These I/Os have slightly higher (propagation delay) than rest pins. these pins same packages different densities pins same relative position smaller larger FBGAs signals with critical timing should avoided. When first implementing design these packages, timing-driven routing Warp later versions will ensure these pins avoided when routing critical signal.
Document 38-03039 Rev.
Page
Delta39KISRCPLD Family
Table FBGA Table CY39100 CY39165 VCCIO7 VCCIO7 VCCIO6 VCCIO6 CY39200 VCCIO7 VCCIO7 VCCIO6 VCCIO6 Table FBGA Table CY39100 VCCIO7 IO/VREF7 CY39165 IO/VREF7 IO/VREF7 IO6[21] IO6[21] VCCIO7 IO/VREF7 CY39200 IO/VREF6 IO/VREF7 IO/VREF7 IO/VREF6 VCCIO7 IO/VREF7 Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table CY39100 IO/VREF6 VCCIO6 IO/VREF7 IO/VREF6 CY39165 VCCIO7 VCCIO6 IO/VREF6
[21]
Table FBGA Table CY39200 VCCIO7 VCCIO6 IO/VREF6 VCCIO6 IO/VREF7 IO/VREF6 CY39100 VCCIO0 IO/VREF7 IO/VREF7 IO6/Lock IO/VREF6 IO/VREF6 VCCIO5 VCCIO7 IO/VREF7 IO/VREF6 VCCPLL VCCIO6 CY39165 IO/VREF0 VCCIO0 IO/VREF7 IO/VREF7 IO6/Lock IO/VREF6 IO/VREF6 VCCIO5 IO/VREF5 VCCIO7 IO/VREF7 IO/VREF6 VCCPLL VCCIO6 IO6[21] CY39200 IO/VREF0 VCCIO0 IO/VREF7 IO/VREF7 IO6/Lock IO/VREF6 IO/VREF6 VCCIO5 IO/VREF5 VCCIO7 IO/VREF7 IO/VREF6 VCCPLL VCCIO6 Page
VCCIO6 IO/VREF7 IO/VREF6 IO6[21] IO6[21]
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table H13[20] H14[20] CY39100 VCCIO7 VCCIO7 VCCIO6 VCCIO6 IO/VREF7 CY39165 VCCIO7 VCCIO7 VCCIO6 VCCIO6
[21]
Table FBGA Table CY39200 VCCIO7 VCCIO7 VCCIO6 VCCIO6 IO/VREF7 J13[20] J14[20] K13[20] K14[20] CY39100 IO/VREF6 TCLK CY39165 IO/VREF6 TCLK
[21]
CY39200 IO/VREF6 TCLK IO/VREF0 VCCIO0 Page
IO/VREF7
IO/VREF0 VCCIO0
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table CY39100 IO/VREF0 VCCIO0 IO/VREF0 GCTL3 GCLK3 GCTL2 GCLK2 IO/VREF5 VCCIO5 VCCJTAG IO/VREF5 VCCIO0 IO/VREF0 GCTL0 GCTL1 IO/VREF5 VCCIO5 CY39165 IO/VREF0 VCCIO0 IO/VREF0 GCTL3 GCLK3 GCTL2 GCLK2 IO/VREF5 VCCIO5 VCCJTAG IO/VREF5 VCCIO5 IO/VREF5 VCCIO0 IO/VREF0 GCTL0 GCTL1 IO/VREF5 VCCIO5 CY39200 IO/VREF0 VCCIO0 IO/VREF0 GCTL3 GCLK3 GCTL2 GCLK2 IO/VREF5 VCCIO5 VCCJTAG IO/VREF5 VCCIO5 IO/VREF5 VCCIO0 IO/VREF0 GCTL0 GCTL1 IO/VREF5 VCCIO5 Table FBGA Table
[20]
CY39100 IO/VREF0 GCLK0 GCLK1 IO/VREF5
CY39165 IO/VREF0 GCLK0 GCLK1 IO/VREF5
CY39200 IO/VREF0 GCLK0 GCLK1 IO/VREF5 Page
N7[20]
[20]
N19[20]
[20]
N21[20]
[20]
P9[20] P10[20]
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table P17[20] P18[20] P19[20] CY39100 VCCPRG VCCIO1 IO/VREF1 IO/VREF4 VCCIO4 VCCPRG IO/VREF1 CY39165 VCCPRG VCCIO1 IO/VREF1 IO/VREF4 VCCIO4 VCCPRG IO/VREF1 VCCIO1 IO/VREF1 CY39200 VCCPRG VCCIO1 IO/VREF1 IO/VREF4 VCCIO4 VCCPRG IO/VREF1 VCCIO1 IO/VREF1 Table FBGA Table T13[20] T14[20] U13[20] U14[20] CY39100 VCCIO1 IO/VREF1 VCCCNFG Config_Done IO/VREF4 VCCIO4 IO/VREF4 Data Reconfig CY39165 VCCIO1 IO/VREF1 VCCCNFG Config_Done IO/VREF4 VCCIO4 IO/VREF4 VCCIO4 IO/VREF4 Data Reconfig CY39200 VCCIO1 IO/VREF1 VCCCNFG Config_Done IO/VREF4 VCCIO4 IO/VREF4 VCCIO4 IO/VREF4 Data Reconfig Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table V13[20] V14[20] CY39100 IO/VREF1 MSEL IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 IO/VREF4 VCCIO2 VCCIO2 VCCIO3 VCCIO3 CY39165 IO/VREF1 MSEL IO/VREF2 IO/VREF2 IO/VREF3[21] IO/VREF3 IO/VREF4 VCCIO2 VCCIO2 VCCIO3 VCCIO3 CY39200 IO/VREF1 MSEL IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 IO/VREF4 VCCIO2 VCCIO2 VCCIO3 VCCIO3 Table FBGA Table CY39100 CCLK VCCCNFG VCCIO2 VCCIO3 VCCIO1 Reset CY39165 CCLK VCCCNFG VCCIO2 VCCIO3 IO/VREF1 VCCIO1 Reset CY39200 CCLK VCCCNFG VCCIO2 VCCIO3 IO/VREF1 VCCIO1 Reset Page
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 CY39100 IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 VCCIO4 IO/VREF2 IO/VREF3 CY39165 IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 VCCIO4 IO/VREF4 IO/VREF2 IO/VREF3 IO3[21] CY39200 IO/VREF2 IO/VREF2 IO/VREF3 IO/VREF3 VCCIO4 IO/VREF4 IO/VREF2 IO/VREF3 Table FBGA Table AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 CY39100 VCCIO2 IO/VREF2 IO/VREF3 VCCIO3 CY39165 VCCIO2 IO/VREF2 VCCIO2 VCCIO3 IO3[21]
[21]
CY39200 VCCIO2 IO/VREF2 VCCIO2 VCCIO3 IO/VREF3 VCCIO3 IO/VREF2 IO/VREF2 Page
IO3[21] IO/VREF3[21] VCCIO3 IO/VREF2 IO/VREF2 IO3[21] IO3[21]
Document 38-03039 Rev.
Delta39KISRCPLD Family
Table FBGA Table AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 CY39100 CY39165 CY39200 IO/VREF3 IO/VREF3 Table FBGA Table AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 CY39100 CY39165 VCCIO2 VCCIO2 VCCIO3 VCCIO3 CY39200 VCCIO2 VCCIO2 VCCIO3 VCCIO3
NoBL, PIM, Spread Aware, AnyVolt, Self-Boot, In-System Reprogrammable, ISR, "CPLDs FPGA Densities," True Vertical Migration, Delta39K trademarks Cypress Semiconductor Corporation. Warp registered trademark Cypress Semiconductor Corporation. Windows Windows Windows trademarks Microsoft Corporation. trademark IDT. trademark Micron, IDT, Cypress Semiconductor Corporation. SpeedWave, ViewDraw trademarks ViewLogic. product company names mentioned this document trademarks their respective holders.
Document 38-03039 Rev.
Page
Cypress Semiconductor Corporation, 2002. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
Delta39KISRCPLD Family
Document History Page
Document Title: Delta39K CPLD Family CPLDs FPGA DensitiesDocument Number: 38-03039 REV. 106503 107625 Issue Date 05/30/01 07/11/01 Orig. Change Description Change Change from Spec 38-00830 38-03039 Deleted 39K15 device associated -250-MHz specs Deleted 144FBGA package associated part numbers Changed spec from "MIL-STD-883" "JEDEC EIA/JESD22-A114-A" Changed Prime 39K50 39K30 from "MHz" "233 MHz" Changed part ordering information accordingly Updated -233-MHz timing specs match modified timing specs achieved design (main affected params: tPD, tMCCO, tIOS, tSCS, tSCS2, fMAX2, tCLMAA, tCLMCYC2, tCHMCYC2, tCHMCLK) Updated standard Timing Delay Specs changed default standard from 3.3V LVCMOS Added paragraph about Delta39K being CompactPCI swap Ready Added mode description Added Standby spec Updated recommended boot PROM 39K165/200 CY3LV002 instead CY3LV020 Updated Delta39K family offering Modified timing parameters tDWSA, tDWOSA, tMCCJ, tLOCK. Added tINDUTY parameter Deleted exception CompactPCI Swap compliance regarding "PCI buffers." Added reference note "Hot Socketing Delta39K" Revised CompactPCI Swap Specification R1.0 R2.0 Combined with spec# 38-03040 Updated tables 39K30 (208PQFP, 256FBGA) 53-93) Updated tables 39K50 (208PQFP, 256/484FBGA, 388BGA) (p.53-93) Added multiplication modes Spread Aware Added parameters (fPLLVCO, PSAPLLI, fMPPLI) Added updated Storage Temperature 39K200-208EQFP (p.16) Changed Icc0 spec 39K165 39K200 (p.16) Updated tCLZ, tCHMCYC2 parameter Values -233MHz Updated Input Output Standard Timing Delay Adjustment table Removed Self Boot Industrial parts from offering Removed Delta39K165Z (1.8V) from offering Removed 144-FBGA package offering Added self-boot Flash Memory endurance data retention data Added Family, Package, Density Migration section Added note 484/676 FBGA table identify slow 39K165 (page Changed data sheet status from Preliminary Final Added note Characteristics (p.16) Updated spec 51-85103 (MG388 package drawing) rev. Changed definition following pins CY39030 -256FBGA package: A10: From IO/Vref7 IO/Vref6 From IO/Vref6 Added Table identify Bank Location Global Clock Global Control Pins
109681
11/16/01
112376 112946
12/21/01 04/04/02
117518 121063 122543
10/04/02 11/06/02 12/10/02
Document 38-03039 Rev.
Page
Other recent searches
SY100EL14V - SY100EL14V SY100EL14V Datasheet
STE40NA60 - STE40NA60 STE40NA60 Datasheet
PT570110 - PT570110 PT570110 Datasheet
LM339 - LM339 LM339 Datasheet
K4N26323AE-GC - K4N26323AE-GC K4N26323AE-GC Datasheet
JTOS-1000W+ - JTOS-1000W+ JTOS-1000W+ Datasheet
BYV25FB-600 - BYV25FB-600 BYV25FB-600 Datasheet
1N3644 - 1N3644 1N3644 Datasheet
1N3645 - 1N3645 1N3645 Datasheet
1N3646 - 1N3646 1N3646 Datasheet
1N3647 - 1N3647 1N3647 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
