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SPLC560C
COM/SEG Driver
MAY. 2005 Version
patent other rights third parties which result from use. addition, Sunplus products authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product reasonably expected result significant injury user, without express written approval Sunplus.
SPLC560C
Table Contents
PAGE
GENERAL DESCRIPTION FEATURES BLOCK DIAGRAM 3.1. BLOCK FUNCTIONS 3.2. INPUT/OUTPUT CIRCUITS SIGNAL DESCRIPTIONS. FUNCTIONAL DESCRIPTIONS.
5.1. FUNCTIONS. 5.2. FUNCTION OPERATIONS 5.3. RELATIONSHIP BETWEEN DISPLAY DATA DRIVER OUTPUT PINS 5.4. PRECAUTIONS ELECTRICAL SPECIFICATIONS 6.1. ABSOLUTE MAXIMUM RATINGS 6.2. RECOMMENDED OPERATING CONDITIONS 6.3. CHARACTERISTICS 6.4. CHARACTERISTICS 6.5. TIMING CHARACTERISTICS SEGMENT MODE. PACKAGE/PAD LOCATIONS 7.1. ASSIGNMENT LOCATIONS 7.2. ORDERING INFORMATION 7.3. PACKAGE INFORMATION DISCLAIMER. REVISION HISTORY
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SPLC560C
COM/SEG DRIVER
GENERAL DESCRIPTION
SPLC560C 160-output segment/common driver suitable driving large/medium scale matrix panels, used personal computers/work-stations. Through (Super Slim TCP) technology, ideal substantially decreasing size frame section module. SPLC560C good both segment driver common driver, create power consuming, high-resolution LCD. Segment Mode Shift clock frequency: 14MHz (Max.) (VDD +5.0V±10%) 8.0MHz (Max.) (VDD +2.5V +4.5V) Adopts data system 4-bit/8-bit parallel input modes selectable with mode (MD) Automatic transfer function enable signal
Automatic counting function which, chip select mode,
FEATURES
Both Segment Mode Common Mode Number drive outputs:
causes internal clock stopped automatically
Supply voltage drive: +15V +30V power consumption output impedance
Supply voltage logic system: +2.5V +5.5V
CMOS silicon gate process (P-type silicon substrate)
Package: 188-pin (Tape Carrier Package) bump chip Common Mode
Built-in bits bi-directional shift register (divisible into bits (VDD +2.5V +5.5V) Shift clock frequency: 4.0MHz (Max.)
Available single mode (160 bits shift register) dual mode bits shift register Y160 Y160
Y80, Y160 Y160 Y81,
above shift directions pin-selectable
Shift register circuit reset function when DISPOFF active
BLOCK DIAGRAM
V12R V43R LEVEL SHIFTER
DISPOFF
counting input data
Line latch circuits reset when DISPOFF active
Y159 Y160
V43L V12L
BITS 4-LEVEL DRIVER
EI01 EI02
ACTIVE CONTROL
BITS LEVEL SHIFTER
BITS LINE LATCH/SHIFT REGISTER
CONTROL LOGIC
8BITS*2 DATA LATCH
DATA LATCH CONTROL
CONVERSION DATA CONTROL
TEST CIRCUIT
Single mode Single mode Dual mode Dual mode
TEST1 TEST2
Remark: TCP's external shape customized. order your TCP's external shape, please contact SUNPLUS salesperson.
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3.1. Block Functions 3.1.1. Active control
case segment mode, controls selection non-selection chip. Following signal, after chip select signal Once data input been completed, input, select signal generated internally until bits data have been read non-selected. select signal cascade connection output, chip case common mode, controls input/output data bidirectional pins.
3.1.5. Line latch/shift register
case segment mode, bits which have been read into data latch simultaneously latched falling edge signal, output level shifter block. case common mode, shifts data from data input falling edge signal.
3.1.6. Level shifter
level, output driver block.
logic voltage signal level-shifted driver voltage
3.1.2. conversion data control
case segment mode, keep input data which clocks 4-bit parallel mode into latch circuit, keep input data which clock 8-bits parallel mode into latch circuit, after that they internal data bits time.
3.1.7. 4-level driver
3.1.3. Data latch control
case segment mode, selects state data latch which reads data signals. shift direction controlled signal shifts based state control circuit.
control logic, every bits data read selection
3.1.4. Data latch
case segment mode, latches data data bus.
latched state each driver output controlled control logic data latch control, bits data read sets bits.
3.2. Input/Output Circuits
DISPOFF signals.
Drives driver output pins from line latch/shift register
data, selecting levels (V0, V12, V43, based S/C,
3.1.8. Control logic
Controls operation each block.
case segment mode,
when signal been input, blocks reset control logic waits selection signal output from active control block.
Internal Circuit
Applicable pins L/R, S/C, DI6-DI0, DISPOFF,
Figure Input Circuit
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Control Signal
Internal Circuit
VSS(0
VSS(0
Figure Input Circuit
Internal Circuit Control Signal Output Signal Control Signal
Figure Input/Output Circuit
Applicable pins DI7,
Applicable pins
Control Signal
Control Signal
Control Signal
Internal Circuit
Control Signal
Applicable pins
Y160
Figure Drive Output Circuit
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SIGNAL DESCRIPTIONS
Mnemonic Y160 V12L V12R V43L V43R EIO1 EIO2 161, 212, 163, 210, 165, 208, 167, 206, 172, Power supply driver Power supply driver Power supply driver Type driver output Power supply driver Description
Input selecting reading direction display data segment mode/Input selecting shift direction shift register common mode Power supply logic system (+2.5V +5.5V)
DISPOFF
Segment mode/common mode selection common mode Display data input segment mode Clock input taking display data segment mode Control input output non-select level common mode AC-converting signal input driver waveform Mode selection input Ground (0V) 169, 170,175 204,
Input/output chip selection segment mode/Shift data input/output shift register
Display data input segment mode/Dual mode data input common mode
Latch pulse input display data segment mode/Shift clock input shift register
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FUNCTIONAL DESCRIPTIONS
5.1. Functions 5.1.1. Segment mode
Mnemonic V0R, V12R, V12L V43R, V43L V5L, Description Logic system power supply connects +2.5V +5.5V Ground connects Bias Power supply driver voltage Normally, bias voltage used resistor divider. Ensure that voltage such that VSSV5
must connect external power supply, supply regular voltage which
assigned specification each power pin.
applications, even though have same voltage level, layout should shorted directly panel. That should have individual path connect-pin. Input pins display data
DISPOFF
4-bit parallel input mode, input data into pins, DI0. 8-bit parallel input mode, input data into pins, DI0. Operations. Clock input taking display data Latch pulse input display data Data read falling edge clock pulse. Data latched falling edge clock pulse. Input selecting reading direction display data When level "L", data read sequentially from When level "H", data read sequentially from Y160. Operations. Control input output non-select level circuit. When level "L", drive output pins (Y160 level output reading data correctly. Table truth values shown "TRUTH TABLE" Function Operations. Segment mode/common mode selection When level "H", segment mode set. signal input driving waveform circuit. Normally, inputs frame inversion signal.
Connect VDD.
Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional
Refer "REALATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional
input signal level-shifted from logic voltage level drive voltage level, controls drive
While "L", contents line latch reset, display data read data latch regardless condition DISPOFF When DISPOFF function canceled, driver outputs
non-select level (V12 V43), then outputs contents data latch next falling edge that time, DISPOFF removal time does correspond what shown characteristics, cannot
input signal level-shifted from logic voltage level drive voltage level, controls drive
driver output pin's output voltage level using line latch output signal signal. Table truth values shown "TRUTH TABLE" Function Operations.
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Mnemonic Mode selection When level "L", 4-bit parallel input mode set. When level "H", 8-bit parallel input mode set. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. EIO1 EIO2 Input/output pins chip selection When input Level "L", EIO1 output EIO2 input. When input Level "H", EIO1 input EIO2 output. cycle (from falling edge falling edge XCK), after which returns "H". During output, while after bits data have been read, Description
During input, chip selected while after signal input. chip non-selected after bits data have been read. Y160 driver output pins
5.1.2. Common mode
Mnemonic V0R, V12R, V12L V43R, V43L V5L, EIO1
EIO2
Table truth values shown "TRUTH TABLE" Function Operations. Description Logic system power supply connects +2.5V +5.5V. Ground connects Bias Power supply driver voltage Normally, bias voltage used resistor divider. Ensure that voltage such that VSSV5 <V43<V12<V0. specification each power pin. Shift clock pulse input bi-directional shift register Data shifted falling edge clock pulse. Shift data input/output bi-directional shift register Output when level "L", input when level "H". When EIO1 used output pin, won't pull-down. Operations. When EIO1 used input pin, will pull-down. Shift data input/output bi-directional shift register Input when level "L", output when level "H". When EIO2 used input pin, will pull-down. When EIO2 used output pin, won't pull-down. Operations. Input selecting shift direction bi-directional shift register level "H".
Corresponding directly each shift register, level (V0, V12, V43, selected output.
must connect external power supply, supply regular voltage, which assigned
Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional
Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional
Data shifted from Y160 when level "L", data shifted from Y160 when Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations.
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Mnemonic signal input driving waveform input signal level-shifted from logic voltage level drive voltage level, controls drive circuit. Normally, input frame inversion signal. driver output pin's output voltage level using shift register output signal signal. Table truth values shown "TRUTH TABLE" Functional Operations. Segment mode/common mode selection When level "L", common mode set. Control input output non-select level circuit. Description
DISPOFF
input signal level-shifted from logic voltage level drive voltage level, controls drive When level "L", drive output pins (Y160 level
Y160
shift data reading correctly. Table truth values shown "TRUTH TABLE" Functional Operations. Mode selection When level "L", single mode operation selected. When level "H", dual mode operation selected. Operations. Dual mode data input When chip used dual mode, will pull-down. When chip used single mode, won't pull-down. Operations. used Connect VDD, avoiding floating. used pull-down common mode, connect open. driver output pins Table truth values shown "TRUTH TABLE" Functional Operations.
While "L", contents shift register reset reading data. When DISPOFF function canceled, driver outputs non-select level (V12 V43), shift data reading next falling edge that time, DISPOFF removal time does correspond what shown characteristics,
Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional
According data shift direction data shift register, data input starting from 81st bit.
Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional
Corresponding directly each shift register, level (V0, V12, V43, selected output.
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5.2. Function Operations 5.2.1. Truth table 5.2.1.1. Segment mode
Latch data DISPOFF Driver output voltage level (Y160
5.2.1.2. Common mode
Latch data DISPOFF
Don't care
Driver output voltage level (Y160
Note1: (0V), (+2.5V +5.5V), Note2: "Don't care" should fixed "L", avoiding floating. There kinds power supply (logic level voltage drive specification each power pin. voltage) driver. Supply regular voltage which assigned
5.3. Relationship between Display Data Driver Output Pins 5.3.1. Segment mode
5.3.1.1. 4-bit parallel mode
EIO1
Output
EIO2 Data Figure clock Input Clock Clock Clock Clock Y149 Input Y150 Y151 Y152 Y160 Y159 Y158 Y157 Y156 Y155 Y154 Y153 Y152 Y151 Y150 Y149 Input Output
Y153 Y154 Y155 Y156
Clock Y157 Y158 Y159 Y160
Clock
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5.3.1.2. 8-bit parallel mode
EIO1 EIO2 Data Input Output Input Input Output Clock Y160 Y159 Y158 Y157 Y156 Y155 Y154 Y153 Clock Y152 Y151 Y150 Y149 Y148 Y147 Y146 Y145 Figure clock Clock Y144 Y143 Clock Y137 Y138 Y139 Y140 Y141 Y142 Clock Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Clock Y153 Y154 Y155 Y156 Y157 Y158
5.3.2. Common mode
(Single)
(Dual)
Note1: (0V), (+2.5V +5.5V), Don't care
Note2: "Don't care" should fixed "L", avoiding floating.
Y139 Y138 Y137 Data transfer direction Y160 Y160 EIO1 L(shift left) Output Input H(shift right) L(shift left) Y160 Output H(shift right) Y160 Input
Y141 Y140
Y142
Y143
Y144
EIO2 Input Output Input
Y159 Y160
Input
Output
Input
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5.3.3. Connection examples plural segment drivers
CASE data Y160 EIO2 EIO1 Y160 EIO2 EIO1 Y160 EIO2 last data EIO1
CASE
data
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EIO1
EIO2 Y160 last data
EIO2
EIO1
EIO2
EIO1
Y160
Y160
MAY. 2005 Version:
SPLC560C
5.3.4. Timing characteristics 4-device casecade connection segment drivers
DATA
LAST DATA
(device (device
(device
(device
n=40 4-bit parallel input mode. n=20 8-bit parallel input mode.
device
device
device
device
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5.3.5. Connection examples plural common drivers
SINGLE MODE (SHIFTING TOWARD LEFT) first Y160 EIO2 EIO1 DISPOFF Y160 EIO2 EIO1 Y160 EIO2 last EIO1
VSS(VDD)
DISPOFF
SINGLE MODE (SHIFTING TOWARD RIGHT)
DISPOFF
VSS(VDD)
DISPOFF DISPOFF EIO1 EIO2 EIO1 EIO2 EIO1 Y160 Y160 first
DISPOFF
DISPOFF
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EIO2 Y160 last
DISPOFF
MAY. 2005 Version:
SPLC560C
5.4. Precautions 5.4.1. Precaution when connecting disconnecting power
This high-voltage driver, permanently damaged high current which flow voltage supplied driver power supply while logic system power supply floating. when connecting logic power supply, logic condition this inside insecurity. Therefore connect driver power supply after resetting logic condition this inside
DISPOFF function.
After that, cancel DISPOFF function
after driver power supply become stable. detail follows: When connecting power supply, connect drive power after connecting logic system power. Furthermore, when disconnecting power, disconnect logic system power after disconnecting driver power. recommend connecting serial resistor (50~100) limiter. fuse drive power system current consideration display grade. Furthermore, when disconnecting power, drive output pins level DISPOFF function.
disconnect logic system power after disconnecting drive power.
suitable value resistor
When connecting power supply, follow recommended sequence shown here.
DISPOFF
After that,
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ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Parameter Supply voltage Symbol Supply voltage Input voltage Storage temperature
Note1: Note2: maximum applicable voltage with respect (0V). conditions AC/DC Electrical Characteristics.
Conditions
Applicable Pins V0L,
Ratings -0.3 +6.5 -0.3 V0-5.0 V0+0.3 -0.3 V0+0.3
Unit
Referenced (0V)
V12L, V12R V43L, V43R V5L, XCK, L/R, S/C, EIO1, EIO2, DISPOFF
TSTG
Note3: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device. normal operational
6.2. Recommended Operating Conditions
Parameter Symbol
Supply voltage Supply voltage
Operating temperature
Note1: applicable voltage with respect (0V). Note2: Ensure that voltage such that VSSV5V43V12V0
6.3. Characteristics 6.3.1. Segment mode
Parameter Input voltage
Output voltage
Input leakage current
Output resistance Stand-by current
Conditions Applicable Pins Min. +2.5 Referenced (0V) V0L, TOPR Symbol Conditions Applicable Pins Min. XCK, L/R, S/C, EIO1, EIO2, DISPOFF EIO1, EIO2 0.8VDD ILIH ILIL -0.4mA VDD-0.4 +0.4mA XCK, L/R, S/C, EIO1, EIO2, DISPOFF Y160 V0L, ISTB IDD1 IDD2 |VON| 0.5V +30V +20V
-0.3 V0+0.3
-0.3 VDD+0.3 +125
Unit
Typ.
Max. +5.5
(VSS +2.5V +5.5V, +15V +30V, +25) Typ. Max. 0.2VDD +0.4 Unit
Supply current (Deselection) Supply current (Selection) Supply current
Note1: +5.0V, +30V, Note2: +5.0V, +30V, fXCK 14.0MHz, No-load, VDD. input data turned over data taking clock (4-bit parallel input mode) Note3: +5.0V, +30V, fXCK 14.0MHz, No-load, VSS. mode. input data turned over data taking clock (4-bit parallel input mode) input data turned over data taking clock (4-bit parallel input Note4: +5.0V, +30V, fXCK 14.0MHz, 41.6KHz, 80Hz, No-load.
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6.3.2. Common mode
(VSS +2.5V +5.5V, +15V +30V, +25) Parameter Input voltage Symbol ILIH ILIL ISTB Conditions -0.4mA +0.4mA |VON| 0.5V +30V +20V Applicable Pins XCK, L/R, S/C, EIO1, EIO2, DISPOFF EIO1, EIO2 XCK, L/R, S/C, EIO1, EIO2, DISPOFF Y160 Min. 0.8VDD VDD-0.4 Typ. Max. 0.2VDD +0.4 Unit
Output voltage
Input leakage current
Output resistance Input pull-down current Stand-by current
XCK, EIO1, EIO2,
Supply current Supply current
Note1: +5.0V, +30V,
Note2: +5.0V, +30V, 41.6KHz, 80Hz case 1/320 duty operation, no-load.
6.4. Characteristics
6.4.1. Segment mode
Parameter Shift clock period
Shift clock pulse width Shift clock pulse width Data setup time Data hold time
Latch pulse pulse width
Shift clock rise latch pulse rise time Shift clock fall latch pulse fall time
Latch pulse rise shift clock rise time Latch pulse fall shift clock fall time Input signal rise time Input signal fall time Enable setup time
V0L, Symbol TWCK Conditions Min. Typ. Max. TF10ns TWCKH TWCKL TWLPH 15pF 15pF 15pF TWDL TPD1, TPD2 TPD3
(VSS +4.5V +5.5V, +15V +30V, +25) Unit
DISPOFF removal time DISPOFF pulse width
Output delay time Output delay time Output delay time
Note1: Take cascade connection into consideration.
Note2: (TWCK TWCKH TWCKL) maximum case high speed operation.
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6.4.2. Segment mode
(VSS +2.5V +4.5V, +15V +30V, +25) Parameter Shift clock period Shift clock pulse width Shift clock pulse width Data setup time Data hold time Latch pulse pulse width Shift clock rise latch pulse rise time Shift clock fall latch pulse fall time Latch pulse rise shift clock rise time Latch pulse fall shift clock fall time Input signal rise time Input signal fall time Enable setup time Symbol TWCK TWCKH TWCKL TWLPH Conditions TF11ns Min. Typ. Max. Unit
DISPOFF removal time
DISPOFF pulse width
Output delay time Output delay time Output delay time
Note1: Take cascade connection into consideration.
Note2: (TWCK TWCKH TWCKL) maximum case high speed operation.
6.5. Timing Characteristics Segment Mode
TWDL 15pF 15pF TPD1, TPD2 TPD3 15pF TWLPH TWCKH TWCKL TWCK LAST DATA DATA TWDL
DISPOFF
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*n=40 4-bit parallel input mode. n=20 8-bit parallel input mode.
DISPOFF
Y160
TPD1 TPD2 TPD3
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6.5.1. Common mode
(VSS +2.5V +5.5V, +15V +30V, +25) Parameter Shift clock period Shift pulse width Data setup time Data hold time Input signal rise time Input signal fall time Symbol TWLP TWLPH TWDL TPD1, TPD2 TPD3 Conditions TF20ns +5.0V±10% +2.5V +4.5V 15pF 15pF 15pF Min. Typ. Max. Unit
DISPOFF removal time DISPOFF pulse width
Output delay time Output delay time Output delay time
6.5.2. Timing characteristics common mode
EIO2 (DI7)
EIO1
DISPOFF
TWLP TWLPH TWDL
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TPD1 TPD2
DISPOFF
TPD3 Y160 [L/R "L"]
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PACKAGE/PAD LOCATIONS
7.1. Assignment Locations
Please contact Sunplus sales representatives more information.
7.2. Ordering Information
Product Number SPLC560C-C SPLC560C-PT051 Chip form Package form Package Type
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7.3. Package Information
INPUT LEAD (coarse pitch outer lead)
OUTPUT LEAD (fine pitch outer lead)
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DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHERMORE, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications.
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. Please note that application circuits illustrated this document reference purposes only.
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REVISION HISTORY
Date MAY. 2005 JUN. 2004 NOV. 2003 FEB. 2003 APR. 2002 Revision Delete Correct Revise from EIO2 EIO1 when L/R=VDD "Single mode (shifting toward right)" "7.2 Package Information" Modify "6.1 Absolute Maximum Ratings" Remove "Preliminary" Correct pitch "7.1 Assignment" Original Description Page
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