October 1987 Revised January 1999 CD4007C Dual Complementary Pair

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October 1987 Revised January 1999 CD4007C Dual Complementary Pair

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CD4007C Dual Complementary Pair Plus Inverter
October 1987 Revised January 1999
CD4007C Dual Complementary Pair Plus Inverter
CD4007C consists three complementary pairs Nand P-channel enhancement mode transistors suitable series/shunt applications. inputs protected from static discharge diode clamps VSS. proper operation voltages pins must constrained between 0.3V 0.3V times.
Features
Wide supply voltage range: High noise immunity: 3.0V 0.45 (typ.)
Ordering Code:
Order Number CD4007CM CD4007CN Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available Tape Reel. Specify appending suffix letter ordering code.
Connection Diagram
Assignments SOIC
Note: P-channel substrates connected N-channel substrates connected VSS.
View
1999 Fairchild Semiconductor Corporation
DS005943.prf
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CD4007C
Absolute Maximum Ratings(Note
Voltage Operating Temperature Range Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline -0.3V +0.3V -40°C +85°C -65°C +150°C Operating Range Lead Temperature (Soldering, seconds) 260°C +3.0V +15V
Note This device should connected circuits with power because high transient voltages cause permanent damage.
Electrical Characteristics
Limits Symbol Parameter Quiescent Device Current Quiescent Device Dissipation Package Output Voltage Level Output Voltage HIGH Level Noise Immunity (All inputs) Noise Immunity (All Inputs) Output Drive Current N-Channel Output Drive Current P-Channel Input Current Conditions 5.0V 5.0V 5.0V 5.0V 5.0V, 3.6V 10V, 7.2V 5.0V, 0.95V 10V, 2.9V 5.0V, 0.4V, 10V, 0.5V, 5.0V, 2.5V, 10V, 9.5V, 0.35 -1.3 -0.65 4.95 9.95 -1.1 -0.55 -40°C 0.05 0.05 4.95 9.95 +25°C 0.005 0.005 0.025 0.05 2.25 2.25 -4.0 -2.5 0.24 -0.9 -0.45 0.05 0.01 0.01 4.95 9.95 +85°C 0.05 0.05 Units
Electrical Characteristics
Symbol tPLH tPHL tTLH tTHL Parameter Propagation Delay Time Transition Time Input Capacitance
(Note
Conditions 5.0V 5.0V Input Units
25°C rise fall times Typical temperature coefficient values 0.3%/°C
Note Parameters guaranteed correlated testing.
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CD4007C
Test Circuits
Switching Time Waveforms
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CD4007C
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Package Number M14A
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CD4007C Dual Complementary Pair Plus Inverter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: critical component component life support Life support devices systems devices systems device system whose failure perform reawhich, intended surgical implant into sonably expected cause failure life support body, support sustain life, whose failure device system, affect safety effectiveness. perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury www.fairchildsemi.com user.
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications.

October 1987 Revised January 1999 CD4007C Dual Complementary Pair

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