µPD78P064B 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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µPD78P064B 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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INTEGRATED CIRCUIT
µPD78P064B
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD78P064B product µPD78064B subseries 78K/0 series, which on-chip mask
µPD78064B replaced one-time PROM.
program write user possible, µPD78P064B best suited evaluation, short-run multiple-device production, early rise upon system development. Functions described detail following User's Manuals, which should read when carrying design work.
µPD78064B Subseries User's Manual: U10785E
78K/0 Series User's Manual Instruction: U12326E
FEATURES
compatible with mask products (except pin) Internal PROM: bytes One-time programming possible (most suitable small-scale production) Internal high-speed RAM: 1024 bytes display RAM: bits Operable same supply voltage mask products (VDD Corresponding QTOPmicrocomputers Remarks differences between PROM products mask products, refer DIFFERENCES BETWEEN PD78P064B MASK PRODUCTS. QTOP Microcomputer general name total support writing service, marking, screening, verification after programming one-time PROM internal signal-chip microcontroller offered NEC.
ORDERING INFORMATION
Part Number Package 100-pin plastic (fine pitch) 100-pin plastic LQFP (fine pitch) 100-pin plastic On-Chip One-time PROM One-time PROM One-time PROM
µPD78P064BGC-7EA µPD78P064BGC-8EU µPD78P064BGF-3BA
Caution
µPD78P064BGC types package. (Refer PACKAGE DRAWINGS). package suppliable your device, consult sales personnels.
information this document subject change without notice. Document U11598EJ2V0DS00 (2nd edition) Date Published 1997 Printed Japan
mark
shows major revised points.
1996
µPD78P064B
78K/0 SERIES DEVELOPMENT
following shows products organized according usage. names parallelograms subseries names.
Products mass production Products under development subseries products compatible with bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A
PD78075BY PD78078Y PD78070AY
EMI-noise reduced version PD78078 timer added PD78054 external interface enhanced ROM-less version µPD78078 Serial PD78078 enhanced function limited. Serial PD78054 enhanced EMI-noise reduced. EMI-noise reduced version PD78054 UART converter were enhanced PD78014 enhanced converter PD780024 enhanced Serial PD78018F added EMI-noise reduced. EMI-noise reduced version µPD78018F Low-voltage (1.8 operation version µPD78014, with larger selection capacities converter 16-bit timer were added µPD78002 converter added µPD78002 Basic subseries control On-chip UART, capable operating voltage (1.8
PD780018Note PD780018Y PD780058 PD780058YNote PD78058F PD78058FY µPD78054 µPD780034 PD780024 PD78014H µPD78018F µPD78014 PD780001 µPD78002 PD78083
Inverter control
PD78054Y µPD780034Y PD780024Y µPD78018FY PD78014Y PD78002Y
64-pin 64-pin
µPD780964 µPD780924
FIPdrive
converter PD780924 enhanced On-chip inverter control circuit UART. EMI-noise reduced.
100-pin 100-pin 78K/0 Series 80-pin 80-pin
PD780208 PD780228 PD78044H µPD78044F
drive
PD78044F were enhanced, Display output total: PD78044H were enhanced, Display output total:
N-ch open drain added PD78044F, Display output total:
Basic subseries driving FIP, Display output total:
100-pin 100-pin 100-pin
PD780308 µPD78064B PD78064
µPD780308Y PD78064Y
µPD78064 enhanced, ROM, capacity increased EMI-noise reduced version PD78064 Basic subseries driving LCDs, On-chip UART
IEBussupported 80-pin 80-pin
PD78098B PD78098
Meter control
EMI-noise reduced version µPD78098 IEBus controller added µPD78054
80-pin 100-pin
PD780973 PD780805
General purpose version automobile meter driving controller PD780805 On-chip automobile meter driving controller/driver
64-pin
PD78P0914
On-chip output, digital code decoder, Hsync counter
Note
Under planning
µPD78P064B
following lists main functional differences between subseries products.
Function Subseries Name Control Capacity 32K-40K 48K-60K 48K-60K 24K-60K 48K-60K 16K-60K 8K-32K (UART: 1ch, time division 3-wire: 1ch) 8K-60K 8K-32K 8K-16K 8K-32K Note 32K-60K 48K-60K 32K-48K 16K-40K (time division UART: 1ch) (UART: 1ch) (UART: 1ch) (UART: 2ch) (time division 3-wire: 1ch) 8-bit 10-bit 8-bit 8-bit 16-bit Watch Timer Serial Interface MIN. Value External Expansion
µPD78075B µPD78078 µPD78070A µPD780018 µPD780058 µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083
(UART: 1ch)
(time division UART: 1ch) (UART: 1ch)
Inverter control drive
µPD780964 µPD780924 µPD780208 µPD780228 µPD78044H µPD78044F
drive
µPD780308B 48K-60K µPD78064 µPD78064
16K-32K 40K-60K 32K-60K 24K-32K 40K-60K
IEBus µPD78098B supported µPD78098 Meter control
(UART: 1ch)
µPD780973 µPD780805
(UART: 1ch)
µPD78P0914
Note 10-bit timer: channel
µPD78P064B
FUNCTION DESCRIPTION
Item Internal memory PROM High-speed display Function bytes 1024 bytesNote bits
General-purpose register Instruction cycles When main system clock selected When subsystem clock selected Instruction
bits registers bits registers banks) µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 (when operating MHz) (when operating 32.768 kHz)
16-bit operation Multiplication/division bits bits, bits bits) manipulation (set, reset, test, boolean operation) correction, etc.
ports Include segment signal output dual-function converter controller/driver
Total CMOS input CMOS input/output 8-bit resolution Segment signal output Common signal output Bias
max. max. 1/2, 1/3, Bias switchable
Serial interface
3-wire serial I/O/SBI/2-wire serial mode selectable 3-wire serial I/O/UART mode selectable 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer
Timer
Timer output Clock output
pins (14-bit output enable pin) 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 MHz, MHz, (when operating main system clock MHz), 32.768 (when operating subsystem clock 32.768 kHz) kHz, kHz, kHz, (when operating main system clock MHz) Maskable Non-maskable Software Internal External Internal Internal External 100-pin plastic (fine pitch) 100-pin plastic LQFP (fine pitch) 100-pin plastic
Buzzer output Vectored interrupt sources
Test input Supply voltage Package
µPD78P064B
CONFIGURATION (Top View) Normal operating mode 100-pin plastic (fine pitch)
µPD78P064BGC-7EA
100-pin plastic LQFP (fine pitch)
µPD78P064BGC-8EU
P72/SCK2/ASCK P71/SO2/TXD P112 P111 P110 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00 RESET
P10/ANI0 AVSS P117 P116 P115 P114 P113
P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVDD AVREF P100 P101 P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ COM0 COM1 COM2
XT1/P07
P70/SI2/RXD P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24
COM3 BIAS VLC0 VLC1 VLC2
Cautions
Connect directly VSS. AVDD shares port power supply with that converter. When using applications where noise from inside microcomputer reduced, connect AVDD separate power supply, whose electrical potential same that VDD.
AVSS shares port with that converter. When using applications where noise from inside microcomputer reduced, connect AVSS separate ground line.
µPD78P064B
100-pin plastic
µPD78P068BGF-3BA
P25/SI0/SB0 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/P34
P26/SO0/SB1 P27/SCK0 P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK XT1/P07 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P110 P111 P112 P113 P114 P115 P116 P117 AVSS P10/ANI0 P11/ANI1 P12/ANI2
P86/P33 P87/P32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24
VLC2 VLC1 VLC0 BIAS COM3 COM2 COM1 COM0
P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVDD AVREF
Cautions
Connect directly VSS. AVDD shares port power supply with that converter. When using applications where noise from inside microcomputer reduced, connect AVDD separate power supply, whose electrical potential same that VDD.
AVSS shares port with that converter. When using applications where noise from inside microcomputer reduced, connect AVSS separate ground line.
P100 P101 P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ
µPD78P064B
ANI0-ANI7 ASCK AVDD AVREF AVSS BIAS COM0-COM3 INTP0-INTP5 P00-P05, P10-P17 P25-P27 P30-P37 P70-P72 P80-P87 P90-P97 P100-P103 P110-P117
Analog Input Asynchronous Serial Clock Analog Power Supply Analog Reference Voltage Analog Ground Power Supply Bias Control Buzzer Clock Common Output Interrupt from Peripherals Port Port Port Port Port Port Port Port Port
RESET S0-S39 SB0, SI0, SO0, SCK0, SCK2 TI00, TI01 TI1,TI2 TO0-TO2 VLC0-VLC2 XT1,
Programmable Clock Reset Receive Data Segment Output Serial Serial Input Serial Output Serial Clock Timer Input Timer Input Timer Output Transmit Data Power Supply Power Supply Ground Programming Power Supply Crystal (Main System Clock) Crystal (Subsystem Clock)
µPD78P064B
PROM programming mode 100-pin plastic (fine pitch)
µPD78P064BGC-7EA
100-pin plastic LQFP (fine pitch)
µPD78P064BGC-8EU
RESET Open
Open
Cautions
RESET Open
Individually connect pull-down resistor. Connect GND. level. connection
µPD78P064B
100-pin plastic
µPD78P064BGF-3BA
Open Open RESET
Cautions
Open
Individually connect pull-down resistor. Connect GND. connection RESET Reset Power Supply Programming Power Supply Ground
RESET level.
Address Chip Enable Data Output Enable Program
µPD78P064B
BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33
16-bit TIMER/ EVENT COUNTER
PORT0 P01-P05
8-bit TIMER/EVENT COUNTER
PORT1
P10-P17
TO2/P32 TI2/P34
8-bit TIMER/EVENT COUNTER
PORT2
P25-P27
PORT3 WATCHDOG TIMER PORT7 WATCH TIMER
P30-P37
P70-P72
PORT8 78K/0 CORE
P80-P87
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SERIAL INTERFACE
PROM
PORT9
P90-P97
PORT10 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 SERIAL INTERFACE PORT11
P100-P103
P110-P117
S0-S23 ANI0/P10ANI7/P17 AVREF CONVERTER CONTROLLER/ DRIVER S24/P97S31/P90 S32/P97S39/P80 COM0-COM3 VLC0-VLC2 BIAS fLCD RESET XT1/P07
INTP0/P00INTP5/P05
INTERRUPT CONTROL
BUZ/P36
BUZZER OUTPUT
PCL/P35
CLOCK OUTPUT CONTROL
AVDD AVSS
SYSTEM CONTROL
µPD78P064B
CONTENTS DIFFERENCES BETWEEN µPD78P064B MASK PRODUCTS FUNCTION TABLE
PINS NORMAL OPERATING MODE PINS PROM PROGRAMMING MODE INPUT/OUTPUT CIRCUITS RECOMMENDED CONNECTION UNUSED PINS
MEMORY SIZE SWITCHING REGISTER (IMS) PROM PROGRAMMING
OPERATING MODES PROM WRITE PROCEDURE PROM READ PROCEDURE
ONE-TIME PROM PRODUCTS SCREENING ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS. APPENDIX RELATED DOCUMENTS
µPD78P064B
DIFFERENCES BETWEEN µPD78P064B MASK PRODUCTS
µPD78P064B single-chip microcontroller with on-chip one-time writable PROM. possible make functions exception PROM specification, mask option drive power supply dividing resistor, same those mask products setting memory size switching register (IMS). Difference between PROM product (µPD78P064B) mask product (µPD78064B) shown Table 1-1.
Table 1-1. Differences between µPD78P064B Mask Products
Item Internal structure Mask option drive power supply dividing resistor Electrical characteristics
µPD78P064B
One-time PROM
Mask Products Mask
Refer Data Sheet each product
Caution
Noise resistance noise radiation different PROM version mask versions. using mask version instead PROM version processes between prototype development full production, sure fully evaluate mask version (not ES).
Remark
internal PROM becomes bytes internal high-speed becomes 1024 bytes RESET input.
µPD78P064B
FUNCTION TABLE
PINS NORMAL OPERATING MODE PORT PINS (1/2)
Name P07Note
Input/Output Input Input/output Port 7-bit input/output port
Function Input only Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software.
After Reset Input Input
Dual-Function INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5
Input Input/output
Input only Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software.Note Port 3-bit input/output port Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software. Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software.
Input Input
ANI0 ANI7
Input/output
Input
SI0/SB0 SO0/SB1 SCK0
Input/output
Input
Input/output
Port 3-bit input/output port Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software.
Input
SI2/RXD SO2/TXD SCK2/ASCK
Notes When P07/XT1 pins used input ports, processor clock control register (PCC) (FRC) on-chip feedback resistor subsystem clock oscillation circuit.) When P10/ANI0 P17/ANI7 pins used analog inputs converter, port input mode. on-chip pull-up resistor automatically disabled.
µPD78P064B
PORT PINS (2/2)
After Reset Input
Name
Input/Output Input/output
Function Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software. Input/output port/segment signal output function specifiable 2-bit units display control register (LCDC). Port 8-bit input/output port. Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software. Input/output port/segment signal output function specifiable 2-bit units display control register. (LCDC). Port 4-bit input/output port Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software. possible directly drive LED. Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software. Falling edge detection possible.
Dual-Function
Input/output
Input
P100 P103
Input/output
Input
P110 P117
Input/output
Input
Caution
perform following operation pins shared with port pins during conversion operation; otherwise, specifications total error during conversion cannot satisfied (except pins shared with segment output pins). Rewriting output latch output used port Changing output level output even when used port
µPD78P064B
PINS OTHER THAN PORT PINS (1/2)
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 SCK0 SCK2 ASCK TI00 TI01
Input/Output Input
Function External interrupt request input with specifiable Valid edges (rising edge, falling edge, both rising falling edges).
After Reset Dual-Function Input P00/TI00 P01/TI01
Input
Serial data input serial interface
Input
P25/SB0 P70/RXD
Output
Serial data output serial interface
Input
P26/SBI P71/TXD
Input/output
Serial data input/output serial interface
Input
P25/SI0 P26/SO0
Input/output
Serial clock input/output serial interface
Input
P72/ASCK
Input Outpu Input Input
Serial data input asynchronouse serial interface Serial data output asynchronous serial interface Serial clock input asynchronous serial interface External count clock input 16-bit timer (TM0). Capture trigger signal input capture register (CR00). External count clock input 8-bit timer (TM1). External count clock input 8-bit timer (TM2).
Input Input Input Input
P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1
Output
16-bit timer (TM0) output (dual-function 14-bit output) 8-bit timer (TM1) output 8-bit timer (TM2) output
Input
Output
Input
Clock output (for trimming main system clock subsystem clock) Buzzer output controller/driver segment signal output
COM0 COM3 VLC0 VLC2 BIAS
Output Output
Input Output Input
P97-P90 P87-P80
Output
controller/driver common signal output drive voltage drive power supply
Output
µPD78P064B
PINS OTHER THAN PORT PINS (2/2)
Name ANI0 ANI7 AVREF AVDD
Input/Output Input Input
Function Analog input converter Reference voltage input converter Analog power supply converter (shared power supply port) Ground potential converter (shared ground potential port)
After Reset Input
Dual-Function
AVSS
RESET
Input Input
System reset input Main system clock oscillation crystal connection
Input
Subsystem clock oscillation crystal connection
Input
Positive power supply (except port) High-voltage applied during program write/verification Connected directly normal operating mode Ground potential (except port)
Cautions AVDD shares port power supply with that converter. When using applications where noise from inside microcomputer reduced, connect AVDD separate power supply, whose electrical potential same that VDD. AVSS shares port with that converter. When using applications where noise from inside microcomputer reduced, connect AVSS separate ground line.
PINS PROM PROGRAMMING MODE
Name RESET
Input/Output Input
Function PROM programming mode setting When +12.5 applied level signal applied RESET pin, this chip PROM programming mode. PROM programming mode setting high-voltage applied during program write/ verification Address Data PROM enable input/program pulse input Read strobe input PROM Program/program inhibit input PROM programing mode. Positive power supply Ground potential
Input
Input Input/output Input Input Input
µPD78P064B
INPUT/OUTPUT CIRCUITS RECOMMENDED CONNECTION UNUSED PINS
Types input/output circuits pins recommended connection unused pins shown Table 2-1. configuration each type input/output circuit, refer Figure 2-1. Table 2-1. Type Input/Output Circuit Each
Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P07/XT1 P10/ANI0 P17/ANI7 P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P80/S39 P87/S32 P90/S31 P97/S24 P100 P103 P110 P117 COM0 COM3 VLC0 VLC2 BIAS RESET AVREF AVDD AVSS Input Leave open Connect Connect separate power supply whose electrical potential same that VDD. Connect separate ground line whose electrical potential same that VSS. Connect directly 17-D 18-B Output Individually connect resistor Leave open 17-E 11-C 10-C Input Connect VDD. Individually connect resistor Input/Output Circuit Type Input Recommended Connection When Used Connect VSS. Individually connect resistor
µPD78P064B
Figure 2-1. List Input/Output Circuits (1/2)
Type Type 10-C
AVDD pull-up enable AVDD
P-ch
data
P-ch IN/OUT
open drain output disable
Schmitt-Triggered Input with Hysteresis Characteristic
N-ch AVSS
Type AVDD Pull-up enable AVDD Data P-ch IN/OUT Output disable N-ch AVSS Input enable
Type 11-C
AVDD pull-up enable
P-ch
P-ch AVDD P-ch IN/OUT
data
output disable Comparator
N-ch P-ch AVSS
N-ch AVSS VREF (Threshold voltage) input enable
Type
Type
AVDD feedback cut-off pull-up enable AVDD data P-ch IN/OUT output disable N-ch AVSS P-ch P-ch
µPD78P064B
Figure 2-1. List Input/Output Circuits (2/2)
Type 17-D Type 18-B
VLC0 P-ch
VLC0 P-ch VLC1 N-ch P-ch data P-ch VLC2 N-ch N-ch
VLC1 N-ch N-ch P-ch
data P-ch VLC2 N-ch
N-ch
P-ch
Type 17-E
AVDD
pull-up enable AVDD data P-ch
P-ch
IN/OUT output disable N-ch AVSS input enable VLC0 P-ch VLC1 N-ch P-ch data P-ch VLC2 N-ch N-ch
µPD78P064B
MEMORY SIZE SWITCHING REGISTER (IMS)
This register disable part internal memories software. setting this memory size switching register (IMS), possible same memory mapping that mask product having different internal memories (ROM, RAM). 8-bit memory manipulating instruction. will result RESET input. Figure 3-1. Memory Size Switching Register Format
Symbol
RAM2
RAM1
RAM0
ROM3
ROM2
ROM1
ROM0
Address FFF0H
After Reset
ROM3 ROM2 ROM1 ROM0
Selection Internal Capacity bytes Setting prohibited
Other than above
RAM2 RAM1 RAM0
Selection Internal High-Speed Capacity 1024 bytes Setting prohibited
Other than above
Table shows values which makes memory same that various mask products. Table 3-1. Memory Size Switching Register Setting Values
Target Mask Product
Setting Value
µPD78064B
µPD78P064B
PROM PROGRAMMING
µPD78P064B on-chip 32K-byte PROM program memory. programming, PROM programming mode RESET pins. processing unused pins, refer Configuration PROM programming mode. Caution When writing program, locations 0000H-7FFFH. (Specify last address 7FFFH). cannot write using PROM programmer that cannot specify addresses write.
OPERATING MODES
When +12.5 applied level signal applied RESET pin, PROM programming mode set. This mode will become operating mode shown Table when pins shown. Further, when read mode set, possible read contents PROM.
Table 4-1. Operating Modes PROM Programming
RESET Operating Mode Page data latch Page write Byte write Program verify Program inhibit +12.5 +6.5 Read Output disable Standby Data output High-impedance High-impedance Data input High-impedance Data input Data output High-impedance
µPD78P064B
Read mode Read mode set. Output disable mode Data output becomes high-impedance, output disable mode, set. Therefore, allows data read from device controlling pin, multiple µPD78P064Bs connected data bus. Standby mode Standby mode set. this mode, data outputs become high-impedance irrespective status. Page data latch mode Page data latch mode beginning page write mode. this mode, page 4-byte data latched internal address/data latch circuit. Page write mode After page bytes addresses data latched page data latch mode, page write executed applying program pulse (active low) with Then, program verification performed, set. programming performed one-time program pulse, write verification operations should executed repeatedly. Byte write mode Byte write executed when program pulse (active low) applied with Then, program verification performed set. programming performed one-time program pulse, write verification operations should executed repeatedly. Program verify mode Program verify mode set. this mode, check write operation performed correctly, after write. Program inhibit mode Program inhibit mode used when pin, pins multiple µPD78P064Bs connected parallel write performed those devices. When write operation performed, page write mode byte write mode described above used. this time, write performed device which driven high.
µPD78P064B
PROM WRITE PROCEDURE Figure 4-1. Page Program Mode Flow Chart
Start Address 12.5
Latch Address address Latch Address address Latch Address address Address address Latch
X=X+1 program pulse
Verify bytes Pass Address Pass
Fail
Verify bytes Pass Write
Fail
Faulty product
Start address Program last address
µPD78P064B
Figure 4-2. Page Program Mode Timing
Page Data Latch
Page Program
Program Verify
Data Input Data Output
µPD78P064B
Figure 4-3. Byte Program Mode Flow Chart
Start Address 12.5
X=X+1 Program pulse Address address Fail Verify Pass Address Pass Fail
Verify bytes Pass Write
Faulty product
Start address Program last address
µPD78P064B
Figure 4-4. Byte Program Mode Timing
Program
Program Verify
Data Input
Data Output
Cautions
should applied before after VPP. must exceed +13.5 including overshoot. Reliability adversely affected removal/reinsertion performed while +12.5 being applied VPP.
µPD78P064B
PROM READ PROCEDURE
contents PROM readable external data according read procedure shown below. RESET level, supply pin, process other unused pins shown Configuration PROM programming mode. Supply pins. Input address read data into pins. Read mode Output data pins. timings above steps shown Figure 4-5. Figure 4-5. PROM Read Timings
Address Input
(Input)
(Input)
Hi-Z
Data Output
Hi-Z
µPD78P064B
ONE-TIME PROM PRODUCTS SCREENING
one-time PROM product (µPD78P064BGC-7EA, µPD78P064BGC-8EU, µPD78P064BGF- 3BA) tested completely before shipped, because structure. recommended perform screening verify PROM after writing necessary data performing high-temperature storage under condition below.
Storage Temperature
Storage Time hours
present, charged one-time PROM after-programming writing, marking, screening, verify service QTOP Microcomputer. details, contact your sales representative.
µPD78P064B
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS 25°C)
Parameter Symbol Supply voltage AVDD AVREF AVSS Input voltage Output voltage Analog input voltage P10-P17 Output current, high Total P01-P05, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 Peak value R.m.s. value Output current, IOLNote Total P01-P05, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 Peak value R.m.s. value +150 Analog input P00-P05, P07, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 (PROM programming mode) Test Conditions Rating -0.3 +7.0 -0.3 +13.5 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +13.5 -0.3 +0.3 AVSS -0.3 AVREF +0.3 Unit
Operating ambient temperature
Tstg
Storage temperature
Note
r.m.s. value should calculated follows: [R.m.s. value] [Peak value] Duty product quality damaged even value only above parameters exceeds absolute maximum rating value exceeds absolute maximum rating instant. That absolute maximum rating rating value which cause product damaged physically. absolute maximum rating values must therefore observed using product.
Caution
Remark Unless specified otherwise, characteristics dual-function pins same those port pins. CAPACITANCE (TA=
Parameter Input capacitance Output capacitance capacitance Symbol COUT unmeasured pins returned Test Conditions MIN. TYP. MAX. Unit
µPD78P064B
MAIN SYSTEM CLOCK OSCILLATION CIRCUIT CHARACTERISTICS
Recommended circuit
Resonator Ceramic resonator
Parameter Oscillator frequency (fX)Note Oscillation stabilization timeNote Oscillator frequency (fX)Note Oscillation stabilization timeNote input frequency (fX)Note input high/low level width (tXH tXL)
Test conditions Oscillator voltage range After reaches oscillator voltage range MIN.
MIN.
TYP.
MAX.
Unit
Crystal resonator
External clock
µPD74HCU04
Notes Indicates only oscillation circuit characteristics. Refer Characteristics" instruction execution time. Time required stabilize oscillation after reset STOP mode release. Cautions When using main system clock oscillator, wiring area enclosed with broken line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground ground pattern which high current flows. fetch signal from oscillator. main system clock oscillation circuit operated subsystem clock when main system clock stopped, reswitching main system clock should performed after stable oscillation time been obtained program.
µPD78P064B
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS +85°C,
Resonator
Recommended Circuit
Parameter Oscillator frequency (fXT)Note
Test Conditions
MIN.
TYP.
MAX.
Unit
Crystal resonator
32.768
Oscillation stabilization timeNote
External clock
input frequency (fXT)Note
input high-/low-level width (tXTH/tXTL)
Notes Indicates only oscillation circuit characteristics. Refer Characteristics" instruction execution time. Time required stabilize oscillation after reached minimum oscillation voltage range. Cautions When using subsystem clock oscillator, wiring area enclosed with broken line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground ground pattern which high current flows. fetch signal from oscillator. subsystem clock oscillation circuit designed amplification circuit provide consumption current, causing misoperation noise more frequently than main system clock oscillation circuit. Special care should therefore taken wiring method when subsystem clock used.
µPD78P064B
RECOMMENDED OSCILLATION CIRCUIT CONSTANT MAIN SYSTEM CLOCK: CERAMIC RESONATOR
Recommended Circuit Constant (pF) Murata Mfg. Co., Ltd. CSA5.00MG CST5.00MGW EF0GC5004A4 Matsushita Electronics Components Co., Ltd. EF0EC5004A4 EF0EN5004A4 EF0S5004B4 KBR-5.0MSA Kyocera Corporation PBRC5.00A KBR-5.0MKS KBR-5.0MWS 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 Built-in Built-in Built-in Built-in Built-in Built-in (pF) Built-in Built-in Built-in Built-in Built-in Built-in Oscillator Voltage Range MIN. MAX. Lead type Round lead type Lead type Chip type Lead type Chip type Lead type Chip type
Manufaturer
Product Name
Frequency (MHZ)
Remarks
Caution
oscillation circuit constants oscillation voltage range indicate conditions stable oscillation guarantee accuracy oscillation frequency. application circuit requires accuracy oscillation frequency, necessary oscillation frequency application circuit. this, necessary directly contact manufacturer resonator being used.
µPD78P064B
CHARACTERISTICS +85°C,
Parameter Symbol Test Conditions P10-P17, P30-P32, VIH1 P35-P37, P80-P87, P90-P97, P100-P103 P00-P05, P25-P27, VIH2 Input voltage, high P33, P34, P70-P72, P110-P117, RESET VIH3 VDD-0.2 VIH4 XT1/P07, P10-P17, P30-P32, VIL1 P35-P37, P80-P87, P90-P97, P100-P103 P00-P05, P25-P27, VIL2 Input voltage, VIL3 P33, P34, P70-P72, P110-P117, RESET VIL4 XT1/P07, VNote Output voltage, high -100 P100-P103 VOL1 Output voltage, P01-P05, P25-P27, P70-P72, P90-P97, P10-P17, P30-P37, P80-P87, P110-P117 VDD-0.5 VDD-1.0 VNote 0.15 0.85 VDD-0.5 MIN. TYP. MAX. Unit
open-drain, pulled
VOL2 VOL3
SB0, SB1, SCK0
Note
When used P07, inverse phase should input using inverter. Unless specified otherwise, characteristics dual-function pins same those port pins.
Remark
µPD78P064B
CHARACTERISTICS
Parameter Symbol Test Conditions P00-P05, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 XT1/P07, P00-P05, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 XT1/P07, VOUT VOUT P01-P05, P10-P17, Software pull-up resistor P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 5.00 MHz, Crystal oscillation (fXX MHz)Note operating mode %Note %Note %Note %Note %Note 0.05 0.05 MIN. TYP. MAX. Unit
Input leakage current, high
ILIH1 ILIH2 ILIL1 ILIH2
Input leakage current,
15.0 27.0 1500 1950 12.5
Output leakage current, high Output leakage current,
ILOH ILOL
IDD1
IDD2
Supply currentNote
IDD3
IDD4
IDD5
IDD6
5.00 MHz, Crystal oscillation (fXX MHz)Note operating mode 5.00 MHz, Crystal oscillation (fXX MHz)Note HALT mode 5.00 MHz, Crystal oscillation (fXX MHz)Note HALT mode 32.768 kHz, Crystal oscillation operating modeNote 32.768 kHz, Crystal oscillation Note HALT mode STOP mode When feedback resistor connected STOP mode When feedback resistor disconnected
Notes Current flowing AVDD pin. including converter, on-chip pull-up resistors dividing resistors. Main system clock fX/2 operation (when oscillation mode selection register (OSMS) 00H) Main system clock operation (when OSMS 01H) When main system clock stopped. High-speed mode operation (when processor clock control register (PCC) 00H) Low-speed mode operation (when 04H) Remark Unless specified otherwise, characteristics dual-function pins same those port pins.
µPD78P064B
CHARACTERISTICS Static Display Mode (VDD
Parameter drive voltage dividing resistor output voltage deviationNote (common) output voltage deviationNote (segment) Symbol VLCD RLCD VODC VODS VLCD VLCD0 VLCD Test Conditions MIN. TYP. MAX. ±0.2 ±0.2 Unit
Note
voltage deviation difference from voltage corresponding ideal value segment common outputs (VLCDn;
Bias Method (VDD
Parameter drive voltage dividing resistor output voltage deviationNote (common) output voltage deviationNote (segment) Symbol VLCD RLCD VODC VODS VLCD VLCD0 VLCD VLCD1 VLCD VLCD2 VLCD Test Conditions MIN. TYP. MAX. ±0.2 ±0.2 Unit
Note
voltage deviation difference from voltage corresponding ideal value segment common outputs (VLCDn;
Bias Method (VDD
Parameter drive voltage dividing resistor output voltage deviationNote (common) output voltage deviationNote(segment) Symbol VLCD RLCD VODC VODS VLCD VLCD0 VLCD VLCD1 VLCD VLCD2 VLCD1 Test Conditions MIN. TYP. MAX. ±0.2 ±0.2 Unit
Note
voltage deviation difference from voltage corresponding ideal value segment common outputs (VLCDn;
µPD78P064B
CHARACTERISTICS Basic Operation
Parameter Cycle time (Min. instruction execution time) Symbol Test Conditions Operating main system clock (fXX MHz)Note Operating main system clock (fXX MHz)Note Operating subsystem clock TI00 input high/ low-level width tTIH00, tTIL00 TI01 input high/ low-level width input frequency TI1, input high/low-level width Interrupt input high/low-level width RESET level width tRST tTIH01, tTIL01 MIN. 40Note 2/fsam+0.1Note 2/fsam+0.2Note 2/fsam+0.5 tTIH, tTIL tINTH, tINTL INTP0 INTP1-INTP5, P110-P117 8/fsamNote
Note
TYP.
MAX.
Unit
Notes Main system clock fX/2 operation (when oscillation mode selection register (OSMS) 00H) Main system clock operation (when OSMS 01H) This value when external clock used. value (min.) when crystal resonator used. combination with bits (SCS0) (SCS1) sampling clock select register (SCS), selection fsam possible between fXX/2N+1, fXX/32, fXX/64 fXX/128 (when
µPD78P064B
main system clock fX/2 operation)
main system clock operation)
Cycle Time
Guaranteed Operation Range
Cycle Time
Guaranteed Operation Range
Supply Voltage
Supply Voltage
Serial Interface Serial interface channel 3-wire serial mode (SCK0. Internal clock output)
Symbol Test Conditions MIN. 1600 3200 tKCY1/2-50 tKCY1/2-100 pFNote TYP. MAX. Unit
Parameter
SCK0 cycle time
tKCY1 tKH1, tKL1 tSIK1
SCK0 high/low-level width
setup time SCK0) hold time (from SCK0) output delay time from SCK0
tKSI1 tKSO1
Note load capacitance SCK0, output line.
µPD78P064B
(ii) 3-wire serial mode (SCK0.External clock input)
Parameter Symbol Test Conditions MIN. 1600 3200 1600 pFNote TYP. MAX. Unit
SCK0 cycle time
tKCY2
SCK0 high/low-level width
tKH2, tKL2 tSIK2 tKSI2 tKSO2 tR2,
setup time SCK0) hold time (from SCK0) output delay time from SCK0 SCK0 rise, fall time
1000
Note load capacitance output line. (iii) mode (SCK0.Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 3200 SCK0 high/low-level width SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SB0, from SCK0 SCK0 from SB0, SB0, high-level width SB0, low-level width tKH3, tKL3 tSIK3 tKCY3/2-50 tKCY3/2-150 tKSI3 tKCY3/2 Test Conditions MIN. TYP. MAX. Unit
tKSO3 tKSB tSBK tSBH pFNote
tKCY3 tKCY3 tKCY3
1000
tSBL
tKCY3
Note load resistance load capacitance SCK0, output line.
µPD78P064B
(iv) mode (SCK0.External clock input)
Parameter SCK0 cycle time Symbol tKCY4 3200 SCK0 high/low-level width SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SB0, from SCK0 SCK0 from SB0, SB0, high-level width SB0, low-level width SCK0 rise, fall time tKH4, tKL4 tSIK4 1600 tKSI4 tKCY4/2 Test Conditions MIN. TYP. MAX. Unit
tKSO4 tKSB tSBK tSBH pFNote
tKCY4 tKCY4 tKCY4
1000
tSBL tR4,
tKCY4 1000
Note load resistance load capacitance output line. 2-wire serial mode (SCK0. Internal clock output)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 Symbol tKCY5 tKH5 tKL5 pFNote Test Conditions MIN. 1600 3200 tKCY5/2-160 tKCY5/2-190 tKCY5/2-50 tKCY5/2-100 TYP. MAX. Unit
tSIK5
tKSI5 tKSO5
Note load resistance load capacitance SCK0, output line.
µPD78P064B
(vi) 2-wire serial mode (SCK0. External clock input)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SCK0 rise, fall time Symbol tKCY6 tKH6 tKL6 tSIK6 tKSI6 tKSO6 tR6, pFNote Test Conditions MIN. 1600 3200 1300 1600 tKCY6/2 1000 TYP. MAX. Unit
Note load resistance load capacitance output line. Serial interface channel 3-wire serial mode (SCK2. Internal clock output)
Symbol Test Conditions MIN. 1600 3200 tKCY7/2-50 tKCY7/2-100 pFNote TYP. MAX. Unit
Parameter
SCK2 cycle time
tKCY7 tKH7, tKL7 tSIK7
SCK2 high/low-level width
setup time SCK2) hold time (from SCK2) output delay time from SCK2
tKSI7 tKSO1
Note load capacitance SCK2, output line.
µPD78P064B
(ii) 3-wire serial mode (SCK2.External clock input)
Parameter Symbol Test Conditions MIN. 1600 3200 1600 pFNote TYP. MAX. Unit
SCK2 cycle time
tKCY8
SCK2 high/low-level width
tKH8, tKL8 tSIK8 tKSI8 tKSO8 tR8,
setup time SCK2) hold time (from SCK2) output delay time from SCK2 SCK2 rise, fall time
1000
Note load capacitance output line. (iii) UART mode (Dedicated baud rate generator output)
Parameter Symbol Test Conditions MIN. TYP. MAX. 78125 39063 19531 Unit
Transfer rate
(iv) UART mode (External clock input)
Parameter Symbol Test Conditions MIN. 1600 3200 1600 39063 19531 9766 1000 TYP. MAX. Unit
ASCK cycle time
tKCY9
ASCK high/low-level width
tKH9, tKL9
Transfer rate
ASCK rise, fall time
tR9,
µPD78P064B
Timing Test Point (Excluding Input)
Test Points
Clock Timing
1/fX
VIH3 (MIN.) VIL3 (MAX.)
Input
1/fXT
tXTL
tXTH VIH4 (MIN.) VIL4 (MAX.)
Input
Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI
tTIL
tTIH
TI1,
µPD78P064B
Serial Transfer Timing 3-wire serial mode:
tKCYm
tKLm SCK0, SCK2 tSIKm tKSIm
tKHm
SI0, tKSOm
Input Data
SO0,
Output Data
mode (bus release signal transfer):
tKCY3, tKL3, SCK0 tKSB tSBL tSBH tSBK tSIK3, tKSI3, tKH3,
SB0, tKSO3,
mode (command signal transfer):
tKCY3, tKL3, SCK0 tKSB tSBK tSIK3, tKSI3.4 tKH3,
SB0, tKSO3,
µPD78P064B
2-wire serial mode:
tKCY5.6 tKL5, SCK0 tSIK5, tKSO5, SB0, tKSI5, tKH5,
UART mode:
tKCY9 tKL9 ASCK tKH9
Converter AVDD AVSS
Parameter Resolution Overall error
Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
AVREF AVDD tCONV tSAMP VIAN AVREF RAIREF 19.1 12/fXX AVSS
Conversion time Sampling time Analog input voltage Reference voltage AVREF-AVSS resistance
AVREF AVDD
Note Quantization error (±1/2 LSB) included. This expressed proportion full-scale value.
µPD78P064B
DATA MEMORY STOP MODE SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
Parameter Data retention supply voltage Data retention power supply current Release signal time Oscillation stabilization wait time tWAIT Release interrupt Note Symbol VDDDR VDDDR Subsystem clock stop feed-back resistor disconnected Release RESET 217/fX Test Conditions MIN. TYP. MAX. Unit
IDDDR
tSREL
Note
combination with bits (OSTS0 OSTS2) oscillation stabilization time select register (OSTS), selection 212/fXX 214/fXX 217/fXX possible.
Data Retention Timing (STOP Mode Release RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retention Mode
STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release Interrupt Signal)
HALT Mode STOP Mode Operating Mode
Data Retention Mode
STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
µPD78P064B
Interrupt Input Timing
tINTL
tINTH
INTP0-INTP5
RESET Input Timing
tRSL
RESET
µPD78P064B
PROM PROGRAMMING CHARACTERISTICS Characteristics PROM Write Mode 0.25 12.5
Parameter Input voltage, high Input voltage, Output voltage, high Output voltage, Input leakage current supply voltage supply voltage supply current supply current Symbol SymbolNote 12.2 6.25 12.5 Test Conditions MIN. -1.0 12.8 6.75 TYP. MAX. Unit
Note
Symbol corresponding µPD27C1001A.
PROM Read Mode
Parameter Input voltage, high Input voltage, Output voltage, high Output voltage, Input leakage current Output leakage current supply voltage supply voltage supply current supply current Symbol VOH1 VOH2 SymbolNote VOH1 VOH2 ICCA1 VIL, -100 VOUT VDD, -0.6 Test Conditions MIN. -1.0 -0.5 +0.6 TYP. MAX. Unit
Note
Symbol corresponding µPD27C1001A.
µPD78P064B
Characteristics PROM Write Mode Page program mode 0.25 12.5
Parameter Address setup time setup time setup time Input data setup time Symbol tOES tCES Address hold time (from tAHL tAHV Input data hold time (from Data output float delay time from setup time setup time Program pulse width Valid data delay time from pulse width during data latching setup time hold time hold time tVPS tVDS tPGMS tCEH tOEH SymbolNote tOES tCES tAHL tAHV tVPS tVCS tPGMS tCEH tOEH Test Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Note
Corresponding µPD27C1001A symbol Byte program mode 0.25 12.5
Parameter Symbol tOES tCES tVPS tVDS tOEH SymbolNote tOES tCES tVPS tVCS Test Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Address setup time PGM) setup time setup time PGM) Input data setup time PGM) Address hold time (from nput data hold time (from PGM) Data output float delay time from setup time PGM) setup time PGM) Program pulse width Valid data delay time from hold time
Note
Corresponding µPD27C1001A symbol
µPD78P064B
PROM Read Mode
Parameter Data output time from address Data output delay time from Data output delay time from Data output float delay time from Data hold time from address Symbol tACC SymbolNote tACC Test Conditions MIN. TYP. MAX. Unit
Note
Corresponding µPD27C1001A symbol
PROM Programming Mode Setting
Parameter PROM programming mode setup time Symbol tSMA Test Conditions MIN. TYP. MAX. Unit
PROM Write Mode Timing (Page program mode)
Page Data Latch Page Program Program Verify
A2-A16 D0-D7 Hi-Z Hi-Z tPGMS tVPS tVDS tCES tDES tCEH tDEH Data Input Data Output Hi-Z tALH tAHV
µPD78P064B
PROM Write Mode Timing (Byte program mode)
Program Program/Verify
A0-A16 D0-D7 Hi-Z Data Input Hi-Z Data Output Hi-Z
Cautions must applied before after VPP. must exceed +13.5 including overshoot. Removing reinserting adversely affect reliability while +12.5 applied VPP. PROM Read Mode Timing
A0-A16
Effective Address
Note Note
Data Output
Note
D0-D7
Hi-Z
Hi-Z
Notes When reading within tACC range, input delay time from fall time must maximum tACC tOE. time from point which either (whichever first) reaches VIH.
µPD78P064B
PROM Programming Mode Setting Timing
RESET
A0-A16
Effective Address
µPD78P064B
PACKAGE DRAWINGS
PLASTIC (FINE PITCH)
detail lead
NOTE
ITEM MILLIMETERS 16.0±0.2 14.0±0.2 14.0±0.2 16.0±0.2 0.22 +0.05 -0.04 0.10 (T.P.) 1.0±0.2 0.5±0.2 0.17 +0.03 -0.07 0.10 1.45 0.125±0.075 5°±5° MAX. INCHES 0.630±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.630±0.008 0.039 0.039 0.009±0.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.004 0.057 0.005±0.003 5°±5° 0.067 MAX. P100GC-50-7EA-2
Each lead centerline located within 0.10 (0.004 inch) true position (T.P.) maximum material condition.
Remark
Dimensions materials products same those mass production product.
µPD78P064B
PLASTIC LQFP (FINE PITCH)
detail lead
NOTE Each lead centerline located within 0.08 (0.003 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 16.00±0.20 14.00±0.20 14.00±0.20 16.00±0.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.00±0.20 0.50±0.20 0.17 +0.03 -0.07 0.08 1.40±0.05 0.10±0.05 1.60 MAX. INCHES 0.630±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.630±0.008 0.039 0.039 0.009±0.002 0.003 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.003 0.055±0.002 0.004±0.002 0.063 MAX. S100GC-50-8EU
Remark
Dimensions materials products same those mass production product.
µPD78P064B
PLASTIC
detail lead
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition. ITEM
P100GF-65-3BA1-2 MILLIMETERS 23.6 20.0 14.0 17.6 0.30 0.10 0.15 0.65 (T.P.) 0.15+0.10 -0.05 0.10 MAX. INCHES 0.929 0.016 0.795+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.031 0.024 0.012+0.004 -0.005 0.006 0.026 (T.P.) 0.071+0.008 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
Remark
Dimensions materials products same those mass production product.
5°±5°
µPD78P064B
RECOMMENDED SOLDERING CONDITIONS
µPD78P064B should soldered mounted under conditions recommended table below. detail recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact sales personnel. Table 8-1. Surface Mounting Type Soldering Conditions µPD78P064BGC-7EA: 100-pin plastic (fine pitch)
µPD78P064BGC-8EU: 100-pin plastic LQFP (fine pitch)
Recommended Soldering Symbols IR35-107-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: Duration: sec. max. above), Number times: Twice max., Time limit: daysNote (thereafter hours prebaking required <Precaution> Products cannot baked while packed anything other than heat resistant tray (i.e. they cannot baked magazine, taping, heat-labile tray). Package peak temperature: Duration: sec. max. above), Number times: Twice max., Time limit: daysNote (thereafter hours prebaking required <Precaution> Products cannot baked while packed anything other than heat resistant tray (i.e. they cannot baked magazine, taping, heat-labile tray). temperature: max., Duration: sec. max. (per device side)
VP15-107-2
Partial heating
Note
storage period after dry-pack decapsulation, storage conditions max.
µPD78P064BGF-3BA: 100-pin plastic
Recommended Soldering Symbols IR35-00-3 VP15-00-3 WS60-00-1
Soldering Method Infrared reflow Wave soldering Partial heating
Soldering Conditions Package peak temperature: Duration: sec. max. above), Number times: Three times max. Package peak temperature: Duration: sec. above), Number times: Three times max. Solder bath temperature: max., Duration: sec. max., Number times: Once, Preheating temperature: max. (Package surface temperature) temperature: max., Duration: sec. max. (per device side)
Caution
more than soldering method should avoided (except case partial heating).
µPD78P064B
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD78P064B. Language Processing Software
RA78K/0Note CC78K/0
Note
78K/0 series common assembler package 78K/0 series common compiler package
DF78064Note CC78K/0-LNote
µPD78064 subseries common device file
78K/0 series common compiler library source file
PROM Writing Tools
PG-1500 PA-78P064GC PA-78P064GF PA-PG-1500 controllerNote PG-1500 control program PROM programmer Programmer adapters connected PG-1500
Debugging Tools
IE-78000-R IE-78000-R-A IE-78000-R-BK IE-780308-R-EM EP-78064GC-R EP-78064GF-R TGC-100SDW Adapter mounted target system board made 100-pin plastic (GC-7EA, GC-8EU type) product Tokyo Eletech Corp. (Tokyo 03-5295-1661). When purchasing this product, consult your distributor. Socket mounted target system board made 100-pin plastic (GF-3BA type) 78K/0 series common system simulators IE-78000-R-A integrated debuggers IE-78000-R screen debuggers 78K/0 series common in-circuit emulators 78K/0 series common in-circuit emulators (for integrated debugger) 78K/0 series common break board
µPD780308 subseries common evaluation emulation boards µPD78064 subseries common emulation probes
EV-9200GF-100 SM78K0Note ID78K0Note SD78K/0Note DF78064Note
µPD78064 subseries common device file
Real-Time
RX78K/0Note MX78K/0Note 78K/0 series real-time 78K/0 series
µPD78P064B
Fuzzy Inference Development Support System
FE9000Note FE9200Note FT9080Note FT9085Note FI78K/IINote FD78K/IINote Fuzzy knowledge data creation tool Translator Fuzzy inference module Fussy inference debugger
Notes PC-9800 series (MS-DOSTM) based PC/ATand compatible machines DOSTM/IBM DOSTM/MS-DOS) based HP9000 series 300(HP-UXTM) based HP9000 series 700(HP-UX) based, SPARCstation(SunOSTM) based, EWS4800 series (EWS-UX/V) based PC-9800 series (MS-DOS WindowsTM) based PC/AT compatible machines DOS/IBM DOS/MS-DOS Windows) based NEWS(NEWS-OSTM) based Remarks third party development tools, refer 78K/0 Series Selection Guide (U11126E). RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, RX78K/0 used combination with DF78064.
µPD78P064B
CONVERSION SOCKET (EV-9200GF-100) PACKAGE DRAWINGS RECOMMENDED BOARD MOUNTING PATTERN Figure A-1. EV-9200GF-100 Package Drawing
EV-9200GF-100
No.1 index
EV-9200GF-100-G0 ITEM MILLIMETERS 24.6 18.6 12.0 22.6 25.3 16.6 19.3 0.35 INCHES 0.969 0.827 0.591 0.732 0.079 0.031 0.472 0.89 0.996 0.236 0.654 0.323 0.315 0.098 0.079 0.014
0.091 0.059
µPD78P064B
Figure A-2. EV-9200GF-100 Board Mounting Pattern
EV-9200GF-100-P0 ITEM Caution MILLIMETERS 26.3 21.6 0.65±0.02 29=18.85±0.05 INCHES 1.035 0.85 0.026+0.001 -0.002 1.142=0.742+0.002 -0.002 0.65±0.02 19=12.35±0.05 0.026+0.001 0.748=0.486+0.003 -0.002 -0.002 15.6 20.3 0.05 0.05 0.35 0.02 0.614 0.799 0.472+0.003 -0.002 0.236+0.003 -0.002 0.014+0.001 -0.001
2.36 0.03 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions mount EV-9200 that target device (QFP) different some parts. recommended mount dimensions QFP, refer "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
µPD78P064B
CONVERSION ADAPTER (TGC-100SDW) PACKAGE DRAWINGS Figure A-3. TGC-100SDW Package Drawing
Reference diagram: TGC-100SDW Package dimension (unit:
Protrusion height
ITEM MILLIMETERS 21.55 0.5x24=12 0.5x24=12 15.0 21.55 INCHES 0.848 0.020x0.945=0.472 0.020 0.020x0.945=0.472 0.591 0.848 ITEM MILLIMETERS 14.45 1.85±0.25 0.25 INCHES 0.569 0.073±0.010 0.138 0.079 0.154 0.010
3.55
10.9 13.3 15.7 18.1 13.75 0.5x24=12.0 1.125±0.3 1.125±0.2 10.0 11.3 18.1
0.140
0.429 0.524 0.618 0.713 0.541 0.020x0.945=0.472 0.044±0.012 0.044±0.008 0.295 0.394 0.445 0.713
16.0 1.125±0.3 0~5°
0.177
0.630 0.044±0.012 0.000~0.197° 0.232 0.031 0.094 0.106 TGC-100SDW-G0E
0.197
0.197 0.051 0.071 0.079
0.035 0.012
Remark Manufactured Tokyo Eletech Corp.
µPD78P064B
APPENDIX RELATED DOCUMENTS
Device Related Documents
Document Name Document Japanese English U10785E U11590E This document U12326E
µPD78064B Subseries User's Manual µPD78064B Data Sheet µPD78P064B Data Sheet
78K/0 Series User's Manual (Instruction) 78K/0 Series Instruction List 78K/0 Series Instruction
U10785J U11590J U11598J U12326J U10903J U10904J Planned
µPD78064B Subseries Special Function Register Table
Development Tool Related Documents (User's Manual) (1/2)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package Operation Assembly language Structured assembly language CC78K Series Compiler Operation Language CC78K0 Compiler Operation Language CC78K/0 Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) Based PG-1500 Controller Series DOS) Based IE-78000-R IE-78000-R-A IE-78000-R-BK IE-780308-R-EM EP-78064 Programming know-how Document Japanese EEU-809 EEU-815 EEU-817 U11802J U11801J U11789J EEU-656 EEU-655 U11517J U11518J EEA-618 U12322J U11940J EEU-704 EEU-5008 U11376J U10057J EEU-867 U11362J EEU-934 English EEU-1399 EEU-1404 EEU-1402 U11802E U11801E U11789E EEU-1280 EEU-1284 U11517E U11518E EEA-1208 U11940E EEU-1291 U10540E U11376E U10057E EEU-1427 U11362E EEU-1469
µPD78P064B
Development Tool Related Documents (User's Manual) (2/2)
Document Name SM78K0 System Sumilator Windows Based SM78K Series System Simulator Reference External components user open interface specification Reference Reference Guide Introduction Reference Introduction Reference Document Japanese EEU-5002 U10092J English U10181E U10092E
ID78K0 Integrated Debugger Based ID78K0 Integrated Debugger Based ID78K0 Integrated Debugger Windows Based SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based SD78K/0 Screen Debugger PC/AT DOS) Based
U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J
U11539E U11649E U10539E EEU-1414 U11279E
Caution above related documents subject change without notice. design purpose, etc., sure latest documents. Embedded Software Related Documents (User's Manual)
Document Name 78K/0 Series Real-Time Basic Installation 78K/0 Series MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger Basic Document Japanese U11537J U11536J U12257J EEU-829 EEU-862 English EEU-1438 EEU-1444
EEU-858
EEU-1441
EEU-921
EEU-1458
Other Related Documents
Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability Quality Control Electrostatic Discharge (ESD) Test Semiconductor Devices Quality Guarantee Guide Microcomputer-Related Product Guide (Products Other Manufacturers) C10535J C11531J C10983J MEM-539 C11893J U11416J Document Japanese C10943X C10535E C11531E C10983E MEI-1202 English
Caution above related documents subject change without notice. design purpose, etc., sure latest documents.
µPD78P064B
[MEMO]
µPD78P064B
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78P064B
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290
Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics Taiwan Ltd. Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96.
µPD78P064B
FIP, QTOP IEBus trademarks Corporation. MS-DOS Windows trademarks Microsoft Corporation. DOS, PC/AT trademarks Corporation. HP9000 series 300, HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. trademark Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation. documents referred this publication include preliminary versions. versions marked such.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
However preliminary
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

µPD78P064B 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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