MC-242454 (MULTI-CHIP PACKAGE) FLASH MEMORY MOBILE SPECIFIED 32M-

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MC-242454 (MULTI-CHIP PACKAGE) FLASH MEMORY MOBILE SPECIFIED 32M-

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INTEGRATED CIRCUIT
MC-242454
(MULTI-CHIP PACKAGE) FLASH MEMORY MOBILE SPECIFIED 32M-BIT FLASH MEMORY 16M-BIT CMOS MOBILE SPECIFIED
Description
MC-242454 stacked type (Multi-Chip Package) 33,554,432 bits (BYTE mode 4,194,304 words bits, WORD mode 2,097,152 words bits) flash memory 16,777,216 bits (1,048,576 words bits) Mobile specified RAM. MC-242454 packaged 77-pin TAPE FBGA 71-pin TAPE FBGA.
Features
General Features Fast access time tACC (MAX.), (MAX.) (VCCf (Flash Memory) (MAX.) (Mobile specified RAM) Supply voltage VCCf VCCm Wide operating temperature
Flash Memory Features bank organization enabling simultaneous execution erase program read Bank organization banks (16M bits bits) Memory organization 4,194,304 words bits (BYTE mode) 2,097,152 words bits (WORD mode) Sector organization sectors bytes words sectors, bytes words sectors) Boot sector allocated lowest address (sector) 3-state output Automatic program Program suspend resume Unlock bypass program Automatic erase Chip erase Sector erase (sectors combined freely) Erase suspend resume Program Erase completion detection Detection through data polling toggle bits Detection through (/BY)
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Document M15372EJ5V0DS00 (5th edition) Date Published July 2001 Printed Japan
mark shows major revised points.
2001
MC-242454
Sector group protection sector protected protected sector temporary unprotected Sectors used boot application Hardware reset standby using /RESET Automatic sleep mode Boot block sector protect (ACC) Conforms common flash memory interface (CFI) Extra Time Protect Sector provided
Mobile specified Features Memory organization 1,048,576 words bits Supply current operating (MAX.) Standby Mode (MAX.) Standby Mode (MAX.) Chip Enable inputs /CEm Byte data control /LB, Standby Mode input MODE Standby Mode Normal standby (Memory cell data hold valid) Standby Mode Memory cell data hold invalid
Ordering Information
Part number Flash Memory Boot sector Flash Memory Access time (MAX.) MC-242454F9-B90-BT3 MC-242454F9-B95-BT3Note MC-242454F9-B10-BT3 MC-242454F9-B90-BS1 MC-242454F9-B95-BS1 MC-242454F9-B10-BS1
Note Note Note
Mobile specified Access time (MAX.)
Package
Lowest address (sector) type)
(VCCf
77-pin TAPE FBGA
71-pin TAPE FBGA
Note Under development
Data Sheet M15372EJ5V0DS
MC-242454
Configurations
/xxx indicates active signal. 77-pin TAPE FBGA
View
MODE CIOf I/O14 I/O5 I/O11 I/O2 I/O8
I/O15, I/O7 I/O6 I/O13 I/O4 I/O3 I/O12 VCCm VCCf I/O10 I/O0 /CEm
/WP(ACC) /RESET RY(/BY) I/O1
I/O9 /CEf
71-pin TAPE FBGA
View
MODE CIOf I/O14 I/O5 I/O11 I/O2 I/O8
I/O15, I/O7 I/O6 I/O13 I/O4 I/O3 I/O12 VCCm VCCf I/O10 I/O0 /CEm
/WP(ACC)/RESET RY(/BY) I/O1
I/O9 /CEf
Common Pins Address inputs I/O0 I/O15 Data inputs outputs Output Enable Write Enable Ground Note Connection Note Internal Connection
Flash Memory Pins Address inputs I/O15, Data inputs outputs (WORD mode) address input (BYTE mode) /CEf Chip Enable (/BY) Ready (Busy) output /RESET Hardware reset input Supply Voltage VCCf /WP(ACC) Hardware Write Protect (Acceleration) CIOf Selects 8-bit 16-bit mode Mobile specified Pins /CEm Chip Enable MODE Standby mode select VCCm Supply Voltage /LB, Byte data select
Note Some signals applied because this internally connected. Leave this connected unconnected (Recommended connected VSS). Remark Refer Package Drawings index mark.
Data Sheet M15372EJ5V0DS
MC-242454
Block Diagram
VCCf /RESET /CEf CIOf /WP(ACC) M-bit Flash Memory 4,194,304 words bits 2,097,152 words bits (/BY)
VCCm
I/O0 I/O15,
/CEm MODE
M-bit Mobile Specified (1,048,576 words bits)
Data Sheet M15372EJ5V0DS
MC-242454
Operations Table
Operation Flash Memory Mobile specified MODE Note Hi-Z Data Data Note Data Data Note Hi-Z Data In/Out Note Write (Mobile specified RAM) Note Hi-Z Hi-Z Data Hi-Z Data In/Out Hi-Z Data Hi-Z Hi-Z Data Hi-Z Data Hi-Z Data In/Out Hi-Z Data In/Out Hi-Z Data Hi-Z Data Data Hi-Z Data Common I/O0 I/O7 Hi-Z I/O8-I/O15 Hi-Z
/RESET /CEf CIOf /WP(ACC) /CEm Full standby Standby Mode Standby Mode Output disable Read (Flash Memory
Note
BYTE mode
WORD mode BYTE mode WORD mode
Write (Flash Memory)
Temporary sector group unprotect Boot block sector protect Flash Memory hardware reset Read (Mobile specified RAM)
Caution Other operations except indicated this table inhibited.
Notes When VIL, applied /WE. When VIH, write operation started. Mobile specified should Standby. Flash Memory should Standby Hardware reset. Remarks VIH, VIL, Sector group protection read product using command. MODE must fixed during active operation. Refer DUAL OPERATION FLASH MEMORY BITS SERIES Information (M14914E) flash memory operations.
Data Sheet M15372EJ5V0DS
MC-242454
Sector Organization Sector Address Table (Flash Memory) Flash Memory bottom boot
Bank Sector Organization bytes words
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Bank 64/32 64/32 64/32 64/32
(1/2)
Address BYTE mode
3FFFFFH 3F0000H 3EFFFFH 3E0000H 3DFFFFH 3D0000H 3CFFFFH 3C0000H 3BFFFFH 3B0000H 3AFFFFH 3A0000H 39FFFFH 390000H 38FFFFH 380000H 37FFFFH 370000H 36FFFFH 360000H 35FFFFH 350000H 34FFFFH 340000H 33FFFFH 330000H 32FFFFH 320000H 31FFFFH 310000H 30FFFFH 300000H 2FFFFFH 2F0000H 2EFFFFH 2E0000H 2DFFFFH 2D0000H 2CFFFFH 2C0000H 2BFFFFH 2B0000H 2AFFFFH 2A0000H 29FFFFH 290000H 28FFFFH 280000H 27FFFFH 270000H 26FFFFH 260000H 25FFFFH 250000H 24FFFFH 240000H 23FFFFH 230000H 22FFFFH 220000H 21FFFFH 210000H 20FFFFH 200000H 1FFFFFH 1F0000H 1EFFFFH 1E0000H 1DFFFFH 1D0000H 1CFFFFH 1C0000H
Sectors Address
FSA70 FSA69 FSA68 FSA67 FSA66 FSA65 FSA64 FSA63 FSA62 FSA61 FSA60 FSA59 FSA58 FSA57 FSA56 FSA55 FSA54 FSA53 FSA52 FSA51 FSA50 FSA49 FSA48 FSA47 FSA46 FSA45 FSA44 FSA43 FSA42 FSA41 FSA40 FSA39 FSA38 FSA37 FSA36 FSA35
WORD mode
1FFFFFH 1F8000H 1F7FFFH 1F0000H 1EFFFFH 1E8000H 1E7FFFH 1E0000H 1DFFFFH 1D8000H 1D7FFFH 1D0000H 1CFFFFH 1C8000H 1C7FFFH 1C0000H 1BFFFFH 1B8000H 1B7FFFH 1B0000H 1AFFFFH 1A8000H 1A7FFFH 1A0000H 19FFFFH 198000H 197FFFH 190000H 18FFFFH 188000H 187FFFH 180000H 17FFFFH 178000H 177FFFH 170000H 16FFFFH 168000H 167FFFH 160000H 15FFFFH 158000H 157FFFH 150000H 14FFFFH 148000H 147FFFH 140000H 13FFFFH 138000H 137FFFH 130000H 12FFFFH 128000H 127FFFH 120000H 11FFFFH 118000H 117FFFH 110000H 10FFFFH 108000H 107FFFH 100000H 0FFFFFH 0F8000H 0F7FFFH 0F0000H 0EFFFFH 0E8000H 0E7FFFH 0E0000H
Sector Address Table Bank Address Table
Bank
Data Sheet M15372EJ5V0DS
MC-242454
(2/2)
Bank Sector Organization bytes words
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
Address BYTE mode
1BFFFFH 1B0000H 1AFFFFH 1A0000H 19FFFFH 190000H 18FFFFH 180000H 17FFFFH 170000H 16FFFFH 160000H 15FFFFH 150000H 14FFFFH 140000H 13FFFFH 130000H 12FFFFH 120000H 11FFFFH 110000H 10FFFFH 100000H 0FFFFFH 0F0000H 0EFFFFH 0E0000H 0DFFFFH 0D0000H 0CFFFFH 0C0000H 0BFFFFH 0B0000H 0AFFFFH 0A0000H 09FFFFH 090000H 08FFFFH 080000H 07FFFFH 070000H 06FFFFH 060000H 05FFFFH 050000H 04FFFFH 040000H 03FFFFH 030000H 02FFFFH 020000H 01FFFFH 010000H 00FFFFH 00E000H 00DFFFH 00C000H 00BFFFH 00A000H 009FFFH 008000H 007FFFH 006000H 005FFFH 004000H 003FFFH 002000H 001FFFH 000000H
Sectors Address
FSA34 FSA33 FSA32 FSA31 FSA30 FSA29 FSA28 FSA27 FSA26 FSA25 FSA24 FSA23 FSA22 FSA21 FSA20 FSA19 FSA18 FSA17 FSA16 FSA15 FSA14 FSA13 FSA12 FSA11 FSA10 FSA9 FSA8 FSA7 FSA6 FSA5 FSA4 FSA3 FSA2 FSA1 FSA0
WORD mode
0DFFFFH 0D8000H 0D7FFFH 0D0000H 0CFFFFH 0C8000H 0C7FFFH 0C0000H 0BFFFFH 0B8000H 0B7FFFH 0B0000H 0AFFFFH 0A8000H 0A7FFFH 0A0000H 09FFFFH 098000H 097FFFH 090000H 08FFFFH 088000H 087FFFH 080000H 07FFFFH 078000H 077FFFH 070000H 06FFFFH 068000H 067FFFH 060000H 05FFFFH 058000H 057FFFH 050000H 04FFFFH 048000H 047FFFH 040000H 03FFFFH 038000H 037FFFH 030000H 02FFFFH 028000H 027FFFH 020000H 01FFFFH 018000H 017FFFH 010000H 00FFFFH 008000H 007FFFH 007000H 006FFFH 006000H 005FFFH 005000H 004FFFH 004000H 003FFFH 003000H 002FFFH 002000H 001FFFH 001000H 000FFFH 000000H
Sector Address Table Bank Address Table
Bank
Data Sheet M15372EJ5V0DS
MC-242454
Sector Group Address Table (Flash Memory)
Sector group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 Sector) FSA70 Sectors) Sectors) Sectors) Sectors) Sectors) Sectors) Sectors) Sectors) Sectors) Sectors) Sectors) Sectors) Sectors) Sectors) Sectors) FSA11-FSA14 FSA15-FSA18 FSA19-FSA22 FSA23-FSA26 FSA27-FSA30 FSA31-FSA34 FSA35-FSA38 FSA39-FSA42 FSA43-FSA46 FSA47-FSA50 FSA51-FSA54 FSA55-FSA58 FSA59-FSA62 FSA63-FSA66 FSA67-FSA69 Size Sector) Sector) Sector) Sector) Sector) Sector) Sector) Sector) Sectors) Sector FSA0 FSA1 FSA2 FSA3 FSA4 FSA5 FSA6 FSA7 FSA8-FSA10
Remark
Data Sheet M15372EJ5V0DS
MC-242454
Command Sequence (Flash Memory)
Command sequence Cycle Data Cycle Address 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH
Note11
Cycle Address AAAH 555H Data
Cycle Address Data
Cycle Address Data
Cycle Address Data
Cycle Address Read Reset Read Reset
Note1 Note1
Data
BYTE mode WORD mode
AAAH 555H
Program
BYTE mode WORD mode
AAAH 555H
AAAH 555H
Program Suspend Program Resume Chip Erase
Note Note
BYTE mode WORD mode
AAAH 555H
AAAH 555H
AAAH 555H
555H 2AAH
AAAH 555H
Sector Erase
BYTE mode WORD mode
AAAH 555H
AAAH 555H
AAAH 555H
555H 2AAH
Sector Erase Suspend Sector Erase Resume Unlock Bypass
Note Note
AAAH 555H
AAAH 555H (BA) AAAH
BYTE mode WORD mode
Unlock Bypass Program Unlock Bypass Reset Product
Note
AAAH
Note
555H
BYTE mode
WORD mode
Note Note
555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H
2AAH
(BA) 555H
Sector Group Protection Sector Group Unprotect Query
Note
BYTE mode WORD mode
Extra Time Protect Sector Entry Extra Time Protect Sector Program
Note
BYTE mode WORD mode BYTE mode WORD mode BYTE mode WORD mode BYTE mode WORD mode
555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH
EOTPSA
AAAH 555H
AAAH 555H
Extra Time Protect Sector Erase
Note
AAAH 555H
AAAH 555H
555H 2AAH
EOTPSA
Extra Time Protect Sector Reset
Note
AAAH 555H
xxxH
Extra Time Protect Sector Protection
Note
EOTPSA
EOTPSA
Data Sheet M15372EJ5V0DS
MC-242454
Notes Both these read reset commands reset device read mode. Programming suspended input bank address being programmed program operation. Programming resumed input bank address being suspended program-suspend operation. Erasure suspended input bank address being erased sector erase operation. Erasure resumed input bank address being suspended sector-erase-suspend operation. Valid only unlock bypass mode. Valid only when /RESET (except Extra Time Protect Sector mode). command sequence that protects sector group excluded. Only valid address. Valid only Extra Time Protect Sector mode. This command used even this data F0H. Remarks Specify address 555H (A10 WORD mode, AAAH (A10 A-1) BYTE mode. Read address Read data Address input xx00H read manufacturer code) xx02H read device code BYTE mode) xx01H read device code WORD mode) Code output. Refer Product code (Manufacturer code Device code) (Flash Memory). Program address Program data FSA: Erase sector address. sector erased selected combination this address. Refer Sector Organization Sector Address Table (Flash Memory). Bank address. Refer Sector Organization Sector Address Table (Flash Memory). Sector group address protected. sector group address (SGA) (A6, (VIL, VIH, VIL). sector group address, refer Sector Group Address Table (Flash Memory). Unprotect sector group address. sector group address (SGA) (A6, (VIH, VIH, VIL). sector group address, refer Sector Group Address Table (Flash Memory). Data verifying whether sector groups read from address specified SPA, SUA, EOTPSA protected. EOTPSA Extra Time Protect Sector area addresses. BYTE mode 000000H 00FFFFH, WORD mode 000000H 007FFFH sector group address don't care except when program erase address read address selected. operation bus, refer Operations Table. address indicates VIL. Refer DUAL OPERATION FLASH MEMORY BITS SERIES Information (M14914E) flash memory commands.
Data Sheet M15372EJ5V0DS
MC-242454
Product Code (Manufacturer Code Device Code) (Flash Memory)
Product Code Manufacturer Code Device code Address inputs Output (BYTE mode), 225FH (WORD mode)
Product Code Manufacturer Code Device code BYTE mode WORD mode
Code outputs 225FH
Remark
VIH, VIL, Hi-Z
Hardware Sequence Flags, Hardware Data Protection (Flash Memory) Refer DUAL OPERATION FLASH MEMORY BITS SERIES Information (M14914E).
Data Sheet M15372EJ5V0DS
MC-242454
Initialization (Mobile specified RAM) MC-242454 initialized power-on sequence according following. stabilize internal circuits, before turning power, longer wait time must precede signal toggling. After wait time, read operation must performed least times. After that, normal operation.
Figure Initialization Timing Chart
VCCm (MIN.) VCCm
Address (Input)
MODE (Input)
(MIN.)
/CEm (Input) (MIN.)
Power
Wait Time
Read Operation times
Normal Operation
Cautions Following power application, make MODE /CEm high level during wait time interval. Following power application, make MODE high level during wait time eight read operations. read operation must satisfy specs described page (Read Cycle (Mobile specified RAM)). address don't care (VIH VIL) during read operation. Read operation must executed with toggled /CEm pin. prevent contention, recommended high level. However, input data pins level during read operation.
Data Sheet M15372EJ5V0DS
MC-242454
Standby Mode (Flash Memory) Standby Mode Standby Mode differ shown below. Table Standby Mode Characteristics
Standby Mode Mode Mode Memory Cell Data Hold Valid Invalid Standby Supply Current (µA) (ISB1) (ISB2)
Standby Mode State Machine (Flash Memory) From Active shift from this state Standby Mode change /CEm from VIH. shift from this state Standby Mode change /CEm from change MODE from VIL. From Standby Mode shift from this state Active, change /CEm from VIL. shift from this state Standby Mode change MODE from VIL. From Standby Mode When shifting from this state Active state Standby Mode necessary MODE perform Dummy Read operation times after waiting same power application. Refer Figure Standby Mode entry recovery Timing Chart (Mobile specified RAM). After shifting Active state, change /CEm VIL. After shifting Standby Mode change either MODE /CEm. Figure Standby Mode State Machine
Power /CEm VIH, MODE Wait
Dummy Read times)
Initial State
/CEm /CEm VIH, MODE
Active
MODE
/CEm VIH, MODE
/CEm VIH, MODE
/CEm VIL, MODE
/CEm VIH, MODE
Standby Mode Standby Mode
Data Sheet M15372EJ5V0DS
MC-242454
Electrical Specifications
Before turning power, input /RESET until VCCf VCCf (MIN.).
Absolute Maximum Ratings
Parameter Supply voltage Symbol VCCf VCCm Input Output voltage Condition with respect with respect with respect /WP(ACC), /RESET Ambient operation temperature Storage temperature Tstg except /WP(ACC), /RESET -0.5
Note
Rating -0.5 +4.0 -0.5 +4.0 -0.5 Note +13.0 VCCf, VCCm (4.0 MAX.) +125
Note
Unit
Notes -1.0 (MIN.) (pulse width VCCf, VCCm (MAX.) (pulse width
Caution Exposing device stress above those listed Absolute Maximum Rating could cause permanent damage. device meant operated under conditions outside limits described operational section this specification. Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Recommended Operating Conditions Common
Parameter Supply voltage Ambient operation temperature Symbol VCCf, VCCm Condition MIN. TYP. MAX. Unit
Flash Memory
Parameter High level input voltage level input voltage Symbol Condition MIN. -0.3 TYP. MAX. VCCf +0.5 Unit
Mobile specified
Parameter High level input voltage level input voltage Symbol Condition MIN. VCCm -0.3
Note
TYP.
MAX. VCCm VCCm
Unit
Note -0.5 (MIN.) (Pulse width:
Data Sheet M15372EJ5V0DS
MC-242454
Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Common
Parameter Input leakage current Output leakage current Symbol Test condition MIN. -1.0 -1.0 TYP. MAX. +1.0 +1.0 Unit
Flash Memory
Parameter High level output voltage level output voltage Power supply current WORD mode Read BYTE mode Symbol ICC1f Test condition -500 VCCf VCCf (MIN.) +1.0 VCCf VCCf (MIN.) VCCf VCCf (MAX.), /CEf VIL, tCYCLE tCYCLE tCYCLE tCYCLE Program, Erase Standby ICC2f ICC3f VCCf VCCf (MAX.), /CEf VIL, VCCf VCCf (MAX.), /CEf /RESET /WP(ACC) VCCf Standby Reset Automatic sleep mode Read during programming Read during erasing Programming during suspend Accelerated programming /RESET high level input voltage Accelerated programming voltage VCCf lock-out voltage
Note
MIN. VCCf-0.3
TYP.
MAX.
Unit
ICC4f ICC5f ICC6f ICC7f ICC8f
VCCf VCCf (MAX.), /RESET VCCf VCCf VCCf /CEf VIL, VIH, Automatic programming during suspend
IACC
(ACC) VCCf
11.5
12.5
VACC VLKO
High Voltage applied High Voltage applied
Note When VCCf equal lower than VLKO, device ignores write cycles. Refer DUAL OPERATION FLASH MEMORY BITS SERIES Information (M14914E).
Mobile specified
Parameter High level output voltage level output voltage Operating supply current Standby supply Standby Mode current Standby Mode Symbol ICCA ISB1 ISB2 -0.5 /CEm VIL, Minimum cycle time, II/O /CEm VCCm MODE VCCm /CEm VCCm MODE Test condition MIN. VCCm VCCm TYP. MAX. Unit
Data Sheet M15372EJ5V0DS
MC-242454
Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Test Conditions Flash Memory Input Waveform (Rise Fall Time
Test Points
Output Waveform
Test Points
Output Load
Data Sheet M15372EJ5V0DS
MC-242454
Mobile specified
Input Waveform (Rise Fall Time
VCCm VCCm VCCm/2 VCCm Test points VCCm/2
Output Waveform
VCCm/2
Test points
VCCm/2
Output Load characteristics directed with note should measured with output load shown Figure.
(tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ,
(Output)
VCCm/2
Data Sheet M15372EJ5V0DS
MC-242454
/CEf, /CEm Timing
Parameter /CEf, /CEm recover time Symbol tCCR Test Condition MIN. TYP. MAX. Unit Note
Read Cycle (Flash Memory)
Parameter Read cycle time VCCf Address access time VCCf /CEf access time VCCf access time Output disable time Output hold time /RESET pulse width /RESET hold time before read /RESET read mode /CEf CIOf low, high CIOf output disable time CIOf high access time VCCf tREADY tELFL/tELFH tFLQZ tFHQV /CEf /CEf tCEf tACC /CEf Symbol Test Condition MIN. TYP. MAX. Unit Note
Remark
time from inactivation /CEf Hi-Z state output.
Data Sheet M15372EJ5V0DS
MC-242454
Write Cycle (Erase Program) (Flash Memory)
Parameter Write cycle time VCCf Address setup time (/WE address) Address setup time (/CEf address) Address hold time (/WE address) Address hold time (/CEf address) Input data setup time Input data hold time hold time Read Toggle bit, Data polling Read recovery time before write (/OE /CEf) Read recovery time before write (/OE /WE) setup time (/CEf /WE) /CEf setup time (/WE /CEf) hold time (/CEf /WE) /CEf hold time (/WE /CEf) Write pulse width /CEf pulse width Write pulse width high /CEf pulse width high Byte programming operation time Word programming operation time Sector erase operation time VCCf setup time (/BY) recovery time /RESET pulse width /RESET high-voltage (VID) hold time from high RY(/BY) when sector group temporarily unprotect /RESET hold time From completion automatic program erase data output time VCCf tBUSY tASO tAHT tCEPH tOEPH tVLHT tVIDR tVACCR tTOW tSPD (/BY) delay time from valid program erase operation Address setup time toggle Address hold time /CEf high toggle /CEf pulse width high toggle pulse width high toggle Voltage transition time Rise time (/RESET) Rise time VACC (/WP(ACC)) Erase timeout time Erase suspend transition time tEOE tGHEL tGHWL tWPH tCPH tBPG tWPG tSER tVCS tRRB tOEH Symbol MIN. TYP. MAX. Unit Note
Notes preprogramming time prior erase operation included. Sector group protection accelerated mode only Sector group protection only. Table only.
Data Sheet M15372EJ5V0DS
MC-242454
Write operation (Erase Program) Performance (Flash Memory)
Parameter Sector erase time Chip erase time Byte programming time Word programming time Chip programming time Description Excludes programming time prior erasure Excludes programming time prior erasure Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead BYTE mode WORD mode Accelerated programming time Erase Program cycle Excludes system-level overhead 100,000 MIN. TYP. MAX. Unit
cycles
Data Sheet M15372EJ5V0DS
MC-242454
Read Cycle (Mobile specified RAM)
Parameter Symbol MC-242454-B90 MIN. Read cycle time Identical address read cycle time Address skew time /CEm pulse width Address access time /CEm access time output valid /LB, output valid Output hold from address change /CEm output impedance output impedance /LB, output impedance /CEm output high impedance output high impedance /LB, output high impedance tRC1 tSKEW tACS tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ MAX. 10,000 10,000 MC-242454-B95 MIN. MAX. 10,000 10,000 MC-242454-B10 MIN. MAX. 10,000 10,000 Unit Note
Notes read cycle (tRC) must satisfy minimum value (tRC(MIN.)) maximum value (tRC(MAX.) µs). indicates time from /CEm level input point address determination point, whichever later, /CEm high level input point next address change start point, whichever earlier. result, there following four conditions tRC. Time from address determination point /CEm high level input point Time from address determination point next address change start point Time from /CEm level input point next address change start point Time from /CEm level input point /CEm high level input point (address access) (address access) (/CEm access) (/CEm access)
identical address read cycle time (tRC1) cycle time read operation when performing continuous read operations toggling /LB, with address fixed /CEm level. Perform settings that (tRC) identical address read cycle times (tRC1) less. tSKEW indicates following three types time depending condition. When switching /CEm from high level level, tSKEW time from /CEm level input point until next address determined. When switching /CEm from level high level, tSKEW time from address change start point /CEm high level input point. When /CEm fixed level, tSKEW time from address change start point until next address determined. Since specs defined tSKEW only when /CEm active, tSKEW subject limitations when /CEm switched from high level level following address determination, when address changed after /CEm switched from level high level. Regarding tACS, only satisfied during address access (refer Note only tACS satisfied during /CEm access (refer Note Regarding tOE, only satisfied becomes active later than /LB, only satisfied become active before /OE.
Data Sheet M15372EJ5V0DS
MC-242454
Write Cycle (Mobile specified RAM)
Parameter Symbol MC-242454-B90 MIN. Write cycle time Identical address write cycle time Address skew time /CEm write /LB, write Address valid write Write pulse width Write recovery time /CEm pulse width Address setup time Byte write hold time Data valid write Data hold time output impedance output high impedance output high impedance Output active from write tWC1 tSKEW tBWH tOLZ tWHZ tOHZ MAX. 10,000 10,000 MC-242454-B95 MIN. MAX. 10,000 10,000 MC-242454-B10 MIN. MAX. 10,000 10,000 Unit Note
Notes write cycle (tWC) must satisfy minimum value (tWC(MIN.)) maximum value (tWC(MAX.) µs). indicates time from /CEm level input point address determination point, whichever after, /CEm high level input point next address change start point, whichever earlier. result, there following four conditions tWC. Time from address determination point /CEm high level input point Time from address determination point next address change start point Time from /CEm level input point next address change start point Time from /CEm level input point /CEm high level input point identical address read cycle time (tWC1) cycle time write cycle when performing continuous write operations with address fixed /CEm level, changing same time, toggling /WE, well when performing continuous write toggling /UB. Make settings that (tWC) identical address write cycle times (tWC1) less. tSKEW indicates following three types time depending condition. When switching /CEm from high level level, tSKEW time from /CEm level input point until next address determined. When switching /CEm from level high level, tSKEW time from address change start point /CEm high level input point. When /CEm fixed level, tSKEW time from address change start point until next address determined. Since specs defined tSKEW only when /CEm active, tSKEW subject limitations when /CEm switched from high level level following address determination, when address changed after /CEm switched from level high level.
Data Sheet M15372EJ5V0DS
MC-242454
Definition write start write
/CEm Write start pattern /LB, Status /WE, /LB, level, time when /CEm changes from high level level Write start pattern /CEm, /LB, level, time when changes from high level level Write start pattern /CEm, level, time when changes from high level level Write pattern /CEm, /WE, /LB, level, time when changes from level high level Write pattern When /CEm, /WE, /LB, level, time when changes from level high level
Definition write recovery time (tWR) Time from write address change start point, from write /CEm high level input point When /CEm, /LB, level continuously written identical address, time from high level input point level input point When /CEm, level continuously written identical address, time from high level input point, whichever later, level input point, whichever earlier. When /CEm level continuously written identical address, time from write point which /LB, starts change from high level level, whichever earliest.
Read Write Cycle (Mobile specified RAM)
Parameter Symbol MC-242454-B90 MIN. Read write cycle time Byte write setup time Byte read setup time tRWC tBWS tBRS MAX. 10,000 MC-242454-B95 MIN. MAX. 10,000 MC-242454-B10 MIN. MAX. 10,000 Unit Note
Notes Make settings that (tRWC) identical address read cycle time (tRC1) identical address write cycle time (tWC1) less when write performed identical address using following read using with /CEm level, when write performed using following read using /UB. Make settings that (tRWC) identical address read cycle time (tRC1) identical address write cycle time (tWC1) less when read performed identical address using following write using with /CEm level, when read performed using following write using /UB.
Data Sheet M15372EJ5V0DS
MC-242454
Figure Alternating Mobile specified Flash Memory Timing Chart
/CEf (Input) tCCR tCCR
/CEm (Input)
Figure Read Cycle Timing Chart (Flash Memory)
Address (Input) tACC /CEf (Input) tCEf (Input) tOEH (Input)
(Output)
Hi-Z
Data
Hi-Z
Figure Read Cycle Timing Chart (Flash Memory)
Address (Input) /RESET (Input) tACC
tREADY tCEf
/CEf (Input) Hi-Z Hi-Z
(Output)
Data
Data Sheet M15372EJ5V0DS
MC-242454
Figure Sector Group Protection Timing Chart (Flash Memory)
VCCf tVCS /RESET (Input)
tVIDR tVLHT
SGAx SGAx SGAy
Address (Input)
(Input)
(Input)
(Input)
/CEf (Input)
(Input) (Input) (Input/Output)
Note
TIMEOUT
Note sector group protection verification result output. sector group protected. sector group protected.
Figure Temporary Sector Group Unprotect Timing Chart (Flash Memory)
VCCf /RESET (Input)
tVCS tVIDR tVLHT
tRRB (Program erase command sequence)
(Input)
/CEf (Input) tVLHT (/BY) (Output) Period during which protection canceled tVLHT
Data Sheet M15372EJ5V0DS
MC-242454
Figure Accelerated Mode Timing Chart (Flash Memory)
VCCf VACC (ACC) (Input)
tVCS tVACCR tVLHT
(Program erase command sequence) (Input)
/CEf (Input) tVLHT (/BY) (Output) Accelerated mode period tVLHT
Figure Dual Operation Timing Chart (Flash Memory)
Address (Input) /CEf (Input) tCEf (Input) tGHWL (Input) (Input Output) Output Input Output Input Output Status tOEH tCEPH tACC tAHT
Data Sheet M15372EJ5V0DS
MC-242454
Figure Write Cycle Timing Chart (/WE Controlled) (Flash Memory)
(3rd write cycle) Address (Input) 555H /CEf (Input) tGHWL (Input) (Input) (Input Output) tWPH /I/O7 DOUT DOUT tBPG tWPG tCEf (Data polling)
Remarks This timing chart shows last write cycles among program command sequence's four write cycles, data polling. This timing chart shows WORD mode's case. BYTE mode, address input different from WORD mode. Command Sequence (Flash Memory). Program address Program data /I/O7 output complement data written device. DOUT output data written device. Figure Write Cycle Timing Chart (/CEf Controlled) (Flash Memory)
(3rd write cycle) Address (Input) 555H /CEf (Input) tGHEL (Input) (Input) (Input Output) /I/O7 DOUT DOUT tBPG tWPG tCEf tCPH (Data polling)
Remarks This timing chart shows last write cycles among program command sequence's four write cycles, data polling. This timing chart shows WORD mode's case. BYTE mode, address input different from WORD mode. Command Sequence (Flash Memory). Program address Program data /I/O7 output complement data written device. DOUT output data written device.
Data Sheet M15372EJ5V0DS
MC-242454
Figure Sector Chip Erase Timing Chart (Flash Memory)
Address (Input) 555H 2AAH /CEf (Input) (Input) tGHWL (Input) (Input) tVCS VCCf (10H chip erase) tWPH 555H 555H 2AAH
Note
Note sector address erased. case chip erase, input 555H (WORD mode), AAAH (BYTE mode). Remark This timing chart shows WORD mode's case. BYTE mode, address input different from WORD mode. Command Sequence (Flash Memory).
Figure Data Polling Timing Chart (Flash Memory)
/CEf (Input) (Input) tOEH tCEf (Input) tBPG, tWPG, tSER I/O7 (Output) /I/O7 DOUT
Note
Hi-Z
I/O0 I/O6 (Output) tBUSY (/BY) (Output)
Status data
Valid data tEOE
Hi-Z
Note I/O7 DOUT True value program data (indicates completion automatic program erase)
Data Sheet M15372EJ5V0DS
MC-242454
Figure Toggle Timing Chart (Flash Memory)
Address (Input) tAHT tAHT /CEf (Input) tASO tCEPH (Input) tOEH (Input) I/O6, I/O2 (Input Output) Input data tBUSY (/BY) (Output) Toggle Toggle tCEf Toggle StopNote toggling Valid data tOEPH tOEH
Note I/O6 stops toggle (indicates automatic program erase completion). Figure I/O2 I/O6 Timing Chart (Flash Memory)
Input automatic Erase erase command suspended (Input)
Erasure
Erase suspended input program command
Erasure resumed
Erasure Completion erasure
Erase suspended read
Erase suspended read Erase suspended input program command
I/O6 (Output)
I/O2 (Output) Toggle I/O2 I/O6 (/CEf used toggle)
Figure (/BY) (Ready Busy) Timing Chart (Flash Memory)
/CEf (Input) Rising edge last write pulse (Input) Automatic program erase
(/BY) (Output) tBUSY
Figure /RESET (/BY) Timing Chart (Flash Memory)
(Input)
/RESET (Input) (/BY) (Output) tREADY
Data Sheet M15372EJ5V0DS
MC-242454
Figure Write CIOf Timing Chart (Flash Memory)
Falling edge last write pulse /CEf, (Input) Input determined CIOf (Input)
Figure BYTE mode Switching Timing Chart (Flash Memory)
/CEf (Input)
CIOf (Input) tELFL Hi-Z Data Output I/O0-I/O14 tACC I/O15 (Output), (Input) Hi-Z Data Output I/O15 tFLQZ Address Input Data Output I/O0-I/O7 Hi-Z
I/O0 I/O14 (Output)
Figure WORD mode Switching Timing Chart (Flash Memory)
/CEf (Input) tCEf CIOf (Input) tELFH I/O0 I/O14 (Output) Hi-Z Data Output I/O0-I/O7 Data Output I/O0-I/O14 Hi-Z
I/O15 (Output), (Input)
Address Input tFHQV
Data Output I/O15
Hi-Z
Data Sheet M15372EJ5V0DS
MC-242454
Figure Read Cycle Timing Chart (Mobile specified RAM)
tSKEW tSKEW
Address (Input)
/CEm (Input)
tACS tCLZ tCHZ
(Input)
tOLZ tOHZ
/LB, (Input)
tBLZ tBHZ
(Output)
Hi-Z
Data
tSKEW
tSKEW
Address (Input)
/CEm (Input)
tCLZ
tCHZ
(Input)
tOLZ tOHZ
/LB, (Input)
tBLZ tBHZ
(Output)
Hi-Z
Data
Caution address changed using value that either lower than minimum value higher than maximum value read cycle time (tRC), none data guaranteed.
Remark read cycle, should fixed High.
Data Sheet M15372EJ5V0DS
Figure Read Cycle Timing Chart (Mobile specified RAM)
tSKEW tSKEW tSKEW tSKEW
Address (Input)
Data Sheet M15372EJ5V0DS
/CEm (Input)
tCLZ tCHZ tACS tCLZ tOLZ tOHZ tCHZ tACS tCLZ tCHZ
(Input)
/LB, (Input)
tBLZ tBLZ tBHZ tBLZ tBHZ tBHZ
(Output)
Hi-Z
Data
Data
Data
Data
Data
Caution address changed using value that either lower than minimum value higher than maximum value read cycle time (tRC), none data guaranteed.
MC-242454
Remark read cycle, should fixed High.
Figure Read Cycle Timing Chart (Mobile specified RAM)
tSKEW
tSKEW
tSKEW
tSKEW
tSKEW
Address (Input)
/CEm (Input)
tCLZ
Data Sheet M15372EJ5V0DS
(Input)
tOLZ
tOHZ tOLZ tBHZ tBLZ tBLZ
tOHZ tOLZ tBHZ
tOHZ
(Input)
I/O0 (Output)
Hi-Z
Data
Data
(Input)
tBLZ
tBHZ tBLZ
tBHZ
I/O8 (Output)
Hi-Z
Data
Data
MC-242454
Caution address changed using value that either lower than minimum value higher than maximum value read cycle time (tRC), none data guaranteed.
Remark read cycle, should fixed High.
MC-242454
Figure Read Cycle Timing Chart (Mobile specified RAM)
tSKEW tSKEW
Address (Input)
tRC1
Note
tRC1
Note
/CEm (Input)
tOLZ tOLZ tOHZ tOHZ
(Input)
tBLZ tBLZ tBHZ tBHZ
/LB, (Input)
Hi-Z
(Output)
Data
Data
Hi-Z
Caution address changed using value that either lower than minimum value higher than maximum value read cycle time (tRC), none data guaranteed.
Note perform continuous read toggling /OE, /UB, with /CEm level identical address, make settings that (tRC) identical address read cycle times (tRC1) less.
Remark read cycle, should fixed High.
Data Sheet M15372EJ5V0DS
MC-242454
Figure Write Cycle Timing Chart (Mobile specified RAM)
tSKEW tSKEW
Address (Input)
/CEm (Input)
(Input)
/LB, (Input)
Hi-Z
(Intput)
Hi-Z
Data
Data
tSKEW
tSKEW
tSKEW
Address (Input)
/CEm (Input)
(Input)
/LB, (Input)
Hi-Z
(Intput)
Hi-Z
Data
Data
Cautions During address transition, least pins /CEm, should inactivated. input data pins while they output state. address changed using value that either lower than minimum value higher than maximum value write cycle time (tWC), none data guaranteed.
Remark
Write operation done during overlap time /CEm, /WE, and/or /UB.
Data Sheet M15372EJ5V0DS
MC-242454
Figure Write Cycle Timing Chart (Mobile specified RAM)
tSKEW tSKEW tSKEW tSKEW tSKEW
Address (Input)
/CEm (Input)
(Input)
tWHZ
(Input)
tOLZ tOHZ Indefinite data
Hi-Z Hi-Z
Hi-Z
Hi-Z
(Intput Output)
Hi-Z
Data
Data
Data
tSKEW
tSKEW
Address (Input)
tWC1 Note tWC1
Note
/CEm (Input)
(Input)
/LB, (Input)
Hi-Z Hi-Z
(Intput)
Hi-Z
Data
Data
Cautions During address transition, least pins /CEm, should inactivated. input data pins while they output state. address changed using value that either lower than minimum value higher than maximum value write cycle time (tWC), none data guaranteed.
Note
changed same time with /CEm level continuous write operation toggling performed, make settings that (tWC) identical address write cycle time (tWC1) less.
Remarks Write operation done during overlap time /CEm, /WE, and/or /UB. When Low, pins always high impedance. When High, read operation executed. Therefore should High make pins high impedance.
Data Sheet M15372EJ5V0DS
MC-242454
Figure Write Cycle Timing Chart (/CEm Controlled) (Mobile specified RAM)
Address (Input)
/CEm (Input)
(Input)
/LB, (Input)
Hi-Z Hi-Z
(Intput)
Hi-Z
Data
Data
Address (Input)
/CEm (Input)
(Input)
/LB, (Input)
Hi-Z Hi-Z
(Intput)
Hi-Z
Data
Data
Cautions During address transition, least pins /CEm, should inactivated. input data pins while they output state. address changed using value that either lower than minimum value higher than maximum value write cycle time (tWC), none data guaranteed.
Remark Write operation done during overlap time /CEm, /WE, and/or /UB.
Data Sheet M15372EJ5V0DS
MC-242454
Figure Write Cycle Timing Chart (/LB, Controlled (Mobile specified RAM)
tSKEW tSKEW
Address (Input)
/CEm (Input)
(Input)
/LB, (Input)
Hi-Z
(Intput)
Hi-Z
Data
Data
tSKEW
tSKEW
Address (Input)
/CEm (Input)
(Input)
/LB, (Input)
Hi-Z
(Intput)
Hi-Z
Data
Data
Cautions During address transition, least pins /CEm, should inactivated. input data pins while they output state. address changed using value that either lower than minimum value higher than maximum value write cycle time (tWC), none data guaranteed.
Remark Write operation done during overlap time /CEm, /WE, and/or /UB.
Data Sheet M15372EJ5V0DS
MC-242454
Figure Write Cycle Timing Chart (/LB, Controlled (Mobile specified RAM)
tSKEW tSKEW
Address (Input)
tWC1
Note
tWC1
Note
/CEm (Input)
(Input)
/LB, (Input)
Hi-Z Hi-Z
(Intput)
Hi-Z
Data
Data
Cautions During address transition, least pins /CEm, should inactivated. input data pins while they output state. address changed using value that either lower than minimum value higher than maximum value write cycle time (tWC), none data guaranteed.
Note changed same time with /CEm level continuous write operation toggling performed, make settings that (tWC) identical address write cycle time (tWC1) less.
Remark Write operation done during overlap time /CEm, /WE, and/or /UB.
Data Sheet M15372EJ5V0DS
MC-242454
Figure Write Cycle Timing Chart (/LB, Independent Controlled (Mobile specified RAM)
Address (Input)
tWC1
Note
tWC1
Note
/CEm (Input)
(Input)
(Input)
(Input)
Hi-Z Hi-Z
I/O0 (Intput)
Data
Hi-Z
I/O8 (Intput)
Hi-Z
Data
Cautions During address transition, least pins /CEm, should inactivated. input data pins while they output state. address changed using value that either lower than minimum value higher than maximum value write cycle time (tWC), none data guaranteed.
Note changed same time with /CEm level continuous write operation toggling performed, make settings that (tWC) identical address write cycle time (tWC1) less.
Remark Write operation done during overlap time /CEm, /WE, and/or /UB.
Data Sheet M15372EJ5V0DS
MC-242454
Figure Write Cycle Timing Chart (/LB, Independent Controlled (Mobile specified RAM)
Address (Input)
/CEm (Input)
(Input)
(Input)
tBWH
(Input)
Hi-Z
I/O0 (Intput)
Hi-Z
Data
I/O8 (Intput)
Hi-Z
Hi-Z
Data
Cautions During address transition, least pins /CEm, should inactivated. input data pins while they output state. address changed using value that either lower than minimum value higher than maximum value write cycle time (tWC), none data guaranteed.
Remark Write operation done during overlap time /CEm, /WE, and/or /UB.
Data Sheet M15372EJ5V0DS
MC-242454
Figure Read Write Cycle Timing Chart (/LB, Independent Controlled (Mobile specified RAM)
tRWC
Address (Input)
tRC1
Note
tWC1
Note
/CEm (Input)
tACS
(Input)
tBWS
(Input)
(Input)
tCLZ tBLZ Hi-Z tBHZ
I/O0 (Output)
Data
Hi-Z
I/O8 (Intput)
Hi-Z
Hi-Z
Data
Cautions During address transition, least pins /CEm, should inactivated. input data pins while they output state. address changed using value that either lower than minimum value higher than maximum value identical address read cycle time (tRC1) identical address write cycle time (tWC1), none data guaranteed.
Note Make settings that (tRWC) identical address read cycle time (tRC1) identical address write cycle time (tWC1) less when write performed identical address using following read using with /CEm level, when write performed using following read using /UB.
Remark Write operation done during overlap time /CEm, /WE, and/or /UB.
Data Sheet M15372EJ5V0DS
MC-242454
Figure Read Write Cycle Timing Chart (/LB, Independent Controlled (Mobile specified RAM)
tRWC
Address (Input)
tWC1Note tRC1 Note
/CEm (Input)
(Input)
(Input)
tBRS
(Input)
Hi-Z tBLZ tBHZ Hi-Z
I/O0 (Input)
Hi-Z
Data
I/O8 (Output)
Hi-Z
Data
Cautions During address transition, least pins /CEm, should inactivated. input data pins while they output state. address changed using value that either lower than minimum value higher than maximum value identical address read cycle time (tRC1) identical address write cycle time (tWC1), none data guaranteed.
Note Make settings that (tRWC) identical address read cycle time (tRC1) identical address write cycle time (tWC1) less when write performed identical address using following read using with /CEm level, when write performed using following read using /UB.
Remark Write operation done during overlap time /CEm, /WE, and/or /UB.
Data Sheet M15372EJ5V0DS
MC-242454
Figure Read Write Cycle Timing Chart (/LB, Independent Controlled (Mobile specified RAM)
tRWC
Address (Input)
tWC1Note tRC1Note
/CEm (Input)
(Input)
(Input)
(Input)
Hi-Z tBLZ tBHZ Hi-Z
I/O0 (Input)
Hi-Z
Data
I/O8 (Output)
Hi-Z
Data
Cautions During address transition, least pins /CEm, should inactivated. input data pins while they output state. address changed using value that either lower than minimum value higher than maximum value identical address read cycle time (tRC1) identical address write cycle time (tWC1), none data guaranteed.
Note Make settings that (tRWC) identical address read cycle time (tRC1) identical address write cycle time (tWC1) less when write performed identical address using following read using with /CEm level, when write performed using following read using /UB.
Remark Write operation done during overlap time /CEm, /WE, and/or /UB.
Data Sheet M15372EJ5V0DS
MC-242454
Figure Standby Mode entry recovery Timing Chart (Mobile specified RAM)
Address (Input)
MODE (Input) /CEm (Input)
Standby Mode
Wait Time
Read Operation times
Normal Operation
Parameter /CEm High MODE
Symbol
MIN.
MAX.
Unit
Note
Cautions Make MODE /CEm high level during wait time. Make MODE high level during wait time eight read operations. read operation must satisfy specs described page (Read Cycle (Mobile specified RAM)). read operation address either VIL. Perform reading toggling /CEm. prevent contention, recommended high level. However, input data pins level during read operation.
Flow Charts (Flash Memory) Refer DUAL OPERATION FLASH MEMORY BITS SERIES Information (M14914E).
Data Sheet M15372EJ5V0DS
MC-242454
Code List (1/2)
Address Data I/O15 I/O0 0051H 0052H 0059H 0002H 0000H 0040H 0000H 0000H 0000H 0000H 0000H 0027H Minimum VCCf voltage (program erase) I/O7 I/O4 V/bit I/O3 I/O0 mV/bit 0036H Maximum VCCf voltage (program erase) I/O7 I/O4 V/bit I/O3 I/O0 mV/bit 0000H 0000H 0004H 0000H 000AH 0000H 0005H 0000H 0004H 0000H 0016H 0002H 0000H 0000H 0000H 0002H 0007H 0000H 0020H 0000H Type erase block Information about erase block Bit0 number sectors Bit16 size Bytes) Minimum voltage Maximum voltage Typical word program time Typical buffer program time Typical sector erase time Typical chip erase time Maximum word program time (typical time Maximum buffer program time (typical time Maximum sector erasing time (typical time Maximum chip erasing time (typical time Capacity Bytes) information organization Maximum number bytes when banks programmed Auxiliary command supported Start address auxiliary algorithm table Main command AMD/FJ standard type Start address PRIMARY table "QRY" (ASCII code) Description
Data Sheet M15372EJ5V0DS
MC-242454
(2/2)
Address Data I/O15 I/O0 003EH 0000H 0000H 0001H 0050H 0052H 0049H 0031H 0032H 0000H Main version (ASCII code) Minor version (ASCII code) Address during command input Necessary Unnecessary 0002H Temporary erase suspend function supported Read only Read Program 0001H Sector group protection supported Supported 0001H Temporary sector group protection supported Supported 0004H 00xxH Sector group protection algorithm Number sectors bank supported MC-242454 0000H Burst mode supported 0000H Page mode supported 0085H Minimum VACC voltage I/O7 I/O4 V/bit I/O3 I/O0 mV/bit 0095H Maximum VACC voltage I/O7 I/O4 V/bit I/O3 I/O0 mV/bit 00xxH Boot organization Bottom boot 0001H Temporary program suspend function supported Supported Information about erase block bit0 number sectors bit16 size Bytes) "PRI" (ASCII code) Description
Data Sheet M15372EJ5V0DS
MC-242454
Package Drawings
77-PIN TAPE FBGA (12x7)
INDEX MARK
ITEM
MILLIMETERS 7.0±0.1 12.0±0.1 1.1±0.1 0.26±0.05 0.84 0.45±0.05 0.08 P77F9-80-BT3
Data Sheet M15372EJ5V0DS
MC-242454
71-PIN TAPE FBGA (11x7) (unit:
INDEX MARK
0.84
0.45
These specifications typical values. This package drawing preliminary version. changed future.
Data Sheet M15372EJ5V0DS
MC-242454
Recommended Soldering Conditions Please consult with sales offices soldering conditions MC-242454.
Types Surface Mount Device MC-242454F9-B90-BT3 77-pin TAPE FBGA MC-242454F9-B95-BT3 77-pin TAPE FBGA MC-242454F9-B10-BT3 77-pin TAPE FBGA MC-242454F9-B90-BS1 71-pin TAPE FBGA MC-242454F9-B95-BS1 71-pin TAPE FBGA MC-242454F9-B10-BS1 71-pin TAPE FBGA
Data Sheet M15372EJ5V0DS
MC-242454
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet M15372EJ5V0DS
MC-242454
Related Documents
Document Name DUAL OPERATION FLASH MEMORY BITS SERIES Information Document Number M14914E
information this document current July, 2001. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

MC-242454 (MULTI-CHIP PACKAGE) FLASH MEMORY MOBILE SPECIFIED 32M-

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