3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE WITH VOLT TOLERANT

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3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE WITH VOLT TOLERANT

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IDT74LVC86A 3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE WITH VOLT TOLERANT
MICRON CMOS Technology 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 1.27mm pitch SOIC, 0.65mm pitch SSOP 0.65mm pitch TSSOP packages Extended commercial range 40°C +85°C 3.3V ±0.3V, Normal Range 2.3V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin inputs, outputs Volt tolerant Supports insertion
IDT74LVC86A
DESCRIPTION
This quadruple 2-input exclusive-OR gate built using advanced dual metal CMOS technology. LVC86A performs Boolean function positive logic. common application true/ complement element. inputs low, other input reproduced true form output. inputs high, signal other input reproduced inverted output. LVC86A been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. Inputs driven from either 3.3V devices. This feature allows this device translator mixed 3.3V/5V system environment.
Drive Features LVC86A: High Output Drivers: ±24mA Reduced system switching noise
APPLICATIONS:
3.3V mixed voltage systems Data communication telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
CONFIGURATION
SO14-1 SO14-2 SO14-3
FUNCTION TABLE (each gate)
Inputs
NOTE: HIGH Voltage Level Voltage Level
Outputs
SOIC/ SSOP/ TSSOP VIEW
DESCRIPTION
Names Description Data Inputs Data Outputs
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4725/-
IDT74LVC86A 3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM TSTG IOUT Description Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each
QUAD Link
CAPACITANCE +25°C, 1.0MHZ)
Unit CI/O Symbol COUT Parameter(1) Input Capacitance Output Capacitance Port Capacitance
QUAD Link
Max. +6.5 +150 ±100
Conditions VOUT
Typ.
Max.
Unit
NOTE: applicable device type.
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: 40°c +85°c
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, 18mA 3.3V 3.6V Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 5.5V 5.5V Min. Typ.(1) Max. Unit
Quiescent Power Supply Current Variation
input 0.6V other inputs
QUAD Link
NOTE: Typical values 3.3V, +25°C ambient.
IDT74LVC86A 3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. 24mA 0.1mA 12mA 2.7V 3.0V 12mA 24mA Max. 0.55
QUAD Link
Unit
2.3V 2.3V 2.7V 3.0V 3.0V Output Voltage 2.3V 3.6V 2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C +85°C.
OPERATING CHARACTERISTICS, 25°C
2.5V±0.2V Symbol Parameter Power Dissipation Capacitance Gate Test Conditions 0pF, 10Mhz Typical 3.3V±0.3V Typical Unit
SWITCHING CHARACTERISTICS
Symbol Parameter tPLH Propagation Delay tPHL tsk(o) Output Skew(2)
2.7V 3.3V±0.3V Unit
2.5V±0.2V
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVC86A 3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
TEST CONDITIONS
Symbol VLOAD VCC(1)= 2.5V ±0.2V
TEST CIRCUITS WAVEFORMS PROPAGATION DELAY
VCC(2)= 3.3V ±0.3V 2.7V Unit
QUAD Link
ITIO tPLH tPLH SITE ITIO
TEST CIRCUITS OUTPUTS
Pulse enerator
LOAD
ENABLE DISABLE TIMES
ABLE tPZL tPLZ LOAD/2 ISAB LOAD/2
D.U.T.
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns. Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns.
ITCH ALLY ITCH ALLY
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
SET-UP, HOLD, RELEASE TIMES
QUAD Link
Open
OUTPUT SKEW
PLH2 tPLH1
PULSE WIDTH
tPLH1 tPHL1
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74LVC86A 3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
ORDERING INFORMATION
Temp. Range Device Type Package
Small Outline (SO14-1) Shrink Small Outline Package (SO14-2) Thin Shrink Small Outline Package (SO14-3) Quadruple 2-Input Exclusive-OR Gate, ±24mA
-40°C +85°C
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3.3V CMOS QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE WITH VOLT TOLERANT

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