PowerPC405 32-bit RISC processor core operating PC-100 Synchronous DRA

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PowerPC405 32-bit RISC processor core operating PC-100 Synchronous DRA

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PowerPC 405GP Embedded Processor Data Sheet
PowerPC405 32-bit RISC processor core operating PC-100 Synchronous DRAM (SDRAM) interface operating 32-bit interface non-ECC applications 40-bit interface serves bits data plus check bits applications On-chip Memory (OCM) External Peripheral Flash ROM/Boot interface Direct support 16-, 32-bit SRAM external peripherals eight devices External Mastering supported support external peripherals, internal UART memory Scatter-gather chaining supported Four channels Revision Compliant Interface (32-bit, 66MHz) interface configured operate synchronously asynchronously chip input clock (I2C) interface General Purpose (GPIO) available Supports JTAG board level testing Internal Processor Local (PLB) runs SDRAM interface frequency Supports PowerPC processor boot from memory Internal Arbiter which disabled with external arbiter Ethernet 10/100Mbps (full-duplex) support with Medium Independent Interface (MII) Programmable Interrupt Controller supports interrupts from variety sources Seven external internal Edge triggered level-sensitive Positive negative active Non-critical critical interrupt processor core Programmable critical interrupt priority ordering Programmable critical interrupt vector faster vector processing Programmable Timers serial ports (16550 compatible UART)
Designed specifically address embedded applications, PowerPC 405GP (PPC405GP) provides high-performance, low-power solution that interfaces wide range peripherals incorporating on-chip power management features intrinsically lower power dissipation requirements. This chip contains high-performance RISC processor core, SDRAM controller, interface, Ethernet interface, control external peripherals, with scatter-gather support, serial ports, interface, general purpose I/O. Technology: CMOS SA12E 0.25 (0.18 Leff) Package: 456-ball (35mm 27mm), 413-ball (25mm) enhanced plastic ball grid array (E-PBGA) Power (estimated): Typical 1.5W, Maximum 2.0W
While information contained herein believed accurate, such information preliminary, should relied upon accuracy completeness, representations warranties accuracy completeness made
PowerPC 405GP Embedded Processor Data Sheet
Contents
Ordering, PVR, JTAG Information Address Support On-Chip Memory Interface SDRAM Memory Controller External Peripheral Controller (EBC) Controller UART Interface General Purpose (GPIO) Controller Universal Interrupt Controller (UIC) 10/100 Mbps Ethernet JTAG Signal List Spread Spectrum Clocking Strapping
Tables
SysMem Memory Address Address Signals Listed Alphabetically Signals Listed Ball Assignment-413-Ball Package Signals Listed Ball Assignment-456-Ball Package Summary Signal Functional Description Absolute Maximum Ratings Package Thermal Specifications Recommended Operating Conditions Capacitance Electrical Characteristics SysClk MemClk Timing Peripheral Interface Clock Timings Specifications-All Specifications-200MHz (Revision Preliminary) Specifications-266MHz (Preliminary) Strapping Assignments
PowerPC 405GP Embedded Processor Data Sheet
Figures
PPC405GP Embedded Controller Functional Block Diagram 25mm, 413-Ball E-PBGA Package 27mm, 456-Ball E-PBGA Package 35mm, 456-Ball E-PBGA Package Input Setup Hold Waveform Output Delay Float Timing Waveform
PowerPC 405GP Embedded Processor Data Sheet
Ordering, PVR, JTAG Information
Processor Frequency 200MHz 200MHz 200MHz 200MHz 200MHz 200MHz 266MHz 266MHz 266MHz 266MHz 266MHz 266MHz Level
Product Name PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP
Order Part Number1 IBM25PPC405GP-3BE200C IBM25PPC405GP3BE200CZ IBM25PPC405GP-3DE200C IBM25PPC405GP3DE200CZ IBM25PPC405GP-3EE200C IBM25PPC405GP3EE200CZ IBM25PPC405GP-3BE266C IBM25PPC405GP3BE266CZ IBM25PPC405GP-3DE266C IBM25PPC405GP3DE266CZ IBM25PPC405GP-3EE266C IBM25PPC405GP3EE266CZ
Package 35mm, E-PBGA 35mm, E-PBGA 27mm, E-PBGA 27mm, E-PBGA 25mm, E-PBGA 25mm, E-PBGA 35mm, E-PBGA 35mm, E-PBGA 27mm, E-PBGA 27mm, E-PBGA 25mm, E-PBGA 25mm, E-PBGA
Value 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145
JTAG 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049
Note Order Part Number indicates tape reel shipping package. Otherwise, chips shipped tray.
This section provides part number nomenclature. availability, contact your local sales office. part number contains part modifier. Included modifier revision code. This refers mask revision number specified part numbering scheme identification purposes only. (Processor Version Register) software accessible contains additional information about revision level part. Refer PPC405GP User's Manual details register content. Part Number
IBM25PPC405GP-3BE200Cx
Shipping Package* Blank Tray Tape reel Case Temperature Range (-40°C +85°C) Processor Speed Revision Level
Part Number Grade Reliability Package
PowerPC 405GP Embedded Processor Data Sheet
PPC405GP Embedded Controller Functional Block Diagram
Universal Interrupt Controller Clock Control Reset Timers Power Mgmt DOCM IOCM SRAM DCRs Control GPIO *Serial Clock UART UART
PPC405 Processor Core JTAG D-Cache Trace
16KB I-Cache
On-chip Peripheral (OPB)
Controller (4-Channel)
Bridge
Ethernet
Processor Local (PLB) Code Decompression (CodePack) Peripheral Interface Clock Timings table
SDRAM Controller 13-bit addr 32-bit data
External Controller
External Master Controller
Bridge
32-bit addr 32-bit data
(async) (sync)
PPC405GP designed using Microelectronics Blue Logicmethodology which major functional blocks integrated together create application-specific ASIC product. This approach provides consistent create complex ASICs using CoreConnectBus Architecture. Note: CoreConnect busses provide: 64-bit interfaces 133MHz 32-bit interfaces 66MHz
PowerPC 405GP Embedded Processor Data Sheet
Address Support
PPC405GP incorporates simple separate address maps. first fixed processor address that serves PowerPC family processors. This address defines possible contents various address regions which processor access. second address Device Configuration Registers (DCR). This address accessed software running PPC405GP processor through MTDCR MFDCR commands.
SysMem Memory Address System Memory
Function Local Memory/Peripherals1 Total Memory Reserved Reserved Configuration Registers Reserved Interrupt Acknowledge Reserved local Configuration Registers Reserved Total UART0 Reserved UART1 Reserved IIC0 Internal Peripherals Reserved Arbiter Reserved GPIO Controller Registers Reserved Ethernet Controller Registers Reserved Expansion ROM2 Boot ROM2, Function Start Address 00000000 80000000 80000000 E8000000 E8010000 E8800000 EC000000 EEC00000 EEC00008 EED00000 EEE00000 EF400000 EF400040 EF600000 EF600300 EF600308 EF600400 EF600408 EF600500 EF600520 EF600600 EF600640 EF600700 EF600780 EF600800 EF600900 F0000000 FFE00000 Address 7FFFFFFF EF5FFFFF E7FFFFFF E800FFFF E87FFFFF EBFFFFFF EEBFFFFF EEC00007 EECFFFFF EEDFFFFF EF3FFFFF EF40003F EF5FFFFF EFFFFFFF EF600307 EF6003FF EF600407 EF6004FF EF60051F EF6005FF EF60063F EF6006FF EF60077F EF6007FF EF6008FF EFFFFFFF FFDFFFFF FFFFFFFF 256B 254MB 128B 10MB 56MB Size 1.74GB 1.63GB 64KB
Notes: Local Memory/Peripheral area memory configured SDRAM, Peripherals. Boot Expansion area memory intended Flash-type devices. While locating volatile SDRAM SRAM this region supported controller recommended that these regions used this purpose. When optional boot from Memory selected, Boot address space begins FFFE 0000 (size 128KB).
PowerPC 405GP Embedded Processor Data Sheet
Address Device Configuration Register
Function Address Space1 Reserved Memory Controller Registers External Controller Registers Decompression Controller Registers Reserved On-Chip Memory Controller Registers Reserved Registers Reserved Bridge Registers Reserved Clock, Control Reset Power Management Interrupt Controller Reserved Controller Registers Reserved Ethernet Registers Reserved [0:2] [0:3] 0100 parm=0x0B0 parm=0x0B8 parm=0x0C0 [0:6] 000110 [0:5] 000100 [0:8] 000001011 [0:8] 000001000 [0:8] 000001001 [0:8] 000001010 Base Address Strap/Parameter Start Address(0:9) Address(0:9) Size (4KB)1 128W 512W
Notes: address space addressable with bits (1024 unique addresses). Each unique address represents single 32-bit (word) register, kiloword (KW) (which equals KB).
PowerPC 405GP Embedded Processor Data Sheet
On-Chip Memory
On-Chip Memory feature comprises memory controller one-port static (SRAM) accessed processor core. Features include: Low-latency access critical instructions data Performance identical cache hits without misses Contents change only under program control
Interface
interface core provides mechanism connecting devices local PowerPC processor local memory. This interface compliant with version Specification. Features include: Internal arbiter external devices speeds 66MHz. Internal arbiter optional disabled systems which employ external arbiter. Compliant frequency 133MHz 64-bit Master 32-bit Slave frequency 66MHz Synchronous operation fractions speed 33MHz maximum Asynchronous operation from frequency 66MHz maximum 32-bit Address/Data Power Management: Power Management v1.1 compliant Supports 1:1, 2:1, 3:1, clock ratios from Buffering between PCI: Target 64-byte write post buffer Target 96-byte read prefetch buffer Slave 8-byte write post buffer Slave 64-byte read prefetch buffer Error tracking/status Supports Target side configuration
PowerPC 405GP Embedded Processor Data Sheet
Supports processor access address spaces: Single-byte reads writes memory single-beat prefetch-burst reads single-beat writes Single-byte configuration reads writes (type type interrupt acknowledge special cycle Supports target access address spaces Supports PowerPC processor boot from memory
SDRAM Memory Controller
PPC405GP Memory Controller core provides latency access path SDRAM memory. variety system memory configurations supported. memory controller supports four logical banks. 256MB bank supported, maximum 1GB. Memory timings, address bank sizes, memory addressing modes programmable. Features include: 11x8 13x11 addressing SDRAM 4-bank) Memory operates same frequency 32-bit memory interface support Programmable address compare each bank memory address space Industry standard 168-pin DIMMS supported (some configurations) 133MHz Memory, includes PC133 support 256MB bank Programmable address mapping timing Auto refresh Page Mode Accesses with open pages Sync DRAM configuration mode command Power Management (self-refresh) Error Checking Correction (ECC) support Standard SEC/DED coverage Aligned nibble error detect Address error logging
PowerPC 405GP Embedded Processor Data Sheet
Mixed ECC/non-ECC banks Bypass mode
External Peripheral Controller (EBC)
eight ROM, EPROM, SRAM, Flash, Slave Peripheral banks supported operation Burst non-burst devices 16-, 32-bit byte-addressable data width support Latch data Ready, Synchronous Asynchronous Programmable clock time-out counter with disable Ready Programmable access timing device Wait States non-burst Burst Wait States first access Wait States subsequent accesses Programmable CSon, CSoff relative address Programmable OEon, WEon, WEoff clock cycles) relative Programmable address mapping Peripheral Device pacing with external "Ready" External master interface Write posting from external master Read prefetching external master reads Bursting capable from external master Allows external master access non-EBC slaves External master control slaves access control
Controller
Supports following transfers: Memory-to-memory transfers Buffered peripheral memory transfers Buffered memory peripheral transfers Four channels Scatter/Gather capability programming multiple operations 16-, 32-bit peripheral support (OPB external)
PowerPC 405GP Embedded Processor Data Sheet
32-bit addressing Address increment decrement Internal 32-byte data buffering capability Supports internal external peripherals Support memory mapped peripherals Support peripherals running slower frequency buses
UART
8-pin UART 4-pin UART interface provided Selectable internal external serial clock allow wide range baud rates Register compatibility with NS16550 register Complete status reporting capability Transmitter receiver each buffered with16-byte FIFOs when FIFO mode Fully programmable serial-interface characteristics Supports using internal engine
Interface
Compliant with Phillips® Semiconductors Specification, dated 1995 Operation 100kHz 400kHz 8-bit data 7-bit address Slave transmitter receiver Master transmitter receiver Multiple masters Supports fixed interface independent byte data buffers Twelve memory-mapped, fully programmable configuration registers programmable interrupt request signal Provides full management protocol Programmable error recovery
PowerPC 405GP Embedded Processor Data Sheet
General Purpose (GPIO) Controller
Controller functions GPIO registers programmed accessed memory-mapped master accesses GPIOs pin-shared with other functions. DCRs control whether particular that GPIO capabilities acts GPIO used another purpose. Twenty-three GPIOs multiplexed with: chip selects seven external interrupts nine instruction trace pins Each GPIO output separately programmable emulate open-drain driver (i.e., drives zero, threestated output
Universal Interrupt Controller (UIC)
Universal Interrupt Controller (UIC) provides control, status, communications necessary between various sources interrupts local PowerPC processor. Features include: Supports external internal interrupts Edge triggered level-sensitive Positive negative active Non-critical critical interrupt PPC405 processor core Programmable critical interrupt priority ordering Programmable critical interrupt vector faster vector processing
10/100 Mbps Ethernet
Capable handling full/half duplex 100Mbps 10Mbps operation Uses Medium Independent Interface (MII) physical layer (PHY included chip)
JTAG
IEEE 1149.1 Test Access Port RISCWatch Debugger support JTAG Boundary Scan Description Language (BSDL)
PowerPC 405GP Embedded Processor Data Sheet
25mm, 413-Ball E-PBGA Package
View
ball corner
15.7
Note: dimensions
0.20 0.25
0.20
Bottom View
25.0 22.0
0.35
25.0
Thermal balls
1.00
GLOB
0.635 SOLDER BALL 0.30 0.10 0.5±0.1 0.539
PowerPC 405GP Embedded Processor Data Sheet
27mm, 456-Ball E-PBGA Package
View
Ejector Mark 1.80 0.10
Small Radius Corner Corresponds Ball Location Index Mark 1.10 16.00 24.0
Bottom View
27.0
0.55 0.15 SOLDERBALL 0.40 0.20 0.45 2.21
0.20
16.00
0.15
Note: dimensions
27.0 25.0 0.35
1.00
Thermal Balls
PowerPC 405GP Embedded Processor Data Sheet
35mm, 456-Ball E-PBGA Package
View
Reserved Area Ejector Mark Corner Shape Chamferred Rounded
Gold Gate Release Corresponds Ball Location
33.5
17.5
Note: dimensions
0.20 35.0 31.75
0.20 0.25 0.35
Bottom View
35.0±0.2
Thermal Balls
1.27
Mold Compound
Substrate
0.65 0.05 SOLDERBALL 0.30 0.15 0.6±0.1 2.49 2.65
PowerPC 405GP Embedded Processor Data Sheet
Lists
PPC405GP embedded controller available 456-ball 413-ball E-PBGA package. 456-ball package available sizes-35 millimeters millimeters. 413-ball package size millimeters. this section there three tables that correlate external signals physical package (ball) which they appear. following table lists external signals alphabetical order shows ball number which signal appears. Multiplexed signals shown with default signal (following reset) brackets alternate signal brackets. page number listed gives page "Signal Functional Description" page where signals indicated interface group begin.
Signals Listed Alphabetically
Signal Name AVDD BankSel0 BankSel1 BankSel2 BankSel3 [BE0]PCIC0 [BE1]PCIC1 [BE2]PCIC2 [BE3]PCIC3 BusReq ClkEn0 ClkEn1 DMAAck0 DMAAck1 DMAAck2 DMAAck3 DMAReq0 DMAReq1 DMAReq2 DMAReq3 DQM0 DQM1 DQM2 DQM3 DQMCB DrvrInh1 DrvrInh2 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMCMDClk EMCMDIO[PHYMDIO] AC19 AB17 AC17 AB14 AB22 AB13 AA12 AC15 AB12 AC14 AC12 AC10 AB11
(Part
Interface Group System SDRAM Page
-Ball 456-Ball AB24 AC24 AD17 AF17 AE15 AC14 AB23 AB25 AC25 AC12 AC10 AC15 AE14 AF15 AF14 AD13 AF13 AF12 AE13 AD12 AD26
SDRAM
External MASTER Peripheral SDRAM SDRAM
External SLAVE Peripheral
External SLAVE Peripheral
SDRAM SDRAM System
SDRAM
Ethernet Ethernet
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name EMCTxD0 EMCTxD1 EMCTxD2 EMCTxD3 EMCTxEn EMCTxErr EOT0[TC0] EOT1[TC1] EOT2[TC2] EOT3[TC3] ExtAck ExtReq ExtReset
(Part
Interface Group Ethernet Ethernet Ethernet External SLAVE Peripheral External MASTER Peripheral External MASTER Peripheral External MASTER Peripheral Page
-Ball 456-Ball
A191 K11-K13 L11-L13 M11-M13 N11-N13 Ground P11-P13 Notes: Reserved 27mm package. 35mm package. 456-ball packages, L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, T11-T16 also thermal balls. 413-ball package, J11, J13, K11-K13, L11-L13, M11-N13, AA10 N11-N13, P11-P13, R11, also thermal balls. L11-L16 AC18 M11-M16 AC23 N11-N16 P11-P16 R11-R16 T11-T16 W261 AA26
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name
(Part
Interface Group Page
-Ball 456-Ball AB13 AB14 AB18 AB22 AC23 AD24 AE25 AF81 AF11 AF16 AF21 AF25 AF26 AB18 AA22 AA23 AA22 AF18 AA24 AB26 AA24
Ground Notes: Reserved 27mm package. 35mm package. 456-ball packages, L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, T11-T16 also thermal balls. 413-ball package, J11, J13, K11-K13, L11-L13, M11-N13, N11-N13, P11-P13, R11, also thermal balls.
Gnt[PCIReq0] GPIO1[TS1E] GPIO2[TS2E] GPIO3[TS1O] GPIO4[TS2O] GPIO5[TS3] GPIO6[TS4] GPIO7[TS5] GPIO8[TS6] GPIO9[TrcClk] [GPIO10]PerCS1 [GPIO11]PerCS2 [GPIO12]PerCS3 [GPIO13]PerCS4 [GPIO14]PerCS5 [GPIO15]PerCS6 [GPIO16]PerCS7 [GPIO17]IRQ0 [GPIO18]IRQ1 [GPIO19]IRQ2 [GPIO20]IRQ3 [GPIO21]IRQ4 [GPIO22]IRQ5 [GPIO23]IRQ6 Halt HoldAck HoldPri HoldReq IICSCL IICSDA IRQ0[GPIO17] IRQ1[GPIO18] IRQ2[GPIO19] IRQ3[GPIO20] IRQ4[GPIO21] IRQ5[GPIO22] IRQ6[GPIO23]
System
System
System
System External MASTER Peripheral External MASTER Peripheral External MASTER Peripheral Internal Peripheral Internal Peripheral
Interrupts
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name MemAddr0 MemAddr1 MemAddr2 MemAddr3 MemAddr4 MemAddr5 MemAddr6 MemAddr7 MemAddr8 MemAddr9 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut1 MemData0 MemData1 MemData2 MemData3 MemData4 MemData5 MemData6 MemData7 MemData8 MemData9 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 AA21 AC22 AA20 AB21 AA19 AB20 AC21 AB19 AC20 AA16 AA15 AB23 AB10 AA11
(Part
Interface Group Page
-Ball 456-Ball AE22 AC21 AE21 AD21 AF22 AE20 AC19 AE19 AD19 AC18 AF19 AD18 AC17 AC26 AA23 AC13 AE12 AD11 AC11 AF10 AE11 AD10
SDRAM
SDRAM
SDRAM
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name AC13
(Part
Interface Group Page
-Ball 456-Ball
OVDD
B171 C131 N241 Output driver voltage U251 Notes: Reserved 27mm package. OVDD 35mm package. AA22 AB19 AB20 AB21 AD141 AE101
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PCIAD0 PCIAD1 PCIAD2 PCIAD3 PCIAD4 PCIAD5 PCIAD6 PCIAD7 PCIAD8 PCIAD9 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCIC0[BE0] PCIC1[BE1] PCIC2[BE2] PCIC3[BE3] PCIClk PCIDevSel PCIFrame PCIGnt0[Req] PCIGnt1 PCIGnt2 PCIGnt3 PCIGnt4 PCIGnt5 PCIIDSel PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0[Gnt] PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr
(Part
Interface Group Page
-Ball 456-Ball
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PCIStop PCITRDY PerAddr0 PerAddr1 PerAddr2 PerAddr3 PerAddr4 PerAddr5 PerAddr6 PerAddr7 PerAddr8 PerAddr9 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0 PerCS1[GPIO10] PerCS2[GPIO11] PerCS3[GPIO12] PerCS4[GPIO13] PerCS5[GPIO14] PerCS6[GPIO15] PerCS7[GPIO16]
(Part
Interface Group Page
-Ball 456-Ball
External SLAVE Peripheral Note: PerAddr0 most significant (msb) this bus.
External SLAVE Peripheral External MASTER Peripheral
External SLAVE Peripheral
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PerData0 PerData1 PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerData8 PerData9 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 PerErr PerOE PerPar0 PerPar1 PerPar2 PerPar3 PerReady PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 [PerWE]PCIINT PHYCol PHYCrS PHYRxClk [PHYMDIO]EMCMDIO PHYRxD0 PHYRxD1 PHYRxD2 PHYRxD3 PHYRxDV PHYRxErr PHYTxClk
(Part
Interface Group Page
-Ball 456-Ball AA25 AF20 AD26 AE23 AF23 AC20 AD20
External SLAVE Peripheral Note: PerData0 most significant (msb) this bus.
External MASTER Peripheral External SLAVE Peripheral External SLAVE Peripheral External SLAVE Peripheral External SLAVE Peripheral External SLAVE Peripheral Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet
AA18
AA13
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name RcvrInh [Req]PCIGnt0
(Part
Interface Group SDRAM System Page
-Ball 456-Ball AF24 A192
Reserved
B173 C133 Other N243 Notes: 413-ball package) must tied OVDD GND. other reserved pins should left unconnected. U253 Reserved 27mm package. 35mm package. W262 Reserved 27mm package. OVDD 35mm package. AF41 AF82 AD143 AE103 AD25 AD22 AE24 AD23 AC22 AE26 AF18 AE18 AD15 AD16 AE16 Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral System System System JTAG External SLAVE Peripheral JTAG JTAG System System JTAG System JTAG
SysClk SysErr SysReset [TC0]EOT0 [TC1]EOT1 [TC2]EOT2 [TC3]EOT3 TestEn TmrClk [TrcClk]GPIO9 TRST [TS1E]GPIO1 [TS2E]GPIO2 [TS1O]GPIO3 [TS2O]GPIO4 [TS3]GPIO5 [TS4]GPIO6 [TS5]GPIO7 [TS6]GPIO8 UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx
AB18 AA17 AC16 AB15 AA14
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name [UART1_CTS]UART1_DSR UART1_DSR[UART1_CTS] [UART1_DTR]UART1_RTS UART1_RTS[UART1_DTR] UART1_Rx UART1_Tx UARTSerClk
(Part
Interface Group Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Page
-Ball 456-Ball
AC11
AE17 AB10 AB11 AB12 AB15 AB16 AB17 AC16
Logic voltage
AB16
SDRAM
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Ball Assignment-413-Ball Package
Ball Signal Name PerAddr4 PerAddr11 PerAddr15 PerAddr18 PerAddr21 DMAAck3 PerAddr25 PerAddr27 OVDD PerAddr28 PerAddr29 DMAAck2 DMAReq1 DMAAck0 PCIAD4 GPIO1[TS1E] GPIO3[TS1O] PCIAD10 PerWBE2 PerWBE1 PerAddr6 PerAddr9 PerAddr14 PerCS6[GPIO15] PerAddr19 PerAddr20 DMAReq2 PerAddr22 PerAddr23 PerAddr26 PerAddr30 DMAAck1 PCIAD1 PCIAD2 Ball Signal Name PCIAD0 PCIAD3 Reserved PCIReq2 PCIReq1 PCIAD11 PCIGnt2 PerPar3 EOT0[TC0] PerAddr3 PerAddr5 PerAddr8 DMAReq3 PerCS4[GPIO13] PerAddr16 PerAddr17 PerCS7[GPIO16] PerAddr2 PerAddr24 DMAReq0 PCIAD5 Reserved PCIAD6 PCIAD7 GPIO2[TS2E] PCIAD8 PHYTxClk PCIC1[BE1] PCIStop PerData27 PerData30 PerBLast PerWBE0 PerCS3[GPIO12] PerAddr7 PerAddr10 PerAddr12 PerAddr13 Ball
(Part
Ball Signal Name PCIINT[PerWE] OVDD PCIReq3 DrvrInh2 PCISErr PCIReq5 PCIAD16 PCIAD18 PerData16 PerData22 Reserved PerData31 PerR/W PerErr OVDD OVDD PerCS1[GPIO10] PCIAD13 OVDD OVDD SysClk DrvInh1 PCIDevSel PCIFrame PCIAD17 PCIGnt5 PerData13 PerData21 PerData25 PerData28 OVDD OVDD PerClk OVDD PerAddr1 OVDD SysReset
Signal Name PerCS5[GPIO14] OVDD PCIReq0[Gnt] PCIC0[BE0] PCIClk Reserved PCIAD9 PCIAD12 PCIAD15 PCIPErr PCIGnt3 PerData24 Reserved PerPar2 PerWBE3 TestEn PCIParity PCIIRDY PCIC2[BE2] PerData23 PerData29 PerPar1 PCIReq4 PCITRDY EMCTxD0 PerData19 PerData20 PerData26 EOT1[TC1] PerAddr0 PerCS2[GPIO11] OVDD PerCS0 PerAddr31
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Ball Assignment-413-Ball Package
Ball Signal Name OVDD OVDD EMCMDClk EMCTxEn EMCTxD2 PCIAD21 PerData12 PerData17 OVDD OVDD OVDD PerOE PCIReset OVDD EMCTxErr EMCTxD1 PCIGnt4 PCIAD23 PerData14 PerData18 PerPar0 PerReady TmrClk RcvInh Ball Signal Name AVDD PCIAD19 OVDD PerData11 PerData9 PerData7 PerData15 MemData20 PCIAD14 PCIAD25 PCIAD20 PCIAD22 PCIIDSel OVDD PerData6 UART1_Tx UART1_RTS [UART1_DTR] UART1_DSR [UART1_CTS] PCIAD28 Ball
(Part
Ball Signal Name BusReq PerData3 MemData31 MemData27 GPIO9[TrcClk] UART0_DTR OVDD OVDD MemData17 OVDD OVDD TRST EMCMDIO [PHYMDIO] PHYCrS Reserved PHYRxErr PCIAD26 PerData4 PerData2 EOT2[TC2] ExtAck UART0_CTS UART0_Tx OVDD MemData18 DQM0 OVDD IRQ5[GPIO22] IRQ0[GPIO17] PCIAD29 PCIGnt1 HoldReq EOT3[TC3]
Signal Name PCIAD24 PerData10 PerData5 HoldPri HoldAck OVDD UART0_DSR SysErr OVDD OVDD OVDD PCIAD27 PCIC3[BE3] PerData8 ExtReset PerData0 MemData28 OVDD OVDD MemData19 OVDD OVDD OVDD OVDD IRQ2[GPIO19] PHYRxDV PCIAD30 EMCTxD3
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Ball Assignment-413-Ball Package
Ball Signal Name ExtReq Reserved Reserved PCIAD31 PerData1 MemData29 MemData24 UART1_Rx MemClkOut0 IRQ4[GPIO21] Reserved PCIGnt0[Req] MemData30 MemData25 MemData23 MemData16 Reserved GPIO8[TS6] IICSDA MemData12 MemData10 OVDD UARTSerClk Ball AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 Signal Name MemAddr8 MemAddr7 PHYRxD3 PHYRxD2 PHYRxD1 ClkEn1 PHYCol IRQ3[GPIO20] IRQ1[GPIO18] MemData26 DQM3 MemData21 MemData14 MemData13 MemData11 MemData9 Reserved MemData8 MemData2 ECC0 PHYRxD0 UART0_Rx MemAddr12 MemAddr11 UART0_DCD PHYRxClk Ball AA19 AA20 AA21 AA22 AA23 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22
(Part
Ball AB23 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 Signal Name MemClkOut1 DQM2 GPIO7[TS5] GPIO5[TS3] DQM1 MemData3 MemData0 ECC6 ECC5 ECC4 OVDD ECC3 ECC1 UART0_RI BankSel2 BankSel0 MemAddr10 MemAddr6 MemAddr1
Signal Name MemAddr4 MemAddr2 MemAddr0 IRQ6[GPIO23] Halt MemData22 MemData15 IICSCL GPIO6[TS4] Reserved MemData7 MemData4 MemData6 MemData5 MemData1 ECC7 ECC2 DQMCB BankSel3 UART0_RTS BankSel1 GPIO4[TS2O] MemAddr9 MemAddr5 MemAddr3 ClkEn0
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Ball Assignment-456-Ball Package
Ball Signal Name PerAddr1 PerCS3[GPIO12] PerAddr8 DMAReq3 PerAddr15 PerCS6[GPIO15] PerAddr19 PerAddr25 PerAddr26 PerAddr28 PerAddr29 PCIAD0 PCIAD3 27/GND PCIAD7 GPIO3[TS1O] PCIAD9 PCIReq3 SysClk PerErr PerCS0 PerAddr2 PerAddr3 PerAddr5 PerAddr9 PerAddr12 PerCS4[GPIO13] PerCS5[GPIO14] PerCS7[GPIO16] PerAddr21 PerAddr24 Ball Signal Name DMAAck2 DMAAck1 PCIAD1 27/OVDD PCIAD6 PCIReq2 PCIClk PCIAD8 PCIAD11 PCIAD12 PCIReset PerR/W PerOE PerCS1[GPIO10] PerCS2[GPIO11] PerAddr6 PerAddr10 PerAddr13 PerAddr16 PerAddr18 DMAReq2 DMAAck3 27/OVDD PerAddr27 PerAddr30 DMAReq0 PCIAD2 PCIAD5 PCIReq0[Gnt] GPIO2[TS2E] PCIReq1 PCIAD13 PCIINT[PerWE] RcvInh PCIAD14 Ball
(Part
Ball Signal Name OVDD OVDD OVDD DrvrInh2 DrvInh1 PHYTxClk PCIParity PerBLast EOT0[TC0] PerWBE2 OVDD OVDD PCIGnt2 PCIC1[BE1] PCIAD15 PerData29 EOT1[TC1] PerPar2 PerPar1 OVDD OVDD PCIReq4 PCISErr PCIPErr PCITRDY 27/GND PerData30 PerData28 PerData31 OVDD OVDD
Signal Name PerWBE3 PerWBE0 PerPar0 PerAddr0 PerAddr4 PerAddr7 PerAddr11 PerAddr14 PerAddr17 PerAddr20 PerAddr23 PerAddr22 DMAReq1 PerAddr31 DMAAck0 PCIAD4 GPIO1[TS1E] PCIC0[BE0] Reserved PCIAD10 SysReset TmrClk AVDD TestEn PerPar3 PerWBE1 PerReady PerClk OVDD OVDD OVDD
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Ball Assignment-456-Ball Package
Ball Signal Name PCIStop EMCMDClk PCIDevSel PCIGnt3 PerData23 PerData26 PerData25 PerData27 PCIIRDY PCIFrame PCIReq5 EMCTxD0 PerData20 27/OVDD PerData22 PerData24 EMCTxEn PCIC2[BE2] EMCTxErr PCIAD16 PerData21 PerData18 PerData19 PCIAD17 EMCTxD2 EMCTxD1 Ball Signal Name PerData12 PerData17 PerData14 PerData15 PCIAD19 PCIGnt5 PCIAD18 PCIAD21 PerData11 PerData13 PerData10 PerData16 PCIGnt4 27/OVDD PCIAD20 PCIAD22 PerData9 PerData7 27/OVDD PerData5 Ball
(Part
Ball Signal Name PerData2 HoldAck PerData1 PerData0 PCIGnt0[Req] PHYRxErr 27/OVDD PCIAD29 HoldReq EOT2[TC2] MemData31 MemData29 IRQ1[GPIO18] PHYRxDV IRQ0[GPIO17] PCIAD31 MemData30 MemData27 MemData28 MemData26 OVDD OVDD PHYCrS IRQ2[GPIO19] IRQ3[GPIO20] 27/GND EOT3[TC3] MemData25 ExtAck ExtReq OVDD OVDD Reserved IRQ4[GPIO21] IRQ5[GPIO22] Reserved
Signal Name
PCIAD26 PCIAD23 EMCTxD3 PCIIDSel PerData8 PerData4 BusReq PerData6 PCIAD25 PCIAD24 PCIAD27 PCIC3[BE3] HoldPri ExtReset PerData3 PCIGnt1 PCIAD28 PCIAD30
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Ball Assignment-456-Ball Package
Ball AA22 AA23 AA24 AA25 AA26 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 Signal Name MemData23 DQM3 MemData22 OVDD OVDD MemClkOut1 IRQ6[GPIO23] PHYCol MemData24 MemData21 GPIO9[TrcClk] UART0_CTS OVDD OVDD OVDD OVDD OVDD OVDD ClkEn0 Ball AB26 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 Signal Name Halt UART1_Rx UART1_Tx UART1_DSR [UART1_CTS] MemData19 DQM2 GPIO8[TS6] MemData12 GPIO5[TS3] DQM1 MemData3 DQM0 MemData0 BankSel3 DQMCB MemAddr12 MemAddr9 MemAddr6 PHYRxD2 MemAddr1 ClkEn1 MemClkOut0 MemData20 UART1_RTS [UART1_DTR] MemData18 MemData17 IICSCL MemData13 MemData10 Ball AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17
(Part
Ball AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal Name UART0_DCD MemAddr7 MemAddr5 MemAddr2 MemAddr0 PHYRxD0 TRST UART0_DTR UART0_Tx Reserved GPIO7[TS5] MemData11 27/GND MemData7 MemData4 ECC5 ECC4 ECC2 ECC1 BankSel1 GPIO4[TS2O] MemAddr10 PHYRxClk MemAddr4 PHYRxD1
Signal Name MemData8 MemData6 MemData2 ECC7 ECC3 27/OVDD UART0_RI UART0_RTS BankSel0 MemAddr11 MemAddr8 PHYRxD3 MemAddr3 SysErr EMCMDIO [PHYMDIO] UART0_DSR MemData16 MemData15 MemData14 IICSDA GPIO6[TS4] MemData9 27/OVDD MemData5 MemData1 ECC6 ECC0 BankSel2 UART0_Rx UARTSerClk
PowerPC 405GP Embedded Processor Data Sheet
Signal List
table following table provides summary number package pins associated with each functional interface group.
Summary
Pins Group
Ethernet SDRAM External peripheral External master Internal peripheral Interrupts JTAG System Total Signal Pins OVDD Thermal (and Gnd) Reserved Total Pins
413-Ball package
456-Ball Package
27mm
table "Signal Functional Description" page each external signal listed along with short description signal function. Some signals multiplexed same package (ball) that used different functions. Multiplexed signals shown default signal followed secondary signal square brackets (for example, GPIO1[TS1E]) signals described consecutively within each functional description. Active-low signals (for example, RAS) marked with overline. expected that single application particular will always programmed serve same function. flexibility multiplexing allows single chip offer richer selection than would otherwise possible. addition multiplexing, many pins also multi-purpose. example, peripheral controller address pins used outputs PPC405GP broadcast address external slave devices when PPC405GP control external bus. When, during course normal chip operation, external master gains ownership external bus, these same pins used inputs which driven external master received PPC405GP. this example, pins also bidirectional, serving both inputs outputs. group pins used strapped inputs during system reset. These pins function strapped inputs only during reset used other functions during normal operation (see "Strapping" page 52). Note that these multiplexed pins since function pins programmable. following table lists signals provided PPC405GP. Please refer "Signals Listed Alphabetically" page number which each signal assigned.
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Description Type
Notes
Interface
PCIAD31:0 Address/Data Bus. Multiplexed address data (bus command) Byte enable parity. Parity even across PCIAD0:31 PCIC0:3[BE0:3]. PCIParity valid cycle after either address data phase. device that drove PCIAD0:31 responsible driving PCIParity next clock. PCIFrame driven current master indicate beginning duration access. PCIIRDY driven current master. Assertion PCIIRDY indicates that initiator ready transfer data. target current transaction drives PCITRDY. Assertion PCITRDY indicates that target ready transfer data. target current transaction assert PCIStop indicate requesting master that wants current transaction. PCIDevSel driven target current transaction. target asserts PCIDevSel when decoded address command encoding claims transaction. PCIIDSel used during configuration cycles select slave interface configuration PCISErr used reporting address parity errors catastrophic failures detected target. PCIPErr used reporting data parity errors transactions. PCIPErr driven active device receiving PCIAD0:31, PCIC0:3[BE0:3], PCIParity, clocks following data which parity detected. PCIClk used asynchronous clock when asynch mode. unused when interface operated synchronously with bus. specific reset interrupt. Open-drain output (two states; open circuit) Peripheral write enable. when four PerWBE0:3 write byte enables low. Multipurpose signal, used PCIReq0 when internal arbiter used, when external arbiter used. tolerant 3.3V tolerant 3.3V
PCIC0:3[BE0:3]
PCIParity
tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V
PCIFrame PCIIRDY
PCITRDY
PCIStop
PCIDevSel
PCIIDSel PCISErr
PCIPErr
PCIClk
tolerant 3.3V tolerant 3.3V tolerant 3.3V tolerant 3.3V
PCIReset
PCIINT[PerWE]
PCIReq0[Gnt]
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name PCIReq1:5 Description Used PCIReq1:5 input when internal arbiter used Gnt0 when internal arbiter used when external arbiter used Used PCIGnt1:5 output when internal arbiter used. Type tolerant 3.3V tolerant 3.3V tolerant 3.3V
Notes
PCIGnt0[Req]
PCIGnt1:5
Ethernet Interface
PHYRxD3:0 EMCTxD3:0 PHYRxErr PHYRxClk Received data. This nibble wide from PHY. data synchronous with PHYRxClk. Transmit data. nibble wide data towards net. data synchronous PHYTxClk. Receive Error. This signal comes from synchronous PHYRxClk. Receiver Medium clock. This signal generated PHY. Receive Data Valid. Data Data valid when this signal activated. Deassertion this signal indicates frame reception. Carrier Sense signal from PHY. This asynchronous signal. Transmit Error. This signal generated Ethernet controller, connected synchronous with PHYTxClk. informs that error detected. Transmit data Enabled. This signal driven EMAC2 PHY. Data valid during active state this signal. Deassertion this signal indicates frame transmission. This signal synchronous PHYTxClk. This clock comes from Medium Transmit clock. Collision signal from PHY. This asynchronous signal. Management Data Clock. MDClk sourced PHY. This clock period 400ns, adjustable EMAC0_STACR[OPBC]. Management information transferred synchronously with respect this clock. Management Data Input/Output bidirectional signal between Ethernet controller PHY. used transfer control status information. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PHYRxDV
PHYCrS
EMCTxErr
EMCTxEn
tolerant 3.3V LVTTL tolerant LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PHYTxClk PHYCol
EMCMDClk
EMCMDIO[PHYMDIO]
tolerant 3.3V LVTTL
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Description Type
Notes
SDRAM Interface
Memory data Notes: MemData0 most significant (msb). MemData31 least significant (lsb). Memory address Notes: MemAddr12 most significant (msb). MemAddr0 least significant (lsb). Bank Address supporting internal banks Address Strobe Column Address Strobe byte lanes (MemData0:7), (MemData8:15), (MemData16:23), (MemData24:31) check bits check bits Select four external SDRAM banks Write Enable SDRAM Clock Enable copies SDRAM clock allows, some cases, glueless SDRAM attach without requiring this signal repowered zero-delay buffer.
MemData0:31
3.3V LVTTL
MemAddr12:0
3.3V LVTTL
BA1:0
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
DQM0:3
3.3V LVTTL
DQMCB ECC0:7 BankSel0:3 ClkEn0:1 MemClkOut0:1
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
External SLAVE Peripheral Interface
Peripheral data used PPC405GP when external master mode, otherwise used external master Note: PerData0 most significant (msb) this bus. Peripheral address used PPC405GP when external master mode, otherwise used external master. Note: PerAddr0 most significant (msb) this bus. Peripheral byte parity signals outputs, these pins byte-enables which valid entire cycle write-byte-enables which valid each byte each data transfer, allowing partial word transactions. outputs, pins used either peripheral controller controller depending upon type transfer involved. Used inputs when external master owns external interface tolerant 3.3V LVTTL
PerData0:31
PerAddr0:31
tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PerPar0:3
PerWBE0:3
tolerant 3.3V LVTTL
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name PerCS0 Description Peripheral chip select bank Seven additional peripheral chip selects General Purpose access this function, software must toggle bit. Used either peripheral controller controller depending upon type transfer involved. When PPC405GP master, enables selected SDRAMs drive bus. Used PPC405GP when external master mode, output either peripheral controller controller depending upon type transfer involved. High indicates read from memory, indicates write memory. Otherwise used external master input indicate direction transfer. Used peripheral slave indicate ready transfer data. Used PPC405GP when external master mode, otherwise used external master. Indicates last transfer memory access. DMAReq0:3 used slave peripherals indicate they prepared transfer data. DMAAck0:3 used PPC405GP indicate that data transfers have occurred. Transfer/Terminal Count Type tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Notes
PerCS1:7[GPIO10:16]
O[I/O]
PerOE
tolerant 3.3V LVTTL
PerR/W
tolerant 3.3V LVTTL
PerReady
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PerBLast
DMAReq0:3 DMAAck0:3 EOT0:3[TC0:3]
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Description Type
Notes
External MASTER Peripheral Interface
PerClk ExtReset HoldReq HoldAck ExtReq ExtAck HoldPri BusReq PerErr Peripheral clock used external master synchronous peripheral slaves Peripheral reset used external master synchronous peripheral slaves Hold Request, used external master request ownership peripheral Hold Acknowledge, used PPC405GP transfer ownership peripheral external master ExtReq used external master indicate prepared transfer data ExtAck used PPC405GP indicate that data transfer occurred. Used external master indicate priority given transfer high, low) Used when PPC405GP needs regain control peripheral interface from external Master Used input. Used record external Master errors external slave peripheral errors tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Internal Peripheral Interface
UARTSerClk Serial Clock used provide alternative clock internally generated serial clock. Used cases where allowable internally generated baud rates satisfactory. This input individually connected either UART. UART0 Serial Data UART0 Serial Data UART0 Data Carrier Detect UART0 Data Ready UART0 Clear Send UART0 Data Terminal Ready UART0 Request Send UART0 Ring Indicator tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RTS UART0_RI
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name UART1_Rx UART1_Tx UART1 Serial Data UART1 Serial Data UART1 Data Ready UART1 Clear Send. access this function, software must toggle bit. UART1 Request Send UART1 Data Terminal Ready. access this function, software must toggle bit. Serial Clock Serial Data Description Type tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Notes
UART1_DSR [UART1_CTS]
UART1_RTS [UART1_DTR]
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
IICSCL IICSDA
Interrupts Interface
Interrupt requests General Purpose I/O. access this function, software must toggle bit.] tolerant 3.3V LVTTL
IRQ0:6[GPIO17:23]
I[I/O]
JTAG Interface
Test data JTAG test mode select Test data JTAG test clock frequency this input, ideally, range from maximum clock frequency. achievable maximum will less, function system implementation characteristics. JTAG reset tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
TRST
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Description Type
Notes
System Interface
SysClk Main system clock input Main system reset. External logic drive this bidirectional (minimum cycles) initiate system reset. PPC405GP then holds output 8192 cycles reset internal external logic connected SysReset. system reset also initiated software. Implemented open-drain (two output states; open circuit). Clean voltage input when Machine Check generated. Halt from external debugger. General Purpose Even Trace execution status.To access this function, software must toggle bit. General Purpose Trace execution status. access this function, software must toggle bit. General Purpose GPIO5:8[TS3:6] Trace status. access this function, software must toggle bit. General Purpose Trace interface clock. toggling signal that always half core frequency. access this function, software must toggle bit. Test Enable. Used only manufacturing tests. Pull down normal operation. Receiver Inhibit. Used only manufacturing tests. Pull normal operation. Driver Inhibit Used only manufacturing tests. Pull normal operation. This input must toggle rate less than half core frequency (less than 100MHz most cases). most cases this input toggles much slower 1MHz 10MHz range). I/O[O] tolerant 3.3V LVTTL tolerant 3.3V LVTTL
SysReset
tolerant 3.3V LVTTL
AVDD SysErr Halt
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
GPIO1[TS1E] GPIO2[TS2E]
I/O[O]
GPIO3[TS1O] GPIO4[TS2O]
I/O[O]
tolerant 3.3V LVTTL
(A22, AF18), (AF18 only)
GPIO9[TrcClk]
I/O[O]
tolerant 3.3V LVTTL
TestEn RcvrInh DrvrInh1:2
3.3V LVTTL Pull-Down tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
TmrClk
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part Multiplexed signals shown brackets following first signal name assigned each multiplexed ball. Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Description Type
Notes
Ground pins
Ground Note: 456-ball packages, L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, T11-T16 also thermal balls. 413-ball package, J11, J13, K11-K13, L11-L13, M11-N13, N11-N13, P11-P13, R11, also thermal balls.
OVDD pins
OVDD Output driver voltage-3.3V
pins
Logic voltage-2.5V
Other pins
Reserved Reserved-Except 413-ball package) AF4, connect signals, voltage, ground these pins. 413-ball package) must tied OVDD GND.
PowerPC 405GP Embedded Processor Data Sheet
Absolute Maximum Ratings
absolute maximum ratings below stress ratings only. Operation beyond these maximum ratings cause permanent damage device
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface) Supply Voltage Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Symbol OVDD AVDD TSTG Value +120 Unit
Package Thermal Specifications
PPC405GP designed operate within case temperature range -40°C 120°C. Thermal resistance values E-PBGA packages convection environment follows: Airflow ft/min (m/sec)
35mm, 456-balls-Junction-to-Case 35mm, 456-balls-Case-to-Ambient1 27mm, 456-balls-Junction-to-Case 27mm, 456-balls-Case-to-Ambient1 25mm, 413-balls-Junction-to-Case 25mm, 413-balls-Case-to-Ambient1 (0.51) (1.02) °C/W °C/W °C/W °C/W °C/W °C/W
Package-Thermal Resistance
Symbol
Unit
Notes: chip mounted JEDEC 2S2P card without heat sink. chip mounted card with least signal power planes, following relationships exist: Case temperature, measured center case surface with device soldered circuit board. TCMax TJMax where TJMax maximum junction temperature power consumption. where ambient temperature power consumption.
PowerPC 405GP Embedded Processor Data Sheet
Recommended Operating Conditions
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability. Notes: drivers meet specifications. recommended that your system design derive supply from OVDD supply minimize possibility being present absence OVDD.
Parameter Logic Supply Voltage Supply Voltage Supply Voltage Input Logic High (3.3V LVTTL receivers) Input Logic High (5.0V LVTTL receivers) Input Logic Output Logic High Output Logic Input Leakage Current pull-up pull-down) Input Leakage Current PullDown Input Leakage Current Pull-Up Input Allowable Overshoot (3.3V LVTTL receivers) Input Allowable Overshoot (5.0V LVTTL receivers) Input Allowable Undershoot (3.3V 5.0V receivers) Output Allowable Overshoot (3.3V 5.0V drivers) Output Allowable Undershoot (3.3V 5.0V drivers) Case Temperature Symbol OVDD AVDD IIL1 IIL2 IIL3 VIMAO3 VIMAO5 VIMAU VOMAO VOMAU3 Minimum (LPDL) Typical Maximum OVDD OVDD (MPUL) (MPUL) OVDD Unit Notes
-250 (LPDL)
OVDD
PowerPC 405GP Embedded Processor Data Sheet
Capacitance
Parameter Input Capacitance Group (3.3V LVTTL //O) Input Capacitance Group tolerant LVTTL I/O) Input Capacitance Group (PCI I/O) Input Capacitance Group only pins) Symbol CIN1 CIN2 CIN3 CIN4 Maximum 0.75 Unit Notes
Electrical Characteristics
Parameter Active Operating Current (VDD)-200MHz Active Operating Current (VDD)-266MHz Active Operating Current (OVDD)-200MHz Active Operating Current (OVDD)-266MHz Voltage (AVDD) Input current Active Operating Power-200MHz Active Operating Power-266MHz Symbol IODD IODD VPLL IPLL Minimum Typical Maximum 2.01 2.61 Unit
Notes: 2.7V, OVDD 85°C, CPU/PLB/OPB/PCI 266/133/66/33MHz. Measurements taken across process (w/c silicon silicon), while running instruction designed simulate maximum environment.
Test Conditions Clock timing switching characteristics specified accordance with operating conditions shown table "Recommended Operating Conditions." specifications characterized OVDD 3.14V 100°C with 50pF test load (CL) shown figure right.
Output 50pf signals
PowerPC 405GP Embedded Processor Data Sheet
SysClk MemClk Timing
Symbol SysClk Input MemClk Output MemClk clock output frequency-200MHz MemClk clock period-200MHz MemClk clock output frequency-266MHz MemClk clock period-266MHz Clock output high time Clock output time nominal period nominal period nominal period nominal period SysClk clock input frequency SysClk clock period Clock edge stability Clock input high time Clock input time 66.6 0.15 nominal period nominal period nominal period nominal period Parameter Units
Note: Input slew rate 2V/ns
Timing Waveform
2.0V 1.5V 0.8V
PowerPC 405GP Embedded Processor Data Sheet
Spread Spectrum Clocking
Care must taken when using spread spectrum clock generator (SSCG) with PPC405GP. This controller uses clock generation inside chip. accuracy with which follows SSCG referred tracking skew. bandwidth phase angle determine much tracking skew there between SSCG given frequency deviation modulation frequency. When using SSCG with PPC405GP following conditions must met: frequency deviation must violate minimum clock cycle time. Therefore, when operating PPC405GP with more internal clocks their maximum supported frequency, SSCG only lower frequency. maximum frequency deviation cannot exceed -3%, modulation frequency cannot exceed 40kHz. some cases, on-board PPC405GP peripherals impose more stringent requirements (see Note Peripheral Clock logic that synchronous peripheral since this clock tracks modulation. SDRAM MemClk since also tracks modulation. Notes: clock specification 66MHz allows maximum frequency deviation modulation between 30kHz 33kHz. asynchronous mode unaffected. serial port baud rates synchronous modulated clock. serial port tolerance approximately 1.5% baud rate before framing errors begin occur. 1.5% tolerance assumes that connected device running precise baud rates. external serial clock used baud rate unaffected modulation Ethernet operation unaffected. operation unaffected. Caution: system designer ensure that SSCG used with PPC405GP meets above requirements does adversely affect other aspects system.
PowerPC 405GP Embedded Processor Data Sheet
Peripheral Interface Clock Timings
Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) Clock frequency (synchronous mode) Clock period (synchronous mode Note PCIClk input high time PCIClk input time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output time PHYTxClk input frequency PHYTxClk period PHYTxClk input high time PHYTxClk input time PHYRxClk input frequency PHYRxClk period PHYRxClk input high time PHYRxClk input time PerClk output frequency-200MHz (for external master synchronous slaves) PerClk period-200MHz PerClk output frequency-266MHz (for external master synchronous slaves) PerClk period-266MHz PerClk output high time PerClk output time UARTSerClk input frequency (Note UARTSerClk period UARTSerClk input high time UARTSerClk input time TmrClk input frequency-200MHz TmrClk period-200MHz TmrClk input frequency-266MHz TmrClk period-266MHz TmrClk input high time TmrClk input time Note nominal period nominal period nominal period nominal period nominal period nominal period nominal period nominal period 2TOPB+2 TOPB+1 TOPB+1 nominal period nominal period Note nominal period nominal period nominal period nominal period 1000/(2TOPB+2ns) nominal period nominal period Units
Notes: asynchronous mode minimum PCIClk frequency Clock. Refer PPC405GP User's Manual more information. synchronous mode clock derived from SysClk PCIClk input unused. TOPB period clock. internal clock runs frequency clock. maximum clock frequency 200MHz parts 66MHz.for 266MHz parts.
PowerPC 405GP Embedded Processor Data Sheet
Input Setup Hold Waveform
SysClk 1.5V Inputs 1.5V Data D0:31 (Inputs)
Valid
1.5V
Valid Valid
Output Delay Float Timing Waveform
SysClk
1.5V
Outputs
1.5V Valid
Outputs
1.5V
PowerPC 405GP Embedded Processor Data Sheet
Note: following Specifications tables timing value means "not applicable." timing value means "don't care."
Specifications-All (Part Notes: timings asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz. Ethernet interface meets timing requirements defined IEEE 802.3 standard.
Input (ns) Signal Setup Time Hold Time (minimum) (minimum) Output (ns) Valid Delay Hold Time (maximum) (minimum) 50pF load 50pF load Output Current (mA) (maximum) (minimum) Clock Notes
Interface
PCIAD31:0 PCIC3:0[BE3:0] PCIClk PCIDevSel PCIFrame PCIGnt0[Req] PCIGnt1:5 PCIIDSel PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0[Gnt] PCIReq1:5 PCIReset PCISErr PCIStop PCITRDY 12.3 12.3 12.3 12.3 12.3 12.3 12.3 12.3 12.3 12.3 12.3 12.3 12.3 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 EMCMDClk PHYTX PHYTX PHYTX PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk async async
async async async async async
Ethernet Interface
EMCMDClk EMCMDIO[PHYMDIO] EMCTxD3:0 EMCTxEn EMCTxErr PHYCol PHYCrS PHYRxClk PHYRxD3:0 PHYRxDV PHYRxErr PHYTxClk settable clock clock period 10ns period
PHYRX PHYRX PHYRX
PowerPC 405GP Embedded Processor Data Sheet
Specifications-All (Part Notes: timings asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz. Ethernet interface meets timing requirements defined IEEE 802.3 standard.
Input (ns) Signal Setup Time Hold Time (minimum) (minimum) Output (ns) Valid Delay Hold Time (maximum) (minimum) 50pF load 50pF load Output Current (mA) (maximum) (minimum) Clock Notes
Internal Peripheral Interface
IICSCL IICSDA UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_RTS [UART1_DTR] UART1_DSR [UART1_CTS] UART1_Rx UART1_Tx UARTSerClk async async async async async
Interrupts Interface
IRQ0:6[GPIO17:23] JTAG Interface TRST
System Interface
DrvrInh1:2 GPIO1[TS1E] GPIO2[TS2E] GPIO3[TS1O] GPIO4[TS2O] GPIO5[TS3] GPIO6[TS4] GPIO7[TS5] GPIO8[TS6] GPIO9[TrcClk] Halt RcvrInh SysClk SysErr SysReset TestEn TmrClk
async
async async async async
PowerPC 405GP Embedded Processor Data Sheet
Specifications-200MHz (Revision Preliminary)
Notes: two-cycle SDRAM command interface driven cycle used cycle Output times table cycle SDRAM output timing relative rising edge internal clock, which integral multiple risingedge aligned with SysClk. Therefore, SDRAM output timings table shown relative SysClk. Timings shown lumped 50pF load, however interface been verified PC100-compliant operation using transmission line circuit analysis. SDRAM CLK0:1 rising edge package precedes internal clock approximately 0.5ns typical clock network lumped 10pF load. PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns.
Input (ns) Signal Setup Time Hold Time (minimum) (minimum) Output (ns) Valid Delay Hold Time (maximum) (minimum) 50pF load 50pF load Output Current (mA) (maximum) (minimum) Clock Notes
SDRAM Interface
BA1:0 BankSel3:0 ClkEn0:1 DQM3:0 DQMCB ECC7:0 MemAddr12:0 MemClkOut0:1 MemData31:0 DMAAck0:3 DMAReq0:3 EOT0:3[TC0:3] PerAddr0:31 PerBLast PerCS0 PerCS1:7[GPIO10:16] PerData0:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq PerClk PerErr SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk
External SLAVE Peripheral Interface
External MASTER Peripheral Interface
PowerPC 405GP Embedded Processor Data Sheet
Specifications-266MHz (Preliminary)
Notes: two-cycle SDRAM command interface driven cycle used cycle Output times table cycle SDRAM output timing relative rising edge internal clock, which integral multiple risingedge aligned with SysClk. Therefore, SDRAM output timings table shown relative SysClk. Timings shown lumped 50pF load, however interface been verified PC100-compliant operation using transmission line circuit analysis. SDRAM CLK0:1 rising edge package precedes internal clock approximately 0.5ns typical clock network lumped 10pF load. PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns.
Input (ns) Signal Setup Time Hold Time (minimum) (minimum) Output (ns) Valid Delay Hold Time (maximum) (minimum) 50pF load 50pF load Output Current (mA) (maximum) (minimum) Clock Notes
SDRAM Interface
BA1:0 BankSe3:0 ClkEn0:1 DQM3:0 DQMCB ECC7:0 MemAddr12:0 MemClkOut0:1 MemData31:0 DMAAck0:3 DMAReq0:3 EOT0:3[TC0:3] PerAddr0:31 PerBLast PerCS0 PerCS1:7[GPIO10:16] PerData0:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq PerClk PerErr SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk
External SLAVE Peripheral Interface
External MASTER Peripheral Interface
PowerPC 405GP Embedded Processor Data Sheet
Strapping
While SysReset input (system reset), state certain pins read enable default initial conditions prior PPC405GP start-up. actual capture instant nearest reference clock edge before deassertion reset. These pins must strapped using external pull-up (logical pull-down (logical resistors select desired default conditions. These pins strap functions only during reset. They used other signals during normal operation. following table lists strapping pins along with their functions strapping options. 456-ball package listed first (for example, AF3), followed corresponding 413-ball package (for example, U8), which appears AF3/U8.
Strapping Assignments
Function Tuning choice choice choice Note. Option AF3/U8 Choice TUNE[5:0] 010001 Choice TUNE[5:0] 010010 Choice TUNE[5:0] 010011 Choice TUNE[5:0] 010100 Choice TUNE[5:0] 010101 Choice TUNE[5:0] 010110 Choice TUNE[5:0] 010111 Choice TUNE[5:0] 100100 Forward Divider Bypass mode Divide Divide Divide Feedback Divider Divide Divide Divide Divide Divider from Divide Divide Divide Divide Divider from Divide Divide Divide Divide D16/A17 B14/A15 P25/R23 L25/K21 Ball Strapping AF2/T8 B15/B14 C12/A8 L24/J22 J26/F22 AD16/AB15
PowerPC 405GP Embedded Processor Data Sheet
Strapping Assignments (Continued)
Function Divider from Divide Divide Divide Divide External Divider from Divide Divide Divide Divide Width 8-bit 16-bit 32-bit Reserved Location PPC405GP Peripheral Attach PPC405GP Attach Asynchronous Mode Enable Synchronous Mode Asynchronous Mode Arbiter Enable Internal Arbiter Disabled Internal Arbiter Enabled Option D18/A20 K25/K20 AC2/N3 U2/P4 Y3/U4 AF18/AB18 Ball Strapping C20/C19 K23/J21 AD2/N7
Note: tune bits adjust parameters that control jitter. recommended values minimize jitter implemented PPC405GP. These bits shown information only; require modification except special clocking circumstances such spread spectrum clocking. details Spread Spectrum Clock Generators (SSCGs) with PPC405GP, visit technical documents area PowerPC site.
PowerPC 405GP Embedded Processor Data Sheet
Copyright International Business Machines Corporation 1999, 2001
Rights Reserved Printed United States America, March 2001 following trademarks International Business Machines Corporation United States, other countries, both: Blue Logic CoreConnect Logo CodePack PowerPC
Other company, product, service names trademarks service marks others. While information contained herein believed accurate, such information preliminary, should relied upon accuracy completeness, representations warranties accuracy completeness made. information contained this document subject change without notice. products described this document intended implantation other life support applications where malfunction result injury death persons. information contained this document does affect change product specifications warranties. Nothing this document shall operate express implied license indemnity under intellectual property rights third parties. information contained this document obtained specific environments, presented illustration. results obtained other operating environments vary. INFORMATION CONTAINED THIS DOCUMENT PROVIDED BASIS. event will liable damages arising directly indirectly from information contained this document. Microelectronics Division 1580 Route Hopewell Junction, 12533-6351 home page www.ibm.com Microelectronics Division home page www.chips.ibm.com
SA14-2521-05

PowerPC405 32-bit RISC processor core operating PC-100 Synchronous DRA

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