SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREE
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M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
REJ03B0134-0100Z Rev.1.00 2002
DESCRIPTION
M37221M4H/M6H/M8H/MAH-XXXSP/FP single-chip microcomputers designed with CMOS silicon gate technology. They have OSD, I2C-BUS interface, PWM, making them perfect channel selection system. M37221EASP/FP have built-in PROM that written electrically.
function Display characters characters lines lines more displayed software) Kinds characters kinds Character display area dots Kinds character sizes kinds Kinds character colors colors Coloring unit character, character background, raster Display position Horizontal: levels Vertical: levels Attribute border
FEATURES
basic instructions size bytes (M37221M4H-XXXSP/FP) bytes (M37221M6H-XXXSP/FP) bytes (M37221M8H-XXXSP/FP) bytes (M37221MAH-XXXSP/FP, M37221EASP/FP) bytes (M37221M4H-XXXSP/FP) bytes (M37221M6H-XXXSP/FP) bytes (M37221M8H-XXXSP/FP) bytes (M37221MAH-XXXSP/FP, M37221EASP/FP) (ROM correction memory included) minimum instruction execution time oscillation frequency) Power source voltage Subroutine nesting maximum levels (M37221M4H/M6H-XXXSP/FP) maximum levels (M37221M8H/MAH-XXXSP/FP, M37221EASP/FP) Interrupts types, vectors 8-bit timers Programmable ports (Ports P30-P32 Input ports (Ports P33, P34) Output ports (Ports P52-P55) drive ports Serial 8-bit channel Multi-master I2C-BUS interface systems) comparator (6-bit resolution) channels converter (6-bit resolution) Note: Only M37221EASP/FP converter.
Memory Number
APPLICATION
output circuit 14-bit 8-bit dissipation High-speed mode VCC=5.5V, oscillation frequency, correction function vectors
Power
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M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP
TABLE CONTENTS
DESCRIPTION FEATURES APPLICATION CONFIGURATION FUNCTIONAL BLOCK DIAGRAM PERFORMANCE OVERVIEW DESCRIPTION FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) MEMORY INTERRUPTS TIMERS SERIAL MULTI-MASTER I2C-BUS INTERFACE OUTPUT FUNCTION COMPARATOR CONVERTER 8.10 CORRECTION FUNCTION 8.11 FUNCTIONS 8.11.1 Display Position 8.11.2 Character Size 8.11.3 Clock 8.11.4 Memory 8.11.5 Color Register 8.11.6 Border 8.11.7 Multiline Display 8.11.8 Output Control 8.11.9 Raster Coloring Function 8.12 SOFTWARE RUNAWAY DETECT FUNCTION 8.13 RESET CIRCUIT 8.14 CLOCK GENERATING CIRCUIT 8.15 DISPLAY OSCILLATION CIRCUIT 8.16 AUTO-CLEAR CIRCUIT 8.17 ADDRESSING MODE 8.18 MACHINE INSTRUCTIONS PROGRAMMING NOTES ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRIC CHARACTERISTICS COMPARISON CHARACTERISTICS CONVERSION CHARACTERISTICS MULTI-MASTER I2C-BUS LINE CHARACTERISTICS PROM PROGRAMMING METHOD DATA REQUIRED MASK ORDERS TIME PROM VERSION M37221EASP/FP MARKING APPENDIX PACKAGE OUTLINE
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M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP
CONFIGURATION
HSYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 CNVSS XOUT
P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5 P31/A-D6 RESET OSC1/P33 OSC2/P34
Outline 42P4B
Fig. Configuration (Top View)
M37221M4H/M6H/M8H/MAH-XXXSP
P50/HSYNC P51/VSYNC P00/PWM0
P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5
P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1
M37221M4H/M6H/M8H/MAH-XXXFP
P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2
CNVSS XOUT
P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5 P31/A-D6 RESET OSC1/P33 OSC2/P34
Outline 42P2R-A/E
Fig. Configuration (Top View)
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HSYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 CNVSS XOUT
P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5/DA1 P31/A-D6/DA2 RESET OSC1/P33 OSC2/P34
M37221EASP
Outline 42P4B
Fig. Configuration (Top View)
P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 CNVSS XOUT
P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3
M37221EAFP
P16/A-D2 P17/A-D3 P30/A-D5/DA1 P31/A-D6/DA2
RESET OSC1/P33 OSC2/P34
Outline 42P2R-A/E
Fig. Configuration (Top View)
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Clock input Clock output XOUT Timing output CNVSS
Reset input RESET
Input ports P33, Clock input display Clock output display OSC1 OSC2
SCLK SOUT
PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
INT3
INT2 INT1
OUT2
OUT1
port
port
port
ports P30-P32
Output ports P52-P55
Notes Only M37221EASP/FP converter.
VSYNC HSYNC
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TIM2 TIM3
Clock generating circuit Timer count source selection circuit
Fig. Functional Block Diagram M37221
Program counter
FUNCTIONAL BLOCK DIAGRAM
M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP
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Timer Timer Timer Control signal Instruction decoder Instruction register circuit Timer Index register Index register Stack pointer
14-bit circuit
Data
Program counter
Address
8-bit arithmetic logical unit
Accumulator
Processor status register
comparator Multi-master 2C-BUS interface
converter (See note)
SI/O(8)
8-bit circuit correction function
M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP
PERFORMANCE OVERVIEW
Table Performance Overview Parameter Number basic instructions Number basic instructions Instruction execution time Memory size M37221M4H-XXXSP/FP M37221M6H-XXXSP/FP M37221M8H-XXXSP/FP M37221MAH-XXXSP/FP, M37221EASP/FP M37221M4H-XXXSP/FP M37221M6H-XXXSP/FP M37221M8H-XXXSP/FP M37221MAH-XXXSP/FP, M37221EASP/FP tInput/Output ports P10, P15-P17 P11-P14 P20, P22-P27 P30, P33, P52-P55 Serial Multi-master I2C-BUS interface comparator converter output circuit Timers correction function Subroutine nesting M37221M4H/M6H-XXXSP/FP M37221M8H/MAH-XXXSP/FP, M37221EASP/FP Interrupt Input Output (the minimum instruction execution time, oscillation quency) (maximum) bytes bytes bytes bytes bytes (ROM correction memory included) bytes (ROM correction memory included) bytes (ROM correction memory included) bytes (ROM correction memory included) bytes bytes 8-bit (N-channel open-drain output structure, used output pins, input pins, input pin) 4-bit (CMOS input/output structure, used output pin, input pins, input pin) 4-bit (CMOS input/output structure, used multi-master I2CBUS interface) 2-bit (CMOS input/output N-channel open-drain output structure, used serial pins) 6-bit (CMOS input/output structure, used serial input pin, timer external clock input pins) 2-bit (CMOS input/output N-channel open-drain output structure, used input pins, conversion output pins <Only M37221EASP/FP>) 1-bit (N-channel open-drain output structure) 2-bit (can used display clock pins) 4-bit (CMOS output structure, used output pins) 8-bit systems) channels (6-bit resolution) (6-bit resolution) (Only M37221EASP/FP) 14-bit 8-bit 8-bit timer vectors levels (maximum) levels (maximum) sources> external interrupt Internal timer interrupt Serial interrupt interrupt Multi-master I2C-BUS interface interrupt f(XIN)/4096 interrupt VSYNC interrupt interrupt Reset built-in circuits (externally connected ceramic resonator quartzcrystal oscillator) Functions
Clock generating circuit
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Table Performance Overview (continued) Parameter display function Number display characters structure Kinds characters Kinds character sizes Character font coloring Display position Power source voltage Power dissipation stop mode Operating temperature range Device structure Package M37221M4H/M6H/M8H/MAH-XXXSP, M37221EASP M37221M4H/M6H/M8H/MAH-XXXFP, M37221EAFP characters lines dots kinds kinds screen: kinds (per character unit) Horizontal: levels, Vertical: levels typ. oscillation frequency f(XIN) MHz, fOSC MHz) typ. oscillation frequency f(XIN) MHz) 1.65 (maximum) CMOS silicon gate process 42-pin plastic molded SDIP 42-pin plastic molded SSOP Functions
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DESCRIPTION
Table Description VCC, VSS. CNVSS RESET Name Power source Input/ Output Name Apply voltage (typical) VCC, VSS.
CNVSS Reset input Input
This connected VSS. enter reset state, reset input must kept more (under normal conditions). more time needed quartz-crystal oscillator stabilize, this condition should maintained required time. This input main clock generating circuit. control generating frequency, external ceramic resonator quartz-crystal oscillator connected between pins XOUT. external clock used, clock source should connected XOUT should left open. Port 8-bit port with direction register allowing each individually programmed input output. reset, this port input mode. output structure N-channel open-drain output (See note Output Pins also used output pins PWM0 PWM4, respectively. output structure N-channel open-drain output. Pins P06, also used external interrupt input pins INT2 INT1 respectively. also used analog input A-D4. Port 8-bit port basically same functions port output structure CMOS output (See note Pins also used output OUT2. output structure CMOS output. Pins P11-P14 used SCL1, SCL2, SDA1 SDA2 respectively, when multi-master I2C-BUS interface used. output structure N-channel open-drain output. Pins P15-P17 also used analog input pins A-D1 A-D3 respectively. also used external interrupt input INT3. Port 8-bit port basically same functions port output structure CMOS output. output structure CMOS output (See note Pins P23, also used timer external clock input pins TIM3, TIM2 respectively. also used serial synchronizing clock input/output SCLK. output structure N-channel open-drain output. Pins P21, also used serial data input/output pins SOUT, respectively. output structure N-channel open-drain output. Ports P30-P32 3-bit port basically same functions port Either CMOS output N-channel open-drain output structure selected port P31. output structure port N-channel open-drain output. (See notes Pins P30, also used analog input pins A-D5, A-D6 respectively. Pins P30, also used conversion output pins DA1, respectively. (See note Ports P33, 2-bit input port. also used clock input OSC1. also used clock output OSC2. output structure CMOS output.
XOUT
Clock input Clock output
Input Output
P00/PWM0- port P05/PWM5, P06/INT2/ A-D4, output P07/INT1 External interrupt input Analog input P10/OUT2, P11/SCL1, P12/SCL2, P13/SDA1, P14/SDA2, P15/A-D1/ INT3, P16/A-D2, P17/A-D3 P20/SCLK, P21/SOUT, P22/SIN, P23/TIM3, P24/TIM2, P25-P27 port output Multi-master I2C-BUS interface Analog input External interrupt input port Timer external clock input Serial synchronizing clock input/ output Serial data input/output P30/A-D5/ DA1, P31/A-D6/ DA2, port
Output Input Input Output Input Input Input
Analog input conversion output
Input Output Input Input Output
P33/OSC1, Input port P34/OSC2 Clock input Clock output
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Table Description (continued) P52/R, P53/G, P54/B, P55/OUT1 HSYNC VSYNC Output port output HSYNC input VSYNC input output Output Output Input Input Output Ports 4-bit output port. output structure CMOS output. Pins P52-P55 also used output pins OUT1 respectively. output structure CMOS output. This horizontal synchronizing signal input OSD. This vertical synchronizing signal input OSD. This 14-bit output pin.
Note Port port direction register that used program each input ("0") output ("1"). pins programmed direction register output pins. When pins programmed "0," they input pins. When pins programmed output pins, output data written into port latch then output. When data read from output pins, data port latch, output level, read. This allows previously output value read correctly even output voltage risen example, directly-driven light emitting diode. input pins floating state, values pins read. When data written input pin, written only into port latch, while remains floating state. swich output structures, following bits. port output mode control register port output mode control register When "0," CMOS output; when "1," N-channel open-drain output. Only M37221EASP/FP have built-in converter.
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Ports P00-P05,
N-channel open drain output
Direction register
Ports P00-P05,
Data Port latch
Note: Each port also used follows: P00-P05 PWM0-PWM5
Ports P30,
Direction register
CMOS output Ports P30,
Data
Port latch
Notes Each port also used follows: OUT2 SCL1 SCL2 SDA1 SDA2 A-D1/INT3 A-D2 A-D3 output structure ports P11-P14 N-channel open-drain output when using multi-master I2C-BUS inter face same with ports output structure ports selected either CMOS output N-channel open-drain output same with ports SCLK SOUT TIM3 TIM2 A-D5/DA1 A-D6/DA2
Ports P06,
N-channel open-drain output
Direction register
Ports P06,
Data Port latch
Note: Each port also used follow: INT2/A-D4 INT1
Fig. block diagram
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HSYNC, VSYNC
D-A, OUT1, OUT2
Schmidt input
Internal circuit
HSYNC, VSYNC
Internal circuit
CMOS output D-A, OUT1, OUT2 Note: Each also used below: OUT1 OUT2
Fig. block diagram
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M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP
FUNCTION BLOCK DESCRIPTION CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses standard Family instruction set. Refer table Family addressing modes machine instructions SERIES <Software> User's Manual details instruction set. Availability Family instructions follows: instructions cannot used. MUL, DIV, instructions used.
8.1.1 Mode Register
mode register includes stack page selection internal system clock selection bit. mode register allocated address 00FB16.
Mode Register
mode register (CM) [Address 00FB16] Name Functions
After reset
Indeterminate
these bits "0." Stack page selection (CM2) (See note) page page
Indeterminate
these bits "1." Note: This after reset release.
Fig. 8.1.1 Mode Register
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MEMORY 8.2.1 Special Function Register (SFR) Area
special function register (SFR) area zero page includes control registers such ports timers.
8.2.6 Interrupt Vector Area
interrupt vector area contains reset interrupt vectors.
8.2.7 Zero Page
zero page addressing mode used specify memory register addresses zero page area. Access this area possible with only bytes zero page addressing mode.
8.2.2
used data storage stack area subroutine calls interrupts.
8.2.3
used storing user programs well interrupt vector area.
8.2.8 Special Page
special page addressing mode used specify memory addresses special page area. Access this area possible with only bytes special page addressing mode.
8.2.4
used specifying character codes colors display.
8.2.5
used storing character data display.
8.2.9 Correction Memory (RAM)
This used program area correction.
M37221M4 H/M6H -XXXSP/FP
000016 Zero page M37221M6HXXXSP/FP (448 bytes) M37221M4HXXXSP/FP (384 bytes) 00C016 area 00FF16 017F16 01BF16 02C016 02E016 02FF16 bytes) (See note) 060016 06B716 used M37221M6HXXXSP/FP (24K bytes) A00016 C00016 bytes)
1000016
11FFF16
used correction function Vector address 02C016 Vector address 02E016
used
used
M37221M4HXXXSP/FP (16K bytes) FF0016 FFDE16 FFFF16
Interrupt vector area
Special page 1FFFF16
Note: Refer Table 8.11.4 RAM.
Fig. 8.2.1 Memory (M37221M4H/M6H-XXXSP/FP)
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M37221M8H/MAH-XXXSP/FP, M37221EASP/FP
000016 Zero page 00C016 area 00FF16 M37221MAHXXXSP/FP, M37221EASP/FP (704 bytes) M37221M8HXXXSP/FP (576 bytes) 01FF16 021716 021B16 02C016 02E016 02FF16 030016 033F16 03BF16 used bytes) (See note) M37221MAHXXXSP/FP, M37221EASP/FP (40K bytes) M37221M8HXXXSP/FP (32K bytes) 060016 06B716 used 600016 800016 used page register used correction function Vector address 02C016 Vector address 02E016
1000016
bytes)
11FFF16
used
FF0016 FFDE16 FFFF16
Interrupt vector area
Special page 1FFFF16 Note: Refer Table 8.11.4 RAM.
Fig. 8.2.2 Memory (M37221M8H/MAH-XXXSP/FP, M37221EASP/FP)
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area (addresses C016 DF16)
<Bit allocation>
Name
State immediately after reset> immediately after reset immediately after reset Indeterminate immediately after reset
Function
function
this write "1") this write "0") Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register allocation
State immediately after reset
Port (P0) Port direction register (D0) Port (P1) Port direction register (D1) Port (P2) Port direction register (D2) Port (P3) Port direction register (D3)
Port (P5) Port direction register (D5) Port output mode control register (P3S) (Note DA-H register (DA-H) DA-L register (DA-L) PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) output control register (PW) output control register (PN) data shift register (S0) address register (S0D) status register (S1) control register (S1D) clock control register (S2) Serial mode register (SM) Serial regsiter (SIO) conversion register (DA1) (Note conversion register (DA2) (Note
DA2S DA1S P31S P30S
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
BSEL1 BSEL0 10BIT
FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE
DA15 DA14 DA13 DA12 DA11 DA10 DA25 DA24 DA23 DA22 DA21 DA20
0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016
Note M37221M4H/M6H/M8H/MAH-XXXSP/FP, bits "0." M37221M4H/M6H/M8H/MAH-XXXSP/FP have this register. this register "0016."
Fig. 8.2.3 Memory Special Function Register (SFR)
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area (addresses E016 FF16)
<Bit allocation>
Name
<State immediately after reset> immediately after reset immediately after reset
Function
function
this write "1") this write "0") Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register
allocation
CV16 CV15 CV14 CV13 CV12 CV11 CV10 CV26 CV25 CV24 CV23 CV22 CV21 CV20
State immediately after reset
Horizontal register (HR) Vertical register (CV1) Vertical register (CV2) Character size register (CS) Border selection register (MD) Color register (CO0) Color register (CO1) Color register (CO2) Color register (CO3) control register (CC) port control register (CRTP) clock selection register (CK) control register (AD1) control register (AD2) Timer (TM1) Timer (TM2) Timer (TM3) Timer (TM4) Timer mode register (T12M) Timer mode register (T34M) PWM5 register (PWM5)
CS21 CS20 CS11 CS10
MD20 CO07 CO06 CO05 CO04 CO03 CO02 CO01 CO17 CO16 CO15 CO14 CO13 CO12 CO11 CO27 CO26 CO25 CO24 CO23 CO22 CO21 CO37 CO36 CO35 CO34 CO33 CO32 CO31 MD10
OUT1 OUT2 R/G/B VSYC HSYC
ADM4
ADM2 ADM1 ADM0
ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
T12M4 T12M3 T12M2 T12M1 T12M0
T34M5 T34M4 T34M3 T34M2 T34M1 T34M0
Interrupt input polarity register (RE) Test register (TEST) mode register (CPUM) Interrupt request register (IREQ1) Interrupt request register (IREQ2) Interrupt control register (ICON1) Interrupt control register (ICON2)
IT3R
0016
IICR VSCR CRTR TM4R TM3R TM2R TM1R
1T2R 1T1R
IT3E IICE VSCE CRTE TM4E TM3E TM2E TM1E
1T2E 1T1E
0016 0016 0016 0016 0016 0016 0016 0016 0016 FF16 0716 FF16 0716 0016 0016 0016 0016 0016 0016 0016
Fig. 8.2.4 Memory Special Function Register (SFR)
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page register area (addresses 21716 21B16)
<Bit allocation>
Name
State immediately after reset> immediately after reset immediately after reset Indeterminate immediately after reset
Function
function
this write "1") this write "0") Address 21716 21816 21916 21A16 21B16 Register
correction address (high-order) correction address (low-order) correction address (high-order) correction address (low-order) correction enable register (RCR)
allocation
State immediately after reset
RCR1 RCR0
0016 0016 0016 0016 0016
Note: Only M37221M4H/M6H/ /MAH-XXXSP/FP M37221EASP/FP have pag.e register.
Fig. 8.2.5 Memory Page Register Area
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<Bit allocation>
Name
<State immediately after reset> immediately after reset immediately after reset Indeterminate immediately after reset
Function
function
this write "1") this write "0") Register
Processor status register (PS) Program counter (PCH) Program counter (PCL)
allocation
State immediately after reset
Contents address FFFF16 Contents address FFFE16
Fig. 8.2.6 Internal State Processor Status Register Program Counter Reset
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INTERRUPTS
Interrupts caused different sources comprising external, internal, software, reset interrupts. Interrupts vectored interrupts with priorities shown Table 8.3.1. Reset also included table operation similar interrupt. When interrupt accepted, contents program counter processor status register automatically stored into stack. interrupt disable flag corresponding interrupt request "0." jump destination address stored vector address enters program counter. Other interrupts disabled when interrupt disable flag "1." interrupts except instruction interrupt have interrupt request interrupt enable bit. interrupt request bits Interrupt Request Registers interrupt enable bits Interrupt Control Registers Figures 8.3.2 8.3.6 show interrupt-related registers. Interrupts other than instruction interrupt reset accepted when interrupt enable "1," interrupt request "1," interrupt disable flag "0." interrupt request program, "1." interrupt enable program. Reset treated non-maskable interrupt with highest priority. Figure 8.3.1 shows interrupt controls.
8.3.1 Interrupt Causes VSYNC, interrupts
VSYNC interrupt interrupt request synchronized with vertical sync signal. interrupt occurs after character block display completed.
INT1 INT3 external interrupts
INT1 INT3 interrupts external interrupt inputs, system detects that level changes from HIGH from HIGH LOW, generates interrupt request. input active edge selected bits interrupt input polarity register (address 00F916) when this "0," change from HIGH detected; when "1," change from HIGH detected. Note that both bits cleared reset.
Timers interrupts
interrupt generated overflow timers
Table 8.3.1 Interrupt Vector Addresses Priority Priority Interrupt Source Reset interrupt INT2 external interrupt INT1 external interrupt Timer interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer interrupt Timer interrupt Timer interrupt Serial interrupt Multi-master I2C-BUS interface interrupt INT3 external interrupt instruction interrupt Vector Addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFDF16, FFDE16 Remarks Non-maskable Active edge selectable Active edge selectable
Active edge selectable Non-maskable
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Serial interrupt
This interrupt request from clock synchronous serial function.
f(XIN)/4096 interrupt
(XIN)/4096 interrupt occurs regularly with f(XIN)/4096 period. output control register "0."
Interrupt request Interrupt enable
Multi-master I2C-BUS interface interrupt
This interrupt request related multi-master I2C-BUS interface.
Interrupt disable flag
instruction Reset
Interrupt request
instruction interrupt
This software interrupt least significant priority. does have corresponding interrupt enable bit, affected interrupt disable flag (non-maskable). Fig. 8.3.1 Interrupt Control
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Interrupt Request Register
Interrupt request register (IREQ1) [Address 00FC16] Name Timer interrupt request (TM1R) Functions After reset interrupt request issued Interrupt request issued Timer interrupt interrupt request issued request (TM2R) Interrupt request issued Timer interrupt interrupt request issued request (TM3R) Interrupt request issued Timer interrupt interrupt request issued request (TM4R) Interrupt request issued interrupt request interrupt request issued Interrupt request issued (CRTR) VSYNC interrupt interrupt request issued request (VSCR) Interrupt request issued Multi-master I2C-BUS interface interrupt request issued interrupt request (IICR) Interrupt request issued interrupt request issued INT3 external interrupt request (IT3R) Interrupt request issued
software, cannot set.
Fig. 8.3.2 Interrupt Request Register
Interrupt Request Register
Interrupt request register (IREQ2) [Address 00FD16] Name INT1 external interrupt
request (IT1R)
Functions interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued
After reset
INT2 external interrupt request (IT2R)
interrupt request issued Interrupt request issued Nothing assigned. This write disable bit. When this read out, value "0." f(XIN)/4096 interrupt interrupt request issued request (MSR) Interrupt request issued Nothing assigned. These bits write disable bits. When these bits read out, values "0." this "0." software, cannot set.
Serial interrupt request (S1R)
Fig. 8.3.3 Interrupt Request Register
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Interrupt Control Register
Interrupt control register (ICON1) [Address 00FE16] Name Functions Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled After reset
Timer interrupt enable (TM1E) Timer interrupt enable (TM2E) Timer interrupt enable (TM3E) Timer interrupt enable (TM4E) interrupt enable (CRTE) VSYNC interrupt enable (VSCE) Multi-master I2C-BUS interface interrupt enable (IICE) INT3 external interrupt enable (IT3E)
Fig. 8.3.4 Interrupt Control Register
Interrupt Control Register
Interrupt control register (ICON2) [Address 00FF16] Name Functions Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled After reset Interrupt disabled Interrupt enabled
INT1 external interrupt enable (IT1E) INT2 external interrupt enable (IT2E) Serial interrupt enable (S1E) this "0." f(XIN)/4096 interrupt enable (MSE) these bits "0."
Fig. 8.3.5 Interrupt Control Register
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Interrupt Input Polarity Register
Interrupt input polarity register(RE) [Address 00F916
Name Functions After reset Positive polarity Negative polarity Positive polarity Negative polarity Positive polarity Negative polarity
Nothing assigned. This write disable bit.
When this read out, value "0."
These bits "0."
INT1 polarity switch (RE3) INT2 polarity switch (RE4) INT3 polarity switch (RE5)
Nothing assigned. This write disable bit. When this read out, value "0."
this "0."
Fig. 8.3.6 Interrupt Input Polarity Register
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TIMERS
This microcomputer timers: timers timers 8-bit timers with 8-bit timer latch. timer block diagram shown Figure 8.4.3. timers count down their divide ratio 1/(n+1), where value timer latch. writing count value corresponding timer latch (addresses 00F016 00F316 timers value also timer, simultaneously. count value decremented timer interrupt request timer overflow next count pulse, after count value reaches "0016."
8.4.1 Timer
Timer select following count sources: f(XIN)/16 f(XIN)/4096 count source timer selected setting timer mode register (address 00F416). Timer interrupt request occurs timer overflow.
reset, timers connected hardware "FF16" automatically timer "0716" timer f(XIN)/16 selected timer count source. internal reset released timer overflow this state internal clock connected. execution instruction, timers connected hardware "FF16" automatically timer "0716" timer However, f(XIN)/16 selected timer count source. both timer mode register (address 00F516) address 00C716 before execution instruction (f(XIN)/16 selected timer count source). internal state released timer overflow this state internal clock connected. result above procedure, program start under stable clock. timer-related registers shown Figures 8.4.1 8.4.2.
8.4.2 Timer
Timer select following count sources: f(XIN)/16 Timer overflow signal External clock from TIM2 count source timer selected setting bits timer mode register (address 00F416). When timer overflow signal count source timer timer functions 8bit prescaler. Timer interrupt request occurs timer overflow.
8.4.3 Timer
Timer select following count sources: f(XIN)/16 External clock from HSYNC External clock from TIM3 count source timer selected setting bits timer mode register (address 00F516). Timer interrupt request occurs timer overflow.
8.4.4 Timer
Timer select following count sources: f(XIN)/16 f(XIN)/2 Timer overflow signal count source timer selected setting bits timer mode register (address 00F516). When timer overflow signal count source timer timer functions 8bit prescaler. Timer interrupt request occurs timer overflow.
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Timer Mode Register
Timer mode register (T12M) [Address 00F416] Name Functions After reset
Timer count source f(XIN)/16 selection (T12M0) f(XIN)/4096 Timer count source selection (T12M1) Interrupt clock source External clock from TIM2 Count start Count stop Count start Count stop f(XIN)/16 Timer overflow
Timer count stop (T12M2) Timer count stop (T12M3) Timer internal count source selection (T12M4) this "0."
Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.4.1 Timer Mode Register
Timer Mode Register
Timer mode register (T34M) [Address 00F516] Name Timer count source selection (T34M0) Timer internal interrupt count source selection (T34M1) Functions f(XIN)/16 External clock source Timer overflow signal f(XIN)/16 Count start Count stop Count start Count stop Internal clock source f(XIN)/2 After reset
Timer count stop (T34M2) Timer count stop (T34M3) Timer count source selection (T34M4)
Timer external count TIM3 input source selection HSYNC input (T34M5)
Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.4.2 Timer Mode Register
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Data
1/4096
Timer latch
T12M0 T12M2
Timer T12M4
Timer interrupt request
Timer latch TIM2 T12M1 T12M3 Timer Timer interrupt request
HSYNC
FF16
Reset instruction
TIM3
T34M5
Timer latch
Timer T34M0 T34M2 Timer interrupt request
Selection gate Connected black colored side reset T34M1 T12M Timer mode register T34M Timer mode register Timer latch Timer T34M4 T34M3
0716
Timer interrupt request
Notes pulse width external clock inputs TIM2 TIM3 needs machine cycles more. When external clock source selected, timers counted rising edge input signal. stop mode wait mode, external clock inputs TIM2 TIM3 cannot used.
Fig. 8.4.3 Timer Block Diagram
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SERIAL
This microcomputer built-in serial which either transmit receive 8-bit data serially clock synchronous mode. serial block diagram shown Figure 8.5.1. synchronous clock (SCLK), data output (SOUT), data input (SIN) also functions port serial mode register (address 00DC16) selects whether synchronous clock supplied internally externally (from SCLK pin). When internal clock selected, bits select whether f(XIN) f(XCIN) divided serial I/O, corresponding port direction register (address 00C516) "0."
operation serial described below. operation serial differs depending clock source; external clock internal clock.
Data Frequency divider
1/16
Synchronization circuit
Selection gate Connected black colored side reset. Serial mode register
latch SCLK latch SOUT(/IN) (See note) Serial shift register (Address 00DD Serial counter Serial interrupt request
Note When data serial register (address 00DD16), register functions serial shift register.
Fig. 8.5.1 Serial Block Diagram
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Internal clock serial counter during write cycle into serial register (address 00DD16), transfer clock goes HIGH forcibly. each falling edge transfer clock after write cycle, serial data output from SOUT pin. Transfer direction selected serial mode register. each rising edge transfer clock, data input from data serial register shifted bit. After transfer clock counted times, serial counter becomes transfer clock stops HIGH. this time interrupt request "1."
External clock external clock selected clock source, interrupt request after transfer clock been counted counts. However, transfer operation does stop, clock should controlled externally. external clock less with duty cycle 50%. serial timing shown Figure 8.5.2. When using external clock transfer, external clock must held HIGH initializing serial counter. When switching between internal clock external clock, switch during transfer. Also, sure initialize serial counter after switching.
Notes programming, note that serial counter writing serial register with managing instructions, such CLB. When external clock used synchronous clock, write transmit data serial register when transfer clock input level HIGH.
Synchronous clock
Transfer clock Serial register write signal (See note) Serial output SOUT Serial input
Interrupt request Note When internal clock selected, SOUT high-impedance after transfer completed.
Fig. 8.5.2 Serial Timing (for first)
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Serial Mode Register
Serial mode register (SM) [Address 00DC16] Name
Functions f(XIN)/4 f(XIN)/16 f(XIN)/32 f(XIN)/64 External clock Internal clock P20, SCLK, SOUT
Internal synchronous clock selection bits (SM0, SM1)
After reset
Synchronous clock selection (SM2) Serial port selection (SM3)
this "0." Transfer direction selection (SM5) Serial input selection (SM6) first first Input signal from pin. Input signal from SOUT pin.
Nothing assigned. This write disable bit. When this read out, value "0."
Fig. 8.5.3 Serial Mode Register
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8.5.1 Serial Common Transmission/Reception mode
writing serial mode register, signals SOUT switched internally able transmit receive serial data. Figure 8.5.4 shows signals serial common transmission/reception mode.
Note: When receiving serial data after writing "FF16" serial register.
SCLK
Clock
SOUT Serial shift register
Serial mode register
Fig. 8.5.4 Signals Serial Common Transmission/Reception Mode
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MULTI-MASTER I2C-BUS INTERFACE
multi-master I2C-BUS interface serial communications circuit, conforming Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection synchronous functions, useful multi-master serial communications. Figure 8.6.1 shows block diagram multi-master I2C-BUS interface Table 8.6.1 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists address register, data shift register, clock control register, control register, status register other control circuits.
Table 8.6.1 Multi-master I2C-BUS Interface Functions Item Function conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 MHz)
Format
Communication mode
clock frequency
System clock f(XIN)/2
Note responsible third party's infringement patent rights other rights attributable control function (bits control register address 00DA16) connections between I2C-BUS interface ports (SCL1, SCL2, SDA1, SDA2).
address register (S0D)
Interrupt generating circuit Interrupt request signal (IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
Address comparator Serial data
(SDA)
Noise elimination circuit
Data control circuit
data shift register
circuit
Internal data
status register (S1)
circuit
Serial clock
(SCL)
Noise elimination circuit
Clock control circuit
FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE
BSEL1 BSEL0 10BIT
clock control register (S2) Clock division
control register (S1D) System clock counter
Fig. 8.6.1 Block Diagram Multi-master I2C-BUS Interface
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8.6.1 Data Shift Register
data shift register address 00D716) 8-bit shift register store receive data write transmit data. When transmit data written into this register, transferred outside from synchronization with clock, each time one-bit data output, data this register shifted left. When data received, input this register from synchronization with clock, each time one-bit data input, data this register shifted left. data shift register write enable status only when control register (address 00DA16) "1." counter reset write instruction data shift register. When both status register (address 00D916) "1," output write instruction data shift register. Reading data from data shift register always enabled regardless value.
Note: write data into data shift register after setting (slave mode), keep interval machine cycles more.
Data Shift Register
data shift register (S0) [Address 00D716 Name Functions After reset Indeterminate
This 8-bit shift register store receive data write transmit data.
Note: write data into data shift register after setting (slave mode), keep interval machine cycles more.
Fig. 8.6.2 Data Shift Register
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8.6.2 Address Register
address register (address 00D816) consists 7-bit slave address read/write bit. addressing mode, slave address written this register compared with address data received immediately after START condition detected.
read/write (RBW)
used when comparing addresses, 7-bit addressing mode. 10-bit addressing mode, first address data received compared with contents (SAD6 SAD0 RBW) address register. cleared automatically when stop condition detected.
Bits slave address (SAD0-SAD6)
These bits store slave addresses. Regardless 7-bit addressing mode 10-bit addressing mode, address data transmitted from master compared with contents these bits.
Address Register
address register (S0D) [Address 00D816]
Name
Read/write (RBW)
Functions
<Only 10-bit addressing slave) mode> last significant address data compared. Wait first byte slave address after START condition (read state) Wait first byte slave address after RESTART condition (write state) both modes> address data compared.
After reset
Slave address (SAD0 SAD6)
Fig. 8.6.3 Address Register
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8.6.3 Clock Control Register
clock control register (address 00DB16) used control, mode frequency.
clock (ACK)
This specifies mode acknowledgment which acknowledgment response data transmission. When this "0," clock mode set. this case, clock occurs after data transmission. When "1," clock mode master generates clock upon completion each 1-byte data transmission.The device transmitting address data control data releases occurrence clock (make HIGH) receives generated data receiving device.
Note: write data into clock control register during transmission. data written during transmission, clock generator reset, that data cannot transmitted normally.
Bits frequency control bits (CCR0-CCR4)
These bits control frequency.
mode specification (FAST MODE)
This specifies mode. When this "0," standard clock mode set. When "1," high-speed clock mode set.
(ACK BIT)
This sets status when clock generated. When this "0," return mode goes occurrence clock. When "1," non-return mode set. held HIGH status occurrence clock. However, when slave address matches address data reception address data "0," automatically made (ACK returned). there mismatch between slave address address data, automatically made HIGH (ACK returned). clock: Clock acknowledgement
Clock Control Register
clock control register (S2) [Address 00DB16]
Name
Functions
After reset
frequency control bits Setup value Standard clock High speed (CCR0 CCR4) CCR4-CCR0 mode clock mode
Setup disabled Setup disabled Setup disabled Setup disabled 83.3 17.2 16.6 16.1 (See note) 34.5 33.3 32.3
500/CCR value 1000/CCR value
MHz, unit kHz) mode specification (FAST MODE) (ACK BIT) clock (ACK) Standard clock mode High-speed clock mode returned. returned. clock clock
Note: high-speed clock mode, duty below period period other cases, duty below. period period
Fig. 8.6.4 Address Register
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8.6.4 Control Register
control register (address 00DA16) controls data communication format.
data format selection (ALS)
This decides whether recognize slave addresses. When this "0," addressing format selected, that address data recognized. When match found between slave address address data result comparison when general call (refer "8.6.5 Status Register," received, transmission processing performed. When this "1," free data format selected, that slave addresses recognized.
Bits counter (BC0-BC2)
These bits decide number bits next 1-byte data transmitted. interrupt request signal occurs immediately after number bits specified with these bits transmitted. When START condition received, these bits become "0002" address data always transmitted received bits.
I2C-BUS interface enable (ESO)
This enables usage multimaster interface. When this "0," interface disabled status become high-impedance. When "1," interface enabled. When "0," following performed. "1," (they bits status register address 00D916 Writing data data shift register (address 00D716) disabled.
addressing format selection (10BIT SAD)
This selects slave address specification format. When this "0," 7-bit addressing format selected. this case, only high-order bits (slave address) address register (address 00D816) compared with address data. When this "1," 10-bit addressing format selected bits address register compared with address data.
Bits connection control bits between C-BUS interface ports (BSEL0, BSEL1)
These bits control connection between ports ports (refer Figure 8.6.5).
BSEL0 SCL1/P11 Multi-master I2C-BUS interface BSEL1 SCL2/P12 BSEL0 SDA1/P13 BSEL1 SDA2/P14
Note: corresponding direction register port multi-master I2C-BUS interface.
Fig. 8.6.5 Connection Port Control BSEL0 BSEL1
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Control Register
control register (S1D) [Address 00DA16]
Name
counter (Number transmit/recieve bits) (BC0 BC2)
Functions
After reset
I2C-BUS interface enable (ESO) Data format selection bit(ALS) Addressing format selection (10BIT SAD)
Disabled Enabled Addressing format Free data format 7-bit addressing format 10-bit addressing format Connection port (See note) None SCL1, SDA1 SCL2, SDA2 SCL1, SDA1, SCL2, SDA2
Connection control bits between I2C-BUS interface ports (BSEL0, BSEL1)
Fig. 8.6.6 Control Register
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8.6.5 Status Register
status register (address 00D916) controls I2C-BUS interface status. low-order bits read-only bits highorder bits read written
I2C-BUS interface interrupt request (PIN)
This generates interrupt request signal. Each time 1-byte data transmitted, state changes from "0." same time, interrupt request signal sent CPU. synchronization with falling edge last clock (including clock) internal clock interrupt request signal occurs synchronization with falling edge bit. When detecting STOP condition slave, multi-master I2C-BUS interface interrupt request (IR) (interrupt request) regardless falling bit. When "0," kept state clock generation disabled. Figure 8.6.8 shows interrupt request signal generating timing chart. following conditions. Writing Executing write instruction data shift register (address 00D716) (See note) When reset
Note: takes BCLK cycles more until becomes after write instructions executed these registers.
last receive (LRB)
This stores last value received data also used receive confirmation. returned when clock occurs, "0." returned, this "1." Except mode, last value received data input. state this changed from executing write instruction data shift register (address 00D716).
general call detecting flag (AD0)
This when general call whose address data received slave mode. general call master device, every slave device receives control data after general call. detecting STOP condition START condition. General call: master transmits general call address "0016" slaves.
slave address comparison flag (AAS)
This flag indicates comparison result address data. slave receive mode, when 7-bit addressing format selected, this either following conditions. address data immediately after occurrence START condition matches slave address stored high-order bits address register (address 00D816). general call received. slave reception mode, when 10-bit addressing format selected, this following condition. When address data compared with address register bits consisting slave address RBW), first bytes match. state this changed from executing write instruction data shift register (address 00D716).
conditions which shown below: Immediately after completion 1-byte data transmission (including when arbitration lost detected) Immediately after completion 1-byte data reception slave reception mode, with immediately after completion slave address general call address reception slave reception mode, with immediately after completion address data reception
busy flag (BB)
This indicates status system. When this "0," this system busy START condition generated. When this "1," this system busy occurrence START condition disabled START condition duplication prevention function (See note). This flag written software only master transmission mode. other modes, this detecting START condition detecting STOP condition. When control register (address 00DA16) reset, flag kept state.
arbitration lost detecting flag (AL)
master transmission mode, when device other than microcomputer sets "L,", arbitration judged have been lost, that this "1." same time, "0," that immediately after transmission byte whose arbitration lost completed, "0." When arbitration lost during slave address transmission, reception mode set. Consequently, becomes possible receive recognize slave address transmitted another master device. Arbitration lost: status which communication master disabled.
communication mode specification (transfer direction specification bit: TRX)
This decides direction transfer data communication. When this "0," reception mode selected data transmitting device received. When "1," transmission mode selected address data control data output into synchronization with clock generated SCL. When control register (address 00DA16) slave reception mode, (transmit) least significant (R/W bit) address data transmitted master "1." When "0," cleared (receive). cleared following conditions. When arbitration lost detected. When STOP condition detected. When occurence START condition disabled START condition duplication prevention function (Note). When START condition detected. When non-return detected. reset
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Communication mode specification (master/slave specification bit: MST)
This used master/slave specification data communications. When this "0," slave specified, that START condition STOP condition generated master received, data communication performed synchronization with clock generated master. When this "1," master specified START condition STOP condition generated, also clocks required data communication generated SCL. cleared following conditions. Immediately after completion 1-byte data transmission when arbitration lost detected When STOP condition detected. When occurence START condition disabled START condition duplication prevention function (Note). reset
Note: START condition duplication prevention function disables START condition generation, counter reset, output, when following condition satisfied: START condition another master device.
Status Register
status register (S1) [Address 00D916]
Name
Last receive (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request (PIN) busy flag (BB)
Functions
Last Last (See note)
After reset
Indeterminate
general call detected General call detected (See note) Address mismatch Address match detected Detected (See note)
(See note) Interrupt request issued interrupt request issued
free busy Slave recieve mode Slave transmit mode Master recieve mode Master transmit mode
Communication mode specification bits (TRX, MST)
Note These bits flags read out, cannnot written.
Fig. 8.6.7 Status Register
IICIRQ
Fig. 8.6.8 Interrupt Request Signal Generation Timing
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8.6.6 START Condition Generation Method
When control register (address 00DA16) "1," execute write instruction status register (address 00D916) MST, bits "1." START condition will then generated. After that, counter becomes "0002" output byte START condition generation timing timing different standard clock mode highspeed clock mode. Refer Figure 8.6.9 START condition generation timing diagram, Table 8.6.2 START condition/ STOP condition generation timing table.
status registe write signal flag Setup time Setup time Hold time time flag
Fig. 8.6.9 START Condition Generation Timing Diagram
8.6.7 STOP Condition Generation Method
When control register (address 00DA16) "1," execute write instruction status register (address 00D916) "0". STOP condition will then generated. STOP condition generation timing flag reset timing different standard clock mode high-speed clock mode. Refer Figure 8.6.10 STOP condition generation timing diagram, Table 8.6.2 START condition/STOP condition generation timing table.
status register write signal flag Setup time Hold time
Reset time flag
Fig. 8.6.10 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Timing Table Item Standard Clock Mode Setup time cycles) (START condition) Setup time 4.25 cycles) (STOP condition) cycles) Hold time Set/reset time cycles) flag High-speed Clock Mode cycles) 1.75 cycles) cycles) cycles)
Note: Absolute time MHz. value parentheses denotes number cycles.
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8.6.8 START/STOP Condition Detect Conditions
START/STOP condition detect conditions shown Figure 8.6.11 Table 8.6.3. Only when conditions Table 8.6.3 satisfied, START/STOP condition detected.
Note: When STOP condition detected slave mode (MST interrupt request signal "IICIRQ" generated CPU.
8.6.9 Address Data Communication
There address data communication formats, namely, 7-bit addressing format 10-bit addressing format. respective address communication formats described below.
7-bit addressing format
support 7-bit addressing format, 10BIT control register (address 00DA16) "0." first 7-bit address data transmitted from master compared with high-order 7bit slave address stored address register (address 00D816). time this comparison, address comparison address register (address 00D816) made. data transmission format when 7-bit addressing format selected, refer Figure 8.6.12, (2).
release time (START condition) (STOP condition) Setup time Setup time Hold time
10-bit addressing format
Hold time support 10-bit addressing format, 10BIT control register (address 00DA16) "1." address comparison made between first-byte address data transmitted from master 7-bit slave address stored address register (address 00D816). time this comparison, address comparison performed between address regis_ (address 00D816) bit, which last address data transmitted from master. 10-bit addressing mode, only specifies direction communication control data also processed address data bit. When first-byte address data matches slave address, status register (address 00D916) "1." After second-byte address data stored into data shift register (address 00D716), perform address comparison between second-byte data slave address software. When address data byte matches slave address, address register (address 00D816) software. This processing match 7-bit slave address data, which received after RESTART condition detected, with value address register (address 00D816). data transmission format when 10-bit addressing format selected, refer Figure 8.6.12, (4).
Fig. 8.6.11 START Condition/STOP Condition Detect Timing Diagram
Table 8.6.3 START Condition/STOP Condition Detect Conditions Standard Clock Mode cycles) release time 3.25 cycles) Setup time 3.25 cycles) Hold time High-speed Clock Mode cycles) release time cycles) Setup time cycles) Hold time
Note: Absolute time MHz. value parentheses denotes number cycles.
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8.6.10 Example Master Transmission
example master transmission standard clock mode, frequency with return mode enable, shown below. slave address high-order bits address register (address 00D816) bit. return mode setting "8516" clock control register (address 00DB16). "1016" status register (address 00D916) hold HIGH. communication enable status setting "4816" control register (address 00DA16). address data destination transmission highorder bits data shift register (address 00D716) least significant bit. "F016" status register (address 00D916) generate START condition. this time, byte clock automatically occurs. transmit data data shift register (address 00D716). this time, clock automatically occurs. When transmitting control data more than byte, repeat step "D016" status register (address 00D916). After this, returned transmission ends, STOP condition will generated.
8.6.11 Example Slave Reception
example slave reception high-speed clock mode, frequency kHz, with non-return mode enabled while using addressing format, shown below. slave address high-order bits address register (address 00D816) bit. non-return mode setting "2516" clock control register (address 00DB16). "1016" status register (address 00D916) hold HIGH. communication enable status setting "4816" control register (address 00DA16). When START condition received, address comparison executed. transmitted address are"0" (general call): status register (address 00D916) interrupt request signal occurs. transmitted addresses match address status register (address 00D916) interrupt request signal occurs. cases other than above: status register (address 00D916) interrupt request signal occurs. dummy data data shift register (address 00D716). When receiving control data more than byte, repeat step When STOP condition detected, communication ends.
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Slave address
Data
Data
bits bits bits master-transmitter transmits data slave-receiver
Slave address
Data
Data
bits bits bits master-receiver receives data from slave-transmitter Slave address bits Slave address byte
Data
Data
bits bits bits bits master-transmitter transmits data slave-receiver with 10-bit address Slave address bits Slave address byte Slave address bits
Data
Data bits
bits bits bits bits master-receiver receives data from slave-transmitter with 10-bit address START condition Restart condition STOP condition Read/Write From master slave From slave master
Fig. 8.6.12 Address Data Communication Format
8.6.12 Precautions when using multi-master I2C-BUS interface Read-modify-write instruction
Precautions executing read-modify-write instructions such SEB, CLB, each register multi-master I2C-BUS interface described below. data shift register (S0) When executing read-modify-write instruction this register during transfer, data become arbitrary value. address register (S0D) When read-modify-write instruction executed this register detection STOP condition, data become arbitrary value. because hardware changes read/write (RBW) timing. status register (S1) execute read-modify-write instruction this register because bits this register changed hardware. control register (S1D) When read-modify-write instruction executed this register detection START condition completion byte transfer, data become arbitrary value. Because hardware changes counter (BC0-BC2) timing. clock control register (S2) read-modify-write instruction executed this register.
START condition generation procedure using multi-master
Procedure example (The necessary conditions procedure described below).
5,S1,BUSBUSY BUSFREE: #$F0, BUSBUSY:
(Take slave address value) (Interrupt disabled) flag confirmation branch process) (Write slave address value) (Trigger START condition generation) (Interrupt enabled)
(Interrupt enabled)
"STA," "STX" "STY" zero page addressing instruction writing slave address value data shift register. "LDM" instruction setting trigger START condition generation. Write slave address value trigger START condition generation continuously shown procedure example. Disable interrupts during following three process steps: flag confirmation Write slave address value Trigger START condition generation When condition flag busy, enable interrupts immediately.
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RESTART condition generation procedure
Procedure example (The necessary conditions procedure described below.) Execute following procedure when "0." #$00, #$F0, Select slave receive mode when "0." write bit. Neither specified writing bit. becomes released. released writing slave address value data shift register. "STA," "STX" "STY" zero page addressing instruction writing. "LDM" instruction setting trigger RESTART condition generation. Write slave address value trigger RESTART condition generation continuously, shown procedure example. Disable interrupts during following process steps: Write slave address value Trigger RESTART condition generation
STOP condition generation procedure
Procedure example (The necessary conditions procedure described below.)
(Select slave receive mode) (Take slave address value) (Interrupt disabled) (Write slave address value) (Trigger RESTART condition generation) (Interrupt enabled)
#$C0, #$D0,
(Interrupt disabled) (Select master transmit mode) (Set NOP) (Trigger STOP condition generation) (Interrupt enabled)
Write when master transmit mode selected. Execute "NOP" instruction after master transmit mode set. Also, trigger STOP condition generation within cycles after selecting master trasmit mode. Disable interrupts during following process steps: Select master transmit mode Trigger STOP condition generation
Writing status register
execute instruction from instruction bits from simultaneously cause released after about machine cycle. Also, execute instruction bits from when "1," cause same problem.
Process after STOP condition generation
write data data shift register status register until busy flag becomes after generation STOP condition master mode. Doing cause STOP condition waveform from being generated normally. Reading registers does cause same problem.
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OUTPUT FUNCTION
This microcomputer equipped with 14-bit (DA) 8-bit PWMs (PWM0-PWM5). have 14-bit resolution with minimum resolution width 0.25 repeat period 4096 (for f(XIN) MHz). PWM0-PWM7 have same circuit structure 8-bit resolution with minimum resolution width repeat period 1024 (for f(XIN) MHz). Figure 8.7.1 shows block diagram. timing generating circuit applies individual control signals PWM0- PWM5 using f(XIN) divided reference signal.
8.7.4 Operating 14-bit
with 8-bit PWM, output control register (address 00D516) reset, already automatically), that count source supplied. Next, select output polarity output control register (address 00D616). Then, 14-bit outputs from output setting output control register reset, this already automatically) select output. output example 14-bit shown Figure 8.7.3. 14-bit divides data latch into low-order bits high-order bits. fundamental waveform determined with high-order 8-bit data "DH." HIGH area with length (HIGH area fundamental waveform) output every short area minimum resolution width ns). HIGH level area increase interval (tm) determined with low-order 6-bit data "DL." HIGH smaller intervals "tm" shown Table longer than that other smaller intervals repeat period 64t. Thus, rectangular waveform with different HIGH width output from pins. Accordingly, output changes unit pulse width changing contents DA-H DA-L registers. length entirely HIGH cannot output, 256/256.
8.7.1 Data Setting
When outputting first high-order bits DA-H register (address 00CE16), then low-order bits DA-L register (address 00CF16). When outputting PWM0-PWM5, 8-bit output data PWMi register means addresses 00D016 00D416, 00F616).
8.7.2 Transferring Data from Registers Circuit
Data transfer from 8-bit register 8-bit circuit executed when writing data register. signal output from 8-bit output corresponds contents this register. Also, data transfer from register (addresses 00CE16 00CF16) 14-bit circuit executed writing data DA-L register (address 00CF16). Reading from DA-H register (address 00CE16) means reading this transferred data. Accordingly, possible confirm data being output from output reading register.
8.7.5 Output after Reset
reset, output ports P00-P05 high-impedance state, contents register circuit undefined. Note that after reset, output undefined until setting register.
8.7.3 Operating 8-bit
following explains operation. First, output control register (address 00D516) reset, already automatically), that count source supplied. PWM0-PWM5 also used ports P00-P05, respectively. those port direction register "1." select each output polarity output control register (address 00D616). Then, bits output control register (PWM output). waveform output from output pins setting these registers. Figure 8.7.2 shows 8-bit timing. cycle composed (28) segments. kinds pulses, relative weight each (bits output inside circuit during cycle. Refer Figure 8.7.2 (a). 8-bit outputs waveform which logical (OR) pulses corresponding contents bits 8-bit register. Several examples shown Figure 8.7.2 (b). kinds output (HIGH area: 0/256 255/256) selected changing contents register. entirely HIGH selection cannot output, i.e. 256/256.
Table 8.7.1 Relation Between Low-order 6-bit Data Highlevel Area Increase Interval Low-order bits Data Area Longer than That Other 000000 000001 000010 000100 001000 010000 100000
Nothing
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Fig. 8.7.1 Block Diagram
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13579
Fig. 8.7.2 Timing
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Pulses showing weight each output 1024 f(XIN) Example 8-bit
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0016
0116
1816 (24)
FF16 (255)
M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP
"2C16" DA-H register.
"2816" DA-L register.
[DA-H register] writing DA-L latch]
[DA-L register]
writing DA-L
These bits decide HIGH level area fundamental waveform.
HIGH level area fundamental waveform
These bits decide smaller interval "tm" which HIGH leval area [HIGH level area fundamental waveform
Minimum resolution width 0.25
High-order 8-bit value latch
Fundamental waveform 0.25 µs44 14-bit output 8-bit counter
Waveform smaller interval "tm" specified low-order bits 0.25 µs45 0.25 14-bit output 8-bit counter
Fundamental waveform smaller interval "tm" which specified low-order bits changed. 0.25 µs44 0.25
14-bit output Low-order 6-bit output latch Repeat period 4096
Fig. 8.7.3 14-bit Timing (f(XIN) MHz)
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Output Control Register
output control register (PW) [Address 00D516] Name Functions count source Count source supply Count source stop selection (PW0) output DA/PN4 selection output (PW1) P00/PWM0 output selection (PW2) P01/PWM1 output selection (PW3) P02/PWM2 output selection (PW4) P03/PWM3 output selection (PW5) P04/PWM4 output selection (PW6) P05/PWM5 output selection (PW7) output PWM0 output output PWM1 output output PWM2 output output PWM3 output output PWM4 output output PWM5 output After reset
Fig. 8.7.4 Output Control Register
Output Control Register
output control register (PN) [Address 00D616] Name Functions
After reset
Nothing assigned. These bits write disable bits. When these bits read out, values "0." output polarity selection (PN2) output polarity selection (PN3) general-purpose output (PN4) Positive polarity Negative polarity Positive polarity Negative polarity Output Output HIGH
Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.7.5 Output Control Register
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COMPARATOR
comparator consists 6-bit converter comparator. comparator block diagram shown Figure 8.8.1. reference voltage "Vref" conversion bits control register (address 00EF16). comparison result analog input voltage reference voltage "Vref" stored control register (address 00EE16). comparison, corresponding bits direction register ports analog input pins. Write data select analog input pins bits control register write digital value corresponding compared bits control register voltage comparison started writing control register completed after machine cycles (NOP instruction
Data
control register
Bits
Comparator control
A-D1 A-D2 A-D3 A-D4 A-D5 A-D6
control register Analog signal switch Comparator
control register
Switch tree
Resistor ladder
Fig. 8.8.1 Comparator Block Diagram
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Control Register
control register (AD1) [Address 00EE16]
Name
Analog input selection bits (ADM0 ADM2)
Functions
A-D1 A-D2 A-D3 A-D4 A-D5 A-D6
After reset
This write disable bit. When this read out, value "0." Storage comparison result (ADM4) Input voltage reference voltage Input voltage reference voltage
Indeterminate
Nothing assigned. This bits write disable bits. When these bits read out, values "0."
Fig. 8.8.2 Control Register
Control Register
control register (AD2) [Address 00EF16]
Name converter bits (ADC0 ADC5)
Functions 1/128Vcc 3/128Vcc 5/128Vcc
After
123/128Vcc 125/128Vcc 127/128Vcc
Nothing assigned. These bits write disable bits. When these bits reed out, values
Fig. 8.8.3 Control Register
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CONVERTER
This microcomputer converters with 6-bit resolution. converter block diagram shown Figure 8.9.1. conversion performed setting value conversion register. result conversion output from setting output enable port output mode control register (bits address 00CD16). output analog voltage determined with value decimal number) conversion register.
output does build buffer, connect external buffer when driving low-impedance load. Note: Only M37221EASP/FP have built-in converter.
Data
conversion register [address 00DE16] Resistor ladder output enable P30/A-D5/DA1
conversion register [address 00DF16] Resistor ladder output enable P31/A-D6/DA2
Fig. 8.9.1 converter block diagram
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output mode control register
output mode control register(P3S) [Address 00CD16] Name
output form selection (P30S) output form selection (P31S) output enable (DA1S) output enable (DA2S)
Functions
CMOS output N-channel open-drain output CMOS output N-channel open-drain output input/output output input/output output
After reset
Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.9.2 output mode control register
conversion
register
conversion register (i=1, (DAi) [Addresses 00DE16, 00DF16] Name
Functions
0/64Vcc 1/64Vcc 2/64Vcc
After reset
conversion selection (DAi0 DAi5)
61/64Vcc 62/64Vcc 63/64Vcc
this "0." Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Note When M37221M4H/M6H/M8H/MAH-XXXSP/FP, there this register. 0016."
Fig. 8.9.3 conversion register
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8.10 CORRECTION FUNCTION
This correct program data ROM. addresses corrected program correction stored correction memory address. There vectors correction Vector address 02C016 Vector address 02E016 address data corrected into correction address register. When value counter matches data address address correction vector, main program branches correction program stored memory. return from correction program main program, code operand instruction (total bytes) necessary correction program. correction function controlled correction enable register.
Notes Specify first address code address) each instruction correction address. instruction (total bytes) return from correction program main program. same correction address both vectors
correction address (high-order) 021716 correction address (low-order) 021816
correction address (high-order) 021916 correction address (low-order) 021A16
Fig. 8.10.1 Correction Address Registers
Correction Enable Register
correction enable register (RCR) [Address 021B16]
Name
Vector enable (RCR0) Vector enable (RCR1)
Functions
Disabled Enabled Disabled Enabled
After reset
these bits "0." Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.10.2 Correction Enable Register
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8.11 FUNCTIONS
Table 8.11.1 outlines functions. This microcomputer incorporates control circuit characters lines. controlled control register. kinds characters displayed. colors specified each character kinds colors displayed screen. combination colors obtained using each output signal Characters displayed dots configuration obtain smooth character patterns (refer Figure 8.11.1). following shows procedure display characters screen. Write display character code RAM. Specify display color using color register. Write color register which display color RAM. Specify vertical position using vertical position register. Specify character size using character size register. Specify horizontal position using horizontal position register. Write display enable designated block display flag control register. When this done, starts according input VSYNC signal.
Table 8.11.1 Features Each Display Mode
Parameter Number display characters structure Kinds characters Kinds character sizes Attribute Character font coloring Character background coloring output Display position Display expansion (multiline display) Functions characters lines dots kinds kinds Border (black) screen kinds (per character unit) screen kinds (per character unit) Horizontal: levels, Vertical: levels Possible
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circuit extended display mode. This mode allows multiple lines lines more) displayed screen interrupting display each time line displayed rewriting data block which display been terminated software. Figure 8.11.1 shows configuration character. Figure 8.11.2 shows block diagram circuit. Figure 8.11.3 shows control register.
dots
dots
Fig. 8.11.1 Configuration Character Display Area
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Clock OSC1 OSC2 HSYNC VSYNC
Display oscillation circuit
Control registers Control circuit Horizontal position register Vertical position register Character size register Color register control register port control register clock selection register (address 00E016) (addresses 00E116, 00E216) (addresses 00E416) (addresses 00E616 00E916) (address 00EA16 (address 00EC16) (address 00ED16)
bits characters lines
dots dots characters
Shift register 12-bit Output circuit Shift register 12-bit
OUT1
OUT2
Data
Fig. 8.11.2 Block Diagram Circuit
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Control Register
control register (CC) [Address 00EA
Name All-blocks display control (CC0) (See note) Block display control (CC1) Block display control (CC2)
Functions All-blocks display All-blocks display Block display Block display Block display Block display
After reset
Nothing assigned. These bits write disable bits. When these bits read out, values "0." /OUT2 switch (CC7) OUT2
Note: Display controlled logical product (AND) between all-blocks display control each block control bit.
Fig. 8.11.3 Control Register
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8.11.1 Display Position
display positions characters specified units called "blocks." There blocks blocks characters displayed each block (refer "8.11.3 Memory OSD"). display position each block both horizontal vertical directions software. display start position horizontal direction selected blocks from 64-step display positions units oscillation cycle). display start position vertical direction each block selected from 128-step display positions units scanning lines.
Blocks displayed conformance with following rules: Block displayed after display block completed (Figure 8.11.4 (a)). When display position block overlapped with that block (Figure 8.11.4 (b)), block displayed front. When another block display position appears while block displayed (Figure 8.11.4 (c)),only block displayed. Similarly, when multiline display, block displayed after display block completed.
Block Block Example when each block separated
Block (Block displayed) Example when block overlaps with block
Block Block Block (second) displayed displayed
Example when block overlaps process block Notes indicates vertical display start position display block indicates horizontal display start position display block
Fig. 8.11.4 Display Position
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vertical display start position determined counting horizontal sync signal (HSYNC). this time, when VSYNC HSYNC positive polarity (negative polarity), count starts rising edge (falling edge) HSYNC signal after fixed cycle rising edge (falling edge) VSYNC signal. interval from rising edge (falling edge) VSYNC signal rising edge (falling edge) HSYNC signal needs enough time machine cycles more) avoid jitters. polarity HSYNC VSYNC signals select with port control register (address 00EC16).
machine cycles more VSYNC signal input 0.125 0.25 [µs] f(XIN) 8MHz) VSYNC control signal microcomputer Period counting HSYNC signal HSYNC signal input machine cycles more
(See note
count When bits port control register (address 00EC16) (negative polarity) Notes vertical position determined counting falling edge HSYNC signal after rising edge VSYNC control signal microcomputer. generate falling edge HSYNC signal near rising edge VSYNC control signal microcomputer avoid jitter. pulse width VSYNC HSYNC needs machine cycles more.
Fig. 8.11.5 Supplement Explanation Display Position
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vertical display start position each block steps (where each step (TH: HSYNC cycle)) values "0016" "7F16" vertical position register (addresses 00E116 00E216) vertical position register shown Figure 8.11.6.
Vertical Position Register
Vertical position register (CVi) [Addresses 00E1 00E216]
Name
Functions
After reset
Vertical display start positions steps (0016 7F16) (CVi CVi0 CVi6) Nothing assigned. This write disable bit. When this read out, value "0."
Indeterminate
Fig. 8.11.6 Vertical Position Register
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horizontal display start position common blocks, steps (where step 4TC, being oscillation cycle) values "0016" "3F16" bits horizontal position register (address 00D116). horizontal position register shown Figure 8.11.7.
Horizontal Position Register
Horizontal position register (HR) [Address 00E0
Name Horizontal display start positions (HR0 HR5)
Functions steps (0016 3F16)
After reset
Nothing assigned. These bits write disable bits. When thses bits read out, values "0."
Fig. 8.11.7 Horizontal Position Register
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8.11.2 Character Size
size characters displayed from sizes each block. character size register (address 00E416) character size. character size block specified using bits character size register; character size block specified using bits Figure 8.11.8 shows character size register. character size selected from sizes: minimum size, medium size large size. Each character size determined number scanning lines height (vertical) direction oscillating cycle display (TC) width (horizontal) direction. minimum size consists scanning line] [1TC]; medium size consists scanning lines] [2TC]; large size consists scanning lines] [3TC]. Table 8.11.2 shows relation between values character size register character sizes.
Character Size Register
Character size register (CS) [Address 00E416]
Name
Functions Minimum size Medium size Large size set. Minimum size Medium size Large size set.
After reset Indeterminate
Character size block selection bits (CS10, CS11) Character size block 2selection bits (CS20,CS21)
Indeterminate
Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.11.8 Character Size Register
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Minimum
Medium
Large
Horizontal display start position
Fig. 8.11.9 Display Start Position Each Character Size (Horizontal Direction)
Table. 8.11.2 Relation between Values Character Size Register Character Sizes
values character size register CSi1 CSi0
Character Width (horizontal) direction size oscillating cycle display Minimum Medium Large This available
Height (vertical) direction scanning lines
Notes display start position horizontal direction affected character size. other words, horizontal display start position common blocks even when character size varies with each block (refer Figure 8.11.9). indicates
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8.11.3 Clock
following types clocks selected display. Main clock supplied from Main clock supplied from divided Clock from ceramic resonator oscillator from pins OSC1 OSC2 Clock from ceramic resonator quartz-crystal oscillator supplied from pins OSC1 OSC2. clock each block selected clock selection register (address 00ED16). When selecting main clock, oscillation frequency MHz.
Clock Selection Register
clock selection register (CK) [Address 00ED16]
Name
Functions
After reset
clock Functions selection bits clock display supplied connecting (CK0,CK1) across pins OSC1 OSC2. Since main clock used clock display, oscillation frequency limited. Because this, character size width (horizontal) direction also limited. this case, pins OSC1 OSC2 also used input ports respectively. oscillation frequency f(XIN) oscillation frequency f(XIN)/1.5
clock supplied connecting following across pins OSC1 OSC2. ceramic resonator only quartz-crystal oscillator only feedback resistor (See note)
these bits "0."
Note: necessary connect other ceramic resonator quartz-crystal oscillator across pINs XOUT.
Fig. 8.11.10 clock selection Circuit
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8.11.4 Memory
There types memory OSD: (addresses 1000016 11FFF16) used store character data (addresses 060016 06B716) used specify characters colors displayed.
(addresses 1000016 11FFF16)
pattern data characters stored ROM. specify kinds character font, necessary write character code (Table 8.11.3) into RAM. capacity bytes. Since bytes required character data, stores kinds characters. space broadly divided into areas. [vertical dots] [horizontal (left side) dots] data display characters stored addresses 1000016 107FF16 1100016 117FF16 [vertical dots] [horizontal (right side) dots] data display characters stored addresses 1080016 10FFF16 1180016 11FFF16 (refer Figure 8.11.11). Note however that highorder bits data written addresses 1080016 10FFF16 1180016 11FFF16 must writing data "FX16"). Data character font specified shown Figure 8.11.11.
10XX016 11XX016
10XXF 11XXF
10XX016 +80016 11XX016 +80016
10XXF +80016 11XXF +80016
Fig. 8.11.11 Character Font Data Storing Address
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Table 8.11.3 Character Code List (Partially Abbreviated)
Character code Character data storage address Left dots lines 1000016 1000F16 1001016 1001F16 1002016 1002F16 1003016 1003F16
(addresses 060016 06B716)
allocated addresses 060016 06B716, divided into display character code specification part, color code specification part each block. Table 8.11.4 shows contents RAM. example, display character position (the left edge) block write character code address 060016, write color code 068016. structure shown Figure 8.11.12.
Right dots lines 1080016 1080F16 1081016 1081F16 1082016 1082F16 1083016 1083F16
0016
0116
0216
0316
7E16
107E016 107EF16 107F016 107FF16 1100016 1100F16 1101016 1101F16
10FE016 10FEF16 10FF016 10FFF16 1180016 1180F16 1181016 1181F16
7F16
8016
8116
FD16
117D016 117DF16 117E016 117EF16 117F016 117FF16
11FD016 11FDF16 11FE016 11FEF16 11FF016 11FFF16
FE16
FF16
Table 8.10.4 Contents
Block Display Position (from left) character character character 22nd character 23rd character 24th character used character character character 22nd character 23rd character 24th character Character Code Specification 060016 060116 060216 061516 061616 061716 061816 061F16 062016 062116 062216 063516 063616 063716 Color Specification 068016 068116 068216 069516 069616 069716 069816 069F16 06A016 06A116 06A216 06B516 06B616 06B716
Block
Block
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Block [Character specification] character 0600 24th character 0617 Character code Specify characters ("00 "FF16") [Color specification] character 0680 24th character 0697 Color register specification Specifying color register Specifying color register Specifying color register Specifying color register Block [Character specification] character 0620 24th character 0637 Character code Specify characters ("00 "FF16") [Color specification] character 06A0 24th character 06B7 Color register specification Specifying color register Specifying color register Specifying color register Specifying color register
Fig. 8.11.12 structure
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8.11.5 Color Register
color displayed character specified setting color registers (CO0 CO3: addresses 00E616 00E916) then specifying that color register with RAM. There color outputs; using combination these outputs, possible colors. However, since only color registers available, colors disabled time. outputs using bits color register. used specify whether character output blank output. Bits used specify character background color. Figure 8.11.12 shows color register.
Color Register
Color regist (COi) [Addresses 00E616 00E916]
Name
Functions
After reset
Nothing assigned. This write disable bit. When this read out, value "0." signal output selection (COi1) signal output selection (COi2) signal output selection (COi3) character output Character output character output Character output character output Character output
signal output (background) background color output selection (COi4) (See note Background color output OUT1 signal output control (COi5) (See notes Character output Blank output
background color output signal output (background) selection (COi6) (See note Background color output signal output (background) background color output selection (COi7) (See note Background color output
Notes When ="0" "1," there output same character border output from OUT1. "0." When only ="1" "0," there output from OUT2.
Fig. 8.11.13 Color Register
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Table 8.11.5 Display Example Character Background Coloring (When Green Character Blue Background Color)
Border selection register
Color register output output OUT1 output Character output Green output (See note Same output character
Video signal character color (green) mixed.
OUT2 output
COi7 COi6 COi5 COi4 COi3 COi2 COi1
(Note
output
Green output Same output Video signal character color (green) mixed. character Green output Blank output
image character background displayed.
Blank output
output (See note
Green Background Blank output Blue
image character background displayed.
output (See note
output Border output (Black)
Border output (Black)
Green output (See note
Video signal character color (green) mixed.
Green output Blank output Black
image character background displayed.
output (See note
Background color border
Border output (Black) Blank output
Green output (See note
Blue
image character background displayed.
Notes When COi5 COi4 "1," there output same character border output from OUT1 pin. COi5 COi4 "0." When only COi7 COi5 "0," there output from OUT2. portion which character dots displayed mixed with video signal. wavy-lined arrows Table denote video signals. indicates indicates
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8.11.6 Border
border clock dot) equivalent size added character displayed both horizontal vertical directions. border output from OUT1 pin. this case, color register (character output). Border specified units block using border selection register (address 00E516). Figure 8.11.14 shows border selection register. Table 8.11.6 shows relationship between values border selection register character border function.
Fig. 8.11.15 Example Border
Border Selection Register
Border selection register (MD) [Address 00E5
Name
Functions
After reset
Block OUT1 output Same output output Indeterminate border selection (MD10) Border output Nothing assigned. This write disable bit. When this read out, value "0."
Block OUT1 output Same output output Indeterminate border selection (MD20) Border output Nothing assigned. These bits write disable bits. When these bits read out, values "0."
Fig. 8.11.14 Border Selection Register
Table 8.11.6 Relationship between Value Border Selection Register Character Border Function
Border selection register MDi0 Functions Example output output OUT1 output output OUT1 output
Ordinary
Border including character
Note: indicates
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8.11.7 Multiline Display
This microcomputer ordinarily display lines screen displaying blocks different vertical positions. addition, display lines using interrupts. interrupt request occurs point which that display each block been completed. other words, when scanning line reaches point display position (specified vertical position registers) certain block, character display that block starts, interrupt occurs point which scanning line exceeds block.
Note: interrupt does occur display when block displayed. other words, block display display control control register (address 00EA16), interrupt request does occur (refer Figure 8.11.16).
Block display) Block display) Block display) Block display)
"OSD interrupt request" "OSD interrupt request" "OSD interrupt request" "OSD interrupt request"
Block display) Block display) Block (off display) Block (off display)
"OSD interrupt request" "OSD interrupt request" "OSD interrupt request" "OSD interrupt request"
display (OSD interrupt request occurs block display)
display (OSD interrupt request does occur block display)
Fig. 8.11.16 Note Occurence Interrupt
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8.11.8 Output Control
output pins OUT1 also function ports P52-P55. corresponding port direction register (address 00CB16) specify these pins output pins, specify general-purpose port OUT2 also function port P10. port control register (address 00EC16) (output mode). After that, control register specify output pin, specify port P10. input polarity HSYNC VSYNC, output polarity signals OUT1 OUT2 specified with port control register (address 00EC). bits specify positive polarity; specify negative polarity (refer Figure 8.11.13). port control register shown Figure 8.11.17.
Port Control Register
port control register (CRTP) [Address 00EC16]
Name HSYNC input polarity switch (HSYC) VSYNC input polarity switch (VSYC)
Functions Positive polarity input Negative polarity input Positive polarity input Negative polarity input
After reset
R/G/B output polarity switch Positive polarity output Negative polarity output (R/G/B) OUT2 output polarity switch (OUT2) OUT1 output polarity switch (OUT1) signal output switch (OP5) signal output switch bit(OP6) signal output switch bit(OP7) Positive polarity output Negative polarity output Positive polarity output Negative polarity output signal output signal output signal output MUTE signal output signal output signal output
Fig. 8.11.17 Port Control Register
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8.11.9 Raster Coloring Function
entire screen (raster) colored setting port control register. Since each pins switched raster coloring output, raster colors obtained. When character color/character background color overlaps with raster color, color OUT1, OUT2), specified character color/character background color, takes priority over raster color. This ensures that character color/character background color mixed with raster color. example raster coloring shown Figure 8.11.18.
Character color "RED" OUT1 OUT2) Border color "BLACK" (OUT1 OUT2) Background color "MAGENTA" OUT1 OUT2) Raster color "BLUE" OUT1 OUT2)
HSYNC OUT1 OUT2
Signals across A-A'
Fig. 8.11.18 Example Raster Coloring
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8.12 SOFTWARE RUNAWAY DETECT FUNCTION
This microcomputer function decode undefined instructions detect software runaway. When undefined op-code input instruction code during operation, following processing done. generates undefined instruction decoding signal. device internally reset undefined instruction decoding signal. result internal reset, same reset processing case ordinary reset operation done, program restarts from reset vector. Note, however, that software runaway detecting function cannot disabled.
SYNC
Address
01,S
01,S-1
01,S-2
FFFE16
FFFF16
ADH,
Data
Reset sequence
Undefined instruction decoding signal occurs.Internal reset signal occurs.
Undefined instruction decode Invalid Program counter Stack pointer ADL, ADH: Jump destination address reset
Fig. 8.12.1 Sequence Detecting Software Runaway Detection
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8.13. RESET CIRCUIT
When oscillation quartz-crystal oscillator ceramic resonator stable power source voltage hold RESET more, then return HIGH. Then, shown Figure 8.13.2, reset released program starts from address formed using content address FFFF16 high-order address content address FFFE16 low-order address. internal states microcomputer reset shown Figures 8.2.3 8.2.6. example reset circuit shown Figure 8.13.1. reset input voltage must kept less until power source voltage surpasses Poweron Power source voltage
Reset input voltage
953AL
RESET
Microcomputer Fig. 8.13.1 Example Reset Circuit
RESET Internal RESET SYNC Address Data 32768 count clock cycle (See note
FFFE
FFFF
ADH,
Reset address from vector table
Notes f(XIN) relation f(XIN) question mark indicates undefined state that depends previous state. Immediately after reset, timer timer connected hardware. this time, "FF16" timer "0716" timer Timer counts down with f(XIN)/16, reset state released timer overflow signal.
Fig. 8.13.2 Reset Sequence
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8.14 CLOCK GENERATING CIRCUIT
built-in clock generating circuit shown Figure 8.13.3. When instruction executed, internal clock stops HIGH. same time, timers connected hardware "FF16" timer "0716" timer Select f(XIN)/16 timer count source (set timer mode register before execution instruction). Moreover, timer timer interrupt enable bits disabled ("0") before execution instruction). oscillator restarts when external interrupt accepted. However, internal clock keeps HIGH until timer overflows, allowing time oscillation stabilization when ceramic resonator quartz-crystal oscillator used. When instruction executed, internal clock stops HIGH oscillator continues running. This wait state released when interrupt accepted (See note). Since oscillator does stop, next instruction executed once. When returning from stop wait state, accept interrupt, corresponding interrupt enable before executing instructions.
Note: wait mode, following interrupts invalid. VSYNC interrupt interrupt Timer interrupt using external clock input from TIM2 count source Timer interrupt using external clock input from TIM3 count source Timer interrupt using f(XIN)/2 count source Timer interrupt using f(XIN)/4096 count source f(XIN)/4096 interrupt Multi-master I2C-BUS interface interrupt
Microcomputer XOUT
COUT
Fig. 8.14.1 Ceramic Resonator Circuit Example
Microcomputer
External oscillation circuit
Fig. 8.14.2 External Clock Input Circuit Example circuit example using ceramic resonator quartz-crystal oscillator) shown Figure 8.14.1. circuit constants accordance with resonator manufacture's recommended values. circuit example with external clock input shown Figure 8.14.2. Input clock pin, open XOUT pin.
Interrupt request Interrupt disable flag Reset
instruction
Reset
Selection gate Connected black side reset. T34M Timer mode register
instruction
instruction
Internal clock
T34M0 T34M2
Timer
Timer
XOUT
Fig. 8.14.3 Clock Generating Circuit Block Diagram
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8.15 DISPLAY OSCILLATION CIRCUIT
oscillation circuit built-in clock oscillation circuits, that clock obtained simply connecting ceramic resonator, quartz-crystal oscillator across pins OSC1 OSC2. Which sub-clock oscillation circuit selected setting bits clock selection register (address 00ED16).
8.17 ADDRESSING MODE
memory access reinforced with kinds addressing modes. Refer SERIES <Software> User's Manual details.
8.18 MACHINE INSTRUCTIONS
There machine instructions. Refer SERIES <Soft- ware> User's Manual details.
TECHNICAL NOTES
divide ratio timer 1/(n+1). Even though instructions executed immediately after interrupt request bits modified program), those instructions only valid contents before modification. least instruction cycle needed (such NOP) between modification interrupt request bits execution instructions. After instructions executed decimal mode), instruction cycle (such NOP) needed before SEC, CLC, instruction executed. instruction needed immediately after execution instruction. order avoid noise latch-up, connect bypass capacitor 0.1µF) directly between pin-VSS pin- CNVSS pin, using thick wire. [Electric Characteristic Differences Between Mask Time PROM Version MCUs] There differences electric characteristics, operation margin, noise immunity, noise radiation between Mask Time PROM version MCUs difference manufacturing processes. When manufacturing application system with time PROM version then switching Mask version, please perform sufficient evaluations commercial samples Mask version.
OSC1
OSC2
Fig. 8.15.1 Display Oscillation Circuit
8.16 AUTO-CLEAR CIRCUIT
When power source supplied, auto-clear function will operate connecting following circuit RESET pin.
Circuit example
RESET
Circuit example
RESET
Note Make level change from point which power source voltage exceeds specified voltage.
Fig. 8.16.1 Auto-clear Circuit Example
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ABSOLUTE MAXIMUM RATINGS
Symbol Input voltage Input voltage Parameter Power source voltage CNVSS P00-P07,P10-P17, P20-P27, P30-P34, OSC1, XIN, HSYNC, VSYNC, RESET P00-P07, P10-P17, P20-P27, P30-P32, OUT1, D-A, XOUT, OSC2 OUT1, P10-P17, P20-P27, P30, P31, OUT1, P00-P07, P10, P15-P17, P20-P23, P30-P32, P11-P14 P24-P27 Conditions voltages based VSS. Output transistors off. Ratings -0.3 -0.3 -0.3 Unit
Output voltage
-0.3
IOL1
Circuit current Circuit current
(Note (Note
IOL2 IOL3 Topr Tstg
Circuit current Circuit current Power dissipation Operating temperature Storage temperature
(Note (Note
RECOMMENDED OPERATING CONDITIONS unless otherwise noted)
Symbol VIH1 Parameter Power source voltage (Note During CPU, operation Power source voltage input voltage P00-P07,P10-P17, P20-P27, P30-P34, SIN, SCLK, HSYNC, VSYNC, RESET, XIN, OSC1, TIM2, TIM3, INT1, INT2, INT3 input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) input voltage P00-P07,P10-P17, P20-P27, P30-P34 input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) input voltage HSYNC, VSYNC, RESET,TIM2, TIM3, INT1, INT2, INT3, XIN, OSC1, SIN, SCLK average output current (Note OUT1, D-A, P10-P17, P20-P27, P30, average output current (Note OUT1, D-A, P00-P07, P10, P15-P17, P20-P27, P30-P32 average output current (Note P11-P14 average output current (Note P24-P27 Oscillation frequency (for operation) (Note Oscillation frequency (for display) (Note OSC1 Input frequency TIM2, TIM3 Input frequency SCLK Input frequency SCL1, SCL2 Limits Typ. Unit
Min. 0.8VCC
Max.
VIH2 VIL1 VIL2 VIL3 IOL1 IOL2 IOL3 fCPU fCRT fhs1 fhs2 fhs3
0.7VCC
Notes total current that flows must (max.). total input current (IOL1 IOL2) must less. total average input current ports 4-P27 must less. Connect more capacitor externally across power source pins VCC-VSS reduce power source noise. Also connect more capacitor externally across pins VCC-CNVSS. quartz-crystal oscillator ceramic resonator oscillation circuit.
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ELECTRIC CHARACTERISTICS (VCC f(XIN) MHz, unless otherwise noted)
Symbol Parameter Power source current System operation Test conditions f(XIN) Stop mode OUT1, D-A, P10-P17 P20-P27, P30, OUT1, D-A, P00-P07, P10, P15-P17, P20-P23, P30-P32 P11-P14 P11-P14
Min.
Limits Typ. Max.
Unit
Test circuit
output voltage output voltage
f(XIN) -0.5 10.0
output voltage output voltage Hysteresis Hysteresis (Note)
IIZH IIZL
input leak current input leak current
RESET HSYNC, VSYNC, TIM2, TIM3, INT1-INT3, SCL1, SCL2, SDA1, SDA2, SIN, SCLK RESET, P00-P07, P10-P17, P20-P27, P30-P37, HSYNC, VSYNC RESET, P00-P07, P10-P17, P20-P27, P30-P37, HSYNC, VSYNC
switch connection resistor (between SCL1 SCL2, SDA1 SDA2)
Notes total current that flows must less. total input current (IOL1 IOL2) must less. total average input current ports P24-P27 must less. Connect more capacitor externally between power source pins VCC-VSS reduce power source noise. Also connect more capacitor externally between pins VCC-CNVSS. quartz-crystal oscillator ceramic resonator oscillation circuit. When using data slicer, MHz. P06, P07, P15, P23, have hysteresis when used interrupt input pins timer input pins. P11-P14 have hysteresis when these pins used multimaster I2C-BUS interface ports. P20-P22 have hysteresis when used serial pins. names each parameter described below. Dedicated pins: dedicated names. Double-/triple-function ports Same limits: port name. Function other than parts vary from port limits: function name.
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Power source voltage
8.00 OSC1 XOUT
Each output
OSC2
made operation state measured current, with ceramic resonator.
After setting each output HIGH level when measuring level when measuring VOL, each measured.
IIZH IIZL
Each input
Each input
4.5V
SCL1 SDA1
SCL2 SDA2
VBS/IBS
Fig.12.1 Measurement
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COMPARISON CHARACTERISTICS
(VCC f(XIN) MHz, unless otherwise noted) Symbol Resolution Absolute accuracy Parameter Test conditions Limits Min. Typ. Max. Unit bits
CONVERSION CHARACTERISTICS
(VCC f(XIN) MHz, unless otherwise noted) Symbol Parameter Test conditions Min. Limits Typ. Max. Unit bits
Resolution Absolute accuracy Setting time Output resistor Note: Only M37221EASP/FP have built-in converter.
MULTI-MASTER I2C-BUS LINE CHARACTERISTICS
Symbol tBUF tHD; tLOW tHD; tHIGH tSU; tSU; tSU; Parameter free time Hold time START condition period clock Rising time both signals Data hold time HIGH period clock Falling time both signals Data set-up time Set-up time repeated START condition Set-up time STOP condition Standard clock mode High-speed clock mode Unit Min. Max. Min. Max. 1000 20+0.1Cb 20+0.1Cb
Note: total capacitance line
tHD;STA tSU;STO
tBUF tLOW
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
Start condition Restart condition Stop condition
Fig.15.1 Definition Diagram Timing Multi-master I2C-BUS
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PROM PROGRAMMING METHOD
built-in PROM Time PROM version (blank) built-in EPROM version read programmed with generalpurpose PROM programmer using special programming adapter. Product M37221EASP M37221EAFP Name Programming Adapter PCA7408 PCA7439
PROM Time PROM version (blank) tested screened assembly process following processes. ensure proper operation after programming, procedure shown Figure 16.1 recommended verify programming.
Programming with PROM programmer
Screening (Caution) (150°C hours)
Verification with PROM programmer
Functional check target device
Caution screening temperature higher than storage temperature. Never expose 150°C exceeding hours.
Fig. 16.1 Programming Testing Time PROM Version
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DATA REQUIRED MASK ORDERS
following necessary when ordering mask product: Mask Order Confirmation Form Mark Specification Form Data written ROM, EPROM form (32-pin Type 27C101, three identical copies)
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TIME PROM VERSION M37221EASP/FP MARKING
M37221EASP XXXXXX
XXXXXX number
M37221EAFP XXXXXX
XXXXXX number
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APPENDIX Configuration (TOP VIEW)
HSYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 CNVSS XOUT
P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5 P31/A-D6 RESET OSC1/P33 OSC2/P34
Outline 42P4B
M37221M4H/M6H/M8H/MAH-XXXSP
P50/HSYNC P51/VSYNC P00/PWM0<b
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