XC95288XL High Performance CPLD DS055 (v1.7) August 2003 Pro
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XC95288XL High Performance CPLD
DS055 (v1.7) August 2003
Product Specification propagation delays Figure architecture overview.
Features
pin-to-pin logic delays System frequency macrocells with 6,400 usable gates Available small footprint packages 144-pin TQFP (117 user pins) 208-pin PQFP (168 user pins) 256-pin (192 user pins) 256-pin FBGA (192 user pins) 280-pin (192 user pins) Optimized high-performance 3.3V systems power operation tolerant pins accept 3.3V, 2.5V signals 3.3V 2.5V output capability Advanced 0.35 micron feature size CMOS Fast FLASHtechnology Advanced system features In-system programmable Superior pin-locking routability with Fast CONNECTII switch matrix Extra wide 54-input Function Blocks product-terms macrocell with individual product-term allocation Local clock inversion with three global product-term clocks Individual output enable output with local inversion Input hysteresis user boundary-scan inputs Bus-hold circuitry user inputs Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control individual outputs Enhanced data security features Excellent quality reliability Endurance exceeding 10,000 program/erase cycles year data retention protection exceeding 2,000V Pin-compatible with 5V-core XC95288 device 208-pin HQFP package
Power Estimation
Power dissipation CPLDs vary substantially depending system frequency, design application output loading. help reduce power dissipation, each macrocell XC9500XL device configured low-power mode (from default high-performance mode). addition, unused product-terms macrocells automatically deactivated software further conserve power. general estimate ICC, following equation used: ICC(mA) MCHS(0.175*PTHS 0.345) MCLP(0.052*PTLP 0.272) 0.04 MCTOG(MCHS +MCLP)* where: MCHS macrocells high-speed configuration PTHS average number high-speed product terms macrocell MCLP macrocells power configuration PTLP average number power product terms macrocell maximum clock frequency MCTOG average flip-flops toggling clock (~12%) This calculation derived from laboratory measurements XC9500XL part filled with 16-bit counters allowing single output (the LSB) enabled. actual value varies with design application should verified during normal system operation. Figure shows above estimation graphical form. more detailed discussion power consumption this device, Xilinx application note XAPP114, "Understanding XC9500XL CPLD Power."
Typical (mA)
Description
XC95288XL 3.3V CPLD targeted high-performance, low-voltage applications leading-edge communications computing systems. comprised 54V18 Function Blocks, providing 6,400 usable gates with
Clock Frequency (MHz)
DS055_01_121501
Figure Typical Frequency XC95288XL
2003 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
DS055 (v1.7) August 2003 Product Specification
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XC95288XL High Performance CPLD
JTAG Port
JTAG Controller
In-System Programming Controller
Fast CONNECT Switch Matrix
Function Block Macrocells
Function Block Macrocells
Blocks I/O/GCK I/O/GSR I/O/GTS
Function Block Macrocells
Function Block Macrocells
Function Block Macrocells
DS055_02_10130
Figure XC95288XL Architecture Function Block outputs (indicated bold line) drive Blocks directly.
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DS055 (v1.7) August 2003 Product Specification
XC95288XL High Performance CPLD
Absolute Maximum Ratings
Symbol TSTG TSOL Description Supply voltage relative Input voltage relative GND(1) Voltage applied 3-state output(1) Value -0.5 -0.5 -0.5 +150 +220 +150 Units
Storage temperature (ambient) Maximum soldering temperature (10s 1/16 Junction temperature
Notes: Maximum undershoot below must limited either 0.5V whichever easier achieve. During transitions, device pins undershoot -2.0 overshoot +7.0V, provided this over- undershoot lasts less than with forcing current being limited Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those listed under Operating Conditions implied. Exposure Absolute Maximum Ratings conditions extended periods time affect device reliability.
Recommended Operation Conditions
Symbol VCCINT VCCIO Parameter Supply voltage internal logic input buffers Commercial Industrial 70oC +85oC -40oC 0.80 VCCIO Units
Supply voltage output drivers 3.3V operation Supply voltage output drivers 2.5V operation Low-level input voltage High-level input voltage Output voltage
Quality Reliability Characteristics
Symbol VESD Data Retention Program/Erase Cycles (Endurance) Electrostatic Discharge (ESD) Parameter 10,000 2,000 Units Years Cycles Volts
Characteristic Over Recommended Operating Conditions
Symbol Parameter Output high voltage 3.3V outputs Output high voltage 2.5V outputs Output voltage 3.3V outputs Output voltage 2.5V outputs Input leakage current high-Z leakage current high-Z leakage current Test Conditions -4.0 -500 Max; Max; Max; VCCIO Max; 3.6V 5.5V capacitance Operating supply current (low power mode, active) GND; GND, load; VCCIO (Typical) Units
DS055 (v1.7) August 2003 Product Specification
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XC95288XL High Performance CPLD
Characteristics
XC95288XL-6 Symbol fSYSTEM TPSU TPCO TPOE TPOD TPAO TWLH TPLH Parameter output valid setup time before hold time after output valid Multiple internal operating frequency setup time before p-term clock input hold time after p-term clock input P-term clock output valid output valid output disable Product term output enabled Product term output disabled output valid P-term output valid pulse width (High Low) P-term clock pulse width (High Low) 208.3 10.8 11.8 XC95288XL-7 125.0 12.0 12.6 XC95288XL-10 10.0 100.0 10.2 11.0 11.0 14.5 15.3 Units
VTEST
Device Output
Output Type
VCCIO 3.3V 2.5V
VTEST 3.3V 2.5V
DS058_03_08150
Figure Load Circuit
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DS055 (v1.7) August 2003 Product Specification
XC95288XL High Performance CPLD
Internal Timing Parameters
XC95288XL-6 Symbol Buffer Delays TGCK TGSR TGTS TOUT Input buffer delay buffer delay buffer delay buffer delay Output buffer delay Output buffer enable/disable delay Product Term Control Delays TPTCK TPTSR TPTTS TPDI TSUI TECSU TECHO TCOI TAOI TRAI TLOGI TLOGILP TPTA TPTA2 TSLEW Product term clock delay Product term set/reset delay Product term 3-state delay Parameter XC95288XL-7 XC95288XL-10 Units
Internal Register Combinatorial Delays Combinatorial logic propagation delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock output valid time Register async. output delay Register async. recover before clock Internal logic delay Internal power logic delay Fast CONNECT feedback delay 10.0
Feedback Delays
Time Adders Incremental product term allocator delay (first incremental delay) Incremental product term allocator delay (subsequent incremental delay) Slew-rate limited delay
DS055 (v1.7) August 2003 Product Specification
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XC95288XL High Performance CPLD
XC95288XL Pins
Function MacroBScan Block cell TQ144 PQ208 BG256 FG256 CS280 Order Function Block Macrocell BScan TQ144 PQ208 BG256 FG256 CS280 Order
30(1) 32(1) 2(1) 3(1) 5(1) 6(1)
44(1) 46(1) 3(1) 5(1) 7(1) 9(1)
T2(1) U2(1) C2(1) D3(1) C1(1) E1(1)
M2(1) M3(1) D3(1) E3(1) D4(1) E5(1)
R3(1) T1(1) C2(1) C1(1) D3(1) E2(1)
Notes: Global control pin.
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DS055 (v1.7) August 2003 Product Specification
XC95288XL High Performance CPLD
XC95288XL Pins (Continued)
Function MacroBScan Block cell TQ144 PQ208 BG256 FG256 CS280 Order Function Block Macrocell BScan TQ144 PQ208 BG256 FG256 CS280 Order
38(1) 143(1)
55(1) 206(1)
W4(1) A2(1)
P5(1) C4(1)
W2(1) C4(1)
Notes: Global control pin.
DS055 (v1.7) August 2003 Product Specification
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XC95288XL High Performance CPLD
XC95288XL Pins (Continued)
Function MacroBScan Block cell TQ144 PQ208 BG256 FG256 CS280 Order Function Block Macrocell BScan TQ144 PQ208 BG256 FG256 CS280 Order
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DS055 (v1.7) August 2003 Product Specification
XC95288XL High Performance CPLD
XC95288XL Pins (Continued)
Function MacroBScan Block cell TQ144 PQ208 BG256 FG256 CS280 Order Function Block Macrocell BScan TQ144 PQ208 BG256 FG256 CS280 Order
DS055 (v1.7) August 2003 Product Specification
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XC95288XL High Performance CPLD
XC95288XL Global, JTAG Power Pins
Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR VCCINT 3.3V TQ144 PQ208 124, 153, BG256 V10, U13, W18, T20, M19, F20, E17, B17, B14, A10, FG256 CS280
U12, V16, R17, F10, L10, G11, M18, G18, D19, H11, J11, C18, A15, A11, T10, V14, V18, P18, K19, G17, C19, D14, D12, D11,
VCCIO 2.5V/3.3 109, 105, 132, 157, 172, 181,
D11, D15, C10, D17, F17, L17, R17, F11, L11, P11, D12, U10, U15, G13,
108, 114, 123,
A16, C14, B15, W10, Y10, Y14, 104,1 129, V15, U18, R19, K20, R10, R11, R12, R13, G18, B16, D13, 130, 141, 156, R14, R15, P15, G10, A11, J10, 163, 177, 190, J11, J12, K10, H10, J10, K10, P14, N15, M15, L15, K15, J15, H15, G15, F15, R15, K11, K12, L10, E15, E14, E13, E12, L11, L12, M10, E11, E10, M11, A19, A20, B19, B20, C19, W20, W19, U17, A19, C17,
Connects
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DS055 (v1.7) August 2003 Product Specification
XC95288XL High Performance CPLD
Device Part Marking Ordering Combination Information
Device Type Package Speed Operating Range
XC95xxxXL TQ144
This line related device part number
Sample package with part marking.
Device Ordering Part Marking Number XC95288XL-6TQ144C XC95288XL-6PQ208C XC95288XL-6BG256C XC95288XL-6FG256C XC95288XL-6CS280C XC95288XL-7TQ144C XC95288XL-7PQ208C XC95288XL-7BG256C XC95288XL-7FG256C XC95288XL-7CS280C XC95288XL-7TQ144I XC95288XL-7PQ208I XC95288XL-7BG256I XC95288XL-7FG256I XC95288XL-7CS280I XC95288XL-10TQ144C XC95288XL-10PQ208C XC95288XL-10BG256C XC95288XL-10FG256C XC95288XL-10CS280C XC95288XL-10TQ144I XC95288XL-10PQ208I XC95288XL-10BG256I XC95288XL-10FG256I XC95288XL-10CS280I
Speed (pin-to-pin delay)
Pkg. Symbol TQ144 PQ208 BG256 FG256 CS280 TQ144 PQ208 BG256 FG256 CS280 TQ144 PQ208 BG256 FG256 CS280 TQ144 PQ208 BG256 FG256 CS280 TQ144 PQ208 BG256 FG256 CS28
Pins 144-pin 208-pin 256-ball 256-ball 280-ball 144-pin 208-pin 256-ball 256-ball 280-pin 144-pin 208-pin 256-ball 256-ball 280-pin 144-pin 208-pin 256-ball 256-ball 280-ball 144-pin 208-pin 256-ball 256-ball 280-ball
Package Type Thin Quad Flat Pack Plastic Quad Flat Package Plastic Ball Grid Array Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Ball Grid Array Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Ball Grid Array Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Ball Grid Array Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Ball Grid Array Plastic Fineline Ball Grid Array Chipscale Package
Operating Range(1)
Notes: Commercial: +70°C; Industrial: -40° +85°C
DS055 (v1.7) August 2003 Product Specification
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XC95288XL High Performance CPLD
Revision History
following table shows revision history this document. Date 09/28/98 02/05/99 06/07/99 02/08/01 03/19/01 06/20/02 05/27/03 08/21/03 Version Initial Xilinx release. Updateed pinouts reflect BG256 (replaces BG352). Added speed CS280 package. Updated timing parameters, added FG256 package. Pinout corrections. Updated equation, page Updated Component Availability Chart: added Industrial. Added additional test conditions measurements Characteristics table. Updated TSOL from 220oC. Added Part Marking Updated Ordering Information. Updated Package Device Marking orientation. Revision
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DS055 (v1.7) August 2003 Product Specification
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