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XC95288XL High Performance CPLD

DS055 (v1.7) August 21, 2003

XC95288XL High Performance CPLD
DS055 (v1.7) August 21, 2003
Product Specification propagation delays of 6 ns. See Figure 2 for architecture overview.
Features
· · · · 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6, 400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I / O pins) - 208-pin PQFP (168 user I / O pins) - 256-pin BGA (192 user I / O pins) - 256-pin FBGA (192 user I / O pins) - 280-pin CSP (192 user I / O pins) Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I / O pins accept 5V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.35 micron feature size CMOS Fast FLASH technology Advanced system features - In-system programmable - Superior pin-locking and routability with Fast CONNECT II switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin with local inversion - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold circuitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10, 000 program / erase cycles - 20 year data retention - ESD protection exceeding 2, 000V Pin-compatible with 5V-core XC95288 device in the 208-pin HQFP package
Power Estimation
208 MHz
Typical ICC (mA)
94 MHz
Description
The XC95288XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of 16 54V18 Function Blocks, providing 6, 400 usable gates with
Clock Frequency (MHz)
Figure 1: Typical ICC vs. Frequency for XC95288XL
DS055 (v1.7) August 21, 2003 Product Specification
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XC95288XL High Performance CPLD
3 JTAG Port 1
JTAG Controller
In-System Programming Controller
54 I / O I / O I / O Fast CONNECT II Switch Matrix I / O 54 18 18
Function Block 1 Macrocells 1 to 18
Function Block 2 Macrocells 1 to 18
Function Block 3 Macrocells 1 to 18
Function Block 4 Macrocells 1 to 18
Function Block 16 Macrocells 1 to 18
Figure 2: XC95288XL Architecture Function Block outputs (indicated by the bold line) drive the I / O Blocks directly.
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DS055 (v1.7) August 21, 2003 Product Specification
XC95288XL High Performance CPLD
Absolute Maximum Ratings
Symbol VCC VIN VTS TSTG TSOL TJ Description Supply voltage relative to GND Input voltage relative to GND(1) Voltage applied to 3-state output(1) Value -0.5 to 4.0 -0.5 to 5.5 -0.5 to 5.5 -65 to +150 +220 +150 Units V V V
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Supply voltage for output drivers for 3.3V operation Supply voltage for output drivers for 2.5V operation Low-level input voltage High-level input voltage Output voltage
Quality and Reliability Characteristics
Symbol TDR NPE VESD Data Retention Program / Erase Cycles (Endurance) Electrostatic Discharge (ESD) Parameter Min 20 10, 000 2, 000 Max Units Years Cycles Volts
DC Characteristic Over Recommended Operating Conditions
DS055 (v1.7) August 21, 2003 Product Specification
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XC95288XL High Performance CPLD
AC Characteristics
XC95288XL-6 Symbol TPD TSU TH TCO fSYSTEM TPSU TPH TPCO TOE TOD TPOE TPOD TAO TPAO TWLH TPLH Parameter I / O to output valid I / O setup time before GCK I / O hold time after GCK GCK to output valid Multiple FB internal operating frequency I / O setup time before p-term clock input I / O hold time after p-term clock input P-term clock output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GSR to output valid P-term S / R to output valid GCK pulse width (High or Low) P-term clock pulse width (High or Low) Min 4.0 0 1.0 2.6 2.4 6.0 Max 6.0 3.8 208.3 6.8 4.5 4.5 8.4 8.4 10.8 11.8 XC95288XL-7 Min 4.8 0 1.6 3.2 4.0 6.5 Max 7.5 4.5 125.0 7.7 5.0 5.0 9.5 9.5 12.0 12.6 XC95288XL-10 Min 6.5 0 2.1 4.4 4.5 7.0 Max 10.0 5.8 100.0 10.2 7.0 7.0 11.0 11.0 14.5 15.3 Units ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns
VTEST
R1 Device Output R2 CL
Output Type
VCCIO 3.3V 2.5V
VTEST 3.3V 2.5V
Figure 3: AC Load Circuit
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DS055 (v1.7) August 21, 2003 Product Specification
XC95288XL High Performance CPLD
Internal Timing Parameters
XC95288XL-6 Symbol Buffer Delays TIN TGCK TGSR TGTS TOUT TEN Input buffer delay GCK buffer delay GSR buffer delay GTS buffer delay Output buffer delay Output buffer enable / disable delay Product Term Control Delays TPTCK TPTSR TPTTS TPDI TSUI THI TECSU TECHO TCOI TAOI TRAI TLOGI TLOGILP TF TPTA TPTA2 TSLEW Product term clock delay Product term set / reset delay Product term 3-state delay 2.0 1.0 6.2 2.4 1.4 7.2 2.7 1.8 7.5 ns ns ns 2.2 1.2 2.2 4.5 2.4 0 2.3 1.5 3.1 5.0 2.5 0 3.5 1.8 4.5 7.0 3.0 0 ns ns ns ns ns ns Parameter Min Max XC95288XL-7 Min Max XC95288XL-10 Min Max Units
Internal Register and Combinatorial Delays Combinatorial logic propagation delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output valid time Register async. S / R to output delay Register async. S / R recover before clock Internal logic delay Internal low power logic delay Fast CONNECT II feedback delay 2.0 1.6 2.0 1.6 6.0 1.0 5.5 1.6 0.4 0.2 6.2 2.6 2.2 2.6 2.2 7.5 1.4 6.4 3.5 1.3 0.5 6.4 3.0 3.5 3.0 3.5 10.0 1.8 7.3 4.2 1.7 1.0 7.0 ns ns ns ns ns ns ns ns ns ns ns
Feedback Delays
Time Adders Incremental product term allocator delay (first incremental delay) Incremental product term allocator delay (subsequent incremental delay) Slew-rate limited delay 0.8 0.3 3.5 0.8 0.3 4.0 1.0 0.4 4.5 ns ns ns
DS055 (v1.7) August 21, 2003 Product Specification
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XC95288XL High Performance CPLD
XC95288XL I / O Pins
Function MacroBScan Block cell TQ144 PQ208 BG256 FG256 CS280 Order Function Block Macrocell BScan TQ144 PQ208 BG256 FG256 CS280 Order
- P1 R1 - P3 R2 - P4 R3 T2(1) U1 T3 - U2(1) V1 - T4 - - C2(1) D2 - D3(1) E4 - C1(1) D1 E3 E2 E1(1) - F3 F2 - G3 -
- L2 L5 - M1 L4 - N1 L3 M2(1) M4 P1 - M3(1) N2 - N4 - - D3(1) D2 - E3(1) C2 - D4(1) B1 E4 C1 E5(1) - E2 F2 - E6 -
- N2 P1 - P2 P3 - P4 R1 R3(1) R2 R4 - T1(1) T2 - T3 - - C2(1) B1 - C1(1) D4 - D3(1) D2 D1 E3 E2(1) - E4 F3 - F4 -
Notes: 1. Global control pin.
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DS055 (v1.7) August 21, 2003 Product Specification
XC95288XL High Performance CPLD
XC95288XL I / O Pins (Continued)
Function MacroBScan Block cell TQ144 PQ208 BG256 FG256 CS280 Order Function Block Macrocell BScan TQ144 PQ208 BG256 FG256 CS280 Order
Notes: 1. Global control pin.
DS055 (v1.7) August 21, 2003 Product Specification
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XC95288XL High Performance CPLD
XC95288XL I / O Pins (Continued)
Function MacroBScan Block cell TQ144 PQ208 BG256 FG256 CS280 Order Function Block Macrocell BScan TQ144 PQ208 BG256 FG256 CS280 Order
- Y11 W11 - V11 U11 - Y12 W12 V12 U12 Y13 - W13 V13 - W14 - - A14 C13 - B13 A13 - D12 C12 A12 B11 C11 - B10 C10 - D10 -
- U9 T9 - W10 V10 - U10 W11 V11 U11 T11 - W12 V12 - T12 - - C14 B14 - A14 C13 - B13 A13 A12 C12 B12 - B11 C11 - A10 -
- Y15 V14 - W15 Y16 - U14 Y17 V16 Y18 V17 - Y19 V18 - W19 - - B18 C17 - D16 A18 - A17 C16 A16 C15 D14 - B15 A15 - C14 -
- P10 T12 - N10 T13 - M11 N11 T14 R12 T15 - R14 N13 - R13 - - B13 B14 - C13 A15 - C12 B12 D13 A14 E13 - A13 C11 - A12 -
- W13 V13 - U13 T13 - W14 T14 W15 V15 W16 - U16 W17 - W18 - - B19 B18 - B17 A18 - A17 D16 C16 B16 A16 - C15 B15 - D15 -
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DS055 (v1.7) August 21, 2003 Product Specification
XC95288XL High Performance CPLD
XC95288XL I / O Pins (Continued)
Function MacroBScan Block cell TQ144 PQ208 BG256 FG256 CS280 Order Function Block Macrocell BScan TQ144 PQ208 BG256 FG256 CS280 Order
- Y20 V19 - U19 T17 - V20 U20 T18 T19 R18 - P17 R20 - P18 - - G19 F19 - E20 G17 - F18 E19 D20 E18 D19 - C20 D18 - C18 -
- P13 P15 - N14 R16 - N15 M15 M13 P16 N16 - M14 L15 - L13 - - F15 E15 - F13 D16 - F14 C16 E14 D15 G12 - C15 D14 - B16 -
- V17 U18 - V19 U19 - T16 T17 T18 T19 R18 - R16 R19 - P17 - - G19 G16 - F19 F18 - F17 F16 E19 E17 E18 - E16 D18 - D17 -
- P19 P20 - N17 N18 - N19 N20 M17 M18 M20 - L19 L18 - L20 - - K19 K18 - K17 J20 - J19 J18 J17 H20 H19 - H18 H17 - G20 -
- M12 M16 - K14 L16 - K13 K15 L12 K16 J14 - J15 J13 - J16 - - K12 J12 - H15 H14 - G16 H13 G15 H16 F16 - H12 E16 - G14 -
- P16 P19 - N17 N18 - N19 N16 M19 M17 M16 - L19 L18 - L17 - - L16 K18 - K17 K16 - J19 J18 J17 J16 H19 - H18 H17 - H16 -
DS055 (v1.7) August 21, 2003 Product Specification
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XC95288XL High Performance CPLD
XC95288XL Global, JTAG and Power Pins
Pin Type I / O / GCK1 I / O / GCK2 I / O / GCK3 I / O / GTS1 I / O / GTS2 I / O / GTS3 I / O / GTS4 I / O / GSR TCK TDI TDO TMS VCCINT 3.3V TQ144 30 32 38 5 6 2 3 143 67 63 122 65 8, 42, 84, 141 PQ208 44 46 55 7 9 3 5 206 98 94 176 96 11, 59, 124, 153, 204 BG256 T2 U2 W4 C1 E1 C2 D3 A2 U16 W16 B12 W17 F1, P2, W5, Y9, V10, U13, W18, T20, M19, F20, E17, B17, B14, A10, C7, B3, G4 FG256 M2 M3 P5 D4 E5 D3 E3 C4 P12 R11 A10 N12 CS280 R3 T1 W2 D3 E2 C2 C1 C4 T15 U14 D13 U15
F4, F7, G6, H6, J6, E1, F2, N3, U5, W9, K6, L7, F8, L8, F9, V9, U12, V16, R17, L9, F10, L10, G11, M18, G18, D19, H11, J11, K11 C18, A15, A11, D8, A4 C3, F1, K1, N4, V2 T6, T10, V14, V18, P18, K19, G17, C19, D14, D12, D11, A7
VCCIO 2.5V / 3.3 V 1, 37, 55, 73, 109, 1, 26, 53, 65, 79, 127 92, 105, 132, 157, 172, 181, 184
D4, D6, D11, D15, F3, K4, D5, F6, L6, P6, C7, N9, C10, D17, F4, F17, K4, L17, R4, R17, U4, F11, L11, P11, D12, U6, U10, U15, U17 G13, L14
A1, A16, C14, T1, E5, F5, G5, H5, J5, B1, K3, T1, Y5, 2, 13, 24, 27, 42, B2, B15, R2, C3, K5, L5, M5, N5, R5, W10, Y10, Y14, 52, 68, 81, 93, 104, 1 08, 129, V15, U18, R19, K20, P3, G7, H7, J7, K7, R6, R7, R8, R9 R10, R11, R12, R13, G8, H8, J8, K8, G9, G18, B16, D13, 130, 141, 156, R14, R15, P15, H9, J9, K9, G10, A11, A6, J9, J10, 163, 177, 190, J11, J12, K9, K10, H10, J10, K10, P14, N15, M15, L15, K15, 207 J15, H15, G15, F15, R15, T16 K11, K12, L9, L10, E15, E14, E13, E12, L11, L12, M9, M10, E11, E10, E9, E8, M11, M12 E7, E6, P5 - A1, A19, A20, B19, B20, C19, W1, W2, W3, W20, Y1 A1, B2, W1, U3, W19, U17, A19, C17, A2, B3
No Connects
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DS055 (v1.7) August 21, 2003 Product Specification
XC95288XL High Performance CPLD
Device Part Marking and Ordering Combination Information
Device Type Package Speed Operating Range
XC95xxxXL TQ144 7C
This line not related to device part number
Sample package with part marking.
Device Ordering and Part Marking Number XC95288XL-6TQ144C XC95288XL-6PQ208C XC95288XL-6BG256C XC95288XL-6FG256C XC95288XL-6CS280C XC95288XL-7TQ144C XC95288XL-7PQ208C XC95288XL-7BG256C XC95288XL-7FG256C XC95288XL-7CS280C XC95288XL-7TQ144I XC95288XL-7PQ208I XC95288XL-7BG256I XC95288XL-7FG256I XC95288XL-7CS280I XC95288XL-10TQ144C XC95288XL-10PQ208C XC95288XL-10BG256C XC95288XL-10FG256C XC95288XL-10CS280C XC95288XL-10TQ144I XC95288XL-10PQ208I XC95288XL-10BG256I XC95288XL-10FG256I XC95288XL-10CS280I
Speed (pin-to-pin delay) 6 ns 6 ns 6 ns 6 ns 6 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns
Pkg. Symbol TQ144 PQ208 BG256 FG256 CS280 TQ144 PQ208 BG256 FG256 CS280 TQ144 PQ208 BG256 FG256 CS280 TQ144 PQ208 BG256 FG256 CS280 TQ144 PQ208 BG256 FG256 CS280
No. of Pins 144-pin 208-pin 256-ball 256-ball 280-ball 144-pin 208-pin 256-ball 256-ball 280-pin 144-pin 208-pin 256-ball 256-ball 280-pin 144-pin 208-pin 256-ball 256-ball 280-ball 144-pin 208-pin 256-ball 256-ball 280-ball
Package Type Thin Quad Flat Pack Plastic Quad Flat Package Plastic Ball Grid Array Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Ball Grid Array Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Ball Grid Array Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Ball Grid Array Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Ball Grid Array Plastic Fineline Ball Grid Array Chipscale Package
DS055 (v1.7) August 21, 2003 Product Specification
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XC95288XL High Performance CPLD
Revision History
The following table shows the revision history for this document. Date 09 / 28 / 98 02 / 05 / 99 06 / 07 / 99 02 / 08 / 01 03 / 19 / 01 06 / 20 / 02 05 / 27 / 03 08 / 21 / 03 Version 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Initial Xilinx release. Updateed pinouts to reflect BG256 (replaces BG352). Added -7 speed and CS280 package. Updated -6 AC and timing parameters, added FG256 package. Pinout corrections. Updated ICC equation, page 1. Updated Component Availability Chart: added -7 Industrial. Added additional IIH test conditions and measurements to DC Characteristics table. Updated TSOL from 260 to 220oC. Added Part Marking and Updated Ordering Information. Updated Package Device Marking Pin 1 orientation. Revision
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DS055 (v1.7) August 21, 2003 Product Specification