XC95288XV High-Performance CPLD DS050 (v2.5) August 2003 Pre

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XC95288XV High-Performance CPLD
DS050 (v2.5) August 2003
Preliminary Product Specification general estimate ICC, following equation used: PTOTAL PINT ICCINT VCCINT Separating internal power here convenient because XC9500XV CPLDs also separate corresponding power pins. strong function load capacitance driven, handled CVf. ICCINT another situation that reflects actual design considered internal switching speeds. estimation expression ICCINT (taken from simulation) ICCINT(mA) HS(0.122 PTHS 0.238) MCLP(0.042 PTLP 0.171) 0.04(MCHS fMAX MCTOG where: MCHS macrocells used high speed mode MCLP #macrocells used power mode PTHS average p-terms used high speed macrocell PTLP average p-terms used over power macrocell fMAX clocking frequency device MCTOG macrocells toggling each clock (12% frequently good estimate This calculation derived from laboratory measurements XC9500XV part filled with 16-bit counters allowing single output (the LSB) enabled. actual value varies with design application should verified during normal system operation. Figure shows above estimation graphical form. more detailed discussion power consumption this device, Xilinx application note XAPP361, "Planning High Speed XC9500XV Designs."
Features
macrocells with 6,400 usable gates Available small footprint packages 144-pin TQFP (117 user pins) 208-pin PQFP (168 user pins) 280-pin (192 user pins) 256-pin FBGA (192 user pins) Optimized high-performance 2.5V systems power operation Multi-voltage operation Advanced system features In-system programmable Four separate output banks Superior pin-locking routability with Fast CONNECTII switch matrix Extra wide 54-input Function Blocks product-terms macrocell with individual product-term allocation Local clock inversion with three global product-term clocks Individual output enable output Input hysteresis user boundary-scan inputs Bus-hold ciruitry user inputs Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control individual outputs Enhanced data security features Excellent quality reliability year data retention protection exceeding 2,000V
Description
XC95288XV 2.5V CPLD targeted high-performance, low-voltage applications leading-edge communications computing systems. comprised 54V18 Function Blocks, providing 6,400 usable gates with propagation delays
Typical (mA)
Power Estimation
Power dissipation CPLDs vary substantially depending system frequency, design application output loading. help reduce power dissipation, each macrocell XC9500XV device configured low-power mode (from default high-performance mode). addition, unused product-terms macrocells automatically deactivated software further conserve power.
Clock Frequency (MHz)
DS050_01_121501
Figure Typical Frequency XC95288XV
2003 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
DS050 (v2.5) August 2003 Preliminary Product Specification
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XC95288XV High-Performance CPLD
JTAG Port
JTAG Controller
In-System Programming Controller
Fast CONNECT Switch Matrix
Function Block Macrocells
Function Block Macrocells
Blocks I/O/GCK I/O/GSR I/O/GTS
Function Block Macrocells
Function Block Macrocells
Function Block Macrocells
DS055_02_10130
Figure XC95288XV Architecture (Function Block outputs (indicated bold line) drive Blocks directly.)
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DS050 (v2.5) August 2003 Preliminary Product Specification
XC95288XV High-Performance CPLD
Absolute Maximum Ratings
Symbol VCCIO TSTG TSOL Description Supply voltage relative Supply voltage output drivers Input voltage relative GND(1) Value -0.5 -0.5 -0.5 -0.5 +150 +220 +150 Units
Voltage applied 3-state output(1) Storage temperature (ambient) Maximum soldering temperature (10s 1/16 Junction temperature
Notes: Maximum undershoot below must limited either 0.5V whichever easier achieve. During transitions, device pins undershoot -2.0V overshoot +3.6V, provided this over- undershoot lasts less than with forcing current being limited Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those listed under Operating Conditions implied. Exposure Absolute Maximum Ratings conditions extended periods time affect device reliability.
Recommended Operation Conditions
Symbol VCCINT Parameter Supply voltage internal logic input buffers Commercial +70oC Industrial -40oC +85oC 2.37 2.37 2.37 1.71 2.62 2.62 2.62 1.89 VCCIO Units
VCCIO
Supply voltage output drivers 3.3V operation Supply voltage output drivers 2.5V operation Supply voltage output drivers 1.8V operation
Low-level input voltage High-level input voltage Output voltage
Quality Reliability Characteristics
Symbol VESD Data retention Program/Erase cycles (endurance) Electrostatic Discharge (ESD) Parameter 1,000 2,000 Units Years Cycles Volts
DS050 (v2.5) August 2003 Preliminary Product Specification
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XC95288XV High-Performance CPLD
Characteristics Over Recommended Operating Conditions
Symbol Parameter Output high voltage 3.3V outputs Output high voltage 2.5V outputs Output high voltage 1.8V outputs Output voltage 3.3V outputs Output voltage 2.5V outputs Output voltage 1.8V outputs Input leakage current Test Conditions -4.0 -1.0 -100 2.62V VCCIO 3.6V 3.6V 2.62V VCCIO 3.6V 3.6V 3.6V capacitance Operating supply current (low power mode, active) GND, load VCCIO Units
Input high-Z leakage current
±150
Characteristics
XC95288XV-6 Symbol fSYSTEM TPSU TPCO TPOE TPOD TPAO TWLH TPLH Parameter output valid setup time before hold time after output valid Multiple internal operating frequency setup time before p-term clock input hold time after p-term clock input P-term clock output valid output valid output disable Product term output enabled Product term output disabled output valid P-term output valid pulse width (High Low) P-term clock pulse width (High Low) 10.8 11.8 XC95288XV-7 125.0 12.0 12.6 XC95288XV-10 100.0 10.2 11.0 11.0 14.5 15.3 Units
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DS050 (v2.5) August 2003 Preliminary Product Specification
XC95288XV High-Performance CPLD
VTEST Device Output
Output Type
VCCIO 3.3V 2.5V 1.8V
VTEST 3.3V 2.5V 1.8V
DS050_03_110101
Figure Load Circuit
Internal Timing Parameters
XC95288XV-6 Symbol Buffer Delays TGCK TGSR TGTS TOUT TPTCK TPTSR TPTTS TPDI TSUI TECSU TECHO TCOI TAOI TRAI TLOGI TLOGILP TPTA TPTA2 TSLEW Input buffer delay buffer delay buffer delay buffer delay Output buffer delay Output buffer enable/disable delay Product term clock delay Product term set/reset delay Product term 3-state delay Combinatorial logic propagation delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock output valid time Register async. output delay Register async. recover before clock Internal logic delay Internal power logic delay Fast CONNECT feedback delay Incremental product term allocator delay Adjacent macrocell p-term allocator delay Slew-rate limited delay 10.0 Parameter XC95288XV-7 XC95288XV-10 Units
Product Term Control Delays
Internal Register Combinatorial Delays
Feedback Delays Time Adders
DS050 (v2.5) August 2003 Preliminary Product Specification
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XC95288XV High-Performance CPLD
XC95288XV Pins
Function Block Macrocell TQ144 PQ208 FG256 CS280 BScan Order Bank Function Block Macrocell TQ144 PQ208 FG256 CS280 BScan Order Bank
30(1) 32(1) 2(1) 3(1) 5(1) 6(1)
44(1) 46(1) 3(1) 5(1) 7(1) 9(1)
M3(1) E3(1) E5(1)
T1(1) C1(1) E2(1)
M2(1) R3(1)
D3(1) C2(1)
D4(1) D3(1)
Notes: Global control
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DS050 (v2.5) August 2003 Preliminary Product Specification
XC95288XV High-Performance CPLD
XC95288XV Pins (continued)
Function MacroBlock cell TQ144 PQ208 FG256 CS280 BScan Order Bank Function Block Macrocell TQ144 PQ208 FG256 CS280 BScan Order Bank
38(1)
55(1)
P5(1) W2(1)
143(1) 206(1) C4(1) C4(1)
Notes: Global control
DS050 (v2.5) August 2003 Preliminary Product Specification
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XC95288XV High-Performance CPLD
XC95288XV Pins (continued)
Function MacroBScan Block cell TQ144 PQ208 FG256 CS280 Order Bank Function MacroBScan Block cell TQ144 PQ208 FG256 CS280 Order Bank
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DS050 (v2.5) August 2003 Preliminary Product Specification
XC95288XV High-Performance CPLD
XC95288XV Pins (continued)
Function Block Macrocell TQ144 PQ208 FG256 CS280 BScan Order Bank Function MacroBlock cell TQ144 PQ208 FG256 CS280 BScan Order Bank
DS050 (v2.5) August 2003 Preliminary Product Specification
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XC95288XV High-Performance CPLD
XC95288XV Global, JTAG Power Pins
Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TDO(1) VCCINT 2.5V TQ144 PQ208 124, 153, FG256 F8., F10, L10, G11, H11, J11, L11, L14, C10, F11, D12, G10, H10, J10, K10, C14, P14, B15, R15, A16, CS280 U12, V16, R17, M18, G18, D19, C18, A15, A11, T10, V14, V18, K19, G17, C19, D14, D12, R10, R11, R12, R13, R14, R15, P15, N15, M15, L15, K15, J15, H15, G15, F15, E15, E14, E13, E12, E11, E10, W19, U17, A19, C17,
VCCIO1 VCCIO2 VCCIO3 VCCIO4
109, 108, 114, 123,
132, 157, 172, 181, 104, 108, 129, 130, 141, 156, 163, 177, 190,
Connects
Notes: voltage controlled VCCIO4.
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DS050 (v2.5) August 2003 Preliminary Product Specification
XC95288XV High-Performance CPLD
Device Part Marking Ordering Combination Information
Device Type Package Speed Operating Range
XC95xxxXV TQ144
This line related device part number
Sample package with part marking.
Device Ordering Part Marking Number XC95288XV-6TQ144C XC95288XV-6PQ208C XC95288XV-6FG256C XC95288XV-6CS280C XC95288XV-7TQ144C XC95288XV-7PQ208C XC95288XV-7FG256C XC95288XV-7CS280C XC95288XV-7TQ144I XC95288XV-7PQ208I XC95288XV-7FG256I XC95288XV-7CS280I XC95288XV-10TQ144C XC95288XV-10PQ208C XC95288XV-10FG256C XC95288XV-10CS280C XC95288XV-10TQ144I XC95288XV-10PQ208I XC95288XV-10FG256I XC95288XV-10CS280I
Speed (pin-to-pin delay)
Pkg. Symbol TQ144 PQ208 FG256 CS280 TQ144 PQ208 FG256 CS280 TQ144 PQ208 FG256 CS280 TQ144 PQ208 FG256 CS280 TQ144 PQ208 FG256 CS28
Pins 144-pin 208-pin 256-ball 280-ball 144-pin 208-pin 256-ball 280-pin 144-pin 208-pin 256-ball 280-pin 144-pin 208-pin 256-ball 280-ball 144-pin 208-pin 256-ball 280-ball
Package Type Thin Quad Flat Pack Plastic Quad Flat Package Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Fineline Ball Grid Array Chipscale Package Thin Quad Flat Pack Plastic Quad Flat Package Plastic Fineline Ball Grid Array Chipscale Package
Operating Range(1)
Notes: Commercial: +70°C; Industrial: -40° +85°C
DS050 (v2.5) August 2003 Preliminary Product Specification
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XC95288XV High-Performance CPLD
Revision History
Date 09/28/98 12/10/98 2/5/99 6/7/99 4/11/00 01/29/01 05/15/01 08/27/01 06/24/02 Version Original creation data sheet. Revision tables. Updated pinouts reflect BG256 (replaces BG352). speed CS280 package. Updated specifications, added bank information pinout tables. Added performance specification, deleted changed BG256 package FG256 package. Updated Frequency Figure Updated formula, Recommended Operation Conditions, Characteristics Internal Timing Parameters Changed VCCIO 3.3V from 3.13 (min), 3.46 3.60 (max); characteristics: added "low" current, changed "Input leakage high current"; Internal Timing: TAOI from 5.9. Updated equation page Updated Figure Load Circuit 1.8V parameters. Added second test condition measurement Characteristics. Added Part Marking Information Ordering Information. Changed Preliminary. Changed speed speed; added Industrial. Updated TSOL from 220oC. Updated Device Part Marking. Updated Package Device Marking orientation. Revision
05/27/03 08/21/03
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DS050 (v2.5) August 2003 Preliminary Product Specification

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