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34x0G Multistandard Sound Processor Family Edition Oct. 1999 6251


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34x0G Multistandard Sound Processor Family
Edition Oct. 1999 6251-476-3PD
34x0G
Contents Page Section 1.1. 1.2. 1.3. 2.1. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.6. 2.6.1. 2.6.2. 2.7. 2.8. 2.9. 2.10. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.4.1. 3.1.4.2. 3.1.4.3. 3.1.4.4. 3.2. 3.3. 3.3.1. 3.3.2. 3.3.2.1. 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.3.2.5. 3.3.2.6. Title
Introduction Features 34x0G Family Differences MSPD 34x0G Version List 34x0G Versions their Application Fields Functional Description Architecture 34x0G Family Sound Processing Analog Sound Input Demodulator: Standards Features Preprocessing Demodulator Signals Automatic Sound Select Preprocessing SCART Input Signals Source Selection Output Channel Matrix Audio Baseband Processing Automatic Volume Correction (AVC) Loudspeaker Headphone Outputs Subwoofer Output Quasi-Peak Detector SCART Signal Routing SCART SCART Select Stand-by Mode Interface Interface Digital Control Pins Status Change Indication Clock Oscillator Crystal Specifications Control Interface Interface Device Subaddresses Description CONTROL Register Protocol Description Proposals General 34x0G Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up Controlling 34x0G Programming Interface User Registers Overview Description User Registers STANDARD SELECT Register Refresh STANDARD SELECT Register STANDARD RESULT Register Write Registers Subaddress 10hex Read Registers Subaddress 11hex Write Registers Subaddress 12hex
34x0G
Contents, continued Page Section 3.3.2.7. 3.4. 3.5. 3.5.1. 3.5.2. 3.5.3. 3.5.4. 3.5.5. 3.5.6. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.2.4. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.3.8. 4.6.3.9. 4.6.3.10. 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. Title Read Registers Subaddress 13hex Programming Tips Examples Minimum Initialization Codes B/G-FM NICAM) BTSC-Stereo BTSC-SAP with Loudspeaker Channel FM-Stereo Radio Automatic Standard Detection Software Flow Interrupt driven STATUS Check Specifications Outline Dimensions Connections Short Descriptions Descriptions Configurations Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions General Recommended Operating Conditions Analog Input Output Recommendations Recommendations Analog Sound Input Signal Crystal Recommendations Characteristics General Characteristics Digital Inputs, Digital Outputs Reset Input Power-Up I2C-Bus Characteristics I2S-Bus Characteristics Analog Baseband Inputs Outputs, AGNDC Sound Inputs Power Supply Rejection Analog Performance Sound Standard Dependent Characteristics Appendix Overview TV-Sound Standards NICAM A2-Systems BTSC-Sound System Japanese Stereo System (EIA-J) Satellite Sound FM-Stereo Radio
34x0G
Contents, continued Page Section 6.1. 6.2. 6.3. 6.3.1. 6.3.1.1. 6.3.1.2. 6.3.2. 6.3.3. 6.3.4. 6.3.5. 6.3.6. 6.3.7. 6.4. 6.4.1. 6.4.2. 6.4.3. 6.4.4. 6.4.5. 6.4.6. 6.4.7. 6.5. 6.5.1. 6.5.2. 6.5.3. 6.5.4. 6.5.5. 6.5.6. 6.5.7. 6.6. 6.6.1. 6.6.2. 6.7. 6.7.1. 6.7.2. 6.8. 6.9. Title
Appendix Manual/Compatibility Mode Demodulator Write Read Registers Manual/Compatibility Mode Write Read Registers Manual/Compatibility Mode Manual/Compatibility Mode: Description Demodulator Write Registers Automatic Switching between NICAM Analog Sound Function Automatic Sound Select Mode Function Manual Mode Threshold Carrier-Mute Threshold Register AD_CV Register MODE_REG FIR-Parameter, Registers FIR1 FIR2 DCO-Registers Manual/Compatibility Mode: Description Demodulator Read Registers NICAM Mode Control/Additional Data Bits Register Additional Data Bits Register Bits Register NICAM Error Rate Register PLL_CAPS Readback Register AGC_GAIN Readback Register Automatic Search Function FM-Carrier Detection Satellite Mode Manual/Compatibility Mode: Description Write Registers Additional Channel Matrix Modes Volume Modes SCART1/2 Outputs Fixed Deemphasis Adaptive Deemphasis NICAM Deemphasis Identification Mode Stereo Systems Notch Manual/Compatibility Mode: Description Read Registers Stereo Detection Register Stereo Systems Level Register Demodulator Source Channels Manual Mode Terrestric Sound Standards Sound Standards Exclusions Audio Baseband Features Phase Relationship Analog Outputs Appendix 34x0G Version History Appendix Application Circuit Data Sheet History
34x0G
Other processed standards Japanese FM-FM multiplex standard (EIA-J) Stereo Radio standard. Current have perform adjustment procedures order achieve good stereo separation BTSC EIA-J. 34x0G optimum stereo performance without adjustments. 34x0G versions software downward-compatible 34x0D. 34x0G further simplifies controlling software. Standard selection requires single transmission only. 34x0G built-in automatic functions: able detect actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels identification signals evaluated internally with subsequent switching between mono/ stereo/bilingual; interaction necessary (Automatic Sound Selection). produced submicron CMOS technology. 34x0G available following packages: PLCC68, PSDIP64, PSDIP52, PQFP80, PLQFP64.
Multistandard Sound Processor Family Release Note: Revision bars indicate significant changes previous edition. hardware software description this document valid 34x0G version following versions.
Introduction 34x0G family single-chip Multistandard Sound Processors covers sound processing analog TV-Standards worldwide, well NICAM digital sound standards. full sound processing, starting with analog sound signal-in, down processed analog AF-out, performed single chip. Figure shows simplified functional block diagram 34x0G. This generation sound processing includes versions processing multichannel television sound (MTS) signal conforming standard recommended Broadcast Television Systems Committee (BTSC). noise reduction, alternatively, MICRONAS Noise Reduction (MNR) performed alignment free.
Sound Sound
Demodulator
Preprocessing
Loudspeaker Sound Processing
Loudspeaker Subwoofer
Source Select
I2S2 SCART1
Headphone Sound Processing
Headphone
Prescale
SCART2 SCART3 SCART4 MONO
SCART Input Select
SCART1 Prescale SCART Output Select SCART2
Fig. 1-1: Simplified functional block diagram 34x0G
34x0G
1.1. Features 34x0G Family Differences MSPD
Feature (New features available MSPD shaded gray.) 3400 3410
3420
3430
3440
3450
Standard Selection with single transmission Automatic Standard Detection terrestrial standards Automatic Sound Selection (mono/stereo/bilingual), registers MODUS, STATUS selectable sound (SIF) inputs Automatic Carrier Mute function Interrupt output programmable (indicating status change) Loudspeaker Headphone channel with volume, balance, bass, treble, loudness AVC: Automatic Volume Correction Subwoofer output with programmable low-pass complementary high-pass filter 5-band graphic equalizer loudspeaker channel Spatial effect loudspeaker channel Four Stereo SCART (line) inputs, Mono input; Stereo SCART outputs Complete SCART in/out switching matrix inputs; output Dolby Logic with 351xA coprocessor analog FM-Stereo satellite standards; AM-SECAM standard Simultaneous demodulation (very) high-deviation FM-Mono NICAM Adaptive deemphasis satellite (Wegener-Panda, acc. ASTRA specification) ASTRA Digital Radio (ADR) together with 3510A NICAM standards Demodulation BTSC multiplex signal channel Alignment free digital noise reduction BTSC Stereo Alignment free digital MICRONAS Noise Reduction (MNR) BTSC Stereo BTSC stereo separation (MSP 3420/40G also EIA-J) significantly better than spec. stereo detection BTSC system Korean FM-Stereo standard Alignment-free Japanese standard EIA-J Demodulation FM-Radio multiplex signal
1.2. 34x0G Version List
Version 3400G 3410G 3420G 3430G 3440G 3450G Status planned available available available available available Description Stereo (A2) Version NICAM Stereo (A2) Version NTSC Version Korea, BTSC with MICRONAS Noise Reduction (MNR), Japanese EIA-J system) BTSC Version NTSC Version Korea, BTSC with noise reduction, Japanese EIA-J system) Global Version (all sound standards)
34x0G
1.3. 34x0G Versions their Application Fields Table provides overview sound standards that processed 34x0G family. addition, 34x0G able handle terrestrial FM-Radio standard. With 34x0G, complete multimedia receiver covering sound standards together with terrestrial satellite radio sound built; even ASTRA Digital Radio processed (with 3510A coprocessor).
Table 1-1: Stereo Sound Standards covered 34x0G Family (details Appendix
Version 3400 TVSystem 5.5/5.85 6.5/5.85 6.0/6.552 6.5/6.2578125 3400 3410 6.5/6.7421875 6.5/5.7421875 3450 6.5/5.85 7.02/7.2 7.38/7.56 etc. 4.5/4.724212 3420, 3440 3430 FM-Radio 10.7 FM-Stereo (A2, D/K3) FM-Mono/NICAM (D/K, NICAM) FM-Mono FM-Stereo ASTRA Digital Radio (ADR) with 3510A FM-Stereo (A2) FM-FM (EIA-J) BTSC-Stereo FM-Stereo Radio SECAM-East Poland China, Hungary FM-Mono/NICAM AM-Mono/NICAM FM-Mono/NICAM FM-Stereo (A2, D/K1) FM-Stereo (A2, D/K2) SECAM-L SECAM-East Scandinavia, Spain France Hong Kong Slovak. Rep. currently broadcast Position Sound Carrier /MHz 5.5/5.7421875 Sound Modulation FM-Stereo (A2) Color System Broadcast e.g. Germany
3400
Satellite
Europe Sat. ASTRA
NTSC NTSC NTSC,
Korea Japan USA, Argentina USA, Europe
Filter Tuner Sound Mixer
Loudspeaker
Mono Vision Demodulator SCART1
Subwoofer
34x0G
Headphone
SCART Inputs Composite Video
SCART2
SCART3 SCART4
SCART1 SCART2
SCART Outputs
I2S1 Dolby Logic Processor 351xA
I2S2
Decoder 3510A
Fig. 1-2: Typical 34x0G application
Source Select
SCART Input Select
SC1_IN_L SC1_IN_R SC2_IN_L SC2_IN_R SC3_IN_L SC3_IN_R SC4_IN_L SC4_IN_R MONO_IN
SCART Output Select
Automatic Sound Select ANA_IN1+ ANA_IN2+
Functional Description
34x0G
DEMODULATOR
(incl. Carrier Mute)
Deemphasis: 50/75 DBX/MNR Panda1
FM/AM
FM/AM
Prescale
Loudspeaker Channel Matrix
Stereo
Bass/ Treble Equalizer
Loudness
Complementary Highpass
Spatial Effects
Balance
Volume
DACM_L
DACM_R
Decoded Standards: NICAM BTSC EIA-J FM-Radio
NICAM Deemphasis: Prescale
Stereo
Lowpass Beeper
Level Adjust
DACM_SUB
Stereo
Standard Sound Detection
Read Register
Headphone Channel Matrix
Volume Bass/ Treble
DACA_L
Loudness
Balance DACA_R
ADR-Bus Interface
I2S_DA_IN1
Interface
I2S1
Prescale
Channel Matrix
Interface
I2S_DA_OUT
I2S_DA_IN2
Interface
I2S2 Quasi-Peak Channel Matrix Quasi-Peak Detector Read Register
Prescale
SCART
SCART1 Channel Matrix
Volume
SCART1_L/R
Prescale SCART2 Channel Matrix Volume SCART2_L/R SC1_OUT_R SC1_OUT_L
SC2_OUT_L
SC2_OUT_R
Fig. 2-1: Signal flow block diagram 34x0G (input output names correspond names)
34x0G
BTSC-Mono SAP: Detection demodulation aural carrier resulting MTS/MPX signal. Detection evaluation pilot carrier, detection demodulation subcarrier. Processing noise reduction MICRONAS Noise Reduction (MNR). Japan Stereo: Detection demodulation aural carrier resulting signal. Demodulation evaluation identification signal demodulation (L-R)-carrier. FM-Satellite Sound: Demodulation carriers. Processing high-deviation mono narrow bandwidth mono, stereo, bilingual satellite sound according ASTRA specification. FM-Stereo-Radio: Detection demodulation aural carrier resulting signal. Detection evaluation pilot carrier demodulation (L-R)-carrier. demodulator blocks 34x0G versions have identical user interfaces. Even completely different systems like BTSC NICAM systems controlled same way. Standards selected means Standard Codes. Automatic processes handle standard detection identification without controller interaction. features 34x0G demodulator blocks Standard Selection: controlling demodulator minimized: parameters, such tuning frequencies filter bandwidth, adjusted automatically transmitting single value STANDARD SELECT register. standards, specific standard codes defined. Automatic Standard Detection: sound standard unknown, 34x0G automatically detect actual standard, switch that standard, respond actual standard code. Automatic Carrier Mute: prevent noise effects identification problems absence carrier, 34x0G offers carrier mute feature, which activated automatically sound standard selected means STANDARD SELECT register. carrier available demodulator channels, corresponding demodulator output muted.
2.1. Architecture 34x0G Family Fig. page shows simplified block diagram block diagram contains features 3450G. Other members 34x0G family have complete features: demodulator handles only subset standards presented demodulator block; NICAM processing only possible 3410G 3450G.
2.2. Sound Processing 2.2.1. Analog Sound Input input pins ANA_IN1+, ANA_IN2+, ANA_IN- offer possibility connect different sound (SIF) sources 34x0G. analog-to-digital conversion preselected sound signal done A/D-converter. analog automatic gain circuit (AGC) allows wide range input levels. highpass filters formed coupling capacitors pins ANA_IN1+ ANA_IN2+ Section "Appendix Application Circuit" page sufficient most cases suppress video components. Some combinations filters sound mixer ICs, however, show large picture components their outputs. this case, further filtering recommended.
2.2.2. Demodulator: Standards Features 34x0G able demodulate TV-sound standards worldwide including digital NICAM system. Depending 34x0G version, following demodulation modes performed: Systems: Detection demodulation separate carriers (FM1 FM2), demodulation evaluation identification signal carrier FM2. NICAM Systems: Demodulation decoding NICAM carrier, detection demodulation analog carrier. D/K-NICAM, carrier have maximum deviation kHz. Very high deviation FM-Mono: Detection robust demodulation carrier with maximum deviation kHz. BTSC-Stereo: Detection demodulation aural carrier resulting MTS/MPX signal. Detection evaluation pilot carrier, demodulation (L-R)-carrier detection subcarrier. Processing noise reduction MICRONAS Noise Reduction (MNR).
34x0G
2.2.3. Preprocessing Demodulator Signals NICAM signals must processed deemphasis filter adjusted level. analog demodulated signals must processed deemphasis filter, adjusted level, dematrixed. correct deemphasis filters already selected setting standard STANDARD SELECT register. level adjustment done means NICAM prescale registers. necessary dematrix function depends selected sound standard actual broadcasted sound mode (mono, stereo, bilingual). manually Matrix Mode register automatically Automatic Sound Selection.
"Stereo channel: Analog digital mono sound, stereo available. case bilingual broadcast, contains language left right). "Stereo channel: Analog digital mono sound, stereo available. case bilingual broadcast, contains language left right). shows source channel assignment demodulated signals case manual mode. manual mode required, more information found section "Demodulator Source Channels Manual Mode" page Table show source channel assignment demodulated signals case Automatic Sound Select mode sound standards. Note: analog primary input channel contains signal mono FM/AM carrier signal carrier. secondary input channel contains signal carrier, signal carrier, signal.
2.2.4. Automatic Sound Select Automatic Sound Select mode, dematrix function automatically selected based identification information STATUS register. interaction necessary when broadcasted sound mode changes (e.g. from mono stereo). demodulator supports identification check switching between mono compatible standards (standards that have same mono carrier) automatically non-audible. B/G-FM B/G-NICAM selected, will switch between these standards. same action performed standards: D/K1-FM, D/K2-FM, D/K-NICAM. Switching only done absence stereo bilingual identification. identification found, keeps detected standard. case high bit-error rates, 34x0G automatically falls back from digital NICAM sound analog mono. Table summarizes actions that take place when Automatic Sound Select switched provide more flexibility, Automatic Sound Select block prepares four different source channels demodulated sound (Fig 2-3). choosing four demodulator channels, preferred sound mode selected each output channels (loudspeaker, headphone, etc.). This done means Source Select registers. following source channels demodulated sound defined: "FM/AM" channel: Analog mono sound, stereo available. case NICAM, analog mono only mono). "Stereo A/B" channel: Analog digital mono sound, stereo available. case bilingual broadcast, contains both languages (left) (right).
2.3. Preprocessing SCART Input Signals SCART inputs need only adjusted level means SCART prescale registers.
primary channel secondary channel
FM/AM Source Select FM-Matrix Prescale
FM/AM
Matrix Output-Ch. Matrices must according standard Matrix
NICAM
NICAM
NICAM (Stereo A/B)
NICAM
Prescale
Fig. 2-2: Source channel assignment demodulated signals Manual Mode
primary channel secondary channel
FM/AM
FM/AM
Matrix Source Select Output-Ch. Matrices must once stereo
Prescale
Automatic Sound Select
Stereo
NICAM
NICAM
Stereo
NICAM
Prescale
Stereo
Matrix
Fig. 2-3: Source channel assignment demodulated signals Automatic Sound Select Mode
34x0G
Table 2-1: Performed actions Automatic Sound Selection
Selected Sound Standard B/G-FM, D/K-FM, M-Korea, M-Japan B/G-NICAM, L-NICAM, I-NICAM, D/K-NICAM Performed Actions Evaluation identification signal automatic switching mono, stereo, bilingual. Preparing four demodulator source channels according Table 2-2. Identification acquired after Evaluation NICAM-C-bits automatic switching mono, stereo, bilingual. Preparing four demodulator source channels according Table 2-2. NICAM detection acquired within case NICAM reception, switches automatically FM/AM mono switches back NICAM possible. hysteresis prevents periodical switching. B/G-FM, B/G-NICAM D/K1-FM, D/K2-FM, D/K3-FM, D/K-NICAM Automatic searching stereo/bilingual-identification case mono transmission. Automatic nonaudible changes between Dual-FM FM-NICAM standards while listening basic FM-Mono sound carrier. Example: starting with B/G-FM-Stereo, there will periodical alternation B/G-NICAM absence FM-Stereo/Bilingual NICAM-identification. Once identification detected, keeps corresponding standard. Evaluation pilot signal automatic switching mono stereo. Preparing four demodulator source channels according Table 2-2. Detection carrier. Pilot detection acquired after absence SAP, switches BTSC-Stereo available. detected, switches automatically (see Table 2-2).
BTSC-STEREO, Radio
BTSC-SAP
Table 2-2: Sound modes demodulator source channels with Automatic Sound Select
Source Channels Automatic Sound Select Mode Broadcasted Sound Standard M-Korea B/G-FM D/K-FM M-Japan Selected Standard Code3) 081) 0B1) Broadcasted Sound Mode FM/AM
(source select:
Stereo
(source select:
Stereo
(source select:
Stereo
(source select:
MONO STEREO BILINGUAL: Languages
Mono Stereo Left Right analog Mono analog Mono analog Mono analog Mono Mono Stereo Mono Stereo Left Mono Right Left Mono Right Mono Stereo
Mono Stereo Left Right analog Mono NICAM Mono NICAM Stereo Left NICAM Right NICAM Mono Stereo Mono Stereo Left Mono Right Left Mono Right Mono Stereo
Mono Stereo analog Mono NICAM Mono NICAM Stereo NICAM Mono Stereo Mono Stereo Mono Mono Mono Stereo
Mono Stereo analog Mono NICAM Mono NICAM Stereo NICAM Mono Stereo Mono Stereo Mono Stereo
B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM
(with high deviation
032) 042), 052)
NICAM available error rate high MONO STEREO BILINGUAL: Languages
MONO STEREO
BTSC
MONO+SAP STEREO+SAP MONO+SAP STEREO+SAP
Radio
MONO STEREO
Automatic Sound Select process will automatically switch mono compatible analog standard. Automatic Sound Select process will automatically switch mono compatible digital standard. Standard Codes defined Table page
34x0G
2.4. Source Selection Output Channel Matrix Source Selector makes possible distribute source signals (one demodulator source channels, SCART, input) desired output channels (loudspeaker, headphone, etc.). input output signals processed simultaneously. Each source channel identified unique source address. each output channel, sound mode sound sound stereo, mono means output channel matrix. Automatic Sound Select output channel matrix stay fixed stereo (transparent) demodulated signals. output level [dBr]
input level [dBr] Fig. 2-4: Simplified characteristics
2.5. Audio Baseband Processing 2.5.1. Automatic Volume Correction (AVC) Different sound sources (e.g. terrestrial channels, channels, SCART) fairly often have same volume level. Advertisements during movies usually have higher volume level than movie itself. This results annoying volume changes. Automatic Volume Correction (AVC) solves this problem equalizing volume level. prevent clipping, AVC's gain decreases quickly dynamic boost conditions. suppress oscillation effects, gain increases rather slowly level inputs. decay time programmable means register (see page 31). input signals ranging from dBr, maintains fixed output level dBr. Fig. shows output level versus input level. prescale volume registers level corresponds full scale input/output. This SCART input/output Vrms Loudspeaker output Vrms
2.5.2. Loudspeaker Headphone Outputs following baseband features implemented loudspeaker headphone output channels: bass/treble, loudness, balance, volume. square wave beeper added loudspeaker headphone channel. loudspeaker channel additionally performs: equalizer (not simultaneously with bass/treble), spatial effects, subwoofer crossover filter.
2.5.3. Subwoofer Output subwoofer signal created combining left right channels directly behind loudness block using formula (L+R)/2. division converter will overloaded, even with full scale input signals. subwoofer signal filtered third-order low-pass with programmable corner frequency followed level adjustment. loudspeaker channels, complementary high-pass filter switched Subwoofer loudspeaker output same volume (Loudspeaker Volume Register).
2.5.4. Quasi-Peak Detector quasi-peak readout register used read quasi-peak level input source. feature based following filter time constants: attack time: decay time:
34x0G
2.7. Interface possible route external coprocessor special effects, like surround processing sound field processing. Routing done with each input source output channel inputs outputs. possible interface formats supported: SONY format: I2S_WS changes word boundaries. PHILIPS format: I2S_WS changes I2S_CL period before word boundaries. interface consists five pins: I2S_DA_IN1, I2S_DA_IN2: input, four channels (two channels line, 2*16 bits) sampling cycle kHz) transmitted. I2S_DA_OUT: output, channels (2*16 bits) sampling cycle kHz) transmitted. I2S_CL: Gives timing transmission serial data (1.024 MHz). I2S_WS: I2S_WS word strobe line defines left right sample. 34x0G normally serves master interface. this case, clock word strobe lines driven 34x0G. slave mode, these lines input 34x0G master clock synchronized times I2S_WS rate kHz). NICAM operation possible this mode. options means MODUS register (see page 25). precise timing diagram shown Fig. 4-26 page
2.6. SCART Signal Routing 2.6.1. SCART SCART Select SCART Input Select SCART Output Select blocks include full matrix switching facilities. design with four pairs SCART-inputs pairs SCART-outputs, external switching hardware required. switches controlled user register (see page 37).
2.6.2. Stand-by Mode 34x0G switched first pulling STANDBYQ then (after delay) switching 5-V, keeping power supply (`Standby'-mode), SCART switches maintain their position function. This allows copying from selected SCART-inputs SCART-outputs set's stand-by mode. case power starting from stand-by (switching supply, RESETQ going high later), internal registers except register (page reset default configuration (see Table page 20). reset position register becomes active after first transmission into Baseband Processing part (subaddress 12hex). transmitting register first, reset state redefined.
34x0G
2.8. Interface ASTRA Digital Radio System (ADR), 3400G, 3410G 3450G performs preprocessing such carrier selection filtering. 3-line ADR-bus, resulting signals transferred 3510A coprocessor, where source decoding performed. prepared upgrade with additional board, following lines 34x0G should provided feature connector: AUD_CL_OUT I2S_DA_IN1 I2S_DA_IN2 I2S_DA_OUT I2S_WS I2S_CL ADR_CL, ADR_WS, ADR_DA more details, please refer 3510A data sheet.
2.10. Clock Oscillator Crystal Specifications 34x0G derives internal system clocks from 18.432-MHz oscillator. NICAM I2SSlave mode, clock phase-locked corresponding source. Therefore, possible NICAM I2S-Slave mode same time. proper performance, clock oscillator requires 18.432-MHz crystal. Note that phase-locked modes (NICAM, I2S-Slave), crystals with tighter tolerance required. Remark using crystal: External capacitors each crystal ground required. They necessary tuning open-loop frequency internal stabilizing frequency closed-loop operation. higher capacitors, lower resulting clock frequency. nominal free running frequency should match 18.432 closely possible. Clock measurements should done AUD_CL_OUT. This must activated this purpose (see Table page 25).
2.9. Digital Control Pins Status Change Indication static level digital input/output pins D_CTR_I/O_0/1 switchable between HIGH I2C-bus means register (see page 37). This enables controlling external hardware switches other devices I2C-bus. digital input/output pins high impedance means MODUS register (see page 25). this mode, pins used input. current state read STATUS register (see page 26). Optionally, D_CTR_I/O_1 used interrupt request signal controller, indicating changes read register STATUS. This makes polling unnecessary, interactions reduced minimum (see STATUS register page MODUS register page 25).
34x0G
performed some other function (for example, servicing internal interrupt), will hold clock line I2C_CL force transmitter into wait state. positions within transmission where this happen indicated 'Wait' section 3.1.3. maximum wait period during normal operation mode less than
Control Interface 3.1. Interface 3.1.1. Device Subaddresses 34x0G controlled slave interface. selected transmitting 34x0G device addresses. order allow three connected single bus, address select (ADR_SEL) been implemented. With ADR_SEL pulled high, low, left open, 34x0G responds different device addresses. device address pair defined write address (80, hex) read address (81, hex) (see Table 3-1). Writing done sending device write address, followed subaddress byte, address bytes, data bytes. Reading done sending write device address, followed subaddress byte address bytes. Without sending stop condition, reading addressed data completed sending device read address (81, hex) reading bytes data. Refer section 3.1.3. protocol section "Programming Tips" page proposals 34x0G telegrams. Table list available subaddresses. Besides possibility hardware reset, also reset means RESET CONTROL register controller bus. internal architecture 34x0G, cannot react immediately request. typical response time about cannot accept another complete byte data until
Internal hardware error handling: case internal hardware error (e.g. interruption power supply MSP), MSP's wait period extended After this time period elapses, releases data clock lines.
Indication solving error status: 34x0G-versions until indicate error status, further acknowledge bits will left high. then reset transmitting reset condition CONTROL while ignoring missing acknowledge bits. 34x0G-versions from indicate error status, remaining acknowledge bits actual I2C-protocol will left high. Additionally, bit[14] CONTROL one. then reset transmitting reset condition CONTROL.
Indication reset (only versions from on): reset, even caused unstable reset line etc., indicated bit[15] CONTROL. general timing diagram shown Fig. 4-25 page
34x0G
Table 3-1: Device Addresses
ADR_SEL Mode device address Write Read Write High Read
Left Open Write Read
Table 3-2: Subaddresses
Name CONTROL TEST WR_DEM RD_DEM WR_DSP RD_DSP Binary Value 0000 0000 0000 0001 0001 0000 0001 0001 0001 0010 0001 0011 Value Mode Read/Write Write Write Write Write Write Function Write: Software reset (see Table 3-3) Read: Hardware error status only internal write address demodulator read address demodulator write address read address
3.1.2. Description CONTROL Register Table 3-3: CONTROL Write Register
Name CONTROL Subaddress Bit[15] (MSB) RESET normal Bits[14:0]
Table 3-4: CONTROL Read Register (only 34x0G-versions from
Name CONTROL Subaddress Bit[15] (MSB) Reset status after last reading CONTROL: reset occured reset occured Bit[14] Internal hardware status: error occured internal error occured Bits[13:0] interest
Reading CONTROL will reset bits[15,14] CONTROL. After Power-on, bit[15] CONTROL will set; must read once resetted.
34x0G
3.1.3. Protocol Description
Write Demodulator
Wait write device address sub-addr addr-byte addr-byte data-byte- data-byte high high
Read from Demodulator
Wait write device address sub-addr addr-byte addr-byte high read device address Wait data-byte- data-byte high
Write Control Test Registers
Wait write device address sub-addr data-byte data-byte high
Note: Wait
I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: I2C_DA from slave MSP, light gray) master controller dark gray) Acknowledge-Bit: HIGH I2C_DA from master (dark gray) indicate `End Read' from indicating internal error state I2C-Clock line held low, while processing command. This waiting time max.
I2C_DA I2C_CL
Fig. 3-1: protocol (MSB first; data must stable while clock high)
34x0G
3.1.4. Proposals General 34x0G Telegrams 3.1.4.1. Symbols write device address (80hex, 84hex 88hex) read device address (81hex, 85hex 89hex) Start Condition Stop Condition Address Byte Data Byte
3.1.4.2. Write Telegrams <daw <daw <daw write CONTROL register write data into demodulator write data into
3.1.4.3. Read Telegrams <daw <dar <daw <dar read data from demodulator read data from
3.1.4.4. Examples RESET statically Clear RESET demodulator stand. 03hex Read STATUS loudspeaker channel source NICAM Matrix STEREO
More examples typical application protocols listed section "Programming Tips" page
34x0G
3.2. Start-Up Sequence: Power-Up Controlling After POWER RESET (see Fig. 4-24), inactive state. registers reset position (see tables 3-6), analog outputs muted. controller initialize registers which non-default setting necessary.
3.3. 34x0G Programming Interface 3.3.1. User Registers Overview 34x0G controlled means user registers. complete list user registers given following tables. registers partitioned into Demodulator section (Subaddress 10hex writing, 11hex reading) Baseband Processing sections (Subaddress 12hex writing, 13hex reading). Write read registers 16-bit wide, whereby denoted [15]. Transmissions have take place 16-bit words (two byte transfers, with most significant byte transferred first). write registers, except demodulator write registers, readable. Unused parts 16-bit write registers must zero. Addresses given this table must written. reasons software compatibility 34x0D, Manual/Compatibility Mode available. More read write registers together with detailed description this mode found "Appendix Manual/Compatibility Mode" page overview 34x0G Write Registers shown Table 3-5; Read Registers given Table 3-6.
34x0G
Table 3-5: List 34x0G Write Registers
Write Register Address (hex) Bits Description Adjustable Range Reset Page
Subaddress 10hex Registers readable STANDARD SELECT MODUS [15.0] [15.0] Initial Programming complete Demodulator Demodulator, Automatic options
Subaddress 12hex Registers readable using Subaddress 13hex Volume loudspeaker channel Volume Mode loudspeaker channel Balance loudspeaker channel [L/R] Balance mode loudspeaker Bass loudspeaker channel Treble loudspeaker channel Loudness loudspeaker channel Loudness filter characteristic Spatial effect strength loudspeaker Spatial effect mode/customize Volume headphone channel Volume Mode headphone channel Volume SCART1 output channel Loudspeaker source select Loudspeaker channel matrix Headphone source select Headphone channel matrix SCART1 source select SCART1 channel matrix source select channel matrix Quasi-peak detector source select Quasi-peak detector matrix Prescale SCART input Prescale FM/AM matrix Prescale NICAM Prescale I2S2 SCART Switches D_CTR_I/O Beeper Prescale I2S1 Mode tone control
[15.8] [7.0]
[+12 -114 MUTE] Steps, Reduce Volume Tone Control Compromise [0.100 100% 0.100%] [-127.0 -127.0 [Linear mode logarithmic mode] [+20 [+15 [NORMAL, SUPER_BASS] [-100%.OFF.+100%] [SBE, SBE+PSE] [+12 -114 MUTE] Steps, Reduce Volume Tone Control [+12 -114 MUTE] [FM/AM, NICAM, SCART, [SOUNDA, SOUNDB, STEREO, MONO.] [FM/AM, NICAM, SCART, [SOUNDA, SOUNDB, STEREO, MONO.] [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO.] [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO.] [FM/AM, NICAM, SCART, [SOUNDA, SOUNDB, STEREO, MONO.] [00hex 7Fhex] [00hex 7Fhex] [NO_MAT, GSTEREO, KSTEREO] [00hex 7Fhex] (MSP 3410G, 3450G only) [00hex 7Fhex] Bits [15.0] [00hex 7Fhex]/[00hex 7Fhex] [00hex 7Fhex] [BASS/TREBLE, EQUALIZER]
MUTE 00hex 100%/100% linear mode NORMAL SBE+PSE MUTE 00hex MUTE FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA 00hex 00hex NO_MAT 00hex 10hex 00hex 00/00hex 10hex BASS/TREB
[15.8] [7.0]
[15.8] [15.8] [15.8] [7.0]
[15.8] [7.0]
[15.8] [7.0]
[15.8] [15.8] [7.0]
[15.8] [7.0]
[15.8] [7.0]
[15.8] [7.0] [15.8] [7.0] [15.8] [15.8] [7.0] [15.8] [15.8] [15.0] [15.0] [15.8] [15.8]
34x0G
Table 3-5: List 34x0G Write Registers, continued
Write Register Equalizer loudspeaker band Equalizer loudspeaker band Equalizer loudspeaker band Equalizer loudspeaker band Equalizer loudspeaker band Automatic Volume Correction Subwoofer level adjust Subwoofer corner frequency Subwoofer complementary high-pass Balance headphone channel [L/R] Balance mode headphone Bass headphone channel Treble headphone channel Loudness headphone channel Loudness filter characteristic Volume SCART2 output channel SCART2 source select SCART2 channel matrix Address (hex) Bits [15.8] [15.8] [15.8] [15.8] [15.8] [15.8] [15.8] [15.8] [7.0] [15.8] [7.0] [15.8] [15.8] [15.8] [7.0] [15.8] [15.8] [7.0] Description Adjustable Range [+12 [+12 [+12 [+12 [+12 [off, decay time] mute] [off, [0.100 100% 0.100%] [-127.0 -127.0 [Linear mode logarithmic mode] [+20 [+15 [NORMAL, SUPER_BASS] [+12 -114 MUTE] [FM, NICAM, SCART, I2S1, I2S2] Reset 00hex %/100 linear mode NORMAL 00hex SOUNDA Page
[SOUNDA, SOUNDB, STEREO, MONO.]
Table 3-6: List 34x0G Read Registers
Read Register Address (hex) Bits Description Adjustable Range Page
Subaddress 11hex Registers writable STANDARD RESULT STATUS [15.0] [15.0] Result Automatic Standard Detection (see Table 3-8) Monitoring internal settings e.g. Stereo, Mono, Mute etc.
Subaddress 13hex Registers writable [15.0] [15.0] [15.8] [7.0] [15.8] [7.0] [00hex 7FFFhex]16 two's complement [00hex 7FFFhex]16 two's complement [00hex FFhex] [00hex FFhex] [00hex FFhex] [00hex FFhex]
Quasi peak readout left Quasi peak readout right hardware version code major revision code product code version code
34x0G
3.3.2. Description User Registers Table 3-7: Standard Codes STANDARD SELECT register
Standard Code (Data hex) Sound Standard Automatic Standard Detection Start Automatic Standard Detection Standard Selection M-Dual FM-Stereo -Dual FM-Stereo1) D/K1-Dual FM-Stereo2) 4.5/4.724212 5.5/5.7421875 6.5/6.2578125 6.5/6.7421875
Sound Carrier Frequencies
34x0G Version
3400, -10, -20, -40, 3400, -10,
D/K2-Dual FM-Stereo2) -FM-Mono with HDEV33), detectable Automatic Standard Detection, HDEV33) SAT-Mono (i.e. Eutelsat, Table 6-17) D/K3-Dual FM-Stereo -NICAM-FM -NICAM-AM -NICAM-FM -NICAM-FM
6.5/5.7421875 5.5/5.85 6.5/5.85 6.0/6.552 6.5/5.85 6.5/5.85 6.5/5.85 3420, -30, -40, 3410,
-NICAM-FM with HDEV24), detectable Automatic Standard Detection, China -NICAM-FM with HDEV33), detectable Automatic Standard Detection, China BTSC-Stereo BTSC-Mono M-EIA-J Japan Stereo FM-Stereo Radio SAT-Mono Table 6-17) SAT-Stereo Table 6-17) (Astra Digital Radio)
10.7 7.02/7.20
3420, -40, 3420, -30, -40, 3400, -10,
case Automatic Sound Select, B/G-codes 3hex 8hex equivalent. case Automatic Sound Select, D/K-codes 4hex, 5hex Bhex equivalent. HDEV3: Max. deviation must exceed HDEV2: Max. deviation must exceed
34x0G
3.3.2.2. Refresh STANDARD SELECT Register general refresh STANDARD SELECT register allowed. However, following method enables watching 34x0G "alive" status detection accidental resets (only versions later): After Power-on, bit[15] CONTROL will set; must read once enable reset-detection feature. Reading CONTROL register checking reset indicator bit[15] bit[15] "0", refresh STANDARD SELECT register allowed. bit[15] "1", indicating reset, refresh STANDARD SELECT register other MSPG registers necessary.
3.3.2.1. STANDARD SELECT Register sound standard 34x0G demodulator determined STANDARD SELECT register. There ways STANDARD SELECT register: Setting demodulator sound standard sending corresponding standard code with single I2C-Bus transmission. Starting Automatic Standard Detection terrestrial standards. This most comfortable demodulator. Within detection set-up actual sound standard performed. detected standard read STANDARD RESULT register control processor. This feature recommended primary set-up set. Outputs should muted during Automatic Standard Detection. Standard Codes listed Table 3-7. Selecting sound standard STANDARD SELECT register initializes demodulator. This includes: AGC, tuning frequency, band-pass filters, demodulation mode (FM, NICAM), carrier mute, deemphasis, identification mode. present sound standard impossible specific version, switches analog mono sound this standard. that case stereo bilingual processing will possible. complete setup sound processing from analog input source selection, transmissions shown Section 3.5. necessary. Note: matrix automatically Automatic Sound Select active (MODUS[0]=1). this case, matrix will initialized with "Sound Mono". During operation, matrix will automatically selected according actual identification information. reasons software compatibility 34x0D, Manual/Compatibility Mode available. detailed description this mode found page
34x0G
3.3.2.3. STANDARD RESULT Register Automatic Standard Detection selected STANDARD SELECT register, status result Automatic Standard Detection process read STANDARD RESULT register. possible results based mentioned Standard Code listed Table 3-8. cases where sound standard been detected standard present, much noise, strong interferers, etc.) STANDARD RESULT register contains 00hex. that case, controller start further actions (for example, standard according preference list manual input). long STANDARD RESULT register contains value greater than FFhex, Automatic Standard Detection still active. During this period, MODUS STANDARD SELECT register must written. STATUS register will updated when Automatic Standard Detection finished. present sound standard impossible specific version, detects switches analog mono sound this standard. Example: MSPs 3430G 3440G will detect B/G-NICAM signal standard will switch analog FMMono sound.
Table 3-8: Results Automatic Standard Detection
Broadcasted Sound Standard Automatic Standard Detection could find sound standard B/G-FM B/G-NICAM FM-Radio M-Korea M-Japan BTSC STANDARD RESULT Register Read 007Ehex 0000hex
0003hex 0008hex 000Ahex 0040hex 0002hex MODUS[14,13]=00) 0020hex MODUS[14,13]=01) 0030hex MODUS[14,13]=10)
L-AM D/K1 D/K2 L-NICAM D/K-NICAM Automatic Standard Detection still active
0009hex MODUS[12]=0) 0004hex MODUS[12]=1) 0009hex MODUS[12]=0) 000Bhex MODUS[12]=1) >07FFhex
34x0G
3.3.2.4. Write Registers Subaddress 10hex Table 3-9: Write Registers Subaddress 10hex Register Address Function Name
STANDARD SELECTION 20hex STANDARD SELECTION Register Defines Sound FM-Radio Standard [15:0] 01hex 02hex 60hex MODUS 30hex MODUS Register General 34x0G Options off/on: Automatic Sound Select disable/enable STATUS change indication means digital D_CTR_I/O_1 Necessary condition: MODUS[3] (active) undefined, must state digital output pins D_CTR_I/O_0 active: D_CTR_I/O_0 output pins (can means register. also: MODUS[1]) tristate: D_CTR_I/O_0 input pins (level read STATUS[4,3]) active/tristate state output pins master/slave mode interface (must Master) case NICAM mode) Sony/Philips format word strobe active/tristate state audio clock output AUD_CL_OUT ANA_IN_1+/ANA_IN_2+; select analog sound input undefined, must MODUS start Automatic Standard Detection Standard Codes (see Table 3-7)) STANDARD_SEL
[11:9]
Preference Automatic Standard Detection: [12] [14:13] [15]
Valid
detected carrier interpreted as:1) standard (SECAM) standard D/K1, D/K2 NICAM detected carrier interpreted as:1) standard (Korea) standard (BTSC) standard (Japan) carrier ignored (chroma carrier) undefined, must
next start Automatic Standard Detection.
34x0G
3.3.2.5. Read Registers Subaddress 11hex Table 3-10: Read Registers Subaddress 11hex Register Address Function
Name
STANDARD RESULT 7Ehex STANDARD RESULT Register Readback detected Sound FM-Radio Standard [15:0] 00hex Automatic Standard Detection could find sound standard Standard Codes (see Table 3-8) STANDARD_RES
02hex 40hex FFhex Automatic Standard Detection still active STATUS 00hex STATUS Register
STATUS
Contains user relevant internal information about status [5,9] undefined detected primary carrier (Mono carrier) primary carrier detected detected secondary carrier (2nd carrier) secondary carrier detected low/high level digital D_CTR_I/O_0 low/high level digital D_CTR_I/O_1 analog sound standard active obtainable digital sound (NICAM) available (MSP 3410G 3450G only) reception condition digital sound (NICAM) high error rate unimplemented sound code data transmission only mono/stereo indication indicates independent mono sound (only NICAM 3410G 3450G) indicates bilingual sound mode present undefined
[15:10]
STATUS change indication activated means MODUS[1]: Each change STATUS register sets digital D_CTR_I/O_1 high level. Reading STATUS register resets D_CTR_I/O_1.
34x0G
3.3.2.6. Write Registers Subaddress 12hex Table 3-11: Write Registers Subaddress 12hex Register Address Function Name
PREPROCESSING 0Ehex FM/AM Prescale [15:8] 00hex 7Fhex 00hex Defines input prescale gain demodulated signal (RESET condition) PRE_FM
modes except satellite AM-mode, combinations prescale value deviation listed below lead internal full scale. mode [15:8] 7Fhex 48hex 30hex 24hex 18hex 13hex deviation deviation deviation deviation deviation deviation (limit)
high deviation mode (HDEV2, Standard Code Chex) [15:8] 30hex 14hex deviation deviation (limit)
very high deviation mode (HDEV3, Standard Code Dhex) [15:8] 20hex 1Ahex deviation deviation (limit)
Satellite with adaptive deemphasis [15:8] 10hex recommendation
mode (MSP Standard Code [15:8] 7Chex recommendation input levels from (Due being switched AM-output level remains stable independent actual SIF-level mentioned input range)
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address
(continued)
Function Matrix Modes Defines dematrix function demodulated signal [7:0] 00hex 01hex 02hex 03hex 04hex matrix (used bilingual unmatrixed stereo sound) German stereo (Standard B/G) Korean stereo (also used BTSC, EIA-J Radio) sound mono (left right channel contain mono sound FM/AM mono carrier) sound mono
Name FM_MATRIX
0Ehex
case Automatic Sound Select, Matrix Mode automatically, i.e. low-part transmission register 0Ehex ignored. enable Forced Mono Mode analog stereo systems overriding internal pilot identification evaluation, following steps must transmitted: MODUS with bit[0] (Automatic Sound Select off) Presc./Matrix with Matrix Sound Mono (SAP: Sound Mono) Select FM/AM source channel, with channel matrix "Stereo" (transparent) 10hex NICAM Prescale Defines input prescale value digital NICAM signal [15:8] 00hex 7Fhex prescale gain examples: 00hex gain 20hex gain (recommendation) 5Ahex gain (maximum gain) 7Fhex 16hex 12hex I2S1 Prescale I2S2 Prescale Defines input prescale value digital input signals [15:8] 00hex 7Fhex prescale gain examples: 00hex gain (recommendation) 10hex gain (maximum gain) 7Fhex 0Dhex SCART Input Prescale Defines input prescale value analog SCART input signal [15:8] 00hex 7Fhex prescale gain examples: 00hex gain VRMS input leads digital full scale) 19hex gain (400 mVRMS input leads digital full scale) 7Fhex PRE_SCART PRE_I2S1 PRE_I2S2 PRE_NICAM
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address Function Name
SOURCE SELECT OUTPUT CHANNEL MATRIX 08hex 09hex 0Ahex 41hex 0Bhex 0Chex Source for: Loudspeaker Output Headphone Output SCART1 Output SCART2 Output Output Quasi-Peak Detector [15:8] "FM/AM": demodulated mono signal "Stereo A/B": demodulator Stereo signal manual mode, this source identical NICAM source 3410D) "Stereo demodulator Stereo Sound Language (only defined Automatic Sound Select) "Stereo demodulator Stereo Sound Language (only defined Automatic Sound Select) SCART input I2S1 input I2S2 input SRC_MAIN SRC_AUX SRC_SCART1 SRC_SCART2 SRC_I2S SRC_QPEAK
demodulator sources, Table 2-2. 08hex 09hex 0Ahex 41hex 0Bhex 0Chex Matrix Mode for: Loudspeaker Output Headphone Output SCART1 Output SCART2 Output Output Quasi-Peak Detector [7:0] Sound Mono Left Mono) 00hex Sound Mono Right Mono) 10hex Stereo (transparent mode) 20hex Mono (sum left right inputs divided 30hex special modes available (see Section 6.5.1. page MAT_MAIN MAT_AUX MAT_SCART1 MAT_SCART2 MAT_I2S MAT_QPEAK
Automatic Sound Select mode, demodulator source channels according Table 2-2. Therefore, matrix modes corresponding output channels should "Stereo" (transparent).
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address Function
Name
LOUDSPEAKER HEADPHONE PROCESSING 00hex 06hex Volume Loudspeaker Volume Headphone [15:8] volume table with step size (maximum volume) 7Fhex 7Ehex 74hex 73hex 72hex 02hex -113 01hex -114 00hex Mute (reset condition) Fast Mute (needs about until signal comFFhex pletely ramped down) [7:5] higher resolution volume table +0.125 increase addition volume table +0.875 increase addition volume table must VOL_MAIN VOL_AUX
[3:0]
clipping mode reduce volume reduce tone control compromise mode
With large scale input signals, positive volume settings lead signal clipping. 34x0G loudspeaker headphone volume function divided into digital analog section. With Fast Mute, volume reduced mute position digital volume only. Analog volume changed. This reduces audible plops. turn volume again, volume step that been used before Fast Mute activated must transmitted. clipping mode "Reduce Volume", following rule used: prevent severe clipping effects with bass, treble, equalizer boosts, internal volume automatically limited level where, combination with either bass, treble, equalizer setting, amplification does exceed clipping mode "Reduce Tone Control", bass treble value reduced amplification exceeds equalizer switched gain those bands reduced, where amplification together with volume exceeds clipping mode "Compromise Mode", bass treble value volume reduced half half amplification exceeds equalizer switched gain those bands reduced half half, where amplification together with volume exceeds Example: Red. Volume Red. Tone Con. Compromise Vol.: Bass: Treble:
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address 29hex Function Automatic Volume Correction (AVC) Loudspeaker Channel [15:12] 00hex 08hex [11:8] 08hex 04hex 02hex 01hex (and reset internal variables) decay time decay time decay time decay time (intended quick adaptation average volume level after channel change) Name
Note: reset internal variables, should switched then again during channel source change. standard applications, recommended decay time sec. Note: should used Dolby Prologic mode (with 35xx), except PANORAMA 3D-PANORAMA mode, when only loudspeaker output active. 01hex 30hex Balance Loudspeaker Channel Balance Headphone Channel [3:0] Balance Mode linear 0hex logarithmic 1hex BAL_MAIN BAL_AUX
[15:8] Linear Mode Left muted, Right 100% 7Fhex Left 0.8%, Right 100% 7Ehex Left 99.2%, Right 100% 01hex Left 100%, Right 100% 00hex Left 100%, Right 99.2% FFhex Left 100%, Right 0.8% 82hex Left 100%, Right muted 81hex [15:8] Logarithmic Mode Left -127 Right 7Fhex Left -126 Right 7Ehex Left Right 01hex Left Right 00hex Left Right FFhex Left Right -127 81hex Left Right -128 80hex Positive balance settings reduce left channel without affecting right channel; negative settings reduce right channel leaving left channel unaffected.
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address 20hex Function Tone Control Mode Loudspeaker Channel [15:8] 00hex FFhex bass treble active equalizer active
Name TONE_MODE
Defines whether Bass/Treble Equalizer activated loudspeaker channel. Bass Equalizer cannot work simultaneously. Equalizer used, Bass, Treble coefficients must zero vice versa. 02hex 31hex Bass Loudspeaker Channel Bass Headphone Channel [15:8] normal range 60hex 58hex 08hex 00hex F8hex A8hex A0hex [15:8] extended range 7Fhex 78hex 70hex 68hex Higher resolution possible: step normal range results gain step about extended range about With positive bass settings, internal clipping occur even with overall volume less than This will lead clipped output signal. Therefore, recommended bass value that, conjunction with volume, would result overall positive gain. BASS_MAIN BASS_AUX
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address 03hex 32hex Function Treble Loudspeaker Channel Treble Headphone Channel [15:8] 78hex 70hex 08hex 00hex F8hex A8hex A0hex Name TREB_MAIN TREB_AUX
Higher resolution possible: step results gain step about With positive treble settings, internal clipping occur even with overall volume less than This will lead clipped output signal. Therefore, recommended treble value that, conjunction with volume, would result overall positive gain. 21hex 22hex 23hex 24hex 25hex Equalizer Loudspeaker Channel Band (below Equalizer Loudspeaker Channel Band (center: Equalizer Loudspeaker Channel Band (center: kHz) Equalizer Loudspeaker Channel Band (center: kHz) Equalizer Loudspeaker Channel Band (above: kHz) [15:8] 60hex 58hex 08hex 00hex F8hex A8hex A0hex EQUAL_BAND1 EQUAL_BAND2 EQUAL_BAND3 EQUAL_BAND4 EQUAL_BAND5
Higher resolution possible: step results gain step about With positive equalizer settings, internal clipping occur even with overall volume less than This will lead clipped output signal. Therefore, recommended equalizer bands value that, conjunction with volume, would result overall positive gain.
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address 04hex 33hex Function Loudness Loudspeaker Channel Loudness Headphone Channel [15:8] Loudness Gain 44hex 40hex 04hex 00hex [7:0] Loudness Mode normal (constant volume kHz) 00hex Super Bass (constant volume kHz) 04hex
Name LOUD_MAIN LOUD_AUX
Higher resolution Loudness Gain possible: step results gain step about Loudness increases volume low- high-frequency signals, while keeping amplitude 1-kHz reference frequency constant. intended loudness according actual volume setting. Because loudness introduces gain, recommended loudness value that, conjunction with volume, would result overall positive gain. corner frequency bass amplification different values. Super Bass mode, corner frequency shifted point constant volume shifted from kHz.
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address 05hex Function Spatial Effects Loudspeaker Channel [15:8] Effect Strength Enlargement 100% 7Fhex Enlargement 3Fhex Enlargement 1.5% 01hex Effect 00hex reduction 1.5% FFhex reduction C0hex reduction 100% 80hex [7:4] Spatial Effect Mode Stereo Basewidth Enlargement (SBE) 0hex Pseudo Stereo Effect (PSE). (Mode Stereo Basewidth Enlargement (SBE) only. (Mode 2hex Spatial Effect High-Pass Gain max. high-pass gain 0hex high-pass gain 2hex high-pass gain 4hex min. high-pass gain 6hex automatic 8hex Name SPAT_MAIN
[3:0]
There several spatial effect modes available: mode (low byte 00hex), spatial effect depends source mode. incoming signal mono, Pseudo Stereo Effect active; stereo signals, Pseudo Stereo Effect Stereo Basewidth Enlargement effective. strength effect controllable upper byte. negative value reduces stereo image. strong spatial effect recommended small sets where loudspeaker spacing rather close. large screen sets, more moderate spatial effect recommended. mode only Stereo Basewidth Enlargement effective. mono input signals, Pseudo Stereo Effect switched worth mentioning, that spatial effects affect amplitude phase response. With lower bits, frequency response customized. value 0hex yields flat response center signals high-pass function only signals. value 6hex flat response only signals, low-pass function center signals. using 8hex, frequency response automatically adapted sound material choosing optimal high-pass gain.
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address Function
Name
SUBWOOFER OUTPUT CHANNEL 2Chex Subwoofer Level Adjustment [15:8] 00hex FFhex E3hex E2hex 80hex 2Dhex Mute SUBW_FREQ SUBW_LEVEL
Subwoofer Corner Frequency [15:8] 5.40 corner frequency 10-Hz steps (range: 50.400
Subwoofer Complementary High-Pass Filter [7:0] 00hex 01hex loudspeaker channel unfiltered complementary high-pass processed loudspeaker output channel
SUBW_HP
SCART OUTPUT CHANNEL 07hex 40hex Volume SCART1 Output Channel Volume SCART2 Output Channel [15:8] volume table with step size (maximum volume) 7Fhex 7Ehex 74hex 73hex 72hex 02hex -113 01hex -114 00hex Mute (reset condition) [7:5] higher resolution volume table +0.125 increase addition volume table +0.875 increase addition volume table 01hex this must 01hex VOL_SCART1 VOL_SCART2
[4:0]
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address Function Name
SCART SWITCHES DIGITAL PINS 13hex Register Defines level digital output pins position SCART switches [15] [14] low/high digital output D_CTR_I/O_0 (MODUS[3]=0) low/high digital output D_CTR_I/O_1 (MODUS[3]=0) ACB_REG
[13:5] SCART Input Select xxxx00xx0 SCART1 input (RESET position) xxxx01xx0 MONO input (Sound Mono must selected channel matrix mode corresponding output channels) xxxx10xx0 SCART2 input xxxx11xx0 SCART3 input xxxx00xx1 SCART4 input xxxx11xx1 mute input [13:5] SCART1 Output Select xx00xxx0x SCART3 input SCART1 output (RESET position) xx01xxx0x SCART2 input SCART1 output xx10xxx0x MONO input SCART1 output xx11xxx0x SCART1 SCART1 output xx00xxx1x SCART2 SCART1 output xx01xxx1x SCART1 input SCART1 output xx10xxx1x SCART4 input SCART1 output xx11xxx1x mute SCART1 output [13:5] SCART2 Output Select 00xxxx0xx SCART1 SCART2 output (RESET position) 01xxxx0xx SCART1 input SCART2 output 10xxxx0xx MONO input SCART2 output 00xxxx1xx SCART2 SCART2 output 01xxxx1xx SCART2 input SCART2 output 10xxxx1xx SCART3 input SCART2 output 11xxxx1xx SCART4 input SCART2 output 11xxxx0xx mute SCART2 output RESET position becomes active time first write transmission control audio processing part. writing register first, RESET state redefined. BEEPER 14hex Beeper Volume Frequency [15:8] Beeper Volume 00hex maximum volume 7Fhex [7:0] Beeper Frequency (lowest) 01hex 40hex FFhex BEEPER
34x0G
3.3.2.7. Read Registers Subaddress 13hex Table 3-12: Read Registers Subaddress 13hex Register Address Function
Name
QUASI-PEAK DETECTOR READOUT 19hex 1ahex Quasi-Peak Detector Readout Left Quasi-Peak Detector Readout Right [15.0] 0hex. 7FFFhex values two's complement (only positive) 34X0G VERSION READOUT REGISTERS 1Ehex Hardware Version Code [15.8] 02hex 34x0G MSP_HARD QPEAK_L QPEAK_R
change hardware version code defines hardware optimizations that have influence chip's behavior. readout this register identical hardware version code chip's imprint. Major Revision Code [7.0] 07hex 34x0G MSP_REVISION
major revision code 34x0G 1Fhex Product Code [15.8] 00hex 0Ahex 1Ehex 28hex 32hex 3400G 3410G 3430G 3440G 3450G MSP_PRODUCT
means MSP-Product Code, control processor able decide which sound standards have considered. Version Code [7.0] 45hex 46hex 34x0G 34x0G MSP_ROM
change version code defines internal software optimizations, that have influence chip's behavior, e.g. features have been included. While software change intended create compatibility problems, customers that want functions identify 34x0G versions according this number. avoid compatibility problems with 3410B 34x0D, offset 40hex added version code chip's imprint.
34x0G
3.5. Examples Minimum Initialization Codes Initialization 34x0G according these listings reproduces sound selected standard loudspeaker output. numbers hexadecimal. examples have following structure: Perform controlled reset Write MODUS register (with Automatic Sound Select).
3.4. Programming Tips This section describes preferred method initializing 34x0G. initialization grouped into four sections: analog signal path, demodulator input, input processing SCART I2S, output processing. Fig. page complete signal flow.
SCART Signal Path Select analog input SCART baseband processing (SCART Input Select) means register. Select source each analog SCART output (SCART Output Select) means register.
Source Selection loudspeaker channel (with matrix STEREO). Prescale and/or NICAM dummy matrix). Write STANDARD SELECT register. Volume loudspeaker channel
Demodulator Input complete setup sound processing from analog input source selection, following steps must performed: MODUS register preferred mode Sound input. Choose preferred prescale NICAM) values. Write STANDARD SELECT register. Automatic Sound Select active, following step done repeatedly: Choose matrix according sound mode indicated STATUS register. SCART Inputs Select preferred prescale SCART. Select preferred prescale inputs (set after RESET).
3.5.1. B/G-FM NICAM)
MODUS-Register: Automatic Source Sel. Matr. FM/AM-Prescale 24hex, FM-Matrix MONO/SOUNDA NICAM-Prescale 5Ahex Standard Select: NICAM Softreset
Loudspeaker Volume
3.5.2. BTSC-Stereo
MODUS-Register: Automatic Source Sel. Matr. FM/AM-Prescale 24hex, FM-Matrix Sound Mono Standard Select: BTSC-STEREO Loudspeaker Volume Softreset
Output Channels Select source channel matrix each output channel. audio baseband processing. Select volume each output channel. 3.5.3. BTSC-SAP with Loudspeaker Channel
MODUS-Register: Automatic Source Sel. Matr. FM/AM-Prescale 24hex, FM-Matrix Sound Mono Standard Select: BTSC-SAP Loudspeaker Volume Softreset
34x0G
3.5.4. FM-Stereo Radio
MODUS-Register: Automatic Source Sel. Matr. FM/AM-Prescale 24hex, FM-Matrix Sound Mono Standard Select: FM-STEREO-RADIO Loudspeaker Volume Softreset
3.5.5. Automatic Standard Detection detailed software flow diagram shown Fig. page
MODUS-Register: Automatic Source Sel. Matr. FM/AM-Prescale 24hex, FM-Matrix Sound Mono NICAM-Prescale 5Ahex Standard Select: Automatic Standard Detection Softreset
Wait till STANDARD RESULT contains value 07FF STANDARD RESULT contains 0000 some error handling ELSE
Loudspeaker Volume
3.5.6. Software Flow Interrupt driven STATUS Check detailed software flow diagram shown Fig. page D_CTR_I/O_1 34x0G connected interrupt input controller, following interrupt handler applied automatically called with each status change 34x0G. interrupt handler adjust display according status information.
Interrupt Handler:
Read STATUS
adjust display with given status information Return from Interrupt
34x0G
Write MODUS Register: Example essential bits: Automatic Sound Select Enable interrupt STATUS changes ANA_IN1+ selected Define Preference Automatic Standard Detection: [12] MHz, SECAM-L [14:13] Ignore carrier
Write SOURCE SELECT Settings
Example: loudspeaker Source Select "Stereo headphone Source Select "Stereo SCART_Out Source Select "Stereo A/B" Channel Matrix mode outputs "Stereo"
Write FM/AM-Prescale Write NICAM-Prescale
Write into STANDARD SELECT Register
(Start Automatic Standard Detection)
previous standard standard manually according picture information
Result
expecting MSPG-interrupt
case MSPGInterrupt Controller:
Read STATUS
Adjust TV-Display
Bilingual, adjust Source Select setting required
Fig. 3-2: Software flow diagram Minimum demodulator setup European Multistandard applying Automatic Sound Select feature
34x0G
Specifications 4.1. Outline Dimensions
1.27 20.32 1.27
25.14 0.12 0.71 0.05
0.48 0.06
0.23 0.04
25.14 0.12
±0.05 4.05 ±0.1 4.75 ±0.15
24.2
SPGS0027-2(P68)/1E
Fig. 4-1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately Dimensions
SPGS0016-5(P64)/1E
SPGS0016-5(P52)/1E
47.0 ±0.1 57.7 ±0.1 ±0.2 ±0.1 19.3 ±0.1 ±0.05
±0.2 ±0.1
15.6 ±0.1 ±0.1
0.28 ±0.06 ±0.2 0.28 ±0.06 ±0.2 ±0.05 1.778 0.48 ±0.06 1.778 55.1 ±0.1 20.3 ±0.5 ±0.05 1.778 0.48 ±0.06 1.778 44.4 ±0.1 16.3
Fig. 4-2: 64-Pin Plastic Shrink Dual-Inline Package (PSDIP64) Weight approximately Dimensions
Fig. 4-3: 52-Pin Plastic Shrink Dual-Inline Package (PSDIP52) Weight approximately Dimensions
1.27 20.32
23.3 24.2
1.27
34x0G
0.17 0.04 10.3 0.37 0.05
18.4
17.2 0.15
0.05 ±0.2
23.2 0.15
SPGS705000-1(P80)/1E
Fig. 4-4: 80-Pin Plastic Quad Flat Pack (PQFP80) Weight approximately 1.61 Dimensions
0.145
0.055
1.75
1.75
0.05
0.22 0.05
D0025/3E
Fig. 4-5: 64-Pin Plastic Low-Profile Quad Flat Pack (PLQFP64) Weight approximately 0.35 Dimensions
12.0
34x0G
4.2. Connections Short Descriptions connected; leave vacant used, leave vacant obligatory; connect described circuit diagram DVSS: used, connect DVSS AHVSS: connect AHVSS
PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PLQFP 64-pin
Name
Type
Connection
used)
Short Description
ADR_WS ADR_DA I2S_DA_IN1 I2S_DA_OUT I2S_WS I2S_CL I2C_DA I2C_CL STANDBYQ ADR_SEL D_CTR_I/O_0 D_CTR_I/O_1 AUD_CL_OUT XTAL_OUT XTAL_IN TESTEN ANA_IN2+
word strobe connected data output I2S1 data input data output word strobe clock data clock connected Stand-by (low-active) address select D_CTR_I/O_0 D_CTR_I/O_1 connected connected connected Audio clock output (18.432 MHz) Test Crystal oscillator Crystal oscillator Test input (can left
vacant, only input also use)
IN/OUT IN/OUT IN/OUT IN/OUT
IN/OUT IN/OUT
AVSS AVSS
ANA_IN-
common (can left vacant, only input also use)
34x0G
PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PLQFP 64-pin
Name
Type
Connection
used)
Short Description
ANA_IN1+ AVSUP AVSUP AVSS AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L ASG2 SC3_IN_R SC3_IN_L ASG4 SC4_IN_R SC4_IN_L AGNDC AHVSS AHVSS CAPL_M AHVSUP CAPL_A
input Analog power supply Analog power supply connected connected Analog ground Analog ground Mono input connected Reference voltage converter SCART input, right SCART input, left Analog Shield Ground SCART input, right SCART input, left Analog Shield Ground SCART input, right SCART input, left Analog Shield Ground SCART input, right SCART input, left connected Analog reference voltage Analog ground Analog ground connected connected Volume capacitor MAIN Analog power supply Volume capacitor
AHVSS
AHVSS
AHVSS
AHVSS
34x0G
PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PLQFP 64-pin
Name
Type
Connection
used)
Short Description
SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R DACM_SUB DACM_L DACM_R VREF2 DACA_L DACA_R RESETQ I2S_DA_IN2 DVSS DVSS DVSS DVSUP DVSUP DVSUP ADR_CL
SCART output left SCART output right Reference ground SCART output left SCART output right connected connected Subwoofer output connected Loudspeaker out, left Loudspeaker out, right Reference ground Headphone out, left Headphone out, right connected connected Power-on-reset connected connected connected I2S2-data input Digital ground Digital ground Digital ground Digital power supply Digital power supply Digital power supply clock
compatibility with 3410B, possible connect with DVSS well.
34x0G
4.3. Descriptions numbers refer 80-pin PQFP package. connected. I2C_CL Clock Input/Output (Fig. 4-12) this pin, I2C-bus clock signal supplied. signal pulled down case wait conditions. I2C_DA Data Input/Output (Fig. 4-12) this pin, I2C-bus data written read from MSP. I2S_CL Clock Input/Output (Fig. 4-15) Clock line bus. master mode, this line driven MSP; slave mode, external clock supplied. I2S_WS Word Strobe Input/Output (Fig. 4-15) Word strobe line bus. master mode, this line driven MSP; slave mode, external word strobe supplied. I2S_DA_OUT Data Output (Fig. 4-11) Output digital serial sound data bus. I2S_DA_IN1 Data Input (Fig. 4-13) First input digital serial sound data bus. ADR_DA Data Output (Fig. 4-11) Output digital serial data 3510A bus. ADR_WS Word Strobe Output (Fig. 4-11) Word strobe output bus. ADR_CL Clock Output (Fig. 4-11) Clock line bus. Pins DVSUP* Digital Supply Voltage Power supply digital circuitry MSP. Must connected power supply. Pins DVSS* Digital Ground Ground connection digital circuitry MSP. I2S_DA_IN2 Data Input (Fig. 4-13) Second input digital serial sound data bus. Pins Pins connected. RESETQ Reset Input (Fig. 4-13) steady state, high level required. level resets 34x0G. Pins Pins connected. Pins DACA_R/L Headphone Outputs (Fig. 4-21) Output headphone signal. 1-nF capacitor AHVSS must connected these pins. offset these pins depends selected headphone volume. VREF2 Reference Ground Reference analog ground. This must connected separately single ground point (AHVSS). VREF2 serves clean ground should used reference analog connections loudspeaker headphone outputs. Pins DACM_R/L Loudspeaker Outputs (Fig. 4-21) Output loudspeaker signal. 1-nF capacitor AHVSS must connected these pins. offset these pins depends selected loudspeaker volume. connected. DACM_SUB Subwoofer Output (Fig. 4-21) Output subwoofer signal. 1-nF capacitor AHVSS must connected this pin. frequency content subwoofer output, value capacitor increased better suppression high-frequency noise. offset this depends selected loudspeaker volume. Pins connected. Pins SC2_OUT_R/L SCART2 Outputs (Fig. 4-23) Output SCART2 signal. Connections these pins must 100- series resistor intended AC-coupled. VREF1 Reference Ground Reference analog ground. This must connected separately single ground point (AHVSS). VREF1 serves clean ground should used reference analog connections SCART outputs. Pins SC1_OUT_R/L SCART1 Outputs (Fig. 4-23) Output SCART1 signal. Connections these pins must 100- series resistor intended AC-coupled.
34x0G
CAPL_A Volume Capacitor Headphone (Fig. 4-18) 10-µF capacitor AHVSUP must connected this pin. serves smoothing filter headphone volume changes order suppress audible plops. value capacitor lowered 1-µF faster response required. area encircled trace lines should minimized; keep traces short possible. This input sensitive magnetic induction. AHVSUP* Analog Power Supply High Voltage Power supplied this analog circuitry (except input). This must connected supply. CAPL_M Volume Capacitor Loudspeaker (Fig. 4-18) 10-µF capacitor AHVSUP must connected this pin. serves smoothing filter loudspeaker volume changes order suppress audible plops. value capacitor lowered faster response required. area encircled trace lines should minimized; keep traces short possible. This input sensitive magnetic induction. Pins Pins connected.
Pins SC2_IN_L/R SCART2 Inputs (Fig. 4-20) analog input signal SCART2 this pin. Analog input connection must AC-coupled. ASG1 Analog Shield Ground Analog ground (AHVSS) should connected this reduce cross-coupling between SCART inputs. Pins SC1_IN_L/R SCART1 Inputs (Fig. 4-20) analog input signal SCART1 this pin. Analog input connection must AC-coupled. VREFTOP Reference Voltage Converter (Fig. 4-17) this pin, reference voltage converter decoupled. must connected AVSS pins with 10-µF 100-nF capacitor parallel. Traces must kept short. connected. MONO_IN Mono Input (Fig. 4-20) analog mono input signal this pin. Analog input connection must AC-coupled. Pins AVSS* Analog Power Supply Voltage Ground connection analog input circuitry MSP. Pins Pins connected.
Pins AHVSS* Analog Power Supply High Voltage Ground connection analog circuitry (except input). AGNDC Internal Analog Reference Voltage This serves internal ground connection analog circuitry (except input). must connected VREF pins with 3.3-µF 100-nF capacitor parallel. This pins shows level typically 3.73 connected. Pins SC4_IN_L/R SCART4 Inputs (Fig. 4-20) analog input signal SCART4 this pin. Analog input connection must AC-coupled. ASG4 Analog Shield Ground Analog ground (AHVSS) should connected this reduce cross-coupling between SCART inputs. Pins SC3_IN_L/R SCART3 Inputs (Fig. 4-20) analog input signal SCART3 this pin. Analog input connection must AC-coupled. ASG2 Analog Shield Ground Analog ground (AHVSS) should connected this reduce cross-coupling between SCART inputs.
Pins AVSUP* Analog Power Supply Voltage Power supplied this analog input circuitry MSP. This must connected supply. ANA_IN1+ Input (Fig. 4-17) analog sound signal supplied this pin. Inputs must AC-coupled. This designed symmetrical input: ANA_IN1+ internally connected input symmetrical amp, ANA_IN- other. ANA_IN- Common (Fig. 4-17) This pins serves common reference ANA_IN1/ inputs. ANA_IN2+ Input (Fig. 4-17) analog sound signal supplied this pin. Inputs must AC-coupled. This designed symmetrical input: ANA_IN2+ internally connected input symmetrical amp, ANA_IN- other. TESTEN Test Enable (Fig. 4-13) This enables factory test modes. normal operation, must connected ground.
34x0G
Pins XTAL_IN, XTAL_OUT Crystal Input Output Pins (Fig. 4-16) These pins connected 18.432 crystal oscillator which digitally tuned integrated shunt capacitances. external clock into XTAL_IN. audio clock output signal AUD_CL_OUT derived from oscillator. External capacitors each crystal ground (AVSS) required. should verified layout, that supply current digital circuitry flowing through ground connection point. This enables factory test modes. normal operation, must left vacant. AUD_CL_OUT Audio Clock Output (Fig. 4-16) This 18.432 main clock output. Pins Pins connected. Pins D_CTR_I/O_1/0 Digital Control Input/ Output Pins (Fig. 4-15) These pins serve general purpose input/output pins. D_CTR_I/O_1 used interrupt request controller. ADR_SEL Address Select (Fig. 4-14) means this pin, three device addresses selected. connected ground (I2C device addresses 80/81hex), supply (84/85hex), left open (88/89hex). STANDBYQ Stand-by normal operation, this must High. 34x0G switched first pulling STANDBYQ then (after delay) switching keeping power supply (`Stand-by'-mode), SCART switches maintain their position function. Application Note: ground pins should connected low-resistive ground plane. supply pins should connected separately with short low-resistive lines power supply. Decoupling capacitors from DVSUP DVSS, AVSUP AVSS, AHVSUP AHVSS recommended closely possible these pins. Decoupling DVSUP DVSS most important. recommend using more than capacitor. choosing different values, frequency range active decoupling extended. application boards use: capacitor with lowest value should placed nearest DVSUP DVSS pins.
34x0G
4.4. Configurations
ADR_WS ADR_DA I2S_DA_IN1 I2S_DA_OUT I2S_WS I2S_CL I2C_DA I2C_CL ADR_CL DVSUP DVSS I2S_DA_IN2 RESETQ
STANDBYQ ADR_SEL D_CTR_I/O_0 D_CTR_I/O_1 AUD_CL_OUT XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN1+ AVSUP
DACA_R DACA_L VREF2 DACM_R DACM_L DACM_SUB SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP CAPL_M
34x0G
AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L ASG2 SC4_IN_L SC4_IN_R ASG4 SC3_IN_L SC3_IN_R AHVSS AGNDC
Fig. 4-6: 68-pin PLCC package
34x0G
AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSS I2S_DA_IN2 RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L DACM_SUB
XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L ASG2 SC3_IN_R SC3_IN_L ASG4 SC4_IN_R SC4_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSS I2S_DA_IN2 RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L DACM_SUB
XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN1+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L SC3_IN_R SC3_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
34x0G
34x0G
Fig. 4-8: 52-pin PSDIP package
Fig. 4-7: 64-pin PSDIP package
34x0G
SC2_IN_L SC2_IN_R ASG1 SC1_IN_L SC1_IN_R VREFTOP MONO_IN AVSS AVSS
ASG2 SC3_IN_R SC3_IN_L ASG4 SC4_IN_R SC4_IN_L AGNDC AHVSS AHVSS
AVSUP AVSUP ANA_IN1+ ANA_IN- ANA_IN2+ TESTEN XTAL_IN XTAL_OUT AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ
CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R DACM_SUB DACM_L DACM_R VREF2 DACA_L
34x0G
I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSUP I2S_DA_IN2 DVSS DVSS DVSS DVSUP RESETQ
DACA_R
Fig. 4-9: 80-pin PQFP package
34x0G
SC2_IN_L SC2_IN_R ASG1 SC1_IN_L SC1_IN_R VREFTOP MONO_IN AVSS
ASG2 SC3_IN_R SC3_IN_L ASG4 SC4_IN_R SC4_IN_L AGNDC AHVSS
AVSUP ANA_IN1+ ANA_IN- ANA_IN2+ TESTEN XTAL_IN XTAL_OUT AUD_CL_OUT D_CTR_I/OUT1 D_CTR_I/OUT0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS I2S_DA_IN2 DVSS DVSUP ADR_CL RESETQ CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R DACM_SUB DACM_L DACM_R VREF2 DACA_L DACA_R
34x0G
Fig. 4-10: 64-pin PLQFP package
34x0G
4.5. Circuits numbers refer PQFP80 package. DVSUP Fig. 4-11: Output Pins (I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL) DVSUP
Fig. 4-15: Input/Output Pins (I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0)
Fig. 4-12: Input/Output Pins (I2C_CL, I2C_DA)
3-30
3-30
Fig. 4-16: Output/Input Pins (XTAL_IN, XTAL_OUT, AUD_CL_OUT) Fig. 4-13: Input Pins (I2S_DA_IN1, I2S_DA_IN2, RESETQ, TESTEN, STANDBYQ) ANA_IN1+ ANA_IN2+ DVSUP
ANA_IN- VREFTOP
ADR_SEL Fig. 4-14: Input (ADR_SEL) Fig. 4-17: Input Pins (VREFTOP, ANA_IN1+, ANA_IN-, ANA_IN2+)
34x0G
3.75
Fig. 4-18: Capacitor Pins (CAPL_A, CAPL_M)
Fig. 4-22: (AGNDC)
3.75
Fig. 4-19: Input (MONO_IN)
3.75
3.75
Fig. 4-23: Output Pins (SC_2_OUT_R/L, SC_1_OUT_R/L)
Fig. 4-20: Input Pins (SC4-1_IN_L/R)
AHVSUP
0.1.2
Fig. 4-21: Output Pins (DACA_R/L, DACM_R/L, DACM_SUB)
34x0G
4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol VSUP1 VSUP2 VSUP3 dVSUP23 PTOT Parameter Ambient Operating Temperature Storage Temperature First Supply Voltage Second Supply Voltage Third Supply Voltage Voltage between AVSUP DVSUP Power Dissipation PLCC68 PSDIP64 PSDIP52 PQFP80 PLQFP64 Input Voltage, Digital Inputs Input Current, Digital Pins Input Voltage, Analog Inputs Input Current, Analog Inputs Output Current, SCART Outputs Output Current, Analog Outputs except SCART Outputs Output Current, other pins connected capacitors SCn_IN_s,3) MONO_IN SCn_IN_s,3) MONO_IN SCn_OUT_s3) DACp_s3) CAPL_p,3) AGNDC Name AHVSUP DVSUP AVSUP AVSUP, DVSUP AHVSUP, DVSUP, AVSUP Min. -0.3 -0.3 -0.3 -0.5
Max. 701)
Unit
1200 1300 1200 1000 9601) -0.3 -0.3
mA2) mA2)
VIdig IIdig VIana IIana IOana IOana ICana
VSUP2+0.3 VSUP1+0.3
PLQFP64: positive value means current flowing into circuit means "1", "2", "3", "4", means "R", means analog outputs short-circuit proof with respect First Supply Voltage ground. Total chip power dissipation must exceed absolute maximum rating.
Stresses beyond those listed "Absolute Maximum Ratings" cause permanent damage device. This stress rating only. Functional operation device these other conditions beyond those indicated "Recommended Operating Conditions/Characteristics" this specification implied. Exposure absolute maximum ratings conditions extended periods affect device reliability.
34x0G
4.6.2. Recommended Operating Conditions 4.6.2.1. General Recommended Operating Conditions Symbol VSUP1 Parameter First Supply Voltage (8-V Operation) First Supply Voltage (5-V Operation) VSUP2 VSUP3 tSTBYQ1 Second Supply Voltage Third Supply Voltage STANDBYQ Setup Time before Turn-off Second Supply Voltage DVSUP AVSUP STANDBYQ, DVSUP Name AHVSUP Min. 4.75 4.75 4.75 Typ. Max. 5.25 5.25 5.25 Unit
4.6.2.2. Analog Input Output Recommendations Symbol CAGNDC Parameter AGNDC-Filter-Capacitor Ceramic Capacitor Parallel CinSC VinSC VinMONO RLSC CLSC CVMA CFMA
Name AGNDC
Min. -20% -20%
Typ.
Max.
Unit
DC-Decoupling Capacitor front SCART Inputs SCART Input Level Input Level, Mono Input SCART Load Resistance SCART Load Capacitance Main/AUX Volume Capacitor Main/AUX Filter Capacitor
SCn_IN_s1)
-20%
MONO_IN SCn_OUT_s1) CAPL_M, CAPL_A DACM_s, DACA_s1) -10% +10%
VRMS VRMS
means "1", "2", "3", means "R", means
34x0G
4.6.2.3. Recommendations Analog Sound Input Signal Symbol CVREFTOP Parameter VREFTOP-Filter-Capacitor Ceramic Capacitor Parallel FIF_FMTV FIF_FMRADIO VIF_FM VIF_AM RFMNI Analog Input Frequency Range Applications Analog Input Frequency FM-Radio Applications Analog Input Range FM/NICAM Analog Input Range AM/NICAM Ratio: NICAM Carrier/FM Carrier (unmodulated carriers) Ratio: NICAM Carrier/AM Carrier (unmodulated carriers) Ratio: FM-Main/FM-Sub Satellite Ratio: FM1/FM2 German FM-System Ratio: Main Carrier/ Color Carrier Ratio: Main Carrier/ Luma Components Passband Ripple Suppression Spectrum above (not Radio) Maximum FM-Deviation (approx.) normal mode HDEV2: high deviation mode HDEV3: very high deviation mode ANA_IN1+, ANA_IN2+, ANA_IN- Name VREFTOP Min.
Typ.
Max.
Unit
10.7 0.45
RAMNI RFM1/FM2 PRIF SUPHF FMMAX
±180 ±360 ±540
34x0G
4.6.2.4. Crystal Recommendations Symbol Parameter Name Min. Typ. Max. Unit
General Crystal Recommendations Crystal Parallel Resonance Frequency Load Capacitance Crystal Series Resistance Crystal Shunt (Parallel) Capacitance External Load Capacitance1) XTAL_IN, XTAL_OUT 18.432
PSDIP approx. PLCC approx. P(L)QFP approx.
Crystal Recommendations Master-Slave Applications (MSP-clock must perform synchronization clock) fTOL DTEM Accuracy Adjustment Frequency Variation versus Temperature Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb AUD_CL_OUT 18.431 18.433
Crystal Recommendations NICAM Applications MSP-clock synchronization clock possible) fTOL DTEM Accuracy Adjustment Frequency Variation versus Temperature Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb AUD_CL_OUT
18.4305 18.4335
Crystal Recommendations analog FM/AM Applications MSP-clock synchronization clock possible) fTOL DTEM Accuracy Adjustment Frequency Variation versus Temperature Required Open Loop Clock Frequency (Tamb AUD_CL_OUT -100 18.429 +100 18.435
Amplitude Recommendation Operation with External Clock Input (Cload after reset typ. VXCA
1)External
External Clock Amplitude
XTAL_IN
capacitors each crystal ground required. They necessary tune open-loop frequency internal stabilize frequency closed-loop operation. different layouts, accurate capacitor size should determined with customer PCB. suggested values (1.5.3.3 figures based experience should serve "start value". define capacitor size, reset without transmitting further telegrams. Measure frequency AUD_CL_OUT-pin. Change capacitor size until free running frequency matches 18.432 closely possible. higher capacity, lower resulting clock frequency.
34x0G
4.6.3. Characteristics
fCLOCK 18.432 MHz, VSUP1 VSUP2 4.75 5.25 min./max. values fCLOCK 18.432 MHz, VSUP1 VSUP2 typical values, Junction Temperature MAIN Loudspeaker Channel, Headphone Channel
4.6.3.1. General Characteristics
Symbol Supply ISUP1A First Supply Current (active) (8-V Operation)
Analog Volume Main Analog Volume Main
Parameter
Name
Min.
Typ.
Max.
Unit
Test Conditions
AHVSUP 17.1 11.2 24.6 16.1
First Supply Current (active) (5-V Operation)
Analog Volume Main Analog Volume Main
DVSUP AVSUP AHVSUP
11.4
16.4 10.7
ISUP2A
Second Supply Current (active) 34x0G version 34x0G version later Third Supply Current (active) 34x0G version 34x0G version later First Supply Current (8-V Operation) (standby mode) First Supply Current (5-V Operation) (standby mode)
ISUP3A
STANDBYQ
ISUP1S
STANDBYQ
Clock fCLOCK DCLOCK tJITTER VxtalDC tStartup VACLKAC VACLKDC routHF_ACL Clock Input Frequency Clock High Ratio Clock Jitter (Verification provided Production Test) DC-Voltage Oscillator Oscillator Startup Time Slew-rate Audio Clock Output Voltage Audio Clock Output Voltage Output Resistance XTAL_IN, XTAL_OUT AUD_CL_OUT XTAL_IN 18.432
VSUP3
load Imax
34x0G
4.6.3.2. Digital Inputs, Digital Outputs
Symbol Parameter Name Min. Typ. Max. Unit Test Conditions
Digital Input Levels VDIGIL VDIGIH Digital Input Voltage Digital Input High Voltage MSP34x0G version MSP34x0G version later Input Impedance Digital Input Leakage Current STANDBYQ D_CTR_I/O_0/1 VSUP2 VSUP2 VSUP2 UINPUT< DVSUP D_CTR_I/O_0/1: tri-state
ZDIGI IDLEAK VDIGIL VDIGIH IADRSEL
Digital Input Voltage Digital Input High Voltage Input Current Address Select
ADR_SEL -500 -220
VSUP2 VSUP2 UADR_SEL= DVSS UADR_SEL= DVSUP
Digital Output Levels VDCTROL VDCTROH Digital Output Voltage Digital Output High Voltage D_CTR_I/O_0 D_CTR_I/O_1 IDDCTR IDDCTR
34x0G
4.6.3.3. Reset Input Power-Up
Symbol Parameter Name Min. Typ. Max.
Unit
Test Conditions
RESETQ Input Levels VRHL VRLH ZRES IRES Reset High-Low Transition Voltage Reset Low-High Transition Voltage Input Impedance Input Leakage Current RESETQ 0.45 0.55 VSUP2 VSUP2 UINPUT< DVSUP
DVSUP AVSUP
4.5V
t/ms
RESETQ
Low-to-High Threshold
High-to-Low Threshold
Note: reset should reach high level before oscillator started. This requires reset delay DVSUP means Volt with DVSUP t/ms
Reset Delay
Internal Reset
High
t/ms Fig. 4-24: Power-up sequence
34x0G
4.6.3.4. I2C-Bus Characteristics
Symbol VI2CIL VI2CIH tI2C1 tI2C2 tI2C5 tI2C6 tI2C3 tI2C4 fI2C VI2COL II2COH tI2COL1 tI2COL2 Parameter C-Bus Input Voltage I2C-Bus Input High Voltage Start Condition Setup Time Stop Condition Setup Time I2C-Data Setup Time before Rising Edge Clock I2C-Data Hold Time after Falling Edge Clock I2C-Clock Pulse Time I2C-Clock High Pulse Time I2C-BUS Frequency I2C-Data Output Voltage I2C-Data Output High Leakage Current I2C-Data Output Hold Time after Falling Edge Clock I2C-Data Output Setup Time before Rising Edge Clock I2C_CL, I2C_DA I2C_CL
Name I2C_CL, I2C_DA
Min.
Typ.
Max.
Unit VSUP2 VSUP2
Test Conditions
II2COL VI2COH
fI2C
1/FI2C I2C_CL TI2C4 TI2C3
TI2C1 I2C_DA input
TI2C5
TI2C6
TI2C2
TI2COL2 I2C_DA output
TI2COL1
Fig. 4-25: timing diagram
34x0G
4.6.3.5. I2S-Bus Characteristics
Symbol VI2SIL Parameter Input Voltage MSP34x0G version MSP34x0G version later Input High Voltage MSP34x0G version MSP34x0G version later Input Impedance Input Leakage Current I2S-Data Input Setup Time before Rising Edge Clock I2S-Data Input Hold Time after Falling Edge Clock I2S-Word Strobe Input Frequency when I2S-Slave Mode I2S-Clock Input Frequency when I2S-Slave-Mode I2S-Clock Input Ratio when I2S-Slave-Mode I2S-Word Strobe Input Setup Time before Rising Edge Clock when I2S-Slave-Mode I2S-Word Strobe Input Hold Time after Falling Edge Clock when I2S-Slave-Mode Output Voltage Output High Voltage I2S-Word Strobe Output Frequency S-Clock Output Frequency I2S-Clock High/Low-Ratio I2S-Data Setup Time before Rising Edge Clock I2S-Data Hold Time after Falling Edge Clock I2S-Word Strobe Setup Time before Rising Edge Clock I2S-Word Strobe Hold Time after Falling Edge Clock I2S_CL, I2S_WS I2S_CL, I2S_DA_OUT
Name I2S_DA_IN1/2 I2S_CL I2S_WS
Min.
Typ.
Max.
Unit
Test Conditions
0.25
VSUP2 VSUP2 VSUP2 VSUP2
VI2SIH
0.75
ZI2SI IDLEAKI2SI tI2S1 tI2S2 fI2SWS fI2SCL RI2SCL tI2SWS1
UINPUT< DVSUP slave mode
I2S_DA_IN1/2, I2S_CL
I2S_WS
32.0
I2S_CL
1.024
I2S_WS, I2S_CL
tI2SWS2
VI2SOL VI2SOH fI2SWS fI2SCL tI2S1/I2S2 tI2S3 tI2S4 tI2S5 tI2S6
I2S_WS, I2S_CL, I2S_DA_OUT I2S_WS I2S_CL
32.0 1024
II2SOL II2SOH NICAM-PLL closed
34x0G
(Data: first)
FI2SWS I2S_WS
SONY Mode PHILIPS Mode PHILIPS/SONY Mode programmable MODUS[6] I2S_CL Detail I2S_DAIN
SONY Mode PHILIPS Mode Detail
left channel Detail I2S_DAOUT
right channel
left channel
right channel
Detail
I2S_CL
FI2SCL
Detail
I2S_CL
TI2SWS1
TI2SWS2
TI2S1
TI2S2
I2S_WS INPUT TI2S5 TI2S6
I2S_DA_IN TI2S3 TI2S4
I2S_WS OUTPUT
I2S_DA_OUT
Fig. 4-26: timing diagram
4.6.3.6. Analog Baseband Inputs Outputs, AGNDC
Symbol Parameter Name Min. Typ. Max. Unit Test Conditions
Analog Ground VAGNDC0 AGNDC Open Circuit Voltage (8-V Operation) MSP34x0G version MSP34x0G version later AGNDC Open Circuit Voltage (5-V Operation) MSP34x0G version MSP34x0G version later RoutAGN AGNDC Output Resistance (8-V Operation) AGNDC Output Resistance (5-V Operation) Analog Input Resistance RinSC RinMONO
AGNDC 3.63 3.67 3.73 3.77 3.83 3.87
Rload
2.39 2.41
2.49 2.51
2.59 2.61
VAGNDC
SCART Input Resistance from MONO Input Resistance from
SCn_IN_s1)
fsignal kHz, 0.05 fsignal kHz,
MONO_IN
means "1", "2", "3", "4";
means
34x0G
Symbol
Parameter
Name
Min.
Typ.
Max.
Unit
Test Conditions
Audio Analog-to-Digital-Converter VAICL Effective Analog Input Clipping Level Analog-to-DigitalConversion (8-V Operation) Effective Analog Input Clipping Level Analog-to-DigitalConversion (5-V Operation) SCART Outputs RoutSC SCART Output Resistance from Deviation DC-Level SCART Output from AGNDC Voltage Gain from Analog Input SCART Output Frequency Response from Analog Input SCART Output Bandwidth: 20000 Effective Signal Level SCART-Output during full-scale Digital Input Signal from (8-V Operation) Effective Signal Level SCART-Output during full-scale Digital Input Signal from (5-V Operation) Main Outputs RoutMA Main/AUX Output Resistance from DC-Level Main/AUX-Output Analog Volume Analog Volume (8-V Operation) DC-Level Main/AUX-Output Analog Volume Analog Volume (5-V Operation) VoutMA Effective Signal Level Main/ AUX-Output during full-scale Digital Input Signal from Analog Volume (8-V Operation) Effective Signal Level Main/ AUX-Output during full-scale Digital Input Signal from Analog Volume (5-V Operation)
SCn_IN_s,1) MONO_IN
2.00
2.25
VRMS
fsignal
1.13
1.51
VRMS
SCn_OUT_s1) SCn_IN_s,1) MONO_IN SCn_OUT_s1) -1.0 -0.5 +0.5 +0.5
fsignal kHz,
dVOUTSC ASCtoSC frSCtoSC
fsignal with resp.
VoutSC
SCn_OUT_s1)
VRMS
fsignal
1.17
1.27
1.37
VRMS
DACp_s1)
fsignal kHz,
VoutDCMA
1.80
2.04
2.28
1.12
1.36
1.60
1.23
1.37
1.51
VRMS
fsignal
0.76
0.90
1.04
VRMS
means "1", "2", "3", "4";
means "R";
means
34x0G
4.6.3.7. Sound Inputs
Symbol RIFIN Parameter Input Impedance Name ANA_IN1+, ANA_IN2+, ANA_IN- VREFTOP 2.45 ANA_IN1+, ANA_IN2+, ANA_IN- ANA_IN1+, ANA_IN2+, ANA_IN- 2.65 2.75 Min. Typ. Max. 11.4 Unit Test Conditions Gain Gain
DCVREFTOP
Voltage VREFTOP 34x0G Version 34x0G Version later Voltage Inputs
DCANA_IN
XTALKIF BWIF
Crosstalk Attenuation Bandwidth Step Width
0.85
fsignal Input Level
4.6.3.8. Power Supply Rejection
Symbol Parameter Name Min. Typ. Max. Unit Test Conditions
PSRR: Rejection Noise AHVSUP PSRR AGNDC From Analog Input Output AGNDC MONO_IN, SCn_IN_s1) MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1) DACp_s1)
From Analog Input SCART Output From Input SCART Output From Input MAIN Output
means "1", "2", "3", "4";
means "R";
means
34x0G
4.6.3.9. Analog Performance
Symbol Parameter Name Min. Typ. Max.
Unit
Test Conditions
Specifications Operation Signal-to-Noise Ratio from Analog Input Output MONO_IN, SCn_IN_s1) Input Level with resp. VAICL, fsig kHz, unweighted Hz.16 Input Level fsig kHz, unweighted Hz.20 Input Level fsig kHz, unweighted Hz.15 Input Level fsig kHz, unweighted Hz.15
from Analog Input SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1)
from Input SCART Output
from Input Main/AUX-Output Analog Volume Analog Volume
DACp_s1)
Total Harmonic Distortion from Analog Input Output MONO_IN, SCn_IN_s1) 0.01 0.03 Input Level with resp. VAICL, fsig kHz, unweighted Hz.16 Input Level dBr, fsig kHz, unweighted Hz.20 Input Level dBr, fsig kHz, unweighted Hz.16 Input Level dBr, fsig kHz, unweighted Hz.16
from Analog Input SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1)
0.01
0.03
from Input SCART Output
0.01
0.03
from Input Main Output
DACA_s, DACM_s1)
0.01
0.03
means "1", "2", "3", "4";
means "R";
means
34x0G
Symbol
Parameter
Name
Min.
Typ.
Max.
Unit
Test Conditions
Specifications Operation Signal-to-Noise Ratio from Analog Input Output MONO_IN, SCn_IN_s1) Input Level with resp. VAICL, fsig kHz, unweighted Hz.16 Input Level fsig kHz, unweighted Hz.20 Input Level fsig kHz, unweighted Hz.15 Input Level fsig kHz, unweighted Hz.15
from Analog Input SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1)
from Input SCART Output
from Input Main/AUX-Output Analog Volume Analog Volume
DACp_s1)
Total Harmonic Distortion from Analog Input Output MONO_IN, SCn_IN_s1) 0.03 Input Level with resp. VAICL, fsig kHz, unweighted Hz.16 Input Level dBr, fsig kHz, unweighted Hz.20 Input Level dBr, fsig kHz, unweighted Hz.16 Input Level dBr, fsig kHz, unweighted Hz.16
from Analog Input SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1)
from Input SCART Output
from Input Main Output
DACA_s, DACM_s1)
means "1", "2", "3", "4";
means "R";
means
34x0G
Symbol
Parameter
Name
Min.
Typ.
Max.
Unit
Test Conditions
XTALK Specifications Operation XTALK Crosstalk Attenuation PLCC68 PSDIP64 Input Level fsig kHz, unused analog inputs connected ground unweighted Hz.20 PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 unweighted Hz.16 PLCC68 PSDIP64 (unweighted Hz.20 same signal source left right disturbing channel, effect each observed output channel
between left right channel within SCART Input/Output pair (LR, SCn_IN SCn_OUT1) SC1_IN SC2_IN Output SC3_IN Output Input SCn_OUT1)
between left right channel within Main Output pair Input DACp1)
between SCART Input/Output pairs disturbing program observed program MONO/SCn_IN SCn_OUT MONO/SCn_IN SCn_OUT1) MONO/SCn_IN SCn_OUT unsel. MONO/SCn_IN Output MONO/SCn_IN SCn_OUT Input SCn_OUT1) MONO/SCn_IN unselected Input SC1_OUT1) PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64
Crosstalk between Main Output pairs Input DACp1)
PLCC68 PSDIP64
(unweighted Hz.16 kHz) same signal source left right disturbing channel, effect each observed output channel (unweighted Hz.20 kHz) same signal source left right disturbing channel, effect each observed output channel
XTALK
Crosstalk from Main Output SCART Output vice versa disturbing program observed program MONO/SCn_IN/DSP SCn_OUT Input DACp1) MONO/SCn_IN/DSP SCn_OUT Input DACp1) Input DACp MONO/SCn_IN SCn_OUT1) Input DACM Input SCn_OUT1) PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64
SCART output load resistance SCART output load resistance
means "1", "2", "3", "4";
means "R";
means
34x0G
4.6.3.10. Sound Standard Dependent Characteristics
Symbol Parameter Name Min. Typ. Max. Unit Test Conditions
NICAM Characteristics (MSP Standard Code dVNICAMOUT S/NNICAM Tolerance Output Voltage NICAM Baseband Signal NICAM Baseband Signal DACp_s, SCn_OUT_s1) -1.5 +1.5 2.12 kHz, Modulator input level dBref NICAM: kHz, unweighted kHz, NIC_Presc 7Fhex Output level VRMS DACp_s 2.12 kHz, Modulator input level dBref FM+NICAM, norm conditions Modulator input level dBref;
THDNICAM BERNICAM fRNICAM XTALKNICAM SEPNICAM
Total Harmonic Distortion Noise NICAM Baseband Signal NICAM: Error Rate NICAM Frequency Response 20.15000 NICAM Crosstalk Attenuation (Dual) NICAM Channel Separation (Stereo) -1.0
10-7
+1.0
Characteristics (MSP Standard Code dVFMOUT S/NFM THDFM Tolerance Output Voltage Demodulated Signal Demodulated Signal Total Harmonic Distortion Noise Demodulated Signal DACp_s, SCn_OUT_s1) -1.5 +1.5 FM-carrier, kHz, deviation; FM-carrier MHz, kHz, deviation; RMS, unweighted (for S/N); full input range, FM-Prescale 46hex, Output Level VRMS DACp_s FM-carrier MHz, Modulator input level -14.6 dBref; FM-carriers 5.5/5.74 MHz, kHz, deviation; Bandpass FM-carriers 5.5/5.74 MHz, kHz, deviation;
fRFM
Frequency Responses, 20.15000
-1.0
+1.0
XTALKFM
Crosstalk Attenuation (Dual)
SEPFM
Channel Separation (Stereo)
DACp_s, SCn_OUT_s1)
Characteristics (MSP Standard Code S/NAM(1) Demodulated Signal measurement condition: RMS/Flat 34x0G Version 34x0G Version later Demodulated Signal measurement condition: QP/CCIR 34x0G Version 34x0G Version later Total Harmonic Distortion Noise Demodulated Signal 34x0G Version 34x0G Version later means "R"; DACp_s, SCn_OUT_s1) level: 0.1-0.8 AM-carrier FM/AM prescaler output VRMS Loudspeaker out; Standard Code 09hex video/chroma components
S/NAM(2)
THDAM
means "1", "2", "3", "4";
means "Loudspeaker (Main)'' ``Headphone (AUX)''
34x0G
Symbol
Parameter
Name
Min.
Typ.
Max.
Unit
Test Conditions
BTSC Characteristics (MSP Standard Code 20hex, 21hex) S/NBTSC BTSC Stereo Signal BTSC-SAP Signal DACp_s, SCn_OUT_s1) SAP, 100% modulation, deemphasis, unweighted SAP, 100% EIM2), unweighted SAP, 1%.66% EIM2),
THDBTSC
THD+N BTSC Stereo Signal THD+N BTSC Signal
fRBTSC
Frequency Response BTSC Stereo, Hz.12 Frequency Response BTSCSAP, Hz.9
-0.5 -1.0
XTALKBTSC
Stereo Stereo
SAP, 100% modulation, deemphasis, Bandpass 1%.66% EIM2),
SEPBTSC
Stereo Separation Hz.10 Hz.12 Pilot deviation threshold Stereo Stereo ANA_IN1+, ANA_IN2+
FMpil
15.843
carrier modulated with 15.743 level mVpp indication: STATUS Bit[6] standard BTSC stereo signal, sound carrier only
fPilot
Pilot Frequency Range
ANA_IN1+ ANA_IN2+
15.563
BTSC Characteristics (MSP Standard Code 20hex, 21hex) with minimum input signal level mVpp (measured without video/chroma signal components) S/NBTSC BTSC Stereo Signal BTSC-SAP Signal DACp_s, SCn_OUT_s1) SAP, 100% modulation, deemphasis, unweighted SAP, 100% EIM2), unweighted SAP, 1%.66% EIM2),
THDBTSC
THD+N BTSC Stereo Signal THD+N BTSC Signal
0.15
fRBTSC
Frequency Response BTSC Stereo, Hz.12 Frequency Response BTSCSAP, Hz.9
-0.5 -1.0
XTALKBTSC
Stereo Stereo
SAP, 100% modulation, deemphasis, Bandpass 1%.66% EIM2),
SEPBTSC
Stereo Separation Hz.10 Hz.12
means "1", "2", "3", "4"; means "R"; means refers 75-µs Equivalent Input Modulation. defined audio-signal level which results stated percentage modulation, when encoding process replaced 75-µs preemphasis network.
34x0G
Symbol
Parameter
Name
Min.
Typ.
Max.
Unit
Test Conditions
EIA-J Characteristics (MSP Standard Code 30hex) S/NEIAJ EIA-J Stereo Signal EIA-J Sub-Channel THDEIAJ THD+N EIA-J Stereo Signal THD+N EIA-J Sub-Channel fREIAJ Frequency Response EIA-J Stereo, Hz.12 Frequency Response EIA-J Sub-Channel, Hz.12 XTALKEIAJ Main MAIN SEPEIAJ Stereo Separation Hz.5 Hz.10 -0.5 -1.0 DACp_s, SCn_OUT_s1) 100% modulation, deemphasis 100% modulation, deemphasis, unweighted
100% modulation, deemphasis, Bandpass EIA-J Stereo Signal, 100% modulation
FM-Radio Characteristics (MSP Standard Code 40hex) S/NUKW THDUKW fRUKW FM-Radio Stereo Signal THD+N FM-Radio Stereo Signal Frequency Response FM-Radio Stereo Hz.15 Stereo Separation Hz.15 Pilot Frequency Range ANA_IN1+ ANA_IN2+ DACp_s, SCn_OUT_s1) 100% modulation, deemphasis, unweighted 1%.100% modulation, deemphasis 19.125 standard radio stereo signal
-1.0 18.844
+0.5
SEPUKW fPilot
means "1", "2", "3", "4";
means "R";
means
34x0G
Appendix Overview TV-Sound Standards 5.1. NICAM
Table 5-1: Summary NICAM sound modulation parameters
Specification Carrier frequency digital sound Transmission rate Type modulation Spectrum shaping Roll-off factor Carrier frequency analog sound component Power ratio between vision carrier analog sound carrier Power ratio between analog modulated digital sound carrier mono mono 6.552 5.85 5.85 kbit/s Differentially encoded quadrature phase shift keying (DQPSK) means Roll-off filters mono terrestrial cable mono 5.85
China/Hu ngary
Poland
Table 5-2: Summary NICAM sound coding characteristics
Characteristics Audio sampling frequency Number channels Initial resolution Companding characteristics Coding compressed samples Preemphasis Audio overload level Values bit/sample near instantaneous, with compression bits/sample 32-samples blocks complement CCITT Recommendation J.17 (6.5 attenuation measured unity gain frequency preemphasis network kHz)
34x0G
5.2. A2-Systems
Table 5-3: parameters Systems Standards B/G, D/K,
Characteristics TV-Sound Standard Carrier frequency Sound Carrier 5.7421875 Sound Carrier 6.2578125 6.7421875 5.7421875 ±27/±50 ±17/±25 ±27/±50 ±15/±25 4.724212
Vision/sound power difference Sound bandwidth Preemphasis Frequency deviation (nom/max) Transmission Modes Mono transmission Stereo transmission Dual sound transmission Identification Transmission Mode Pilot carrier frequency Max. deviation portion Type modulation modulation depth Modulation frequency (L+R)/2
mono (L+R)/2
mono (L-R)/2 language
language
54.6875
55.0699
±2.5
mono: unmodulated stereo: 117.5 dual: 274.1 149.9 276.0
34x0G
5.3. BTSC-Sound System
Table 5-4: parameters BTSC-Sound Systems
Aural Carrier (L+R) Carrier frequency (fhNTSC 15.734 kHz) (fhPAL 15.625 kHz) Sound bandwidth Preemphasis Max. deviation Aural Carrier Max. Freq. Deviation Subcarrier Modulation Type
BTSC-MPX-Components Pilot (L-R) Prof.
Baseband
0.05 (total) kHz1)
0.05 kHz1)
0.05
0.05
does exceed interleaving effects
5.4. Japanese Stereo System (EIA-J)
Table 5-5: parameters Japanese FM-Stereo Sound System EIA-J
Aural Carrier Carrier frequency 15.734 kHz) Sound bandwidth Preemphasis Max. deviation portion Aural Carrier Max. Freq. Deviation Subcarrier Modulation Type Transmitter-sided delay Mono transmission Stereo transmission Bilingual transmission Language EIA-J-MPX-Components (L+R) Baseband 0.05 (L-R) 0.05 Language Identification none unmodulated 982.5 922.5
34x0G
5.5. Satellite Sound
Table 5-6: parameters Satellite Sound
Carrier Frequency 7.02/7.20 7.38/7.56 7.74/7.92 Maximum Deviation Sound Mode Mono Mono/Stereo/Bilingual Mono/Stereo/Bilingual Mono/Stereo/Bilingual Bandwidth Deemphasis adaptive adaptive adaptive
5.6. FM-Stereo Radio
Table 5-7: parameters FM-Stereo Radio Systems
Aural Carrier (L+R) Carrier frequency kHz) Sound bandwidth Preemphasis: Europe Max. deviation Aural Carrier (100%) 10.7 Baseband 0.05 FM-Radio-MPX-Components Pilot (L-R) 0.05 RDS/ARI
34x0G
Appendix Manual/Compatibility Mode adapt modes STANDARD SELECT register individual requirements reasons compatibility 34x0D, 34x0G offers Manual/Compatibility Mode, which provides sophisticated programming 34x0G. Using STANDARD SELECT register generally provides more economic program 34x0G will result optimal behavior. Therefore, recommended Manual/Compatibility mode. Only those cases, where compatibility with 34x0D strictly required, should Manual/Compatibility mode used. Note: case Automatic Sound Select (MODUS[0]=1), modifications demodulator write registers listed below, except AUTO_FM/AM, ignored.
34x0G
6.1. Demodulator Write Read Registers Manual/Compatibility Mode Table 6-1: Demodulator Write Registers; Subaddress: 10hex; these registers readable!
Demodulator Write Registers AUTO_FM/AM Address (hex) MSPVersion 3410, 34501) Description MODUS[0]=1 (Automatic Sound Select): Switching Level threshold Automatic Switching between NICAM FM/AM case NICAM reception MODUS[0]=0 (Manual Mode): Activation configuration Automatic Switching between NICAM FM/AM case NICAM reception A2_Threshold CM_Threshold AD_CV MODE_REG 3410, 34501) Stereo Identification Threshold Carrier-Mute Threshold SIF-input selection, configuration AGC, Carrier-Mute Function Controlling MSP-Demodulator Interface options. soon this register applied, 34x0G works 34x0D compatibility mode. Warning: this mode, BTSC, EIA-J, FM-Radio disabled. Only 34x0D features available; MODUS STATUS register allowed. 34x0G reset normal mode first programming MODUS register followed transmitting valid standard code STANDARD SELECTION register. FIR1 FIR2 DCO1_LO DCO1_HI DCO2_LO DCO2_HI PLL_CAPS
Reset Mode
Page
19hex 2Ahex
FIR1-filter coefficients channel bit) FIR2-filter coefficients channel bit), offset (total bit) Increment channel Part Increment channel High Part Increment channel Part Increment channel High Part interest customer Switchable capacitors tune open-loop frequency
BTSC, EIA-J, FM-Radio mode
Table 6-2: Demodulator Read Registers; Subaddress: 11hex; these registers writable!
Demodulator Read Registers C_AD_BITS ADD_BITS CIB_BITS ERROR_RATE PLL_CAPS AGC_GAIN Address (hex) MSPVersion 3410, 3450 Description NICAM-Sync bit, NICAM-C-Bits, three LSBs additional data bits NICAM: [10:3] additional data bits NICAM: CIB1 CIB2 control bits NICAM error rate, updated with customer customer Page
34x0G
6.2. Write Read Registers Manual/Compatibility Mode Table 6-3: DSP-Write Registers; Subaddress: 12hex, registers readable well
Write Register Volume SCART1 channel: Ctrl. mode Fixed Deemphasis Adaptive Deemphasis Identification Mode Notch Volume SCART2 channel: Ctrl. mode Address (hex) Bits [7.0] [15.8] [7.0] [7.0] [7.0] [7.0]
Operational Modes Adjustable Range [Linear mode logarithmic mode] OFF] [OFF, WP1] [B/G, [ON, OFF] [Linear mode logarithmic mode]
Reset Mode 00hex 00hex
Page
Table 6-4: Read Registers; Subaddress: 13hex, registers writable
Additional Read Registers Stereo detection register Stereo Systems level readout FM1/Ch2-L level readout FM2/Ch1-R Address (hex) Bits [15.8] [15.0] [15.0] Output Range [80hex 7Fhex] [8000hex 7FFFhex] [8000hex 7FFFhex] two's complement two's complement two's complement Page
34x0G
Individual configuration threshold done using Table 6-5, whereby bits AUTO_FM ignored. recommended internal setting used standard selection. optimum NICAM sound assigned output channels selecting "Stereo A/B", "Stereo "Stereo source channels.
6.3. Manual/Compatibility Mode: Description Demodulator Write Registers 6.3.1. Automatic Switching between NICAM Analog Sound case NICAM reception loss NICAM-carrier, 34x0G offers Automatic Switching (fall back) analog sound (FM/AMMono), without necessity controller reading evaluating parameters. proper NICAM signal returns, switching back this source performed automatically well. feature evaluates NICAM ERROR_RATE switches, necessary, output channels which assigned NICAM source, analog source, vice versa. appropriate hysteresis algorithm avoids oscillating effects (see Fig. 6-1). STATUS[9] C_AD_BITS[11] (Addr: 0023 hex) provide information about actual NICAM-FM/AM-status.
6.3.1.2. Function Manual Mode manual mode (MODUS[0]=0) required, activation configuration Automatic Switching feature done described Table 6-5. Note, that channel matrix corresponding output channels must according NICAM mode need changed FM/AM-fallback case. Example: Required threshold 500: bits [10:1]=00 1111 1010
6.3.1.1. Function Automatic Sound Select Mode
Selected Sound
Automatic Sound Select feature (MODUS[0]=1) includes procedure mentioned above. default, internal ERROR_RATE threshold 700dec. i.e. NICAM analog Sound ERROR_RATE analog Sound NICAM ERROR_RATE 700/2 ERROR_RATE value corresponds approximately 5.46*10-3/s.
NICAM
analog Sound
ERROR_RATE threshold/2 threshold
Fig. 6-1: Hysteresis Automatic Switching
Table 6-5: Coding Automatic NICAM/Analog Sound Switching; Reset Status: Mode
Mode Description Compatible 3410B, i.e. automatic switching disabled Automatic Switching with internal threshold (Default, Automatic Sound Select Automatic Switching with external threshold (Customizing Automatic Sound Select) Forced analog mono mode, i.e. Automatic Switching disabled (Customizing Automatic Sound Select) AUTO_FM [11:0] Addr. 21hex Bits [10:1] [11] [10:1] [11] [10:1] 25.1000 threshold/2 [11] [10:1] [11] ERROR_RATEThreshold/dec none Source Select: Input NICAM Path1) always NICAM; Mute case NICAM available NICAM FM/AM, depending ERROR_RATE
customer; recommended range: 50.2000 none always FM/AM
case Automatic Sound Select (MODUS[0] NICAM path assigned "Stereo A/B", "Stereo "Stereo source channels (see Table page 11).
case Automatic Sound Select (MODUS[0] AUTO_FM ignored
34x0G
6.3.2. Threshold threshold between Stereo/Bilingual Mono Identification Standard been made programmable according user's preferences. internal hysteresis ensures robustness stability. Table 6-6: Write Register Subaddress 10hex Threshold Register Address THRESHOLDS 22hex (write) THRESHOLD Register Function
Name
A2_THRESH
Defines threshold EIA_J standards Stereo Bilingual detection [11.0] 7F0hex 190hex 0A0hex [15.12] force Mono Identification default setting after reset minimum Threshold stable detection must
recommended range 0A0hex.3C0hex
6.3.3. Carrier-Mute Threshold Carrier-Mute threshold been made programmable according user's preferences. internal hysteresis ensures stable behavior. Table 6-7: Write Register Subaddress 10hex Carrier-Mute Threshold Register Address THRESHOLDS 24hex (write) Carrier-Mute THRESHOLD Register Defines threshold carrier mute feature [6.0] 00hex 2Ahex 7Fhex Carrier-Mute always (both channels muted) default setting after reset Carrier-Mute always (both channels forced must CM_THRESH Function Name
[15.7]
recommended range 14hex.50hex
34x0G
6.3.4. Register AD_CV this register longer

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