Programmable Logic Device February 2004 ver. Features.
|
|
|
Top Searches for this datasheet
APEX 20KC
Programmable Logic Device
February 2004 ver.
Features.
Programmable logic device (PLD) manufactured using 0.15-µm alllayer copper-metal fabrication process faster design performance than APEX20KE devices Pin-compatible with APEX 20KE devices High-performance, low-power copper interconnect MultiCorearchitecture integrating look-up table (LUT) logic embedded memory logic used register-intensive functions Embedded system blocks (ESBs) used implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, content-addressable memory (CAM) High-density architecture 200,000 million typical gates (see Table 38,400 logic elements (LEs) 327,680 bits that used without reducing available logic Note EP20K400C
1,052,000 400,000 16,640 212,992 1,664
Table APEX 20KC Device Features Feature
Maximum system gates Typical gates ESBs Maximum bits PLLs Speed grades Maximum macrocells Maximum user pins Notes Table
EP20K200C
526,000 200,000 8,320 106,496
EP20K600C
1,537,000 600,000 24,320 311,296 2,432
EP20K1000C
1,772,000 1,000,000 38,400 327,680 2,560
embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes 57,000 additional gates. PLL: phase-locked loop. speed grade provides fastest performance.
Altera Corporation
DS-APEX20KC-2.2
APEX 20KC Programmable Logic Device
.and More Features
Low-power operation design 1.8-V supply voltage (see Table Copper interconnect reduces power consumption MultiVoltI/O support 1.8-V, 2.5-V, 3.3-V interfaces ESBs offering programmable power-saving mode Flexible clock management circuitry with four phase-locked loops (PLLs) Built-in low-skew clock tree eight global clock signals ClockLockfeature reducing clock delay skew ClockBoostfeature providing clock multiplication division ClockShiftfeature providing programmable clock phase delay shifting Powerful features Compliant with peripheral component interconnect Special Interest Group (PCI SIG) Local Specification, Revision 3.3-V operation bits Support high-speed external memories, including synchronous dynamic (SDRAM) static (SRAM) input output LVDS channels megabits second (Mbps) Direct connection from pins local interconnect providing fast times complex logic MultiVolt support 1.8-V, 2.5-V, 3.3-V interfaces Programmable clamp VCCIO Individual tri-state output enable control each Programmable output slew-rate control reduce switching noise Support advanced standards, including low-voltage differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, SSTL-3 SSTL-2, GTL+, HSTL Class Supports hot-socketing operation Pull-up pins before during configuration
Table APEX 20KC Supply Voltages Feature
Internal supply voltage (VCCINT)
Voltage
MultiVolt interface voltage levels (VCCIO) Note Table
APEX 20KC devices 5.0-V tolerant using external resistor.
Altera Corporation
APEX 20KC Programmable Logic Device Data Sheet
Advanced interconnect structure Copper interconnect high performance Four-level hierarchical FastTrack® interconnect structure providing fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such fast adders, counters, comparators (automatically used software tools megafunctions) Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used software tools megafunctions) Interleaved local interconnect allows drive other through fast local interconnect Advanced software support Software design support automatic place-and-route provided Altera® QuartusII development system Windows-based PCs, SPARCstations, 9000 Series 700/800 workstations Altera MegaCore® functions Altera Megafunction Partners Program (AMPPSM) megafunctions optimized APEX 20KC architecture available NativeLinkintegration with popular synthesis, simulation, timing analysis tools Quartus SignalTap® embedded logic analyzer simplifies in-system design evaluation giving access internal nodes during device operation Supports popular revision-control software packages including PVCS, RCS, SCCS Notes (1), 652-Pin
Table APEX 20KC Package Options Count Device
EP20K200C EP20K400C EP20K600C EP20K1000C
208-Pin PQFP 240-Pin PQFP
356-Pin
Altera Corporation
APEX 20KC Programmable Logic Device
Table APEX 20KC FineLine Package Options Count Notes (1), Device
EP20K200C EP20K400C EP20K600C EP20K1000C Notes Tables
counts include dedicated input clock pins. APEX 20KC device package types include plastic quad flat pack (PQFP), 1.27-mm pitch ball-grid array (BGA), 1.00-mm pitch FineLine BGApackages. This device uses thermally enhanced package, which taller than regular package. Consult Altera Device Package Information Data Sheet detailed package size information.
1,020
Table APEX 20KC Package Sizes Feature
Pitch (mm) Area (mm2) Length Width
208-Pin PQFP
0.50 30.4 30.4
240-Pin PQFP
0.50 1,218 34.9 34.9
356-Pin
1.27 1,225 35.0 35.0
652-Pin
1.27 2,025 45.0 45.0
Table APEX 20KC FineLine Package Sizes Feature
Pitch (mm) Area Length Width
1.00
1.00
1,020
1.00 1,089
General Description
Similar APEX APEX 20KE devices, APEX 20KC devices offer MultiCore architecture, which combines strengths LUT-based product-term-based devices with enhanced memory structure. LUT-based logic provides optimized performance efficiency datapath, register-intensive, mathematical, digital signal processing (DSP) designs. Product-term-based logic optimized complex combinatorial paths, such complex state machines. LUT- productterm-based logic combined with memory functions wide variety MegaCore AMPP functions make APEX 20KC architecture uniquely suited SOPC designs. Applications historically requiring combination LUT-, product-term-, memory-based devices integrated into APEX 20KC device.
Altera Corporation
APEX 20KC Programmable Logic Device
APEX 20KC devices include additional features such enhanced standard support, CAM, additional global clocks, enhanced ClockLock clock circuitry. Table shows features included APEX 20KC devices. Table APEX 20KC Device Features (Part Feature
MultiCore system integration Hot-socketing support SignalTap logic analysis 32-/64-bit, 33-MHz 32-/64-bit, 66-MHz MultiVolt Full support Full support Full support Full compliance Full compliance speed grades selected devices 1.8-V, 2.5-V, 3.3-V VCCIO VCCIO selected bank bank 5.0-V tolerant with external resistor Clock delay reduction clock multiplication Drive ClockLock output off-chip External clock feedback ClockShift circuitry LVDS support four PLLs ClockShift clock phase adjustment Eight
APEX 20KC Devices
ClockLock support
Dedicated clock input pins
Altera Corporation
APEX 20KC Programmable Logic Device
Table APEX 20KC Device Features (Part Feature
standard support
APEX 20KC Devices
1.8-V, 2.5-V, 3.3-V, 5.0-V 3.3-V PCI-X 3.3-V GTL+ LVCMOS LVTTL True-LVDSand LVPECL data pins EP20K400C larger devices) LVDS LVPECL clock pins devices) LVDS LVPECL data pins Mbps EP20K200C devices) HSTL Class PCI-X SSTL-2 Class SSTL-3 Class Dual-port FIFO
Memory support
APEX 20KC devices reconfigurable 100% tested prior shipment. result, test vectors have generated faultcoverage purposes. Instead, designer focus simulation design verification. addition, designer does need manage inventories different application-specific integrated circuit (ASIC) designs; APEX 20KC devices configured board specific functionality required. APEX 20KC devices configured system power-up with data stored Altera serial configuration device provided system controller. Altera offers in-system programmability (ISP)-capable EPC16, EPC8, EPC4, EPC2, EPC1 configuration devices one-time programmable (OTP) EPC1 configuration devices, which configure APEX 20KC devices serial data stream. Moreover, APEX 20KC devices contain optimized interface that permits microprocessors configure APEX 20KC devices serially parallel, synchronously asynchronously. interface also enables microprocessors treat APEX 20KC devices memory configure device writing virtual memory location, making reconfiguration easy.
Altera Corporation
APEX 20KC Programmable Logic Device
After APEX 20KC device been configured, reconfigured in-circuit resetting device loading data. Real-time changes made during system operation, enabling innovative reconfigurable computing applications. APEX 20KC devices supported Altera Quartus development system, single, integrated package that offers schematic design entry, compilation logic synthesis, full simulation worst-case timing analysis, SignalTap logic analysis, device configuration. Quartus software runs Windows-based PCs, SPARCstations, 9000 Series 700/800 workstations. Quartus software provides NativeLink interfaces other industrystandard UNIX workstation-based tools. example, designers invoke Quartus software from within third-party design tools. Further, Quartus software contains built-in optimized synthesis libraries; synthesis tools these libraries optimize designs APEX 20KC devices. example, Synopsys Design Compiler library, supplied with Quartus development system, includes DesignWare functions optimized APEX 20KC architecture.
Functional Description
APEX 20KC devices incorporate LUT-based logic, product-term-based logic, memory into device all-copper technology process. Signal interconnections within APEX 20KC devices well from device pins) provided FastTrack interconnect-a series fast, continuous column channels that entire length width device. Each element (IOE) located each column FastTrack interconnect. Each contains bidirectional buffer register that used either input output register feed input, output, bidirectional signals. When used with dedicated clock pin, these registers provide exceptional performance. IOEs provide variety features, such 3.3-V, 64-bit, 66-MHz compliance; JTAG support; slew-rate control; tri-state buffers. APEX 20KC devices offer enhanced support, including support 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, LVPECL, 3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, 3.3-V standards.
Altera Corporation
APEX 20KC Programmable Logic Device
implement variety memory functions, including CAM, RAM, dual-port RAM, ROM, FIFO functions. Embedding memory directly into improves performance reduces area compared distributed-RAM implementations. Moreover, abundance cascadable ESBs allows APEX 20KC devices implement multiple wide memory blocks high-density designs. ESB's high speed ensures implement small memory blocks without speed penalty. Additionally, designers ESBs create many different-sized memory blocks system requires. Figure shows overview APEX 20KC device. Figure APEX 20KC Device Block Diagram
Clock Management Circuitry
ClockLock
FastTrack Interconnect
Four-input data path functions. Product-term integration high-speed control logic state machines.
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
IOEs support PCI, GTL+, SSTL-3, LVDS, other standards.
Flexible integration embedded memory, including CAM, RAM, ROM, FIFO, other memory functions.
APEX 20KC devices provide four dedicated clock pins four dedicated input pins that drive register control inputs. These signals ensure efficient distribution high-speed, low-skew control signals, which dedicated routing channels provide short delays skews. Four dedicated inputs drive four global signals. These four global signals also driven internal logic, providing ideal solution clock divider internally generated asynchronous clear signals with high fan-out. dedicated clock pins featured APEX 20KC devices also feed logic. devices also feature ClockLock ClockBoost clock management circuitry.
Altera Corporation
APEX 20KC Programmable Logic Device
MegaLAB Structure
APEX 20KC devices constructed from series MegaLABstructures. Each MegaLAB structure contains logic array blocks (LABs), ESB, MegaLAB interconnect, which routes signals within MegaLAB structure. EP20K1000C devices, MegaLAB structures contain LABs. Signals routed between MegaLAB structures pins FastTrack interconnect. addition, edge LABs driven pins through local interconnect. Figure shows MegaLAB structure. Figure MegaLAB Structure
MegaLAB Interconnect
Adjacent IOEs
LE10
LE10
LE10
Local Interconnect
LABs
Logic Array Block
Each consists LEs, LEs' associated carry cascade chains, control signals, local interconnect. local interconnect transfers signals between same adjacent LABs, IOEs, ESBs. Quartus Compiler places associated logic within adjacent LABs, allowing fast local interconnect high performance. Figure shows APEX 20KC LAB. APEX 20KC devices interleaved structure. This structure allows each drive local interconnect areas, minimizing MegaLAB FastTrack interconnect providing higher performance flexibility. Each drive other through fast local interconnect.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure Structure
Interconnect
MegaLAB Interconnect
drive local, MegaLAB, row, column interconnects.
To/From Adjacent LAB, ESB, IOEs To/From Adjacent LAB, ESB, IOEs
Local Interconnect
Column Interconnect driven local interconnect areas. These drive local interconnect areas.
Each contains dedicated logic driving control signals ESBs. control signals include clock, clock enable, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, synchronous load signals. maximum control signals used time. Although synchronous load clear signals generally used when implementing counters, they also used with other functions. Each clocks clock enable signals. Each LAB's clock clock enable signals linked (e.g., particular using CLK1 will also CLKENA1). with same clock different clock enable signals either both clock signals placed into separate LABs. both rising falling edges clock used LAB, both LABwide clock signals used.
Altera Corporation
APEX 20KC Programmable Logic Device
LAB-wide control signals generated from local interconnect, global signals, dedicated clock pins. inherent skew FastTrack interconnect enables used clock distribution. Figure shows control signal generation circuit. Figure Control Signal Generation
Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect SYNCLOAD LABCLKENA2 SYNCCLR LABCLK2 LABCLKENA1 LABCLR1
LABCLK1
LABCLR2
Notes Figure
LABCLR1 LABCLR2 signals also control asynchronous load asynchronous preset within LAB. SYNCCLR signal generated local interconnect global signals.
Logic Element
smallest unit logic APEX 20KC architecture, compact provides efficient logic usage. Each contains four-input LUT, which function generator that quickly implement function four variables. addition, each contains programmable register carry cascade chains. Each drives local interconnect, MegaLAB interconnect, FastTrack interconnect routing structures. Figure
Altera Corporation
APEX 20KC Programmable Logic Device
Figure APEX 20KC Logic Element
Register Bypass LAB-wide LAB-wide Synchronous Synchronous Load Clear Cascade-In Packed Register Select Programmable Register
Carry-In
data1 data2 data3 data4
Look-Up Table (LUT)
Carry Chain
Cascade Chain
Synchronous Load Clear Logic
FastTrack Interconnect, MegaLAB Interconnect, Local Interconnect
CLRN FastTrack Interconnect, MegaLAB Interconnect, Local Interconnect
labclr1 labclr2 Chip-Wide Reset
Asynchronous Clear/Preset/ Load Logic
Clock Clock Enable Select labclk1 labclk2
labclkena1 labclkena2 Carry-Out Cascade-Out
Each LE's programmable register configured operation. register's clock clear control signals driven global signals, general-purpose pins, internal logic. combinatorial functions, register bypassed output drives outputs Each outputs that drive local, MegaLAB, FastTrack interconnect routing structure. Each output driven independently LUT's register's output. example, drive output while register drives other output. This feature, called register packing, improves device utilization because register used unrelated functions. also drive registered unregistered versions output.
Altera Corporation
APEX 20KC Programmable Logic Device
APEX 20KC architecture provides types dedicated high-speed data paths that connect adjacent without using local interconnect paths: carry chains cascade chains. carry chain supports high-speed arithmetic functions such counters adders, while cascade chain implements wide-input functions such equality comparators with minimum delay. Carry cascade chains connect through LABs same MegaLAB structure.
Carry Chain
carry chain provides very fast carry-forward function between LEs. carry-in signal from lower-order drives forward into higherorder carry chain, feeds into both next portion carry chain. This feature allows APEX 20KC architecture implement high-speed counters, adders, comparators arbitrary width. Carry chain logic created automatically Quartus Compiler during design processing, manually designer during design entry. Parameterized functions such DesignWare functions from Synopsys library parameterized modules (LPM) functions automatically take advantage carry chains appropriate functions. Quartus Compiler creates carry chains longer than automatically linking LABs together. enhanced fitting, long carry chain skips alternate LABs MegaLAB structure. carry chain longer than skips either from even-numbered next evennumbered LAB, from odd-numbered next oddnumbered LAB. example, last first upper-left MegaLAB structure carries first third MegaLAB structure. Figure shows n-bit full adder implemented with carry chain. portion generates bits using input signals carry-in signal; routed output register bypassed simple adders used accumulator functions. Another portion carry chain logic generates carry-out signal, which routed directly carryin signal next-higher-order bit. final carry-out signal routed where driven onto local, MegaLAB, FastTrack interconnect routing structures.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure APEX 20KC Carry Chain
Carry-In
Register
Carry Chain
Register
Carry Chain
Register
Carry Chain
Register
Carry-Out
Carry Chain
Altera Corporation
APEX 20KC Programmable Logic Device
Cascade Chain
With cascade chain, APEX 20KC architecture implement functions with very wide fan-in. Adjacent LUTs compute portions function parallel; cascade chain serially connects intermediate values. cascade chain logical logical (via Morgan's inversion) connect outputs adjacent LEs. Each additional provides four more inputs effective width function, with short cascade delay. Cascade chain logic created automatically Quartus Compiler during design processing, manually designer during design entry. Cascade chains longer than implemented automatically linking LABs together. enhanced fitting, long cascade chain skips alternate LABs MegaLAB structure. cascade chain longer than skips either from even-numbered next even-numbered LAB, from odd-numbered next odd-numbered LAB. example, last first upper-left MegaLAB structure carries first third MegaLAB structure. Figure shows cascade function connect adjacent form functions with wide fan-in. Figure APEX 20KC Cascade Chain
Cascade Chain Cascade Chain
d[3.0]
d[3.0]
d[7.4]
d[7.4]
d[(4n 1).(4n
d[(4n 1).(4n
Altera Corporation
APEX 20KC Programmable Logic Device
Operating Modes
APEX 20KC operate following three modes:
Normal mode Arithmetic mode Counter mode
Each mode uses resources differently. each mode, seven available inputs LE-the four data inputs from local interconnect, feedback from programmable register, carry-in cascade-in from previous LE-are directed different destinations implement desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, synchronous load, clock enable control register. These LAB-wide signals available modes. Quartus software, conjunction with parameterized functions such DesignWare functions, automatically chooses appropriate mode common functions such counters, adders, multipliers. required, designer also create special-purpose functions that specify which operating mode optimal performance. Figure shows operating modes.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure APEX 20KC Operating Modes
Normal Mode
Carry-In data1 data2 data3 data4 4-Input
Cascade-In
LAB-Wide Clock Enable
CLRN
Cascade-Out
Arithmetic Mode
Carry-In Cascade-In
LAB-Wide Clock Enable
data1 data2
3-Input 3-Input Carry-Out Cascade-Out
CLRN
Counter Mode
Carry-In
Cascade-In
LAB-Wide Synchronous Load
LAB-Wide Synchronous Clear LAB-Wide Clock Enable
data1 data2 data3 (data) 3-Input Carry-Out Cascade-Out
3-Input
CLRN
Notes Figure
normal mode support register packing. There LAB-wide clock enables LAB. When using carry-in normal mode, packed register feature unavailable. register feedback multiplexer available each LAB. DATA1 DATA2 input signals supply counter enable, down control, register feedback signals other than second LAB. LAB-wide synchronous clear wide synchronous load affect registers LAB.
Altera Corporation
APEX 20KC Programmable Logic Device
Normal Mode normal mode suitable general logic applications, combinatorial functions, wide decoding functions that take advantage cascade chain. normal mode, four data inputs from local interconnect carry-in inputs four-input LUT. Quartus Compiler automatically selects carry-in DATA3 signal inputs LUT. output combined with cascade-in signal form cascade chain through cascade-out signal. normal mode support packed registers. Arithmetic Mode arithmetic mode ideal implementing adders, accumulators, comparators. arithmetic mode uses 3-input LUTs. computes three-input function; other generates carry output. shown Figure first uses carry-in signal data inputs from local interconnect generate combinatorial registered output. example, when implementing adder, this output three signals: DATA1, DATA2, carry-in. second uses same three signals generate carry-out signal, thereby creating carry chain. arithmetic mode also supports simultaneous cascade chain. arithmetic mode drive registered unregistered versions output. Quartus software implements parameterized functions that arithmetic mode automatically where appropriate; designer does need specify carry chain will used. Counter Mode counter mode offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load options. counter enable synchronous up/down control signals generated from data inputs local interconnect. synchronous clear synchronous load options LAB-wide signals that affect registers LAB. Consequently, counter mode, other that must used part same counter used combinatorial function. Quartus software automatically places registers that used counter into other LABs.
Altera Corporation
APEX 20KC Programmable Logic Device
counter mode uses 3-input LUTs: generates counter data, other generates fast carry bit. 2-to-1 multiplexer provides synchronous loading, another gate provides synchronous clearing. cascade function used counter mode, synchronous clear load overrides signal carried cascade chain. synchronous clear overrides synchronous load. arithmetic mode drive registered unregistered versions output.
Clear Preset Logic Control
Logic register's clear preset signals controlled LAB-wide signals. directly supports asynchronous clear function. Quartus Compiler NOT-gate push-back technique emulate asynchronous preset emulate simultaneous preset clear asynchronous load. However, this technique uses three additional register. emulation performed automatically when design compiled. Registers that emulate simultaneous preset load will enter unknown state upon power-up when chip-wide reset asserted. addition clear preset modes, APEX 20KC devices provide chip-wide reset (DEV_CLRn) that resets registers device. this controlled through option Quartus software that before compilation. chip-wide reset overrides other control signals. Registers using asynchronous preset preset when chip-wide reset asserted; this effect results from inversion technique used implement asynchronous preset.
FastTrack Interconnect
APEX 20KC architecture, connections between LEs, ESBs, pins provided FastTrack interconnect. FastTrack interconnect series continuous horizontal vertical routing channels that traverse device. This global routing structure provides predictable performance, even complex designs. contrast, segmented routing FPGAs requires switch matrices connect variable number routing paths, increasing delays between logic resources reducing performance. FastTrack interconnect consists column interconnect channels that span entire device. interconnect routes signals throughout MegaLAB structures; column interconnect routes signals throughout column MegaLAB structures. When using column interconnect, IOE, drive other IOE, device. Figure
Altera Corporation
APEX 20KC Programmable Logic Device
Figure APEX 20KC Interconnect Structure
Interconnect
MegaLAB
MegaLAB
MegaLAB
MegaLAB
Column Interconnect
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
line driven directly LEs, IOEs, ESBs that row. Further, column line drive line, allowing IOE, drive elements different column interconnect. interconnect drives MegaLAB interconnect drive LEs, IOEs, ESBs particular MegaLAB structure. column line directly driven LEs, IOEs, ESBs that column. column line device's left right edge also driven IOEs. column line used route signals from another. column line drive line; also drive MegaLAB interconnect directly, allowing faster connections between rows. Figure shows FastTrack interconnect uses local interconnect drive within MegaLAB structures.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure FastTrack Connection Local Interconnect
MegaLAB Structure
MegaLAB Structure Column MegaLAB Interconnect Column Interconnect Drives MegaLAB Interconnect
MegaLAB Interconnect Drives Local Interconnect Column
Altera Corporation
APEX 20KC Programmable Logic Device
Figure shows intersection column interconnect, these forms interconnects drive each other. Figure Driving FastTrack Interconnect
Interconnect
MegaLAB Interconnect
Column Interconnect
Local Interconnect
APEX 20KC devices include enhanced interconnect structure faster routing input signals with high fan-out. Column pins drive FastRowinterconnect, which routes signals directly into local interconnect without having drive through MegaLAB interconnect. FastRow lines traverse MegaLAB structures. Also, these pins drive local interconnect directly fast setup times. EP20K400C larger devices, FastRow interconnect drives MegaLAB structures left corner, MegaLAB structures right corner, MegaLAB structures bottom left corner, MegaLAB structures bottom right corner. EP20K200C smaller devices, FastRow interconnect drives MegaLAB structures MegaLAB structures bottom device. devices, FastRow interconnect drives local interconnect appropriate MegaLAB structures except local interconnect side MegaLAB opposite ESB. Pins using FastRow interconnect achieve faster set-up time, signal does need MegaLAB interconnect line reach destination Figure shows FastRow interconnect.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure APEX 20KC FastRow Interconnect
FastRow Interconnect Drives Local Interconnect MegaLAB Structures Select Vertical Pins Drive Local Interconnect FastRow Interconnect
FastRow Interconnect
Local Interconnect
MegaLAB
LABs
MegaLAB
Table summarizes various elements APEX 20KC architecture drive each other.
Altera Corporation
APEX 20KC Programmable Logic Device
Table APEX 20KC Routing Scheme Source
Column
Destination
Local MegaLAB Interconnect Interconnect FastRow Column FastTrack Interconnect FastTrack Interconnect Interconnect
Column Local interconnect MegaLAB interconnect FastTrack interconnect Column FastTrack interconnect FastRow interconnect
Product-Term Logic
product-term portion MultiCore architecture implemented with ESB. configured block macrocells ESB-by-ESB basis. Each inputs from adjacent local interconnect; therefore, driven MegaLAB interconnect adjacent LAB. Also, nine macrocells feed back into through local interconnect higher performance. Dedicated clock pins, global signals, additional inputs from local interconnect drive control signals. product-term mode, each contains macrocells. Each macrocell consists product terms programmable register. Figure shows product-term mode.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure Product-Term Logic
Dedicated Clocks Global Signals
MegaLAB Interconnect
Macrocell Inputs CLK[1.0] ENA[1.0] CLRN[1.0] Column Interconnect
From Adjacent
Local Interconnect
Macrocells
APEX 20KC macrocells configured individually either sequential combinatorial logic operation. macrocell consists three functional blocks: logic array, product-term select matrix, programmable register. Combinatorial logic implemented product terms. productterm select matrix allocates these product terms either primary logic inputs gates) implement combinatorial functions, parallel expanders used increase logic available another macrocell. product term inverted; Quartus software uses this feature perform Morgan's inversion more efficient implementation wide functions. Quartus Compiler NOT-gate push-back technique emulate asynchronous preset. Figure shows APEX 20KC macrocell.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure APEX 20KC Macrocell
ESB-Wide ESB-Wide ESB-Wide Clears Clock Enables Clocks Parallel Logic Expanders (From Other Macrocells)
Programmable Register
ProductTerm Select Matrix
Clock/ Enable Select
Output
CLRN
Signals from Local Interconnect Clear Select
registered functions, each macrocell register programmed individually implement operation with programmable clock control. register bypassed combinatorial operation. During design entry, designer specifies desired register type; Quartus software then selects most efficient register operation each registered function optimize resource utilization. Quartus software other synthesis tools also select most efficient register operation automatically when synthesizing designs. Each programmable register clocked ESB-wide clocks. ESB-wide clocks generated from device dedicated clock pins, global signals, local interconnect. Each clock also associated clock enable, generated from local interconnect. clock clock enable signals related particular ESB; macrocell using clock also uses associated clock enable. both rising falling edges clock used ESB, both ESB-wide clock signals used.
Altera Corporation
APEX 20KC Programmable Logic Device
programmable register also supports asynchronous clear function. Within ESB, asynchronous clears generated from global signals local interconnect. Each macrocell either choose between asynchronous clear signals choose cleared. Either clear signals inverted within ESB. Figure shows control logic when implementing product-terms. Figure Product-Term Mode Control Logic
Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect
CLK2
CLKENA2
CLK1
CLKENA1 CLR2
CLR1
Parallel Expanders
Parallel expanders unused product terms that allocated neighboring macrocell implement fast, complex logic functions. Parallel expanders allow product terms feed macrocell logic directly, with product terms provided macrocell parallel expanders provided neighboring macrocells ESB. Quartus Compiler allocate sets parallel expanders macrocells automatically. Each parallel expanders incurs small, incremental timing delay. Figure shows APEX 20KC parallel expanders.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure APEX 20KC Parallel Expanders
From Previous Macrocell
ProductTerm Select Matrix
Macrocell ProductTerm Logic Parallel Expander Switch
ProductTerm Select Matrix Parallel Expander Switch
Macrocell ProductTerm Logic
Signals from Local Interconnect
Next Macrocell
Embedded System Block
implement various types memory blocks, including dual-port RAM, ROM, FIFO, blocks. includes input output registers; input registers synchronize writes, output registers pipeline designs improve system performance. offers dual-port mode, which supports simultaneous reads writes different clock frequencies. Figure shows block diagram. Figure Block Diagram
wraddress[] data[] wren inclock inclocken inaclr rdaddress[] rden outclock outclocken outaclr
Altera Corporation
APEX 20KC Programmable Logic Device
ESBs implement synchronous RAM, which easier than asynchronous RAM. circuit using asynchronous must generate write enable (WE) signal, while ensuring that data address signals meet setup hold time specifications relative signal. contrast, ESB's synchronous generates signal self-timed with respect global clock. Circuits using ESB's selftimed must only meet setup hold time specifications global clock. inputs driven adjacent local interconnect, which turn driven FastTrack MegaLAB interconnect. Because driven local interconnect, adjacent drive directly fast memory access. outputs drive FastTrack MegaLAB interconnects. addition, outputs, nine which unique output lines, drive local interconnect fast connection adjacent fast feedback product-term logic. When implementing memory, each configured following sizes: 1,024 2,048 combining multiple ESBs, Quartus software implements larger memory blocks automatically. example, blocks combined form block, blocks combined form block. Memory performance does degrade memory blocks 2,048 words deep. Each implement 2,048-word-deep memory; ESBs used parallel, eliminating need external control logic associated delays. create high-speed memory block that more than 2,048 words deep, ESBs drive tri-state lines. Each tri-state line connects ESBs column MegaLAB structures, drives MegaLAB interconnect column FastTrack interconnect throughout column. Each incorporates programmable decoder activate tri-state driver appropriately. instance, implement 8,192-word-deep memory, four ESBs used. Eleven address lines drive memory, more drive tri-state decoder. Depending which 2,048-word memory page selected, appropriate driver turned driving output tri-state line. Quartus software automatically combines ESBs with tri-state lines form deeper memory blocks. internal tri-state control logic designed avoid internal contention floating lines. Figure
Altera Corporation
APEX 20KC Programmable Logic Device
Figure Deep Memory Block Implemented with Multiple ESBs
Address Decoder
System Logic
implements forms dual-port memory: read/write clock mode input/output clock mode. also used bidirectional, dual-port memory applications which ports read write simultaneously. implement this type dual-port memory, ESBs used support simultaneous reads writes. also Altera megafunctions implement dual-port applications where both ports read write, shown Figure Figure APEX 20KC Implementing Dual-Port
Port address_a[] data_a[] we_a clkena_a Clock Port address_b[] data_b[] we_b clkena_b Clock
Altera Corporation
APEX 20KC Programmable Logic Device
Read/Write Clock Mode
read/write clock mode contains clocks. clock controls registers associated with writing: data input, write address. other clock controls registers associated with reading: read enable (RE), read address, data output. also supports clock enable asynchronous clear signals; these signals also control read write registers independently. Read/write clock mode commonly used applications where reads writes occur different system frequencies. Figure shows read/write clock mode. Figure Read/Write Clock Mode
Dedicated Inputs Global Signals Dedicated Clocks RAM/ROM Data 1,024 2,048 Data
Note
data[
MegaLAB, FastTrack Local Interconnect
ress[
Address
wren
Write Enable
utclken nclken
nclock
Write Pulse Generator
utclock
Note Figure
registers cleared asynchronously local interconnect signals, global signals, chip-wide reset.
Altera Corporation
APEX 20KC Programmable Logic Device
Input/Output Clock Mode
input/output clock mode contains clocks. clock controls registers inputs into ESB: data input, read address, write address. other clock controls data output registers. also supports clock enable asynchronous clear signals; these signals also control reading writing registers independently. Input/output clock mode commonly used applications where reads writes occur same system frequency, require different clock enable signals input output registers. Figure shows input/output clock mode. Figure Input/Output Clock Mode
Dedicated Inputs Global Signals Dedicated Clocks data[
Note
RAM/ROM Data 1,024 2,048 Data
MegaLAB, FastTrack Local Interconnect
rdaddress[
Read Address
wraddress[
Write Address
rden Read Enable
wren
outclken
Write Enable
inclken
inclock
Write Pulse Generator
outclock
Note Figure
registers cleared asynchronously local interconnect signals, global signals, chip-wide reset.
Altera Corporation
APEX 20KC Programmable Logic Device
Single-Port Mode
APEX 20KC also supports single-port mode, which used when simultaneous reads writes required. Figure Figure Single-Port Mode
Dedicated Inputs Global Signals Dedicated Clocks data[
Note
RAM/ROM Data 1,024 2,048 Data
MegaLAB, FastTrack Local Interconnect
address[
Address
wren Write Enable
outclken
inclken
inclock
Write Pulse Generator
outclock
Note toFigure
registers asynchronously cleared local interconnect signals, global signals, chip-wide reset.
Content-Addressable Memory
APEX 20KC devices, implement CAM. thought inverse RAM. When read, outputs data given address. Conversely, outputs address given data word. example, data FA12 stored address outputs when FA12 driven into
Altera Corporation
APEX 20KC Programmable Logic Device
used high-speed search operations. When searching data within block, search performed serially. Thus, finding particular data word take many cycles. searches addresses parallel outputs address storing particular word. When match found, match flag high. Figure shows block diagram.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure APEX 20KC Block Diagram
wraddress[] data[] wren inclock inclocken inaclr data_address[] match outclock outclocken outaclr
used application requiring high-speed searches, such networking, communications, data compression, cache management. APEX 20KC on-chip provides faster system performance than traditional discrete CAM. Integrating logic into APEX 20KC device eliminates off-chip on-chip delays, improving system performance. When mode, implements 32-word, 32-bit CAM. Wider deeper implemented combining multiple CAMs with some ancillary logic implemented LEs. Quartus software combines ESBs automatically create larger CAMs. supports writing "don't care" bits into words memory. "don't care" used mask comparisons; "don't care" effect matches. output encoded unencoded. When encoded, outputs encoded address data's location. instance, data located address output When unencoded, uses outputs show location data over clock cycles. this case, data located address 12th output line goes high. When using unencoded outputs, clock cycles required read output because 16-bit output used show status words. encoded output better suited designs that ensure duplicate data written into CAM. duplicate data written into locations, CAM's output will incorrect. contain duplicate data, unencoded output better solution; with unencoded outputs distinguish multiple data locations. pre-loaded with data during configuration, written during system operation. most cases, clock cycles required write each word into CAM. When "don't care" bits used, third clock cycle required.
Altera Corporation
APEX 20KC Programmable Logic Device
more information APEX 20KC devices CAM, Application Note (Implementing High-Speed Search Applications with APEX CAM).
Driving Signals
ESBs provide flexible options driving control signals. Different clocks used inputs outputs. Registers inserted independently data input, data output, read address, write address, signals. global signals local interconnect drive signals. global signals, dedicated clock pins, local interconnect drive clock signals. Because drive local interconnect, control signals clock, clock enable, asynchronous clear signals. Figure shows control signal generation logic. Figure Control Signal Generation
Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect RDEN
WREN
INCLKENA
OUTCLKENA
OUTCLR
INCLOCK
OUTCLOCK
INCLR
local interconnect, which driven adjacent (for high-speed connection ESB) MegaLAB interconnect. drive local, MegaLAB, FastTrack interconnect routing structure drive IOEs same MegaLAB structure anywhere device.
Altera Corporation
APEX 20KC Programmable Logic Device
Implementing Logic
addition implementing logic with product terms, implement logic functions when programmed with read-only pattern during configuration, creating large LUT. With LUTs, combinatorial functions implemented looking results, rather than computing them. This implementation combinatorial functions faster than using algorithms implemented general logic, performance advantage that further enhanced fast access times ESBs. large capacity ESBs enables designers implement complex functions logic level without routing delays associated with linked distributed blocks. Parameterized functions such functions take advantage automatically. Further, Quartus software implement portions design with ESBs where appropriate.
Programmable Speed/Power Control
APEX 20KC ESBs offer high-speed mode that supports very fast operation ESB-by-ESB basis. When high speed required, this feature turned reduce ESB's power dissipation 50%. ESBs that power incur nominal timing delay adder. This Turbo Bitoption available ESBs that implement product-term logic memory functions. that used will powered down that does consume current. Designers program each APEX 20KC device either high-speed low-power operation. result, speed-critical paths design high speed, while remaining paths operate reduced power.
Structure
APEX 20KC contains bidirectional buffer register that used either input register external data requiring fast setup times output register data requiring fast clock-to-output performance. IOEs used input, output, bidirectional pins.
Altera Corporation
APEX 20KC Programmable Logic Device
APEX 20KC devices include enhanced IOE, which drives FastRow interconnect. FastRow interconnect connects column directly local interconnect within MegaLAB structures. This feature provides fast setup times pins that drive high fan-outs with complex logic, such designs. fast bidirectional timing, registers using local routing improve setup times timing. APEX 20KC also includes direct support open-drain operation, giving faster clock-to-output open-drain signals. Some programmable delays APEX 20KC offer multiple levels delay fine-tune setup hold time requirements. Quartus Compiler sets these delays default minimize setup time while providing zero hold time. Quartus Compiler uses programmable inversion option invert signals from column interconnect automatically where appropriate. Because APEX 20KC offers output enable pin, Quartus Compiler emulate open-drain operation efficiently. APEX 20KC includes programmable delays that activated ensure zero hold times, minimum clock-to-output times, input register-to-core register transfers, core-to-output register transfers. path which directly drives register require delay ensure zero hold time, whereas path which drives register through combinatorial logic require delay. Table describes APEX 20KC programmable delays their logic options Quartus software. Table APEX 20KC Programmable Delay Chains Programmable Delay
Input core delay Input input register delay Core output register delay Output register delay Clock enable delay
Quartus Logic Option
Decrease input delay internal cells Decrease input delay input registers Decrease input delay output register Increase delay output Increase clock enable delay
Quartus Compiler program these delays automatically minimize setup time while providing zero hold time.
Altera Corporation
APEX 20KC Programmable Logic Device
register APEX 20KC programmed power-up high after configuration complete. programmed power-up low, asynchronous clear control register. programmed power-up high, asynchronous preset control register. This feature useful cases where APEX 20KC device controls activelow input another device; prevents inadvertent activation input upon power-up. Figure shows fast bidirectional pins implemented APEX 20KC devices. This feature useful cases where APEX 20KC device controls active-low input another device; prevents inadvertent activation input upon power-up.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure APEX 20KC Bidirectional Registers
Row, Column, FastRow, Dedicated Local Interconnect Clock Inputs Dedicated Inputs Peripheral Control
Notes (1),
Register
CLRN
Chip-Wide Reset
OE[7.0]
Chip-Wide Output Enable
Input Core Delay Input Core Delay Core Output Register Delay Input Input Register Delay CLK[1.0] Output Register Output Register Delay
VCCIO
Optional Clamp
Open-Drain Output Slew-Rate Control
CLRN/
CLK[3.0] ENA[5.0] Clock Enable Delay CLRn[1.0]
Chip-Wide Reset Input Register
CLRN
Input Core Delay
Chip-Wide Reset
Altera Corporation
APEX 20KC Programmable Logic Device Data Sheet Notes Figure
This programmable delay four settings: three levels delay. output enable input registers registers adjacent bidirectional pin.
Each drives row, column, MegaLAB, local interconnect when used input bidirectional pin. drive local, MegaLAB, row, column interconnect; column drive column interconnect. Figure shows connects interconnect. Figure Connection Interconnect
Interconnect MegaLAB Interconnect
drive through row, column, MegaLAB interconnect.
Each drive local, MegaLAB, row, column interconnect. Each data signal driven local interconnect.
drive through local interconnect faster clock-to-output times.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure shows column connects interconnect. Figure Column Connection Interconnect
Each drive column interconnect. IOEs also drive FastRow column interconnects. Each data signal driven local interconnect.
drive through local interconnect faster clock-to-output times.
drive column through row, column, MegaLAB interconnect.
Column Interconnect
Interconnect
MegaLAB Interconnect
Dedicated Fast Pins
APEX 20KC devices incorporate enhancement support bidirectional pins with high internal fan-out such control signals. These pins called dedicated fast pins (FAST1, FAST2, FAST3, FAST4) replace dedicated inputs. These pins used fast clock, clear, high fan-out logic signal distribution. They also drive out. dedicated fast data output tri-state control driven local interconnect from adjacent MegaLAB high speed.
Altera Corporation
APEX 20KC Programmable Logic Device
Advanced Standard Support
APEX 20KC IOEs support following standards: LVTTL, LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, PCI-X, 3.3-V AGP, LVDS, LVPECL, GTL+, CTT, HSTL Class SSTL-3 Class SSTL-2 Class
more information standards supported APEX 20KC devices, Application Note (Using Selectable Standards Altera Devices). APEX 20KC device contains eight banks. packages, banks linked form four banks. banks directly support standards except LVDS LVPECL. banks support LVDS LVPECL Mbps channel with addition external resistors. addition, block within bank contains circuitry support high-speed True-LVDS LVPECL inputs, another block within bank supports high-speed True-LVDS LVPECL outputs. LVDS blocks support standards. Each bank VCCIO pins. single device support 1.8-V, 2.5-V, 3.3-V interfaces; each bank support different standard independently. Each bank also separate VREF level that each bank support terminated standards (such SSTL-3) independently. Within bank, terminated standards supported. EP20K400C larger APEX 20KC devices support LVDS interface data pins (EP20K200C devices support LVDS clock pins, data pins). EP20K400C EP20K600C devices support LVDS data pins Mbps channel. EP20K1000C devices support LVDS channels Mbps. Each bank support multiple standards with same VCCIO output pins. Each bank support voltage-referenced standard, support multiple standards with same VCCIO voltage level. example, when VCCIO bank support LVTTL, LVCMOS, 3.3-V PCI, SSTL-3 inputs outputs. When LVDS banks used LVDS standard, they support other standards. Figure shows arrangement APEX 20KC banks.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure APEX 20KC Banks
Bank
Bank
Bank
LVDS Output Block Bank
Regular Banks Support LVPECL LVTTL LVCMOS 3.3-V GTL+ HSTL SSTL-2 Class SSTL-3 Class Individual Power
Bank LVDS Input Block
Bank
Bank
Notes Figure
Bank
more information placing pins LVDS blocks, refer "Guidelines Using LVDS Blocks" section Application Note (Using LVDS APEX 20KE Devices). LVDS input output blocks used LVDS, they support standards used input, output, bidirectional pins with VCCIO
Power Sequencing Socketing
Because APEX 20KC devices used mixed-voltage environment, they have been designed specifically tolerate possible power-up sequence. Therefore, VCCIO VCCINT power supplies powered order.
Altera Corporation
APEX 20KC Programmable Logic Device
Signals driven into APEX 20KC devices before during powerup without damaging device. addition, APEX 20KC devices drive during power-up. Once operating conditions reached device configured, APEX 20KC devices operate specified user.
MultiVolt Interface
APEX architecture supports MultiVolt interface feature, which allows APEX devices packages interface with systems different supply voltages. devices have pins internal operation input buffers (VCCINT), another output drivers (VCCIO). APEX 20KC devices support MultiVolt interface feature. APEX 20KC VCCINT pins must always connected 1.8-V power supply. With 1.8-V VCCINT level, input pins 1.8-V, 2.5-V, 3.3-V tolerant. VCCIO pins connected either 1.8-V, 2.5-V, 3.3-V power supply, depending standard requirements. When VCCIO pins connected 1.8-V power supply, output levels compatible with 1.8-V systems. When VCCIO pins connected 2.5-V power supply, output levels compatible with 2.5-V systems. When VCCIO pins connected 3.3-V power supply, output high compatible with 3.3-V 5.0-V systems. APEX 20KC device 5.0-V tolerant with addition resistor clamp diode enabled.
more information 5.0-V tolerance, refer "5.0-V Tolerance APEX 20KE Devices White Paper," information found therein also applies APEX 20KC devices. Table summarizes APEX 20KC MultiVolt support.
Table APEX 20KC MultiVolt Support VCCIO
Notes Table
clamping diode must disabled drive input with voltages higher than VCCIO, except 5.0-V input case. APEX 20KC device made 5.0-V tolerant with addition external resistor clamp diode enabled. When VCCIO APEX 20KC device drive 2.5-V device with 3.3-V tolerant inputs.
Input Signals
Output Signals
Altera Corporation
APEX 20KC Programmable Logic Device
Open-drain output pins APEX 20KC devices (with series resistor pull-up resistor 5.0-V supply) drive 5.0-V CMOS input pins that require When inactive, trace will pulled resistor. open-drain will only drive tristate; will never drive high. rise time dependent value pull-up resistor load impedance. current specification should considered when selecting pull-up resistor.
ClockLock ClockBoost Features
APEX 20KC devices support ClockLock ClockBoost clock management features, which implemented with PLLs. ClockLock circuitry uses synchronizing that reduces clock delay skew within device. This reduction minimizes clock-to-output setup times while maintaining zero hold times. ClockBoost circuitry, which provides clock multiplier, allows designer enhance device area efficiency sharing resources within device. ClockBoost circuitry allows designer distribute low-speed clock multiply that clock on-device. APEX 20KC devices include high-speed clock tree; unlike ASICs, user does have design optimize clock tree. ClockLock ClockBoost features work conjunction with APEX 20KC device's high-speed clock provide significant improvements system performance bandwidth. APEX 20KC devices speed grades have PLLs support ClockLock ClockBoost features. ClockLock ClockBoost features APEX 20KC devices enabled through Quartus software. External devices required these features.
APEX 20KC ClockLock Feature
APEX 20KC devices include four PLLs, which used independently. PLLs designed either general-purpose LVDS devices that support LVDS pins). remaining PLLs designed general-purpose use. EP20K200C devices have PLLs; EP20K400C larger devices have four PLLs. following sections describe some features offered APEX 20KC PLLs.
External Feedback
ClockLock circuit's output driven off-chip clock other devices system; further, feedback loop routed off-chip. This feature allows designer exercise fine control over interface between APEX 20KC device another high-speed device, such SDRAM.
Altera Corporation
APEX 20KC Programmable Logic Device
Clock Multiplication
APEX 20KC ClockBoost circuit multiply divide clocks programmable number. clock multiplied m/(n where range from ranges from Clock multiplication division used time-domain multiplexing other functions, which reduce design requirements.
Clock Phase Delay Adjustment
APEX 20KC ClockShift feature allows clock phase delay adjusted. clock phase adjusted steps. clock delay adjusted increase decrease clock delay arbitrary amount, clock period.
LVDS Support
APEX 20KC devices support differential LVDS buffers input output clock signals that interface with external devices. This controlled Quartus software assigning clock pins with LVDS standard assignment. high-speed PLLs designed support LVDS interface. When using LVDS, clock runs slower rate than data transfer rate. Thus, PLLs used multiply clock internally capture LVDS data. example, clock support Mbps LVDS data transfer. this example, multiplies incoming clock eight support high-speed data transfer. PLLs EP20K400C larger devices high-speed LVDS interfacing.
Lock Signals
APEX 20KC ClockLock circuitry supports individual LOCK signals. LOCK signal drives high when ClockLock circuit locked onto input clock. LOCK signals optional each ClockLock circuit; when used, they pins.
Altera Corporation
APEX 20KC Programmable Logic Device
ClockLock ClockBoost Timing Parameters
ClockLock ClockBoost circuitry function properly, incoming clock must meet certain requirements. these specifications met, circuitry lock onto incoming clock, which generates erroneous clock within device. clock generated ClockLock ClockBoost circuitry must also meet certain specifications. incoming clock meets these requirements during configuration, APEX 20KC ClockLock ClockBoost circuitry will lock onto clock during configuration. circuit will ready immediately after configuration. APEX 20KC devices, clock input standard programmable, cannot respond clock until device configured. locks onto input clock soon configuration complete. Figure shows incoming generated clock specifications. more information ClockLock ClockBoost circuitry, Application Note 115: Using ClockLock ClockBoost Features APEX Devices.
Figure Specifications Incoming Generated Clocks
parameter refers nominal input clock period; parameter refers nominal output clock period.
CLK1, CLK2 CLK4 INDUTY CLKDEV
Input Clock
INCLKSTB
OUTDUTY
ClockLock Generated Clock
JITTER
JITTER
Note Figure
Rise fall times measured from 90%.
Altera Corporation
APEX 20KC Programmable Logic Device
Tables summarize ClockLock ClockBoost parameters APEX 20KC devices. Table APEX 20KC ClockLock ClockBoost Parameters Symbol
INDUTY INJITTER tOUTJITTER
Note
input period 0.35% output period
Parameter
Input rise time Input fall time Input duty cycle Input jitter peak-to-peak jitter ClockLock ClockBoost-generated clock Duty cycle ClockLock ClockBoost-generated clock
Condition
Unit
tOUTDUTY
tLOCK (2), Time required ClockLock ClockBoost acquire lock
Table APEX 20KC Clock Input Output Parameters (Part Symbol Parameter Standard
Note Speed Grade
Speed Grade
Units
fVCO fCLOCK0 fCLOCK1 fCLOCK0_EXT
Voltage controlled oscillator operating range Clock0 output frequency internal Clock1 output frequency internal Output clock frequency external clock0 output 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL GTL+ SSTL-2 Class SSTL-2 Class SSTL-3 Class SSTL-3 Class LVDS
Altera Corporation
APEX 20KC Programmable Logic Device
Table APEX 20KC Clock Input Output Parameters (Part Symbol Parameter Standard
Note Speed Grade
Speed Grade
Units
fCLOCK1_EXT
Output clock frequency external clock1 output
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL GTL+ SSTL-2 Class SSTL-2 Class SSTL-3 Class SSTL-3 Class LVDS
Input clock frequency
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL GTL+ SSTL-2 Class SSTL-2 Class SSTL-3 Class SSTL-3 Class LVDS
Notes Tables
input clock specifications must met. lock onto incoming clock clock specifications met, creating erroneous clock within device. maximum lock time 2,000 input clock cycles, whichever occurs first. Before configuration, circuits disable powered down. During configuration, PLLs remain disabled. PLLs begin lock once device user mode. clock enable feature used, lock begins once CLKLK_ENA goes high user mode. operating range fVCO LVDS mode. Contact Altera Applications information these parameters.
SignalTap Embedded Logic Analyzer
APEX 20KC devices include device enhancements support SignalTap embedded logic analyzer. including this circuitry, APEX 20KC device provides ability monitor design operation over period time through IEEE Std. 1149.1 (JTAG) circuitry; designer analyze internal logic speed without bringing internal signals pins. This feature particularly important advanced packages such FineLine packages because adding connection during debugging process difficult after board designed manufactured.
Altera Corporation
APEX 20KC Programmable Logic Device
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
APEX 20KC devices provide JTAG circuitry that complies with IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing performed before after configuration, during configuration. APEX 20KC devices also JTAG port configuration with Quartus software with hardware using either Files (.jam) Byte-Code Files (.jbc). Finally, APEX 20KC devices JTAG port monitor logic operation device with SignalTap embedded logic analyzer. APEX 20KC devices support JTAG instructions shown Table
Table APEX 20KC JTAG Instructions JTAG Instruction Description
SAMPLE/PRELOAD Allows snapshot signals device pins captured examined during normal device operation, permits initial data pattern output device pins. Also used SignalTap embedded logic analyzer. EXTEST BYPASS Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins. Places 1-bit bypass register between pins, which allows data pass synchronously through selected devices adjacent devices during normal device operation. Selects 32-bit USERCODE register places between pins, allowing USERCODE serially shifted TDO. Selects IDCODE register places between TDO, allowing IDCODE serially shifted TDO. Used when configuring APEX 20KC device JTAG port with MasterBlasteror ByteBlasterMVdownload cable, when using File Byte-Code File embedded processor. Monitors internal device operation with SignalTap embedded logic analyzer.
USERCODE IDCODE Instructions
SignalTap Instructions
Altera Corporation
APEX 20KC Programmable Logic Device
APEX 20KC device instruction register length bits. APEX 20KC device USERCODE register length bits. Tables show boundary-scan register length device IDCODE information APEX 20KC devices. Table APEX 20KC Boundary-Scan Register Length Device
EP20K200C EP20K400C EP20K600C EP20K1000C
Boundary-Scan Register Length
1,164 1,506 1,806 2,190
Table 32-Bit APEX 20KC Device IDCODE Device Version Bits)
EP20K200C EP20K400C EP20K600C EP20K1000C Notes Table
most significant (MSB) left. IDCODE's least significant (LSB) always
IDCODE Bits) Part Number Bits)
1000 0010 0000 0000 1000 0100 0000 0000 1000 0110 0000 0000 1001 0000 0000 0000
Manufacturer Identity Bits)
0110 1110 0110 1110 0110 1110 0110 1110
Bit)
0000 0000 0000 0000
Figure shows timing requirements JTAG signals.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure APEX 20KC JTAG Waveforms
tJPZX tJSSU Signal Captured Signal Driven tJSH JPCO JPXZ JPSU
tJSZX
tJSCO
tJSXZ
Table shows JTAG timing parameters values APEX 20KC devices. Table APEX 20KC JTAG Timing Parameters Values Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock output Update register high impedance valid output Update register valid output high impedance
Parameter
Unit
more information, following documents:
Application Note (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing Altera Devices)
Altera Corporation
APEX 20KC Programmable Logic Device Data Sheet
Programming Test Language Specification
Generic Testing
Each APEX 20KC device functionally tested. Complete testing each configurable SRAM logic functionality ensures 100% yield. test measurements APEX 20KC devices made under conditions equivalent those defined "Timing Model" section page Multiple test patterns used configure devices during stages production flow. test criteria include:
Power supply transients affect measurements. Simultaneous transitions multiple outputs should avoided accurate measurement. Threshold tests must performed under conditions. Large-amplitude, fast-ground-current transients normally occur device outputs discharge load capacitances. When these transients flow through parasitic inductance between device ground test system ground, significant reductions observable noise immunity result.
Operating Conditions
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, capacitance 1.8-V APEX 20KC devices. Note
-0.5 -0.5 -0.5 bias Under bias PQFP, RQFP, TQFP, packages, under bias Ceramic packages, under bias
Table APEX 20KC Device Absolute Maximum Ratings Symbol Parameter
Conditions
With respect ground
Unit
CCINT Supply voltage CCIO input voltage output current, Storage temperature Ambient temperature Junction temperature
Altera Corporation
APEX 20KC Programmable Logic Device
Table APEX 20KC Device Recommended Operating Conditions Symbol
CCINT CCIO
Parameter
Supply voltage internal logic input buffers Supply voltage output buffers, 3.3-V operation Supply voltage output buffers, 2.5-V operation Supply voltage output buffers, 1.8-V operation (3), (3), (3), (3), (2),
Conditions
1.71 (1.71) 3.00 (3.00) 2.375 (2.375) 1.71 (1.71) -0.5
1.89 (1.89) 3.60 (3.60) 2.625 (2.625) 1.89 (1.89) CCIO
Unit
Input voltage Output voltage Operating junction temperature Input rise time (10% 90%) Input fall time (90% 10%)
commercial industrial
Table APEX 20KC Device Operating Conditions Symbol
Notes (6),
Parameter
Input leakage current Tri-stated leakage current supply current (standby) (All ESBs power-down mode)
Conditions
-0.5 ground, load, toggling inputs, speed grade ground, load, toggling inputs, speed grades
Unit
CONF
Value pull-up resistor before during configuration
CCIO CCIO 2.375 CCIO 1.71
operating specifications APEX 20KC standards listed Tables
Altera Corporation
APEX 20KC Programmable Logic Device
Table APEX 20KC Device Capacitance Symbol
CINCLK COUT
Note (10) Conditions
Parameter
Input capacitance Input capacitance dedicated clock Output capacitance
Unit
VOUT
Notes Tables through
Operating Requirements Altera Devices Data Sheet. Minimum input -0.5 During transitions, inputs undershoot -2.0 overshoot input currents less than time periods shorter than Numbers parentheses industrial-temperature-range devices. Maximum rise time must rise monotonically. pins, including dedicated inputs, clock, I/O, JTAG pins, driven before VCCINT VCCIO powered. Typical values CCINT CCIO These values specified under APEX 20KC device recommended operating conditions, shown Table page This value specified normal device operation. value vary during power-up. pull-up resistance values will lower external source drives higher than VCCIO. (10) Capacitance sample-tested only.
Tables through list operating specifications supported standards. These tables list minimal specifications only; APEX 20KC devices exceed these specifications. Table LVTTL Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
-0.3
Maximum
VCCIO
Units
VCCIO VCCIO
Altera Corporation
APEX 20KC Programmable Logic Device
Table LVCMOS Specifications Symbol
VCCIO
Parameter
Power supply voltage range High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
-0.3
Maximum
VCCIO
Units
VCCIO -0.1 VCCIO
VCCIO
Table 2.5-V Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 -0.3
Maximum
2.625 VCCIO
Units
-0.1
Altera Corporation
APEX 20KC Programmable Logic Device
Table 1.8-V Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
0.65 VCCIO
Maximum
VCCIO 0.35 VCCIO
Units
VCCIO 0.45
0.45
Table 3.3-V Specifications Symbol
VCCIO
Parameter
supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
VCCIO -0.5
Typical
Maximum
VCCIO VCCIO
Units
VCCIO IOUT -500 IOUT 1,500
VCCIO
VCCIO
Altera Corporation
APEX 20KC Programmable Logic Device
Table 3.3-V PCI-X Specifications Symbol
VCCIO VIPU Lpin
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input pull-up voltage Input leakage current High-level output voltage Low-level output voltage Inductance
Conditions
Minimum
VCCIO -0.5 VCCIO
Typical
Maximum
VCCIO 0.35 VCCIO
Units
VCCIO IOUT -500 IOUT 1,500
-10.0 VCCIO
10.0
VCCIO 15.0
Table 3.3-V LVDS Specifications Symbol
VCCIO
Parameter
supply voltage Differential output voltage Change between high Change between high Differential input threshold Receiver input voltage range Receiver differential input resistor (external APEX devices)
Conditions
Minimum
3.135
Typical
Maximum
3.465
Units
Output offset voltage
1.125
1.25
1.375
-100
Altera Corporation
APEX 20KC Programmable Logic Device
Table GTL+ Specifications Symbol
VREF
Parameter
Termination voltage Reference voltage High-level input voltage Low-level input voltage Low-level output voltage
Conditions
Minimum
1.35 0.88 VREF
Typical
Maximum
1.65 1.12
Units
VREF 0.65
Table SSTL-2 Class Specifications Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF 0.04 1.15 VREF 0.18 -0.3
Typical
VREF 1.25
Maximum
2.625 VREF 0.04 1.35 VCCIO VREF 0.18
Units
-7.6
0.57 0.57
Altera Corporation
APEX 20KC Programmable Logic Device
Table SSTL-2 Class Specifications Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF 0.04 1.15 VREF 0.18 -0.3
Typical
VREF 1.25
Maximum
2.625 VREF 0.04 1.35 VCCIO VREF 0.18
Units
-15.2 15.2
0.76 0.76
Table SSTL-3 Class Specifications Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF 0.05 VREF -0.3
Typical
VREF
Maximum
VREF 0.05 VCCIO VREF
Units
Altera Corporation
APEX 20KC Programmable Logic Device
Table SSTL-3 Class Specifications Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF 0.05 VREF -0.3
Typical
VREF
Maximum
VREF 0.05 VCCIO VREF
Units
Table HSTL Class Specifications Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 VREF 0.05 0.68 VREF -0.3
Typical
VREF 0.75
Maximum
1.89 VREF 0.05 0.90 VCCIO VREF
Units
VCCIO
Altera Corporation
APEX 20KC Programmable Logic Device
Table 3.3-V Specifications Symbol
VCCIO VREF
Parameter
supply voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input leakage current
Conditions
Minimum
3.15 0.39 VCCIO VCCIO
Typical
Maximum
3.45 0.41 VCCIO VCCIO VCCIO
Units
IOUT -500 IOUT 1,500 VCCIO
VCCIO
VCCIO
Table Specifications Symbol
VCCIO VTT/VREF
Parameter
supply voltage Termination reference voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
1.35 VREF
Typical
Maximum
1.65
Units
VREF VCCIO VREF VREF
VOUT VCCIO Output leakage current (when output high
Notes Tables through
parameter refers high-level output current. parameter refers low-level output current. This parameter applies open-drain pins well output pins. VREF specifies center point switching range.
Figure shows output drive characteristics APEX 20KC devices.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure Output Drive Characteristics APEX 20KC Devices
Typical Output Current (mA) VCCINT VCCIO Room Temperature
Note
VCCINT VCCIO 2.5V Room Temperature
Typical Output Current (mA)
Output Voltage
Output Voltage
Typical Output Current (mA) VCCINT 1.8V VCCIO 1.8V Room Temperature
Output Voltage
Note Figure
These transient (AC) currents.
Altera Corporation
APEX 20KC Programmable Logic Device
Timing Model
high-performance FastTrack MegaLAB interconnect routing resources ensure predictable performance, accurate simulation, accurate timing analysis. This predictable performance contrasts with that FPGAs, which segmented connection scheme therefore have unpredictable performance. Figure shows fMAX timing model APEX 20KC devices. Figure fMAX Timing Model
Routing Delay
F1-4 F5-20 F20+
ESBARC ESBSRC ESBAWC ESBSWC ESBWASU ESBWDSU ESBSRASU ESBWESU ESBDATASU
ESBWADDRSU ESBRADDRSU ESBDATACO1 ESBDATACO2 ESBDD PTERMSU PTERMCO
Figures show asynchronous synchronous timingwaveforms, respectively, macroparameters Table
Altera Corporation
APEX 20KC Programmable Logic Device
Figure Asynchronous Timing Waveforms
Asynchronous Read
Rdaddress
tESBARC
Data-Out
Asynchronous Write
tESBWP tESBWDSU tESBWDH
Data-In
din0
tESBWASU tESBWCCOMB
din1
tESBWAH
Wraddress
tESBDD
Data-Out
din0
din1
dout2
Altera Corporation
APEX 20KC Programmable Logic Device
Figure Synchronous Timing Waveforms
Synchronous Read
Rdaddress
tESBDATASU
tESBDATAH
tESBARC
tESBDATACO2
Data-Out
Synchronous Write (ESB Output Registers Used)
Data-In
din1
din2
din3
Wraddress
tESBWESU tESBDATASU
tESBDATAH
tESBWEH
tESBSWC tESBDATACO1
Data-Out
dout0
dout1
din1
din2
din3
din2
Figure shows timing model bidirectional timing.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure Synchronous Bidirectional External Timing
Register
Dedicated Clock
tXZBIDIR tZXBIDIR tOUTCOBIDIR
Bidirectional
CLRN Output Register
CLRN Input Register (1),
tINSUBIDIR tINHBIDIR
CLRN
Notes Figure
output enable input registers registers adjacent bidirectional pin. "Output Enable Routing Single-Pin" option Quartus software output enable register. "Decrease Input Delay Internal Cells OFF" option Quartus software LAB-adjacent input register. This maintains zero hold time LAB-adjacent registers while giving fast, position-independent setup time. "Decrease Input Delay Internal Cells move input register farther away from bidirectional faster setup time with zero hold time. exact position where zero hold occurs with minimum setup time varies with device density speed grade.
Tables describes fMAX timing parameters shown Figure Table describes functional timing parameters. Table APEX 20KC fMAX Timing Parameters Symbol
tLUT register setup time before clock register hold time before clock register clock-to-output delay delay data-in data-out
Parameter
Altera Corporation
APEX 20KC Programmable Logic Device
Table APEX 20KC fMAX Timing Parameters Symbol
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO asynchronous read cycle time synchronous read cycle time asynchronous write cycle time synchronous write cycle time write address setup time with respect write address hold time with respect data setup time with respect data hold time with respect read address setup time with respect read address hold time with respect setup time before clock when using input register data setup time before clock when using input register write address setup time before clock when using input registers read address setup time before clock when using input registers clock-to-output delay when using output registers clock-to-output delay without output registers data-in data-out delay mode macrocell input non-registered output macrocell register setup time before clock macrocell register clock-to-output delay
Parameter
Table APEX 20KC fMAX Routing Delays Symbol
tF1-4 tF5-20 tF20+
Parameter
Fan-out delay estimate using local interconnect Fan-out delay estimate using MegaLab interconnect Fan-out delay estimate using FastTrack interconnect
Altera Corporation
APEX 20KC Programmable Logic Device
Table APEX 20KC Minimum Pulse Width Timing Parameters Symbol
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Parameter
Minimum clock high time from clock Minimum clock time from clock clear pulse width preset pulse width Clock high time Clock time Write pulse width Read pulse width
Tables describe APEX 20KC external timing parameters. timing values these pin-to-pin delays reported pins using 3.3-V LVTTL standard. Table APEX 20KC External Timing Parameters Symbol
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL
Note Conditions
Clock Parameter
Setup time with global clock register Hold time with global clock register Clock-to-output delay with global clock output register Setup time with clock input register Hold time with clock input register Clock-to-output delay with clock output register
Altera Corporation
APEX 20KC Programmable Logic Device
Table APEX 20KC External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL
Note Condition
Parameter
Setup time bidirectional pins with global clock LAB-adjacent input register Hold time bidirectional pins with global clock LAB-adjacent input register Clock-to-output delay bidirectional pins with global clock register Synchronous output enable register output buffer disable delay Synchronous output enable register output buffer enable delay Setup time bidirectional pins with clock LAB-adjacent input register Hold time bidirectional pins with clock LAB-adjacent input register Clock-to-output delay bidirectional pins with clock register Synchronous output enable register output buffer disable delay with Synchronous output enable register output buffer enable delay with
Notes Tables
These timing parameters sample-tested only. more information, refer Table
Tables define timing delays each standard. Some output standards require test load circuits timing measurements shown Figures through Table APEX 20KC Selectable Standard Input Adder Delays (Part Symbol
LVCMOS LVTTL GTl+ SSTL-3 Class SSTL-3 Class SSTL-2 Class SSTL-2 Class
Note Condition
Parameter
Input adder delay LVCMOS standard Input adder delay LVTTL standard Input adder delay 2.5-V standard Input adder delay 1.8-V standard Input adder delay standard Input adder delay GTL+ standard Input adder delay SSTL-3 Class standard Input adder delay SSTL-3 Class standard Input adder delay SSTL Class standard Input adder delay SSTL Class standard
Altera Corporation
APEX 20KC Programmable Logic Device
Table APEX 20KC Selectable Standard Input Adder Delays (Part Symbol
LVDS
Note Condition
Parameter
Input adder delay LVDS standard Input adder delay standard Input adder delay standard
Table APEX 20KC Selectable Standard Output Adder Delays Symbol
LVCMOS LVTTL
Note Condition
Parameter
Output adder delay LVCMOS standard Output adder delay LVTTL standard
Cload 564.5 Cload Cload Cload Cload
Output adder delay 2.5-V standard
Output adder delay 1.8-V standard
Output adder delay standard
GTl+ SSTL-3 Class
Output adder delay GTL+ standard
Output adder delay SSTL-3 Class standard Cload1 Cload2 Output adder delay SSTL-3 Class standard Cload1 Cload2 Output adder delay SSTL-2 Class standard Output adder delay SSTL-2 Class standard Output adder delay LVDS standard Output adder delay standard Output adder delay standard Cload R=100
SSTL-3 Class
SSTL-2 Class SSTL-2 Class LVDS Note Tables
These delays report differences delays different standards. delay standard that used external timing parameters. Figure more information.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure Test Conditions LVTTL, GTL+ Standards
VCCIO
Ouptut
Cload
Figure Test Conditions SSTL-3 Class Standards
VCCIO
Output Cload2
Cload1
Figure Test Conditions LVDS Standard
Positive Output
Negative Output
Cload
Altera Corporation
APEX 20KC Programmable Logic Device
Tables through show fMAX external timing parameters EPC20K200C, EP20K400C, EP20K600C, EP20K1000C devices. Table EP20K200C fMAX Timing Microparameters Symbol Speed Grade
tLUT 0.01 0.10 0.27 0.65
Speed Grade
0.01 0.10 0.30 0.78
Speed Grade
0.01 0.10 0.32 0.92
Unit
Table EP20K200C fMAX Timing Microparameters Symbol Speed Grade
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO 0.58 1.10 0.45 0.44 0.57 0.44 1.25 0.00 0.00 2.01 -0.20 0.02 1.09 2.10 2.50 1.48 0.72 1.29
Speed Grade
1.51 2.49 3.46 3.44 0.50 0.50 0.63 0.50 1.43 0.03 0.00 2.27 -0.24 0.00 1.28 2.52 2.97 1.78
Speed Grade
1.69 2.72 3.86 3.85 0.54 0.55 0.68 0.55 1.56 0.11 0.00 2.45 -0.28 -0.02 1.43 2.82 3.32 2.00 0.81 1.45
Unit
1.30 2.35 2.92 3.05
Altera Corporation
APEX 20KC Programmable Logic Device
Table EP20K200C fMAX Routing Delays Symbol Speed Grade
tF1-4 tF5-20 tF20+
Speed Grade
0.17 0.94 1.13
Speed Grade
0.20 1.12 1.35
Unit
0.15 0.81 0.98
Table EP20K200C Minimum Pulse Width Timing Parameters Symbol Speed Grade
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP 1.33 1.33 0.20 0.20 1.33 1.33 1.05 0.87
Speed Grade
1.66 1.66 0.20 0.20 1.66 1.66 1.28 1.06
Speed Grade
2.00 2.00 0.20 0.20 2.00 2.00 1.44 1.19
Unit
Table EP20K200C External Timing Parameters Symbol Speed Grade
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 1.23 0.00 2.00 0.81 0.00 0.50 2.36 3.79
Speed Grade
1.26 0.00 2.00 0.92 0.00 0.50 2.62 4.31
Speed Grade
1.33 0.00 2.00 4.70
Unit
Altera Corporation
APEX 20KC Programmable Logic Device
Table EP20K200C External Bidirectional Timing Parameters Symbol Speed Grade
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL 2.82 0.00 0.50 2.36 4.69 4.69 1.38 0.00 2.00 3.79 6.12 6.12 3.47 0.00 0.50 2.62 4.82 4.82
Speed Grade
1.78 0.00 2.00 4.31 6.51 6.51
Speed Grade
1.99 0.00 2.00 4.70 7.89 7.89
Unit
Table EP20K400C fMAX Timing Parameters Symbol Speed Grade
tLUT 0.01 0.10 0.27 0.65
Speed Grade
0.01 0.10 0.30 0.78
Speed Grade
0.01 0.10 0.32 0.92
Unit
Altera Corporation
APEX 20KC Programmable Logic Device
Table EP20K400C fMAX Timing Parameters Symbol Speed Grade
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO 0.58 1.10 0.45 0.44 0.57 0.44 1.25 0.00 0.00 2.01 -0.20 0.02 1.09 2.10 2.50 1.48 0.72 1.29
Speed Grade
1.51 2.49 3.46 3.44 0.50 0.50 0.63 0.50 1.43 0.03 0.00 2.27 -0.24 0.00 1.28 2.52 2.97 1.78
Speed Grade
1.69 2.72 3.86 3.85 0.54 0.55 0.68 0.55 1.56 0.11 0.00 2.45 -0.28 -0.02 1.43 2.82 3.32 2.00 0.81 1.45
Unit
1.30 2.35 2.92 3.05
Table EP20K400C fMAX Routing Delays Symbol Speed Grade
tF1-4 tF5-20 tF20+
Speed Grade
0.17 1.06 1.96
Speed Grade
0.19 1.25 2.30
Unit
0.15 0.94 1.73
Altera Corporation
APEX 20KC Programmable Logic Device
Table EP20K400C Minimum Pulse Width Timing Parameters Symbol Speed Grade
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP 1.33 1.33 0.20 0.20 1.33 1.33 1.05 0.87
Speed Grade
1.66 1.66 0.20 0.20 1.66 1.66 1.28 1.06
Speed Grade
2.00 2.00 0.20 0.20 2.00 2.00 1.44 1.19
Unit
Table EP20K400C External Timing Parameters Symbol Speed Grade
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 1.37 0.00 2.00 0.80 0.00 0.50 2.27 4.25
Speed Grade
1.52 0.00 2.00 0.91 0.00 0.50 2.55 4.61
Speed Grade
1.64 0.00 2.00 5.03
Unit
Altera Corporation
APEX 20KC Programmable Logic Device
Table EP20K400C External Bidirectional Timing Parameters Symbol Speed Grade
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL 3.22 0.00 0.50 2.27 4.62 4.62 1.29 0.00 2.00 4.25 6.55 6.55 3.80 0.00 0.50 2.55 4.84 4.84
Speed Grade
1.67 0.00 2.00 4.61 6.97 6.97
Speed Grade
1.92 0.00 2.00 5.03 7.35 7.36
Unit
Table EP20K600C fMAX Timing Parameters Symbol Speed Grade
tLUT 0.01 0.10 0.27 0.65
Speed Grade
0.01 0.10 0.30 0.78
Speed Grade
0.01 0.10 0.32 0.92
Unit
Altera Corporation
APEX 20KC Programmable Logic Device
Table EP20K600C fMAX Timing Parameters Symbol Speed Grade
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO 0.58 1.10 0.45 0.44 0.57 0.44 1.25 0.00 0.00 2.01 -0.20 0.02 1.09 2.10 2.50 1.48 0.72 1.29
Speed Grade
1.51 2.49 3.46 3.44 0.50 0.50 0.63 0.50 1.43 0.03 0.00 2.27 -0.24 0.00 1.28 2.52 2.97 1.78
Speed Grade
1.69 2.72 3.86 3.85 0.54 0.55 0.68 0.55 1.56 0.11 0.00 2.45 -0.28 -0.02 1.43 2.82 3.32 2.00 0.81 1.45
Unit
1.30 2.35 2.92 3.05
Table EP20K600C fMAX Routing Delays Symbol Speed Grade
tF1-4 tF5-20 tF20+
Speed Grade
0.16 1.05 1.98
Speed Grade
0.18 1.20 2.23
Unit
0.15 0.94 1.76
Altera Corporation
APEX 20KC Programmable Logic Device
Table EP20K600C Minimum Pulse Width Timing Parameters Symbol Speed Grade
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP 1.33 1.33 0.20 0.20 1.33 1.33 1.05 0.87
Speed Grade
1.66 1.66 0.20 0.20 1.66 1.66 1.28 1.06
Speed Grade
2.00 2.00 0.20 0.20 2.00 2.00 1.44 1.19
Unit
Table EP20K600C External Timing Parameters Symbol Speed Grade
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 1.28 0.00 2.00 0.80 0.00 0.50 2.37 4.29
Speed Grade
1.40 0.00 2.00 0.91 0.00 0.50 2.63 4.77
Speed Grade
1.45 0.00 2.00 5.11
Unit
Altera Corporation
APEX 20KC Programmable Logic Device
Table EP20K600C External Bidirectional Timing Parameters Symbol Speed Grade
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL 3.99 0.00 0.50 2.37 6.35 6.35 2.03 0.00 2.00 4.29 8.31 8.31 4.77 0.00 0.50 2.63 6.94 6.94
Speed Grade
2.57 0.00 2.00 4.77 9.14 9.14
Speed Grade
2.97 0.00 2.00 5.11 9.76 9.76
Unit
Table EP20K1000C fMAX Timing Microparameters Symbol Speed Grade
tLUT 0.01 0.10 0.27 0.66
Speed Grade
0.01 0.10 0.30 0.79
Speed Grade
0.01 0.10 0.32 0.92
Unit
Altera Corporation
APEX 20KC Programmable Logic Device
Table EP20K1000C fMAX Timing Microparameters Symbol Speed Grade
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO 0.61 1.13 0.51 0.38 0.62 0.38 1.40 0.00 0.00 1.92 -0.20 0.00 1.12 2.11 2.56 1.49 0.69 1.32
Speed Grade
1.57 2.50 3.46 3.43 0.50 0.51 0.62 0.51 1.47 0.07 0.00 2.19 -0.28 -0.03 1.30 2.53 2.96 1.79
Speed Grade
1.65 2.73 3.86 3.83 0.52 0.57 0.66 0.57 1.53 0.18 0.00 2.35 -0.32 -0.05 1.46 2.84 3.30 2.02 0.77 1.48
Unit
1.48 2.36 2.93 3.08
Table EP20K1000C fMAX Routing Delays Symbol Speed Grade
tF1-4 tF5-20 tF20+
Speed Grade
0.17 1.31 2.71
Speed Grade
0.19 1.50 3.19
Unit
0.15 1.13 2.30
Altera Corporation
APEX 20KC Programmable Logic Device
Table EP20K1000C Minimum Pulse Width Timing Parameters Symbol Speed Grade
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP 1.33 1.33 0.20 0.20 1.33 1.33 1.04 0.87
Speed Grade
1.66 1.66 0.20 0.20 1.66 1.66 1.26 1.05
Speed Grade
2.00 2.00 0.20 0.20 2.00 2.00 1.41 1.18
Unit
Table EP20K1000C External Timing Parameters Symbol Speed Grade
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 1.14 0.00 2.00 0.81 0.00 0.50 2.32 4.63
Speed Grade
1.14 0.00 2.00 0.92 0.00 0.50 2.55 5.26
Speed Grade
1.11 0.00 2.00 5.69
Unit
Altera Corporation
APEX 20KC Programmable Logic Device
Table EP20K1000C External Bidirectional Timing Parameters Symbol Speed Grade
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL 4.17 0.00 0.50 2.32 6.67 6.67 1.86 0.00 2.00 4.63 8.98 8.98 5.27 0.00 0.50 2.55 7.18 7.18
Speed Grade
2.54 0.00 2.00 5.26 9.89 9.89
Speed Grade
3.15 0.00 2.00 5.69 10.67 10.67
Unit
Tables show selectable standard input output delays APEX 20KC devices. select standard input output delay other than LVCMOS, delay selected speed grade LVCMOS value. Table Selectable Standard Input Delays Symbol Speed Grade
LVCMOS LVTTL GTL+ SSTL-3 Class SSTL-3 Class SSTL-2 Class SSTL-2 Class LVDS
Speed Grade
0.00 0.00 0.00 0.11 0.04 0.25 -0.13 -0.13 -0.13 -0.13 -0.17 0.00 0.00
Speed Grade
0.00 0.00 0.00 0.14 0.03 0.23 -0.13 -0.13 -0.13 -0.13 -0.16 0.00 0.00
Unit
0.00 0.00 0.00 0.04 0.00 -0.30 -0.19 -0.19 -0.19 -0.19 -0.19 0.00 0.00
Altera Corporation
APEX 20KC Programmable Logic Device
Table Selectable Standard Output Delays Symbol Speed Grade
LVCMOS LVTTL GTL+ SSTL-3 Class SSTL-3 Class SSTL-2 Class SSTL-2 Class LVDS
Speed Grad
0.00 0.00 0.00 1.41 -0.53 -0.29 -0.71 -0.71 -0.71 -0.71 -0.70 0.00 0.00
Speed Grade
0.00 0.00 0.00 1.57 -0.56 -0.39 -0.75 -0.75 -0.75 -0.75 -0.73 0.00 0.00
Unit
0.00 0.00 0.00 1.18 -0.52 -0.18 -0.67 -0.67 -0.67 -0.67 -0.69 0.00 0.00
Power Consumption Configuration Operation
estimate device power consumption, interactive power estimator Altera site http://www.altera.com.
APEX 20KC architecture supports several configuration schemes. This section summarizes device operating modes available device configuration schemes.
Operating Modes
APEX architecture uses SRAM configuration elements that require configuration data loaded each time circuit powers process physically loading SRAM data into device called configuration. During initialization, which occurs immediately after configuration, device resets registers, enables pins, begins operate logic device. pins tri-stated during power-up, before during configuration. Together, configuration initialization processes called command mode; normal device operation called user mode. Before during device configuration, pins pulled VCCIO built-in weak pull-up resistor.
Altera Corporation
APEX 20KC Programmable Logic Device
SRAM configuration elements allow APEX 20KC devices reconfigured in-circuit loading configuration data into device. Real-time reconfiguration performed forcing device into command mode with device pin, loading different configuration data, reinitializing device, resuming user-mode operation. In-field upgrades performed distributing configuration files.
Configuration Schemes
configuration data APEX 20KC device loaded with five configuration schemes (see Table 70), chosen basis target application. EPC16, EPC2, EPC1 configuration device, intelligent controller, JTAG port used control configuration APEX 20KC device. When configuration device used, system configure automatically system power-up. Multiple APEX 20KC devices configured five configuration schemes connecting configuration enable (nCE) configuration enable output (nCEO) pins each device. Table Data Sources Configuration Configuration Scheme
Configuration device Passive serial (PS) Passive parallel asynchronous (PPA) Passive parallel synchronous (PPS) JTAG
Data Source
EPC16, EPC8, EPC4, EPC2, EPC1 configuration device MasterBlaster ByteBlasterMV download cable serial data source Parallel data source Parallel data source MasterBlaster ByteBlasterMV download cable microprocessor with Standard Test Programming Language (STAPL) File
Device PinOuts Ordering Information
more information configuration, Application Note (Configuring SRAM-Based Devices). Altera site (http://www.altera.com) Altera Digital Library pin-out information.
Figure describes ordering codes Stratix devices. more information specific package, refer Altera Device Package Information Data Sheet.
Altera Corporation
APEX 20KC Programmable Logic Device
Figure APEX 20KC Device Packaging Ordering Information
EP20K Family Signature EP20K: APEX 1000C 1020 Optional Suffix Indicates specific device options shipment method. Engineering sample
Device Type 200C 400C 600C 1000C Package Type Plastic quad flat package (PQFP) Ball-grid array (BGA) FineLine Speed Grade with being fastest
Operating Temperature Commercial temperature Industrial temperature -40° 100°
Count Number pins particular package
Revision History
information contained APEX 20KC Programmable Logic Device Data Sheet version supersedes information published previous versions.
Version
following changes were made APEX 20KC Programmable Logic Device Data Sheet version 2.2:
Updated Tables Updated notes Tables
Version
following changes were made APEX 20KC Programmable Logic Device Data Sheet version 2.1:
Removed figure Test Conditions. Updated conditions Tables Added Tables Updated Table Added Figures through Updated Tables through Updated Tables through Removed notes Tables through Various textual changes throughout document.
Altera Corporation
APEX 20KC Programmable Logic Device
Altera Corporation
APEX 20KC Programmable Logic Device
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Copyright 2002 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, mask work rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
Altera Corporation
Other recent searches
TLK2201JR - TLK2201JR TLK2201JR Datasheet
SiR436DP - SiR436DP SiR436DP Datasheet
FMVC46 - FMVC46 FMVC46 Datasheet
CLC430 - CLC430 CLC430 Datasheet
BTL-55BLDS-XX-X - BTL-55BLDS-XX-X BTL-55BLDS-XX-X Datasheet
BAL99 - BAL99 BAL99 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
