Differential LVPECL/LVECL/HSTL Clock Data Driver MAX9325 low-skew

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Differential LVPECL/LVECL/HSTL Clock Data Driver MAX9325 low-skew

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19-2511; 10/02
Differential LVPECL/LVECL/HSTL Clock Data Driver
MAX9325 low-skew, differential driver features extremely output-to-output skew (50ps max) part-to-part skew (225ps max). These features make device ideal clock data distribution across backplane board. device selects differential HSTL LVECL/LVPECL inputs repeats them eight differential outputs. Outputs compatible with LVECL LVPECL, directly drive terminated transmission lines. differential inputs configured accept single-ended signal when unused complementary input connected on-chip reference output voltage VBB. inputs have internal pulldown resistors internal pulldowns fail-safe circuit ensure differential default outputs when inputs left open VEE. MAX9325 operates over 2.375V 3.8V supply range interfacing differential HSTL LVPECL signals. This allows high-performance clock data distribution systems with nominal +2.5V +3.3V supply. LVECL operation, device operates with -2.375V -3.8V supply. MAX9325 offered 28-lead PLCC spacesaving 28-lead packages. MAX9325 specified operation from -40°C +85°C. 50ps (max) Output-to-Output Skew 1.5psRMS (max) Random Jitter Guaranteed 300mV Differential Output 700MHz +2.375V +3.8V Supplies Differential HSTL/LVPECL -2.375V -3.8V Supplies Differential LVECL Selectable Differential Inputs On-Chip Reference Single-Ended Inputs Outputs Inputs Open Compatible with MC100LVE310
Features
MAX9325
Ordering Information
PART MAX9325EQI MAX9325EGI TEMP RANGE -40°C +85°C -40°C +85°C PIN-PACKAGE PLCC
Applications
Precision Clock Distribution Low-Jitter Data Repeaters
Functional Diagram appears data sheet.
Configurations
VIEW
INPUT SELECT TRUTH TABLE CLK_SEL INPUT CLOCK CLK0, CLK0 SELECTED CLK1, CLK1 SELECTED
CLK_SEL CLKO CLKO CLK1
CLK_SEL CLKO CLKO CLK1
MAX9325
MAX9325
CLK1
N.C.
CLK1
N.C.
*CORNER PINS EXPOSED CONNECTED VEE.
Maxim Integrated Products
PLCC
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Differential LVPECL/LVECL/HSTL Clock Data Driver MAX9325
ABSOLUTE MAXIMUM RATINGS
.-0.3V +4.1V Inputs (CLK_, CLK_, CLK_SEL) .-0.3V (VCC 0.3V) CLK_ CLK_ .±3.0V Continuous Output Current .50mA Surge Output Current.100mA Sink/Source Current.±0.65mA Continuous Power Dissipation +70°C) 28-Lead PLCC (derate 10.5mW/°C above +70°C) .842mW Still .+95°C/W .+25°C/W 28-Lead (derate 20.8mW/°C above +70°C) .1667mW Still .+48°C/W .+2°C/W Operating Temperature Range .-40°C +85°C Junction Temperature .+150°C Storage Temperature Range .-65°C +150°C Protection Human Body Model (CLK_, CLK_, Q_).2kV Soldering Temperature (10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
((VCC VEE) 2.375V 3.8V, Typical values (VCC VEE) 3.3V, (VCC 1V), (VCC 1.5V).) (Notes 1-4)
PARAMETER SYMBOL CONDITIONS -40°C +25°C +85°C UNITS
SINGLE-ENDED INPUT (CLK_SEL) Single-Ended Input High Voltage Single-Ended Input Voltage Input Current Figure 1.165 1.165 1.165
Figure VIH,
-10.0
1.475 +150
-10.0
1.475 +150
-10.0
1.475 +150
DIFFERENTIAL INPUT (CLK_, CLK_) Single-Ended Input High Voltage Single-Ended Input Voltage Differential Input High Voltage Figure 1.165 1.165 1.165
Figure
1.475
1.475
1.475
VIHD
Figure
Differential LVPECL/LVECL/HSTL Clock Data Driver
ELECTRICAL CHARACTERISTICS (continued)
((VCC VEE) 2.375V 3.8V, Typical values (VCC VEE) 3.3V, (VCC 1V), (VCC 1.5V).) (Notes 1-4)
PARAMETER Differential Input Voltage SYMBOL VILD CONDITIONS Figure (VCC VEE) 3.0V, Figure (VCC VEE) 3.0V, Figure VIH, VIL, VIHD, VILD -40°C 0.095 0.095 -10.0 0.095 +150.0 0.095 0.095 -10.0 +25°C 0.095 +150.0 0.095 0.095 -10.0 +85°C 0.095 +150.0 UNITS
MAX9325
Differential Input Voltage
VIHD VILD
Input Current OUTPUT (Q_, Single-Ended Output High Voltage Single-Ended Output Voltage Differential Output Voltage
Figure
1.085 0.977 0.880 1.025 0.949 0.88 1.025 0.929 0.88
Figure
1.810 1.695 1.620 1.810 1.697 1.62 1.810 1.698 1.62
Figure
REFERENCE VOLTAGE OUTPUT (VBB) Reference Voltage Output SUPPLY Supply Current (Note ±0.5mA (Note 1.38 1.318 1.26 1.38 1.325 1.26 1.38 1.328 1.26
Differential LVPECL/LVECL/HSTL Clock Data Driver MAX9325
ELECTRICAL CHARACTERISTICS-PLCC Package
((VCC VEE) 2.375V 3.8V, 500MHz, input transition time 125ps (20% 80%). Typical values (VCC VEE) 3.3V, (VCC 1V), (VCC 1.5V).) (Note
PARAMETER Differential Input-to-Output Delay Single-Ended Input-to-Output Delay Output-toOutput Skew Part-to-Part Skew Added Random Jitter Added Deterministic Jitter Switching Frequency Output Rise/Fall Time (20% 80%) SYMBOL tPLHD tPHLD tPLH tPHL tSKOO tSKPP CONDITIONS -40°C +25°C +85°C UNITS
Figure
Figure (Note
(Note Differential input (Note 0.5GHz clock pattern (Note 1.0Gbps, 2E23 PRBS pattern (Note 300mV clock pattern
psRMS
psP-P
fMAX
Figure
Differential LVPECL/LVECL/HSTL Clock Data Driver MAX9325
ELECTRICAL CHARACTERISTICS-QFN Package
((VCC VEE) 2.375V 3.8V, 500MHz, input transition time 125ps (20% 80%). Typical values (VCC VEE) 3.3V, (VCC 1V), (VCC 1.5V).) (Note
PARAMETER Differential Input-to-Output Delay Single-Ended Input-to-Output Delay Output-toOutput Skew Part-to-Part Skew Added Random Jitter Added Deterministic Jitter Switching Frequency Output Rise/Fall Time (20% 80%) SYMBOL tPLHD tPHLD tPLH tPHL tSKOO tSKPP CONDITIONS -40°C +25°C +85°C UNITS
Figure
Figure (Note
(Note Differential input (Note 0.5GHz clock pattern (Note 1.0Gbps, 2E23 PRBS pattern (Note 300mV clock pattern
psRMS
psP-P
fMAX
Figure
Note Note Note Note Note Note Note Note Note Note Note
Measurements made with device thermal equilibrium. Current into defined positive. Current defined negative. parameters production tested +25°C guaranteed design over full operating temperature range. Single-ended input operation using limited (VCC VEE) 3.0V 3.8V. only inputs that same device reference. pins open except VEE. Guaranteed design characterization. Limits sigma. Measured from point input signal with point equal VBB, point output signal. Measured between outputs same part signal crossing points same-edge transition. Differential input signal. Measured between outputs different parts under identical condition same-edge transition. Device jitter added input signal. Differential input signal.
Differential LVPECL/LVECL/HSTL Clock Data Driver MAX9325
Typical Operating Characteristics
(PLCC package, typical values (VCC VEE) 3.3V, (VCC 1V), (VCC 1.5V), 500MHz, input transition time 125ps (20% 80%).)
SUPPLY CURRENT (IEE) TEMPERATURE
MAX9325 toc01
OUTPUT AMPLITUDE (VOH VOL) FREQUENCY
MAX9325 toc02
SUPPLY CURRENT (mA)
OUTPUT VOLTAGE
1000 1500 TEMPERATURE (°C) FREQUENCY (MHz)
TRANSITION TIME TEMPERATURE
MAX9325 toc03
PROPAGATION DELAY TEMPERATURE
MAX9325 toc05
TRANSITION TIME (ps)
PROPAGATION DELAY (ps)
tPHLD tPLHD
TEMPERATURE (°C)
TEMPERATURE (°C)
Differential LVPECL/LVECL/HSTL Clock Data Driver
Description
PLCC Exposed Exposed NAME FUNCTION Positive Supply Voltage. Bypass each with 0.1µF 0.01µF ceramic capacitors. Place capacitors close device possible, with smaller value capacitor closest device. Inverting Differential Clock Input Internal 105k pulldown VEE. Reference Output Voltage. Connect inverting noninverting clock input provide reference single-ended operation. When used, bypass with 0.01µF ceramic capacitor. Otherwise leave open. Noninverting Differential Clock Input Internal 105k pulldown VEE. Inverting Differential Clock Input Internal 105k pulldown VEE. Connected Inverting Output. Typically terminate with resistor Noninverting Output. Typically terminate with resistor Inverting Output. Typically terminate with resistor Noninverting Output. Typically terminate with resistor Inverting Output. Typically terminate with resistor Noninverting Output. Typically terminate with resistor Inverting Output. Typically terminate with resistor Noninverting Output. Typically terminate with resistor Inverting Output. Typically terminate with resistor Noninverting Output. Typically terminate with resistor Inverting Output. Typically terminate with resistor Noninverting Output. Typically terminate with resistor Inverting Output. Typically terminate with resistor Noninverting Output. Typically terminate with resistor Inverting Output. Typically terminate with resistor Noninverting Output. Typically terminate with resistor Negative Supply Voltage Clock Select Input. When driven low, CLK0 input selected. Drive high select CLK1 Input. CLK_SEL threshold equal VBB. Internal pulldown VEE. Noninverting Differential Clock Input Internal 105k pulldown VEE. Internally Connected
MAX9325
CLK0 CLK1 CLK1 N.C. CLK_SEL CLK0
Differential LVPECL/LVECL/HSTL Clock Data Driver MAX9325
VIHD (MAX) VIHD VILD VILD (MAX) VIHD (MIN) VIHD VILD VILD (MIN)
DIFFERENTIAL INPUT VOLTAGE DEFINITION
SINGLE-ENDED INPUT VOLTAGE DEFINITION
Figure Input Voltage Definitions
VIHD VIHD VILD
tPLHD tPHLD
VILD
(DIFFERENTIAL)
DIFFERENTIAL OUTPUT WAVEFORM
Figure Differential Input (CLK_, CLK_) Output (Q_, Delay Timing Diagram
Differential LVPECL/LVECL/HSTL Clock Data Driver MAX9325
CLK_ WHEN CLK_
CLK_ WHEN CLK_
tPLH tPHL
Figure Single-Ended Input (CLK_, CLK_) Output (Q_, Delay Timing Diagram
Detailed Description
MAX9325 low-skew, differential driver features extremely output-to-output skew (50ps max) part-to-part skew (225ps max). These features make device ideal clock data distribution across backplane board. device selects differential HSTL LVECL/LVPECL inputs, repeats them eight differential outputs. Outputs compatible with LVECL LVPECL, directly drive terminated transmission lines. selects between differential inputs, CLK0, CLK0 CLK1, CLK1. switched single-ended CLK_SEL input. logic selects CLK0, CLK0 input. logic high selects CLK1, CLK1 input. logic threshold CLK_SEL internal voltage reference. selected input reproduced eight differential outputs speeds 700MHz. differential inputs configured accept single-ended signal when unused complementary input connected on-chip reference output voltage (VBB). single-ended input least ±95mV differential input least 95mV switches outputs levels specified Electrical Characteristics. maximum magnitude differential input from CLK_ CLK_ ±3.0V
±(VCC VEE), whichever less. This limit also applies difference between single-ended input reference voltage input. single-ended CLK_SEL input pulldown that selects default input, CLK0, CLK0, when CLK_SEL left open VEE. differential inputs have 105k pulldowns VEE. Internal pulldowns fail-safe circuit ensure differential default outputs when inputs left open VEE. Specifications high voltages differential input (VIHD VILD) differential input voltage (VIHD VILD) apply simultaneously. interfacing differential HSTL LVPECL signals, these devices operate over +2.375V +3.8V supply range, allowing high-performance clock data distribution systems with nominal +2.5V +3.3V supply. differential LVECL operation, these devices operate from -2.375V -3.8V supply.
Single-Ended Operation
CLK_SEL single-ended input with input threshold internally VBB, driven single-ended LVPECL/LVECL signal. CLK_, CLK_ differential inputs configured accept single-ended inputs when operating supply voltages greater than 2.58V. recommended supply voltage single-ended operation 3.0V 3.8V. dif9
Differential LVPECL/LVECL/HSTL Clock Data Driver
ferential input configured single-ended operation connecting on-chip reference voltage, VBB, unused complementary input reference. example, differential CLK0, CLK0 input converted noninverting, single-ended input connecting CLK0 connecting single-ended input CLK0. Similarly, inverting input obtained connecting CLK0 connecting single-ended input CLK0. With differential input configured singleended (using VBB), single-ended input driven with single-ended LVPECL/LVECL signal. When configuring differential input single-ended input, user must ensure that supply voltage (VCC VEE) greater than 2.58V. This because input high minimum level must (VEE 1.2V) higher proper operation. reference voltage must least (VEE 1.2V) higher same reason because becomes high-level input when other single-ended input swings below minimum output MAX9325 (VCC 1.38V). Substituting minimum output (VBB 1.2V) results minimum supply (VCC VEE) 2.58V. Rounding standard supplies gives single-ended operating supply ranges 3.0V 3.8V MAX9325. When using reference output, bypass with 0.01µF ceramic capacitor VCC. used, leave open. reference source sink 0.5mA, which sufficient drive inputs.
MAX9325
Traces
Circuit board trace layout very important maintain signal integrity high-speed differential signals. Maintaining integrity accomplished part reducing signal reflections skew, increasing common-mode noise immunity. Signal reflections caused discontinuities characteristic impedance traces. Avoid discontinuities maintaining distance between differential traces, using sharp corners using vias. Maintaining distance between traces also increases common-mode noise immunity. Reducing signal skew accomplished matching electrical length differential traces.
Exposed-Pad Package
28-lead package (MAX9325EGI) exposed paddle bottom package that provides primary heat removal path from board, well excellent electrical grounding board. MAX9325EGI's exposed internally connected connect exposed separate circuit ground plane unless circuit ground same.
Chip Information
TRANSISTOR COUNT: 1030 PROCESS: Bipolar
Functional Diagram
MAX9325 CLK0 CLK0 105k CLK1 CLK1 105k CLK_SEL
Applications Information
Output Termination
Terminate outputs through (VCC equivalent Thevenin terminations. Terminate each output with identical termination each output distortion. When single-ended signal taken from differential output, terminate both Ensure that output currents exceed current limits specified Absolute Maximum Ratings table. Under operating conditions, device's total thermal limits should observed.
Supply Bypassing
Bypass each with high-frequency surfacemount ceramic 0.1µF 0.01µF capacitors. Place capacitors close device possible with 0.01µF capacitor closest device pins. multiple vias when connecting bypass capacitors ground. When using reference output, bypass with 0.01µF ceramic capacitor VCC. reference used, left open.
Differential LVPECL/LVECL/HSTL Clock Data Driver
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
MAX9325
INCHES 0.165 0.180 0.090 0.120 0.145 0.156 0.020 -0.013 0.021 0.026 0.032 0.009 0.011 0.050 INCHES 0.385 0.395 0.350 0.356 0.290 0.330 0.200 0.495 0.456 0.430 0.695 0.656 0.630
4.20 4.57 3.04 2.29 3.96 3.69 -0.51 0.53 0.33 0.81 0.66 0.28 0.23 1.27
9.78 8.89 7.37 5.08 12.32 11.43 9.91 7.62 17.40 16.51 14.99 12.70
10.03 9.04 8.38 12.57 11.58 10.92 17.65 16.66 16.00 20.19 19.20 18.54 25.27 24.33 23.62
0.485 0.450 0.390 0.300 0.685 0.650 0.590 0.500 0.785 0.750 0.690 0.600 0.985 0.950 0.890 0.800
0.795 19.94 0.756 19.05 0.730 17.53 15.24 0.995 25.02 0.958 24.13 0.930 22.61 20.32
NOTES:
DOES INCLUDE MOLD FLASH. MOLD FLASH PROTRUSIONS EXCEED .20mm (.008") SIDE. LEADS COPLANAR WITHIN .10mm. CONTROLLING DIMENSION: MILLIMETER MEETS JEDEC MO047-XX SHOWN TABLE. NUMBER PINS.
PROPRIETARY INFORMATION TITLE:
FAMILY PACKAGE OUTLINE: 20L, 28L, 44L, 52L, PLCC
APPROVAL DOCUMENT CONTROL REV.
21-0049
PLCC.EPS
Differential LVPECL/LVECL/HSTL Clock Data Driver MAX9325
Package Information (continued)
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
QFN.EPS
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2002 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

Differential LVPECL/LVECL/HSTL Clock Data Driver MAX9325 low-skew

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