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SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR PRESET
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SN54HC74 PACKAGE SN74HC74 PACKAGE (TOP VIEW)
description
'HC74 contain independent D-type positive-edge-triggered flip-flops. level preset (PRE) clear (CLR) inputs sets resets outputs regardless levels other inputs. When inactive (high), data data input meeting setup time requirements transferred outputs positive-going edge clock (CLK) pulse. Clock triggering occurs voltage level directly related rise time CLK. Following hold-time interval, data input changed without affecting levels outputs. SN54HC74 characterized operation over full military temperature range -55°C 125°C. SN74HC74 characterized operation from -40°C 85°C.
1CLR 1CLK 1PRE
2CLR 2CLK 2PRE
SN54HC74 PACKAGE (TOP VIEW)
1CLR 2CLR 1CLK 1PRE
2CLK 2PRE
internal connection FUNCTION TABLE INPUTS OUTPUTS
This configuration unstable; that does persist when returns inactive (high) level.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR PRESET
logic symbol
1PRE 1CLK 1CLR 2PRE 2CLK 2CLR
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12. numbers shown packages.
logic diagram (positive logic)
absolute maximum ratings over operating free-air temperature range
Supply voltage range, -0.5 Input clamp current, VCC) (see Note Output clamp current, VCC) (see Note Continuous output current, VCC) Continuous current through Package thermal impedance, (see Note package 127°C/W package 158°C/W package 78°C/W package 170°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD except through-hole packages, which trace length zero.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR PRESET
recommended operating conditions
SN54HC74 Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition (rise fall) time Operating free-air temperature 3.15 1.35 1000 SN74HC74 3.15 1.35 1000 UNIT
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS -5.2 3.98 5.48 25°C 1.998 4.499 5.999 0.002 0.001 0.001 0.17 0.15 ±0.1 0.26 0.26 ±100 SN54HC74 ±1000 SN74HC74 3.84 5.34 0.33 0.33 ±1000 UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR PRESET
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
fclock Clock frequency Pulse duration high Data Setup time before inactive Hold time, data after 25°C SN54HC74 SN74HC74 UNIT
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) fmax 25°C SN54HC74 SN74HC74 UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance flip-flop TEST CONDITIONS load UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR PRESET
PARAMETER MEASUREMENT INFORMATION
From Output Under Test Test Point (see Note Low-Level Pulse High-Level Pulse VOLTAGE WAVEFORMS PULSE DURATIONS Data Input Out-of-Phase Output In-Phase Output tPLH tPHL tPLH tPHL
LOAD CIRCUIT
Reference Input
Input
VOLTAGE WAVEFORMS SETUP HOLD INPUT RISE FALL TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY OUTPUT TRANSITION TIMES NOTES: includes probe test-fixture capacitance. Phase relationships between waveforms were chosen arbitrarily. input pulses supplied generators having following characteristics: MHz, clock inputs, fmax measured when input duty cycle 50%. outputs measured time with input transition measurement. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated

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