Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX

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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX

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19-2119; 8/01
Flash Programmable 12-Bit Integrated Data-Acquisition Systems
MAX7651/MAX7652 complete 12-bit data-acquisition systems featuring algorithmic, switched-capacitor, analog-to-digital converter (ADC), pulsewidth-modulated digital-to-analog converter (DAC), three timer/counters, industry-standard 8051 microprocessor core with variety peripherals. Powerdown capability full functionality with supply voltages make MAX7651/MAX7652 suitable portable power-sensitive applications. MAX7651/MAX7652 perform fully differential voltage measurements with 12-bit resolution, programmable gain, separate track-and-hold both positive negative inputs. converter accepts versatile input modes consisting four 2-channel signal pairs eight 1-channel signals relative floating common. MAX7651/MAX7652 microprocessor systems feature CPU, bytes RAM, flash memory, four 8-bit ports, UARTs, interrupt controller, watchdog timer. Only four clock cycles required complete each microprocessor instruction. MAX7651/MAX7652 available 64-pin TQFP packages.
Features
12-Bit 53ksps with Fully Differential Inputs Dual 8-Bit Outputs Three Timers 4-Clock Cycle 8051-Compatible Instruction with Dual Data Pointers Programmable Watchdog Supervisor Four Parallel Ports Dual Serial Ports 375kb) Single-Supply Operation
MAX7651/MAX7652
12MHz Clock Speed 64-Pin TQFP Package
Ordering Information
PART MAX7651CCB MAX7651ECB MAX7652CCB MAX7652ECB TEMP. RANGE +70°C -40°C +85°C +70°C -40°C +85°C PIN-PACKAGE TQFP TQFP TQFP TQFP
Applications
Hand-Held Instruments Portable Data-Acquisition Systems Temperature Controllers Smart Transmitters Data Loggers Multi-Channel Data-Acquisition with Data Formatting
configuration appears data sheet.
Functional Diagram
UPPER BYTE FLASH 2000H- 3FCOH LOWER BYTE FLASH 0000H- 1FFFH 8051
MAX7651 MAX7652
FOUR 8-BIT PORTS
BYTES
MEMORY ADDRESS DATA BUSES INTERRUPT CONTROLLER AIN0 12-BIT CONVERTER ANALOG INPUTS AIN7 REF+ REFACOM INT0 INT1
WATCHDOG TIMER
SERIAL PORT
SERIAL PORT
TIMER TIMER TIMER T2_OUT
PULSEWIDTH MODULATOR
T2_OUT
PWMA PWMB OUTPUT OUTPUT
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
ABSOLUTE MAXIMUM RATINGS
AVDD, PWMV, DVDD AGND_ .-0.3V AVDD, DVDD DGND.-0.3V AVDD DVDD .-0.3V +0.3V AGND, PWMG DGND .-0.3V +0.3V Analog Inputs (AIN_, ACOM, XTAL1, XTAL2) AGND.-0.3V AVDD_ 0.3V Analog Outputs (PWMA, PWMB) AGND_.-0.3V AVDD_ 0.3V Digital (A_, AD_, ALE/PROG, EA/VPP, INT0, INT1, P_._, PSEN, RST) DGND .-0.3V DVDD 0.3V REF+, REF- AGND_ .-0.3V AVDD_ 0.3V Short-Circuit Duration (PWM_, P_._, ALE/PROG, PSEN).1s Continuous Power Dissipation +70°C) 64-Pin TQFP (derate 5.00mW/°C above +70°C).500mW Operating Temperature Range MAX765_CCB .0°C +70°C MAX765_ECB .-40°C +85°C Junction Temperature .+150°C Storage Temperature Range .-65°C +150°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(MAX7651 AVDD VPWMV DVDD VREF+ +4.5V +5.5V, VREF- fXTAL 12MHz. MAX7652 AVDD VPWMV DVDD +2.7V +3.6V, VREF+ +2.5V, VREF- ACOM AVDD/2, fXTAL 12MHz. TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER ACCURACY Resolution Differential Relative Accuracy (Note Single-ended Differential Nonlinearity (Note2) Offset Error (Note Offset Temperature Coefficient Gain Error (Note Gain Temperature Coefficient Channel-to-Channel Matching (Note Offset gain ±0.25 Differential Single-ended MAX7651 MAX7652 MAX7651 MAX7652 ±0.5 ±0.5 ±2.3 ±0.25 ±1.5 ±1.0 ±4.0 ±1.5 LSB/°C ppm/°C bits SYMBOL CONDITIONS UNITS
DYNAMIC SPECIFICATIONS (53ksps, 1kHz SINE-WAVE INPUT, 5Vp-p (MAX7651), 2.5Vp-p (MAX7652)) Signal-to-Noise Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Small-Signal Bandwidth Full-Power Bandwidth SINAD SFDR Differential Single-ended unaliased harmonics Differential Single-ended (Note -3dB rolloff Differential Single-ended
Flash Programmable 12-Bit Integrated Data-Acquisition Systems
ELECTRICAL CHARACTERISTICS (continued)
(MAX7651 AVDD VPWMV DVDD VREF+ +4.5V +5.5V, VREF- fXTAL 12MHz. MAX7652 AVDD VPWMV DVDD +2.7V +3.6V, VREF+ +2.5V, VREF- ACOM AVDD/2, fXTAL 12MHz. TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER CONVERSION RATE Conversion Time Conversion Rate ANALOG INPUTS (AIN0-AIN7, ACOM) Input Voltage Range Common-Mode Range Input Current Input Capacitance DIGITAL INPUTS Input Voltage -0.5 (DVDD 0.9) (DVDD (DVDD DVDD Input high voltage, XTAL Internal Reset Pulldown Resistance Logical High-to-Low Transition Current Logical Zero Input Current, Ports ALE, PSEN Input Leakage Current, Port Input Capacitance DIGITAL OUTPUTS Output Voltage Output High Voltage ISINK MAX7651: ISOURCE MAX7652: ISOURCE 0.45 MAX7651 MAX7652 Guaranteed design DVDD AVDD AVDD tCONV fXTAL 12MHz fXTAL 12MHz 18.7 53.6 ksps SYMBOL CONDITIONS UNITS
MAX7651/MAX7652
Input high voltage, except XTAL Input Voltage High
RRST
(Note
DVDD DGND
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
ELECTRICAL CHARACTERISTICS (continued)
(MAX7651: AVDD VPWMV DVDD VREF+ +4.5V +5.5V, VREF- fXTAL 12MHz. MAX7652: AVDD VPWMV DVDD +2.7V +3.6V, VREF+ +2.5V, VREF- ACOM AVDD/2, fXTAL 12MHz. TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER Reference Voltage Range Reference Input Current Reference Input Capacitance POWER REQUIREMENTS Analog Supply Current Digital Supply Current Idle-Mode Digital Supply Current Stop-Mode Supply Current Analog Power-Supply Rejection Ratio OUTPUTS Output Voltage Output High Voltage Program Pulse Width Program Address Data Setup tPROGL tASUW Guaranteed design MAX7651 Program Cycle Time tWRITE MAX7652 Verify Address Data Verify Access Time Minimum P2.7 Pulse Width Minimum P2.7 Pulse Width High Clock Period Erase Mode Setup Program Pulse Width Erase Cycle Time tADSUR tREAD tP27L tP27H tP23SU tERASLOW tMASSERASE Guaranteed design 10tCK 3tCK 3tCK 10tCK 8.29 ISINK ISOURCE 10tCK 3tCK 7tCK 54000 7tCK 54000 3tCK 9tCK 16tCK 72000 32tCK 72000 PSRR MAX7651, during page erase MAX7652, during page erase MAX7651 MAX7652 IAVDD IDVDD (Note SYMBOL CONDITIONS UNITS EXTERNAL VOLTAGE REFERENCE CHARACTERISTICS (REF+, REF-) VREF+ VREF0 AVDD
FLASH EXTERNAL PROGRAMMING (FIGURE NOTE
FLASH EXTERNAL MASS ERASE (FIGURE NOTE
Flash Programmable 12-Bit Integrated Data-Acquisition Systems
TIMING CHARACTERISTICS
(MAX7651: AVDD VPWMV DVDD VREF+ +4.5 +5.5V, VREF- fXTAL 12MHz. MAX7652: AVDD VPWMV DVDD +2.7V +3.6V, VREF+ +2.5V, VREF- ACOM AVDD/2, fXTAL 12MHz. TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Figure
PARAMETER Pulse Width (High) EXTERNAL CLOCK Clock Frequency Clock Period Clock High Time Clock Time Clock Rise Time Clock Fall Time tCLCL tCHCX tCLCX tCLCH tCHCL Guaranteed design Guaranteed design 1.5tCLCL 0.5tCLCL 0.5tCLCL 2.5tCLC 0.5tCLCL 2tCLCL 2tCLCL tCLCL 3tCLCL SYMBOL CONDITIONS tCK) UNITS
MAX7651/MAX7652
INSTRUCTION TIMING CHARACTERISTICS Pulse Width Address Valid Address Hold after Valid Instruction PSEN PSEN Pulse Width PSEN Valid Instruction Input Instruction Hold after PSEN Input Instruction Float after PSEN Address Valid Instruction PSEN Address Float tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
TIMING CHARACTERISTICS (continued)
(MAX7651: AVDD VPWMV DVDD VREF+ +4.5 +5.5V, VREF- fXTAL 12MHz. MAX7652: AVDD VPWMV DVDD +2.7V +3.6V, VREF+ +2.5V, VREF- ACOM AVDD/2, fXTAL 12MHz. TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Figure
PARAMETER SYMBOL CONDITIONS tMCS Guaranteed design tMCS Guaranteed design tMCS tMCS tMCS tMCS Data Hold After tRHDX tMCS Data Float After tRHDZ tMCS tMCS Valid Data tLLDV tMCS tMCS Port Address Valid Data tAVDV1 tMCS tMCS tAVDV2 tMCS tMCS tLLWL tMCS tMCS tAVWL1 tMCS tMCS tAVWL2 tMCS 0.5tCLCL 1.5tCLCL tCLCL 2tCLCL tCLCL 2tCLCL tCLCL 2tCLCL 2.5tCLCL 1.5tCLCL tMCS 3tCLCL 2tCLCL tMCS 3tCLCL 2tCLCL tMCS 0.5tCLCL 1.5tCLCL 2tCLCL tMCS 2tCLCL tMCS 2tCLCL tMCS UNITS
MOVX TIMING CHARACTERISTICS (Note Pulse Width Pulse Width tRLRH tWLWH
Valid Data
tRLDV
Port Address Valid Data
Port Address Valid
Port Address Valid
Flash Programmable 12-Bit Integrated Data-Acquisition Systems
TIMING CHARACTERISTICS (continued)
(MAX7651: AVDD VPWMV DVDD VREF+ +4.5 +5.5V, VREF- fXTAL 12MHz. MAX7652: AVDD VPWMV DVDD +2.7V +3.6V, VREF+ +2.5V, VREF- ACOM AVDD/2, fXTAL 12MHz. TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Figure
PARAMETER Data Valid Transition SYMBOL tMCS tQVWX tMCS tMCS Data Valid Before High tQVWH tMCS tMCS Data Hold After High tWHQX tMCS Address Float tRLAZ tMCS High High tWHLH tMCS SERIAL PORT TIMING CHARACTERISTICS Serial Port Clock Cycle Time Output Data Setup Clock Rising Edge Output Data Hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge Input Data Valid tXLXL tQVXH tXHQX tXHDX tXHDV clocks/cycle) clocks/cycle) clocks/cycle) clocks/cycle) clocks/cycle) clocks/cycle) clocks/cycle) clocks/cycle) clocks/cycle) clocks/cycle) tCLCL tCLCL tCLCL tCLCL tCLCL tCLCL tCLCL tCLCL 11tCLCL 3tCLCL tCLCL CONDITIONS tCLCL 2tCLCL tMCS tCLCL 2tCLCL tCLCL UNITS
MAX7651/MAX7652
Note Relative accuracy deviation analog value code from theoretical value after offset gain errors have been nullified. Note AVDD +5.0V, (VREF+) (VREF-) +5.0V AVDD +3.0V, (VREF+) (VREF-) +2.5V. Note Ground "ON" channel; 10kHz sine-wave applied "off" channels. Note PSEN reset cycle. Note digital inputs DGND DVDD. fXTAL Note Table Data Memory Stretch Values. Note minimum frequency when writing internal flash 4MHz.
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table Data Memory Stretch Values
MEMORY CYCLES (default) READ/WRITE STROBE WIDTH (CLOCKS) STROBE WIDTH TIME 12MHz 167ns 334ns 668ns 997ns 1330ns 1666ns 2000ns 2333ns tMCS 0tCLCL 4tCLCL 8tCLCL 12tCLCL 16tCLCL 20tCLCL 24tCLCL 28tCLCL
Table External Flash Programming Modes
MODE Write Lower FLASH Read Lower FLASH Write Lock Write Lock Write Lock Mass Erase Read Bytes Write Upper FLASH Read Upper FLASH PSEN ALE/PROG EA/VPP P2.6 P2.7 P3.6 P3.7 P2.5
Note program lock bits, must duration "Write Lockbit" cycle. Note INT0 INT1 open-drain must either driven require pullup (typically 10k) DVDD.
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
PROGRAMMING tERASLOW ALE/ ~PROG tP23SU 3tCK (min) ~EA/VPP (LOGIC "1")
~PSEN
P2.6
P2.7
P3.6
P3.7 P2.5 P3.4 (READY/~BSY) tMASSERASE
Figure FLASH External Mass Erase Waveforms
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
P1.0-P1.7 92.0-P2.4 P2.5 LOWER UPPER PORT
PROGRAMMING ADDRESS
VERIFICATION ADDRESS
DATA tPROGL
DATA
ALE/~PROG tADSUW 3tCK (min) EA/Vpp (LOGIC "1") tWRITE P2.7 (READ CYCLE) tP27L 10tCK (min) P3.4 (READY/~BSY) tREAD tP27H 3tCK (min) tADSUR
Figure FLASH External Programming Verification Waveforms
tLHLL tAVLL
tLLIV
tPLPH tPLIV
PSEN
tLLPL tPLAZ
tPXIZ
tPXIX tLLAX PORT ADDRESS A0-A7 tAVIV INSTRUCTION ADDRESS A0-A7
PORT
ADDRESS A8-A15
ADDRESS A8-A15
Figure External Program Memory Read Cycle
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
tLLDV tWHLH PSEN tLLWL tRLRH tRLDV tRLAZ tRHDX tRHD2 PORT INSTRUCTION ADDRESS A0-A7 tAVDV1 tAVDV2 PORT DATA ADDRESS A0-A7
ADDRESS A8-A15
Figure External Data Memory Read Cycle
tWHLH PSEN tWLWH
tQVWH PORT INSTRUCTION ADDRESS A0-A7 tQVWX tAVWL1 PORT tAVWL2
tWHQX ADDRESS A0-A7
DATA
ADDRESS A8-A15
Figure External Program Memory Write Cycle
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Typical Operating Characteristics
+25°C, unless otherwise noted.) MAX7651: AVDD VPWMV DVDD VREF+ 5.0V, VREF- VCOM AVDD/2, fXTAL 12MHz. MAX7652: AVDD VPWMV DVDD VREF+ 3.0V, VREF- VCOM AVDD/2, fXTAL 12MHz.
SINGLE-ENDED OUTPUT CODE
MAX7651 toc01
OUTPUT CODE
MAX7651 toc02
NEGATIVE GAIN ERROR SUPPLY VOLTAGE
SINGLE-ENDED
MAX7651/2 toc03
(LSB) -0.2 -0.4 -0.6 -0.8
(LSB) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 DIFFERENTIAL
(LSB)
-0.2 -0.4 -0.6 -0.8 -1.0 -2000 -1500 -1000 -500 CODE 1000 1500 2000
-1.0 -2000 -1500 -1000 -500
CODE
1000 1500 2000
1000 1500 2000 2500 3000 3500 4000 4500 CODE
OFFSET ERROR SUPPLT VOLTAGE
MAX7651/2 toc04
OFFSET ERROR vs.TEMPERATURE
MAX7651 toc05
POSITIVE GAIN ERROR SUPPLY VOLTAGE
MAX7651 toc06
-0.1 OFFSET ERROR (LSB) -0.2 -0.3 -0.4 -0.5 -0.6 DIFFERENTIAL
DIFFERENTIAL GAIN ERROR (LSB)
OFFSET ERROR (LSB)
SINGLE-ENDED
SINGLE-ENDED
SINGLE-ENDED
-0.5 DIFFERENTIAL -1.0 SUPPLY VOLTAGE
-0.5
-0.7 TEMPERATURE (°C)
-1.0 SUPPLY VOLTAGE
POSITIVE GAIN ERROR TEMPERATURE
MAX7651 toc07
NEGATIVE GAIN ERROR TEMPERATURE
MAX7651 toc08
OUTPUT HIGH SOURCE CURRENT
MAX7651 toc09
GAIN ERROR (LSB) DIFFERENTIAL -0.2 -0.4 SINGLE-ENDED -0.6 -0.8
DIFFERENTIAL GAIN ERROR (LSB) SINGLE-ENDED
5.000
OUTPUT HIGH
4.950 AVDD 4.900
4.850
4.800 .-40 TEMPERATURE (°C) SOURCE CURRENT (mA)
TEMPERATURE (°C)
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Typical Operating Characteristics (continued)
+25°C, unless otherwise noted.) MAX7651: AVDD VPWMV DVDD VREF+ 5.0V, VREF- VCOM AVDD/2, fXTAL 12MHz. MAX7652: AVDD VPWMV DVDD VREF+ 3.0V, VREF- VCOM AVDD/2, fXTAL 12MHz.
OUTPUT HIGH SOURCE CURRENT
MAX7651 toc10
OUTPUT SINK CURRENT
MAX7651 toc11
ANALOG SUPPLY CURRENT INPUT VOLTAGE
MAX7651 toc12
3.000
ANALOG SUPPLY CURRENT (mA)
OUTPUT (mV)
OUTPUT HIGH
2.950
AVDD AVDD
2.900 AVDD 2.850
2.800 SOURCE CURRENT (mA)
SINK CURRENT (mA)
INPUT VOLTAGE
ANALOG SUPPLY CURRENT TEMPERATURE
MAX7651 toc13
DIGITAL SUPPLY CURRENT vs.TEMPERATURE
MAX7651 toc14
DIGITAL SUPPLY CURRENT CLOCK FREQUENCY
DIGITAL SUPPLY CURRENT (mA)
MAX7651 toc15
AVDD ANALOG SUPPLY CURRENT (mA)
11.75 DIGITAL SUPPLY CURRENT (mA)
11.50
11.25
AVDD
11.00
10.75
TEMPERATURE (°C)
10.50 TEMPERATURE (°C)
CLOCK FREQUENCY (MHz)
IDLE-MODE SUPPLY CURRENT INPUT VOLTAGE
MAX7651 toc16
POWER-DOWN CURRENT INPUT VOLTAGE
MAX7651 toc17
IDLE-MODE SUPPLY CURRENT (mA)
POWER-DOWN CURRENT (µA)
INPUT VOLTAGE INPUT VOLTAGE
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Description
NAME AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AVDD AGND REF+ REFPWMV PWMG PWMA PWMB INT0 INT1 P3.7/RD P3.6/WR P3.5/T1 P3.4/T0/ READY P3.3 P3.2 FUNCTION Analog Input Negative differential input relative AIN1 positive differential input relative ACOM. (See Table Analog Input Positive differential input relative AIN0 positive differential input relative ACOM. (See Table Analog Input Negative differential input relative AIN3 positive differential input relative ACOM. (See Table Analog Input Positive differential input relative AIN2 positive differential input relative ACOM. (See Table Analog Input Negative differential input relative AIN5 positive differential input relative ACOM. (See Table Analog Input Positive differential input relative AIN4 positive differential input relative ACOM. (See Table Analog Input Negative differential input relative AIN7 positive differential input relative ACOM. (See Table Analog Input Positive differential input relative AIN6 positive differential input relative ACOM. (See Table Positive Analog Supply Voltage. Analog power source converter other analog functions excluding converter. Bypass with 0.1µF parallel with 10µF capacitor AGND. Analog Ground. Connect PWMG AGND. High-Side Reference Input. High-side reference voltage conversions. Must between AVDD AGND. Bypass AGND with 0.1µF parallel with 10µF capacitor AGND. Low-Side Reference Input. Low-side reference voltage conversions. Must between AVDD AGND. connected AGND bypass AGND with 0.1µF parallel with 10µF capacitor AGND. Positive Analog Supply Voltage Analog power source converter outputs. Bypass with 0.1µF parallel with 10µF capacitor PWMG. Ground PWM. Connect AGND. Output Output Converter Digital-to-Analog Conversions. Output Output Converter Digital-to-Analog Conversions. External Interrupt Input (active-low) External Interrupt Input (active-low) P3.7: General Purpose Port (most significant bit) Read Output. Read strobe accessing external data memory (active-low) P3.6: General Purpose Port Write Output. Write strobe writing external data memory (active-low) P3.5: General Purpose Port Timer External Input P3.4: General Purpose Port Timer External Input READY: Ready State Output (external flash programming mode only) P3.3: General Purpose Port P3.2: General Purpose Port
Flash Programmable 12-Bit Integrated Data-Acquisition Systems
Description (continued)
NAME P3.1/ TXD0 P3.0/ RXD0 DGND DVDD P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5 P2.6 P2.7 PSEN ALE/ PROG DGND DVDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P3.1: General Purpose Port TXD0: Transmit Serial Output Serial Port P3.0: General Purpose Port (least significant bit) RXD0: Receive Serial Input Serial Port Digital Ground. Connect DGND AGND power source. Connect pins together. Positive Digital Supply Voltage. Bypass with 0.1µF parallel with 10µF capacitor DGND. Connect pins together. P2.0: General Purpose Port (least significant bit) Internal Flash Memory Address P2.1: General Purpose Port Internal Flash Memory Address P2.2: General Purpose Port A10: Internal Flash Memory Address P2.3: General Purpose Port A11: Internal Flash Memory Address P2.4: General Purpose Port A12: Internal Flash Memory Address P2.5: General Purpose Port Upper Lower Internal Flash Memory Select (see Table P2.6: General Purpose Port Flash Programming Mode Select (see Table P2.7: General Purpose Port (most significant bit) Flash Programming Mode Select (see Table Program Store Enable (active-low). Qualifies program read from external devices. ensure flash data integrity during insertions, RLOAD must greater than equal 200k. ALE: Address Latch Enable. ensure flash data integrity during insertions, RLOAD must greater than equal 200k. PROG: Flash Memory Program Pulse Digital Ground. Connect pins together. Positive Digital Supply Voltage. Bypass with 0.1µF parallel with 10µF capacitor DGND. Connect pins together. P0.0: General Purpose Port (least significant bit) AD0: Internal Flash Memory Data External Memory Data (least significant bit) P0.1: General Purpose Port AD1: Internal Flash Memory Data External Memory Data P0.2: General Purpose Port AD2: Internal Flash Memory Data External Memory Data P0.3: General Purpose Port AD3: Internal Flash Memory Data External Memory Data P0.4: General Purpose Port AD4: Internal Flash Memory Data External Memory Data FUNCTION
MAX7651/MAX7652
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Description (continued)
NAME P0.5/ P0.6/ P0.7/ P1.0/T2/ T2OUT/ P1.1/ T2EX/ P1.2/ RXD1/ P1.3/ TXD1/ P1.4/ P1.5/ P1.6/ P1.7/ EA/VPP XTAL2 XTAL1 DGND DVDD TEST ACOM P0.5: General Purpose Port AD5: Internal Flash Memory Data external memory P0.6: General Purpose Port AD6: Internal Flash Memory Data external memory P0.7: General Purpose Port (most significant bit) AD7: Internal Flash Memory Data external memory P1.0: General Purpose Port (least significant bit) Timer External Input T2OUT: Timer External Output AD0: Internal Flash Memory Address P1.1: General Purpose Port T2EX: Timer External Capture/Reload Trigger AD1: Internal Flash Memory Address P1.2: General Purpose Port RXD1: Receive Serial Input UART AD2: Internal Flash memory Address P1.3: General Purpose Port TXD1: Transmit Serial Input UART AD3: Internal Flash Memory Address P1.4: General Purpose Port AD4: Internal Flash Memory Address P1.5: General Purpose Port AD5: Internal Flash Memory Address P1.6: General Purpose Port AD6: Internal Flash Memory Address P1.7: General Purpose Port AD7: Internal Flash Memory Address Connect DGND external ROM. Connect DVDD internal flash memory. VPP: Flash Programming Voltage (external flash programming mode only) Active High Reset. Connected internal 130k pulldown resistor. Connect 2.2µF (typ) capacitor from DVDD RST. Clock Output. Connect crystal across XTAL1 XTAL2. on-chip clock signal available XTAL2. Leave XTAL2 unconnected when XTAL1 driven with external clock. Clock Input. Connect crystal across XTAL1 XTAL2. Alternatively, drive XTAL1 with CMOScompatible clock leave XTAL2 unconnected. Digital Ground. Connect pins together. Positive Digital Supply Voltage. Bypass with 0.1µF parallel with 10µF capacitor DGND. Connect pins together. Test Point. Must connected DGND. Analog Common Input. Negative differential input relative AIN_ single-ended measurements (see Table Connect AVDD/2 maximum input range. FUNCTION
Flash Programmable 12-Bit Integrated Data-Acquisition Systems
Detailed Description
MAX7651/MAX7652 Architecture
MAX7651/MAX7652 complete 12-bit dataacquisition systems featuring algorithmic, switchedcapacitor, analog-to-digital converter (ADC), dual pulse-width-modulated digital-to-analog converter (DAC), industry-standard 8051 microprocessor core with variety timing peripherals. Using external oscillator with operating frequency between 1MHz 12MHz, MAX7651/MAX7652 execute majority commands only four clock periods yield average speed improvement times over typical 8051 microprocessors requiring clock periods instructions. MAX7651/MAX7652 Programmer's Reference Manual further details. On-chip peripherals include four 8-bit parallel ports, serial ports, three general-purpose timers, watchdog timer. MAX7651/MAX7652 also feature 16kB banks flash memory bytes high-speed random access memory. Figure shows program memory organization. When high, access internal blocks flash memory beginning addresses 0000H (lower block) 2000H (upper block). Addresses 0000H-0002H 0003H-006AH lower block reserved reset vector interrupt vectors, respectively (see Table Addresses 3FC0H-3FFFH upper block also reserved cannot accessed CPU. Addresses 4000H-FFFFH external ROM. When low, external must used program addresses (0000H-FFFFH). Figure shows data memory (RAM) organization. first bytes partitioned between internal 128-byte blocks. lower block (addresses 0000H- 007FH) used registers scratchpad memory accessed either directly indirectly (see MAX7651/MAX7652 Programmer's Reference Manual upper block (addresses 0080H-00FFH) reflects special function registers (SFRs) when accessed directly, separate scratchpad memory when accessed indirectly. Addresses 0100H-FFFFH reserved external RAM. Table shows mapping memory Table shows contents power-up reset. Unshaded register designations consistent with industry standard 8051. Shaded register designations
MAX7651/MAX7652
Memory Organization
MAX7651/MAX7652 support 64kB external program (read-only) memory data (randomaccess) memory conformance with 8051 industry standard.
FFFFH
EXTERNAL
LOWER BYTES UPPER BYTES INDIRECT ADDRESSING LOWER BYTES DIRECT INDIRECT ADDRESSING SPACE DIRECT ADDRESSING
4000H
DIRECT
3FFFH 3FCOH
RESERVED UPPER INTERNAL
3FFFH EXTERNAL 0000H
BANK SELECT BIT-ADDRESSABLE REGISTERS BANK BANK BANK BANK
2000H 1FFFH
LOWER INTERNAL
006AH INTERRUPT VECTORS RESET VECTOR 0001H 0002H 0000H
0000H
Figure Program Memory Organization
Figure Data Memory (RAM) Organization
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table Reset Interrupt Vector Locations
ADDRESS RANGE 0000H-0002H 0003H-000AH 000BH-0012H 0013H-001AH 001BH-0022H 0023H-002AH 002BH-0032H 0033H-003AH 003BH-0042H 0043H-004AH 004BH-0052H 0053H-005AH 005BH-0062H 0063H-006AH Reset Vector INTERRUPT VECTORS INT0 (external interrupt Timer INT1 (external interrupt Timer Serial Port transmit/receive Timer Reserved Serial Port transmit/receive Flash memory write/page erase (end conversion) Reserved Reserved Watchdog timer FUNCTION NATURAL PRIORITY*
*Lower priority number takes precedence.
Table Memory Organization
ADDRESS EICON T2CON SCON1 SCON0 TCON SBUF0 EXIF TMOD DPL0 DPH0 DPL1 DPH1 CKCON Reserved PCON SBUF1 RCAP2L ADDAT0 Reserved VERSION RCAP2H ADDAT1 Reserved Reserved Reserved Reserved ADCON PWPS PWDA PWDB EEAL EEAH EEDAT EESTCMD PWMC
Note SFRs column addressable. Other SFRs addressable. Note VERSION contains silicon will change future MAX7651/MAX7652 revisions.
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table Contents Power-Up Reset
REGISTER ADDRESS DPL0 DPH0 DPL1 DPH1 PCON TCON TMOD CKCON EXIF SCON0 SBUF0 SCON1 SBUF1 ADDAT0 ADDAT1 ADCON T2CON RCAP2L RCAP2H EICON PWPS PWDTA PWDTB
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table Contents Power-Up Reset (continued)
REGISTER EEAL EEAH EEDAT EESTCMD PWMC ADDRESS
unique MAX7651/MAX7652. Subsequent sections this data sheet explain functions. RESERVED addresses used MAX7651/ MAX7652 testing should accessed user software. Undesignated addresses implemented will return indefinite data when read.
other bits have significance this register. When SEL= DPTR instructions DPH0 DPL0, when SEL=1, DPTR instructions DPH1 DPL1. Program code developed 8051 platforms that single data pointer (DPH0 DPL0) requires modification (the default value). Power Control PCON Power Control provides software control over power modes. both IDLE STOP modes, processing suspended internal registers maintain their current data. STOP mode additionally disables internal clock analog circuitry. enabled interrupt used terminate IDLE mode. reset necessary terminate STOP mode sufficient terminate IDLE mode. Table shows PCON format.
Special Function Registers Microprocessor Operations Control
Accumulator Accumulator used arithmetic operations including addition, subtraction, multiplication, division, Boolean manipulation. Accumulator specific instructions designate accumulator "A". used multiply divide operations. otherwise available scratchpad register. Program Status Word Program Status Word contains bits that indicate state microprocessor CPU. Table shows individual functions. Stack Pointer Stack Pointer contains "top-of-thestack" address internal RAM. This address increments before data stored during PUSH CALL executions. default value after reset, that stack begins 08H. Dual Data Pointer SFRs MAX7651/MAX7652 feature dual data pointers enhance execution times when moving large blocks data. DPTR-related instructions bits contained pairs DPH0 DPL0 DPH1 DPL1 address external data peripherals. (SEL) within determines data pointer.
Instruction
MAX7651/MAX7652 instruction compatible with 8051 industry standard. MAX7651/ MAX7652 Programmer's Reference Manual complete listing.
Analog-to-Digital Converter
Operation Figure shows simplified model converter input structure associated switch timing. Once initiated, voltage conversion requires periods external master clock. Capacitor CHOLD charges difference between inputs AIN+ AIN- during eight clock periods acquisition time that begin rising edge clock cycle This charge sample subsequently transferred (through action SW5) during eight clock periods that begin rising edge clock cycle asserts conversion complete flag rising-edge clock cycle (see Special Function Registers).
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
VREF+ 2.1pF CREF VREF1 VREF3 AIN5 1.50pF CHOLD VREF+ AIN+
WRITE
INPUT SAMPLE
Figure Input Structure Switch Timing
Since acquisition time limited eight clock periods, acquired voltage CHOLD have significant error analog input source impedance (Rs) large. Limit worst-case error ensuring, tCLK CHOLD where tCLK clock period. Smaller values necessary antialiasing filter used. continuously samples positive negative difference between external reference voltages REF+ REF- reconfiguring capacitor CREF over alternate eight clock-period intervals. Switch pairs forced respectively, rising edge clock cycle five ensure synchronization with conversions. Capacitor CHOLD also charges difference
between REF+ REF- rising edge clock cycle remains charged until next conversion. Nevertheless, continuous CREF charging requirements dominate loading REF+ REF- inputs. Analog Inputs MAX7651/MAX7652 operate either single-ended differential mode. single-ended mode, eight input channels (AIN0-AIN7) assigned AIN+, ACOM assigned AIN- (see Figure differential mode, eight input channels assigned AIN+ AIN- with four distinct pairings. Table shows input assignments different values bits Control (see Special Function Registers). Analog Input Protection Internal protection diodes clamp analog inputs AVDD AGND, channels swing within AGND
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
0.3V AVDD 0.3V without damage. accurate conversions inputs should extend beyond supply rails. Transfer Function Figure shows bipolar two's complement transfer function. single-ended conversion range extends from -VREF/2 +VREF/2, where VREF VREF+ VREF-. differential conversion range extends from -VREF +VREF. Each single-ended differential mode reflects voltage increments VREF/4096 2VREF/4096, respectively. Special Function Registers ADCON Control establishes operating conditions input configurations. Table shows individual functions. "write" ADCON initiates conversion process.
Table Program Status Word (PSW) Format
(MSB) NAME (LSB)
DESCRIPTION Carry Flag. "1", following additional operation that results carry subtraction operation that results borrow. Otherwise cleared Auxiliary Carry Flag. Similar used operations. User Flag General-purpose flag software control. Register Select Bits. These select four banks eight registers that occupy first addresses lower internal RAM. SELECTED REGISTER BANK Register bank addresses 00H-07H Register bank addresses 08H-0FH Register bank addresses 10H-17H Register bank addresses 18H-1FH
RS1,
Overflow Flag. "1", arithmetic operation that yields overflow. Otherwise cleared zero. User Flag General-purpose flag software control. Parity flag. "1", when module accumulator bits (odd number 1's), otherwise clear zero (even number 1's).
Table Power Control (PCON) Format
(MSB) SMOD0 6,5,4 NAME SMOD0 STOP IDLE Reserved General Flag General-purpose flag software control. General Flag General-purpose flag software control. STOP Mode Select. STOP stops crystal oscillator powers down analog circuitry. IDLE Mode Select. IDLE results suspension processing. STOP (LSB) IDLE
DESCRIPTION Serial Port Baud-Rate Doubler Enable. SMOD0 doubles baud rate.
Flash Programmable 12-Bit Integrated Data-Acquisition Systems
External Reference
MAX7651/MAX7652 require external reference voltages VREF+ VREF-. single reference voltage used VREF+, when VREF- connected AGND. positive reference voltages must greater than analog supply voltage capable supplying 30µA. Bypass each reference voltage AGND with 0.1µF capacitor parallel with 10µF capacitor.
Digital-to-Analog Converters (DACs)
MAX7651/MAX7652 provide pulse-width modulated (PWM) DACs applications that require high conversion accuracy. Figure shows pulsewidth-modulator block diagram. clock signal divided where content Pulse-Width Prescaler (PWPS) register. This reduced frequency signal used drive modulo255 counter. When counter value exceeds value stored SFRs PWDA (Output PWDB
MAX7651/MAX7652
+VREF -VREF
1LSB VREF 4096
+VREF -VREF VREF (VREF+) (VREF-)
1LSB 2VREF 4096
VREF (VREF+) (VREF-)
(VAIN) (VACOM)
(VAIN+) (VAIN-)
INPUT VOLTAGE (LSBs) 1LSB
INPUT VOLTAGE (LSBs) 1LSB
Figure Single-Ended Mode Transfer Function
Figure Differential Mode Transfer Function
Table Analog Input Selection
MODE Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Differential Differential Differential Differential AIN+ AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN1 AIN3 AIN5 AIN7 REF+ AINACOM ACOM ACOM ACOM ACOM ACOM ACOM ACOM AIN0 AIN2 AIN4 AIN6 REF-
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
USER ACCESSIBLE REGISTER PWDA REGISTER MAGNITUDE COMPARATOR FROM CRYSTAL OSCILLATOR DIVIDE MODULO COUNTER MAGNITUDE COMPARATOR PWMB OUTPUT PWMA OUTPUT TPWPERIOD 2(PWPS+1) 255/FOSC TPWHIGH (255 PWD(X))/255 TPWPERIOD FOSC CRYSTAL FREQUENCY PINS TPWHIGH TPWPERIOD
PWPS USER ACCESSIBLE REGISTER
Figure Output Waveform
PWDB REGISTER USER ACCESSIBLE REGISTER
Five watchdog-related control bits status flags located different special function registers. Table shows particular functions locations.
Figure Block Diagram
8051-Compatible Peripherals
Parallel Ports Like other 8051-based systems, MAX7651/ MAX7652 features four 8-bit parallel ports that support general input output, address data lines, various special functions. Each bidirectional port latch register (SFRs P3), input buffer, output driver. Port open-drain. Writing logic level establishes high-impedance input. When used general-purpose output, requires external pull-up resistor validate logic level When used address/data output, features internal active high driver. Port bidirectional Flash data port during Flash programming verification. Port Port bidirectional port with internal pullups. Port pins that have written them pulled high internal pullups serve inputs. Port receives low-order address bytes during Flash programming verification. Port Port bidirectional port with internal pullups. Port pins that have written them pulled high internal pullups serve inputs. Port also serves high-order address data (for 16-bit operations) during accesses external memory, using strong internal pullups when emitting 1's. Port Port bidirectional port with internal pullups. Port pins that have written them pulled high internal pullups serve inputs. ports support special functions listed Table Write corresponding port register enable alternative function.
(Output corresponding output transitions from high (Figure Writing PWDA PWDB, yields waveform with 100% duty cycle (High), writing PWDA PWDB yields waveform with duty cycle (Low). Writing intermediate register value yields waveform with duty cycle 255) 100%. Tables show formats PWPS, PWDA, PWDB SFR's. External low-pass filters needed obtain voltages between from outputs. Simple filters preferred. Choose avoid excessive loading, choose <0.1µF avoid large transient currents that reflect switching action. Each filtered output source sink 2mA. exceed this specification. larger output capability required, provide appropriate buffer such unity-gain amp. circuitry Outputs enabled with Pulse-Width Modulator Control (PWMC) SFR. Table shows PWMC format.
Watchdog Timer
MAX7651/MAX7652 features watchdog timer that resolves irregular software control. watchdog timer resets microprocessor software fails reset timer within four pre-selected time intervals. timer generates optional interrupt after 216, 219, 222, clock periods external oscillator. generates reset signal after additional clock periods. Table indicates specific interrupt reset times that apply 12MHz clock frequency.
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table Control (ADCON) Format-SFR Address
(MSB) CCVT NAME CCIE OVRN (LSB)
DESCRIPTION Conversion Complete Flag (Read Only). MAX7651/MAX7652 this flag following conversion indicate valid data ADDAT1 ADDAT0 data SFRs (see below). cleared when ADDAT1 read CPU. Continuous Conversion Enable (Read/Write). When CCVT performs continuous conversions rate clock cycles/conversion. Conversions continue until MAX7651/ MAX7652 reset until CCVT cleared, which case conversions stops after current conversion ends. Conversion Complete Interrupt Enable (Read/Write). When CCIE interrupt generated each conversion. Overrun Flag (Read Only). MAX7651/MAX7652 this flag whenever conversion completes while set. previous conversion result overwritten. OVRN cleared when ADDAT1 read CPU. Analog Input Multiplexer Select Bits. Used establish input configurations single-ended differential conversions (see Table
CCVT
CCIE
OVRN
M3-M0
Note: SFRs ADDAT1 ADDAT0 contain results individual conversions with formats shown Tables read ADDAT1 clears OVRN flags ADCON.
Table Data-1 (ADDAT1) Format-SFR Address
(MSB) SIGN (LSB)
Table Data-0 (ADDAT0) Format-SFR Address
(MSB) (LSB)
Table Pulse-Width Prescaler (PWPS) Format-SFR address
(MSB) PWPS7 PWPS6 PWPS5 PWPS4 PWPS3 PWPS2 PWPS1 (LSB) PWPS0
Table Pulse-Width Data (PWDA) Format-SFR address
(MSB) PWDA7 PWDA6 PWDA5 PWDA4 PWDA3 PWDA2 PWDA1 (LSB) PWDA0
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table Pulse-Width Data (PWDB) Format-SFR address
(MSB) PWDB7 PWDB6 PWDB5 PWDB4 PWDB3 PWDB2 PWDB1 (LSB) PWDB0
Table Pulse-Width-Modulator Control (PWMC) Format-SFR Address
(MSB) PWON NAME PWON PWENA PWENB PWENA (LSB) PWENB
DESCRIPTION Pulse-Width-Modulator Enable. PWON enable divide-by-two, PWPS prescaler, modulo-255 counter circuit functions. used Output Enable. enable output Output Enable. enable output
Table Watchdog Interrupt Reset Times (fCK 12MHz)
INTERRUPT TIMOUT clocks clocks clocks clocks TIME (ms) 5.461 43.691 349.525 2796.000 RESET TIMOUT clocks clocks clocks clocks TIME (ms) 5.474 43.734 349.567 2796.042
Serial Interface Ports MAX7651/MAX7652 each have serial interfaces that operate according 8051 industry standard. Serial Port uses SFRs SCON0 SBUF0 control buffer functions. Serial Port uses SFRs SCON1 SBUF1 with identical functionality. MAX7651/MAX7652 Programmer's Reference Manual details concerning serial-port data operations timing information. Timers/Counters MAX7651/MAX7652 have three timer/counters that function several different modes applications such UART baud-rate control. three timer/counters operate according 8051 industry standard. Specifically, control (TCON), mode (TMOD), timer-0 parameter (TL0, TH0), Timer1 parameter (TL1, TH1), Timer-2 parameter (TL2, TH2, RCAP2L, RCAP2H) SFRs have conventional formats. MAX7651/ MAX7652 Programmer's Reference Manual information concerning timer/counter applications.
Crystal Oscillator
MAX7651/MAX7652 each have single-stage inverter (Input XTAL1, Output XTAL2) that supports crystal controlled oscillator. crystal oscillator frequency should between MHz. Note: External flash memory programming requires minimum crystal oscillator frequency 4MHz.
Crystal Specification:
Rs(typ) Rs(max) Load Capacitance Oscillation Mode Frequency Tolerance Holder Capacitance Motional Inductance (typ) Motional capacitance (typ) 25-40 10-15pF Fundamental 12,000MHz (max) ±0.01% 50mH 0.0035pF
Flash Programmable 12-Bit Integrated Data-Acquisition Systems
external oscillator also used clock MAX7651/MAX7652 frequencies between 12MHz, provided that duty cycle between 60%. When using external clock source connect clock XTAL1, with XTAL2 unconnected.
Using FLASH Memory
upper lower blocks internal Flash memory each organized 64-byte pages. Read, write, page-erase operations cannot applied either block while executing program commands from other block. Note: Standard MOVC operations supported. FLASH Memory Special Function Registers Tables show formats EEAH EEAL SFRs. EEAH register specifies applicable Flash memory block (high low) page address within that block. EEAL register specifies byte address within specified page. Table shows format Flash memory data (EEDAT) that used 8-bit read write transfers from specified address. Table shows format Flash memory status command (EESTCMD) SFR. Bits RDYHI RDYLO cleared zero when read, write, pageerase operation applied high flash memory block. These bits once flash
MAX7651/MAX7652
Applications Information
Performing Conversion
example conversion with MAX7651/ MAX7652 follows: Write ADCON SFR, setting CCIE bits M3-M0 appropriate values desired differential single-ended analog input configuration (Tables Wait clock cycles receive Interrupt indication that conversion complete. Read conversion data SFRs ADDAT0 ADDAT1 described Tables
Table Watchdog Timer Control Status Bits
NAME DESCRIPTION Watchdog Interrupt Flag. WDIF after completion interrupt timeout period (see Table 14). WDIF must cleared software before exiting interrupt service routine. Otherwise interrupt reoccurs upon exiting. WDIF automatically cleared either external assertion WDT-generated reset. Watchdog Reset Flag. WTRF status/control indicating that Watchdog counter counted additional clocks past interrupt generated processor RESET. 8051's "reset" routine should check WTRF flag determine source reset. Additionally, WTRF flag been Watchdog Timer counts will reset when zero written WTRF flag. This allows processor regain synchronization with after reset occurred. WTRF also cleared when zero written Enable Watchdog Timer. enable watchdog timer. assertion external automatically clears EWT. cleared after being set. watchdog timer count will suspend until again. Reset Watchdog Timer. Writing will reset watchdog counter ONLY count been reached (WDIF clock window expired (WTRF Writing before timeout period will reset watchdog timer. Watchdog Control Controls watchdog interrupt timeout (see Table 14). Watchdog Control Controls watchdog interrupt timeout (see Table 14). Enable Watchdog Interrupt. interrupt will generated after interrupt timeout period when EWDI Either WDT-generated reset assertion external automatically clears EWDI.
WDIF
EICON
WTRF
EICON
EWDI
EICON CKCON CKCON
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table Alternate Port Functions
PORT P1.3 P1.2 P1.1 P1.0 P3.7 P3.6 P3.5 P3.4 P3.1 P3.0 ALTERNATIVE FUNCTION TXD1 RXD1 T2EX T2/T2_OUT T0/READY TXD0 RXD0 Transmit Serial Output Serial Port Receive Serial Input Serial Sort Timer External Capture/Reload Trigger Timer External Input/Output Read Output Write Output Timer External Input Timer External Input/Ready State Output (External Flash Programming mode only) Transmit Serial Output UART Receive Serial Input UART DESCRIPTION
Table Flash Address High (EEAH) Format-SFR Address
(MSB) BLOCK EEAH6 NAME BLOCK EEAH_ EEAH5 EEAH4 EEAH3 EEAH2 EEAH1 (LSB) EEAH0
DESCRIPTION Flash Memory Block. BLOCK access high Flash memory block. BLOCK access Flash memory block. Page Address. Determines Flash memory page. EEAH6 MSB.
Table Flash Address (EEAL) Format-SFR Address
(MSB) NAME EEAL_ used. Byte within Page Address Bit. Determines byte address within Flash memory page. EEAL5 MSB. EEAL5 EEAL4 EEAL3 EEAL2 EEAL1 (LSB) EEAL0
DESCRIPTION
memory operation complete. Never attempt execute flash memory command when either RDYHI RDYLO (command action progress). Flash Memory Read read Flash memory, load address into SFRs EEAH EEAL. Then write EESTCMD. results read operation will available EEDAT next instruction cycle.
Flash Memory Write Erase operations bits "1". After byte been programmed must erased before re-written. write Flash memory, load address into SFRs EEAH EEAL, load data into EEDAT. Then write EESTCMD. execution time flash memory write 63µs (typ) independent clock.
Flash Programmable 12-Bit Integrated Data-Acquisition Systems
Note: write same location more than twice before next page/mass erase operation. Flash Memory Page Erase page erase operation sets bits within page "1"s. erase page from Flash memory, load page address into EEAH, register EEAL used. Then write EESTCMD. execution time page erase 9.4ms (typ) independent clock. Note: attempt apply read, write, pageerase operations flash memory block which currently executing program instructions. Force PROG low. P3.4 (READY) will indicate write progress. When P3.4 returns high (write complete after approximately 63µs), PROG high. Power-down sequence. Remove drive from allow PSEN ALE/PROG float high. Pull low. High-Z digital pins. Remove power from power pins. Note: write same location more than twice before next page/mass erase operation. External Flash Memory Verify (Table External Verify: lock bits have been programmed, programmed flash array(s) read back through address data lines verification. lock bits cannot verified directly. Verification lock bits achieved observing that their features enabled. External verify (readback) power-up sequence: Power-up MAX7651/MAX7652 with asserted, allow PSEN float state (they will internally pulled-up during assertion). Wait 10ms internal bandgap oscillator stabilize. Pull PSEN LOW, HIGH, HIGH, P2.6, P2.7, P3.6, P3.7, P2.5, Flash Programming Modes (Table reading either LOWER UPPER flash memory block. Note: P2.7 cycled low/high perform FLASH read operation. Minimum time P2.7 clock cycles. External verify power-down sequence: Power-down sequence A)Remove drive from allow PSEN ALE/ PROG float high. Pull low. Hi-z digital pins. Remove power from power pins.
MAX7651/MAX7652
External Flash Memory Programming
MAX7651/MAX7652 normally shipped with internal Flash memory blocks fully erased (all bits ready external programming. External write, read (verify), mass-erase operations available. Flash memory addresses either upper lower 8-kbyte blocks specified Ports Before applying external Flash memory operations, power-up MAX7651/MAX7652 with asserted. ALE, PSEN, ports pulled high with weak resistive pullups. Port requires external pullups. Wait least 10ms oscillator internal circuitry stabilize. program, verify masserase flash memory programming steps outlined below. Note: Failure follow proper power-up conditions specified flash memory programming steps result loss flash data integrity. External Flash Memory Program (Table Erase operations. bits "1". After byte been programmed must erased before re-written. Power-up device with asserted allow PSEN float state (they will internally pulled-up during assertion). Wait 10ms internal bandgap oscillator stabilize. Apply memory location address lines ports Apply data data lines port Raise DVDD pull PSEN low. P2.6, P2.7, P3.6, P3.7 levels shown Table P2.5 high lower higher Flash memory block.
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
External Flash Memory Mass Erase mass erase operation sets bits, including lock bits (Table 22). External Erase: Both FLASH arrays simultaneously mass-erased electrically using proper combination control signals shown Table erase operation must executed before either memory programmed. Lock bits also erased (Set External chip erase power-up sequence: Power-up chip with asserted, allow PSEN float state (they will internally pulled-up during assertion). Wait 10ms internal bandgap oscillator stabilize. Pull PSEN LOW, HIGH, P2.6, P2.7, P3.6, P3.7, P2.5, Mass Erase mode Flash Programming Modes (table P3.4 will during mass erase cycle return mass erase cycle. External chip erase power-down sequence: Power-down sequence A)Remove drive from allow PSEN ALE/ PROG float high. Pull low. digital pins. Remove power from power pins. Figure shows timing waveforms that apply Flash memory mass erase operation. Flash Memory Lock Bits MAX7651/MAX7652 each contains three lock bits which left unprogrammed (logic "1") programmed (logic "0") obtain additional features listed table below: When lock programmed (set logic "0"), logic level sampled latched during deassertion. Subsequent changes logic levels have effect. device powered-up without reset (RST), latch initializes random value holds that value until pulsed high, then low. necessary that latched value agreement with current logic level that order device function properly. Signature Bytes MAX7651/MAX7652 contain three signature bytes with information shown Table Read each byte following Flash Memory Read procedure, P2.6, P2.7, P3.6, P3.7 low. Signature bytes affected mass erase page erase operations.
Table Flash Memory Data (EEDAT) Format-SFR Address
(MSB) EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 (LSB) EEDAT0
Table Flash Status Control (EESTCMD) Format-SFR Address
(MSB) RDYHI/ EECMD7 RDYLO/ EECMD6 NAME RDYHI EECMD5 EECMD4 EECMD3 EECMD2 EECMD1 (LSB) EECMD0
DESCRIPTION High Block Ready Status. MAX7651/MAX7652 RDYHI during read, write, pageerase operations that applied 8-kbyte "high" block flash memory. otherwise Block Ready Status. MAX7651/MAX7652 RDYLO during read, write, pageerase operations that applied 8-kbyte "low" block flash memory. otherwise Flash Memory Command Bits. Used specify read, write, page-erase memory commands. EECMD7 MSB.
RDYLO EECMD
Flash Programmable 12-Bit Integrated Data-Acquisition Systems
Interrupt System
MAX7651/MAX7652 program-assist interrupts that either external internal 8051 system. Table shows locations interrupt enable priority control. Shaded Table regions reflect 8051 industry standard. IE.7 high enable interrupts. MAX7651/MAX7652 Programmer's Reference Manual. clock cycles needed (four twelve) increment each timer/counter number clock cycles needed execute MOVX instruction. MAX7651/ MAX7652 Programmer's Reference Manual further details.
MAX7651/MAX7652
Analog Digital Supplies
MAX7651/MAX7652 have multiple power-supply inputs: analog AVDD three digital DVDD. pulse width modulators have their power supply inputs, PWMV PWMG. Decouple supply inputs with 0.1µF capacitor parallel with 10µF capacitor, with both capacitors close supply pins possible with shortest possible connection ground plane.
Timers
MAX7651/MAX7652 feature several modes timing control through CKCON special function register. Table shows CKCON format. individual control bits used number
Table
PARAMETER TPROGL TASUW TWRITE TADSUR TREAD TP27L TP27H 10TCK 3TCK 83ns 250ns 10TCK 3TCK 7TCK 54µs 3TCK 8TCK 50ns Read access time 7TCK 72µs COMMENTS TPROGL must equal TWRITE during lockbit writes
Note: P2.6, P2.7, P3.6, P3.7 must also meet TASUW (min) timing specification.
Table Lock Protection Modes
PROGRAM LOCK BITS PROTECTION TYPE program lock features (Default after mass erase) MOVC instructions executed from external program memory disabled from fetching code bytes from internal memory, sampled latched reset (RST), further external data programming both FLASH arrays disabled. Verify (read) disabled. (see Mode External execution disabled override, Mode
Table MAX7651/MAX7652 Signature Bits
ADDRESS DATA MEANING JEDEC Continuation Byte Manufactured Maxim MAX7651/MAX7652
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table MAX7651/MAX7652 Interrupts (Note
INTERRUPT INT0 INT1 FLASH WDTI EXF0 EXF2 TI_0 RI_0 EXF2 TI_1 RI_1 ASSOCIATED FEATURE External Interrupt External Interrupt Flash Operation Complete Operation Complete Watchdog Timer Timer Timer Serial Port Timer Serial Port ENABLE (NOTE IE.0 IE.2 EIE.0 EIE.1 EICON.1 IE.1 IE.3 IE.4 IE.5 IE.6 PRIORITY (NOTE IP.0 IP.1 EIP.0 EIP.1 EIP.4 IP.1 IP.3 IP.4 IP.5 IP.6 PRIORITY
Note Shaded areas reflect 8051 industry standard. Note Enable high enable interrupt. Note Priority high eatablish high priority.
Table CKCON Address
(MSB) NAME WD10 TIMER2 TIMER1 TIMER0 MD2, MD1, adjust Read/Write strobe width clocks). number clock cycles plus MD2, MD1, decimal value. LSB. TIMER2 TIMER1 TIMER0 (LSB)
DESCRIPTION adjust interrupt interval watchdog timer. (See Watchdog Timer.) Timer Control. TIMER2 TIMER2-associated counter increments four clock intervals. TIMER2 increments clock intervals. Timer Control. TIMER1 Timer1-associated counter increments four clock intervals. TIMER1 increments clock intervals. Timer Control. TIMER0 Timer0-associated counter increments four clock intervals. TIMER0 increments clock intervals.
Power Requirements
MAX7651 operates from while MAX7652 operates from analog digital supply voltages. analog supply current typically 2mA. typical digital supply currents (continuous conversions 12MHz clock frequency) 13mA +5V, respectively. Current consumption will vary
depending read/write flash read/write page erase duty cycle. Idle Mode idle mode, processing suspended internal data registers maintain their current data. However, unlike typical 8051 systems, clock disabled internally. PCON.0 (IDLE) high enter Idle
Flash Programmable 12-Bit Integrated Data-Acquisition Systems
mode after instruction complete. Figure shows related timing characteristics. Enable interrupt clear PCON.0 exit Idle mode (See Figure related timing). Assert alternately. Stop Mode stop mode, internal clock analog circuitry powered-down. PCON.1 (STOP) HIGH enter Stop mode after instruction complete. Figure shows related timing characteristics. only exit Stop mode assert RST.
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity deviation values actual transfer function from straight line. This straight line either best straight-line line drawn between endpoints transfer function, once offset gain errors have been nullified. static linearity parameters MAX7651/MAX7652 measured using best straight-line method.
MAX7651/MAX7652
IDLE PCON.0
ADDR
-PSEN
Figure Idle Mode Entry Timing
INTO IDLE ~PSEN ADDR ADDRESS LAST EXECUTED INSTRUCTION 003H
Figure Idle Mode Exit Timing
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
CYCLE STOP PCON.1 ~PSEN ADDR
Figure Stop Mode Timing
Differential Nonlinearity (DNL)
Differential nonlinearity difference between actual step width ideal value 1LSB. error specification less than 1LSB guarantees missing codes monotonic transfer function.
SINAD (dB) (SignalRMS NoiseRMS)
Effective Number Bits (ENOB)
ENOB indicates global accuracy specific input frequency sampling rate. ideal ADCs error consists quantization noise only. With input range equal full-scale range ADC, calculate effective number bits follows: ENOB (SINAD 1.76) 6.02
Offset Error
offset error difference between ideal actual offset points. ADC, offset point midstep value when digital output zero.
Gain Error
gain full-scale error difference between ideal actual gain points transfer function, after offset error been canceled out. gain point midstep value when digital output full-scale.
Total Harmonic Distortion (THD)
ratio first five harmonics input signal fundamental itself. This expressed
Signal-To-Noise Ratio (SNR)
waveform perfectly reconstructed from digital samples, ratio full-scale analog input (RMS value) quantization error (residual error). ideal theoretical minimum analog-to-digital noise caused quantization error only results directly from ADCs resolution Bits): (6.02 1.76)dB reality, there other noise sources besides quantization noise including thermal noise, reference noise, clock jitter. Therefore, computed taking ratio signal noise which includes spectral components minus fundamental, first five harmonics, offset.
where fundamental amplitude, through amplitudes 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR ratio amplitude fundamental maximum signal component value next largest distortion component.
Chip Information
TRANSISTOR COUNT: 358,000 PROCESS: CMOS
Signal-To-Noise Plus Distortion (SINAD)
Signal-To-Noise Plus Distortion ratio fundamental input frequency's amplitude equivalent other output signals.
Flash Programmable 12-Bit Integrated Data-Acquisition Systems
Configuration
P1.0/T2/T2OUT/AD0
MAX7651/MAX7652
P1.3/TXD1/AD3
P1.2/RXD1/AD2
VIEW
P1.7/AD7 P1.6/AD6 P1.5/AD5 P1.4/AD4 EA/VPP ACOM XTAL1 XTAL2 DGND DVDD TEST
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AVDD
P1.1/T2EX/AD1
P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0
AGND REF+ REF- PWMV PWMG PWMA PWMB
MAX7651 MAX7652
DVDD DGND ALE/PROG PSEN P2.7 P2.6 P2.5 P2.4/A12
INT0
INT1
A9/P2.1
A10/P2.2
RD/P3.7
WR/P3.6
RXD0/P3.0
READY/T0/P3.4
TXD0/P3.1
64-TQFP
A11/P2.3
T1/P3.5
A8/P2.0
DGND
DVDD
P3.3
P3.2
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Package Information
64L, 10x10x1.4 TQFP.EPS
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2001 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX

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