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2000 Technology, Inc. rights reserved. Technology, Inc. retains right make changes this product time, without notice. Products have minor variations this publication. assumes liability whatsoever, including infringement patent copyright, sale products. Technology logo registered trademarks Technology, Inc. Other brands names property their respective owners. Document Number: GEN-GEN-RH-P1 Printed USA, October 2000
Contents
Introduction About this Handbook. General Information about Reliability Programs General Information about Test Programs. Reliability Monitoring Lead Scan. Packing/Shipping Monitor Electrical Test Characterization. Environmental Testing. Burn-in High Temperature Operating Life (HTOL). Temperature Cycle Autoclave 85°C/85% (Relative Humidity/Temperature) Highly Accelerated Stress Test (HAST) High Temperature Storage Moisture Induced Stress Testing. Salt Atmosphere Acceleration Stress Factors
3.10
Mechanical Testing Lead Integrity Bond Strength (Destructive Bond Pull Test) Shear Strength Solderability Testing. General Information Solder Solder Reflow Methods Electrical Testing.
Latch-Up Testing. Electrostatic Discharge Testing Production Testing 5.3.1 Contact Test 5.3.1.1 Continuity Test 5.3.1.2 Functional Continuity Test 5.3.2 Gross IDD. 5.3.3 Gross Functional. 5.3.4 Static 5.3.5 VIL/VIH
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Contents
5.3.6 VOL/VOH 5.3.7 Leakage Test (IIL/IIH). Device Characterization. 5.4.1 Parameters 5-10 5.4.1.1 Setup Time 5-10 5.4.1.2 Data Hold Time 5-10 5.4.1.3 Output Delay Time 5-10 5.4.2 Level Conditions During Characterization 5-11 5.4.3 Characterization Temperatures 5-11 5.4.4 High Speed Digital Testers. 5-11 Failure Analysis. Failure Mechanisms Failure Probabilities Rates. General Product Information.
Fabrication Process Technology Device Packaging Terminology Device Packaging Configurations. Device Packaging Diagrams. Part Number Definitions. 7.5.1.1 Current Part Number Labeling Method. 7.5.1.2 Former Part Number Labeling Method Device Class Types Tray Types. References.
Appendix Definition Terms .A-1
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Figures
Figure 1-1. Reliability Testing Structural Chart. Figure 2-1. Monitoring Program Flow Diagram Figure 3-1. Temperature Acceleration Factor Temperature. Figure 3-2. Stress Voltage Acceleration Factor Voltage Figure 4-1. Application Applied Force Shear Strength Testing Figure 4-2. Infrared Reflow Temperature Profile. Figure 4-3. Vapor Phase Reflow Temperature Profile Figure 5-1. Human Body Model, Test Circuit. Figure Charge Device Model, Test Circuit. Figure 5-3. Continuity Test Circuit Input Pins. Figure 5-4. Continuity Test Circuit Output Pins. Figure 5-5. Leakage Test Circuit. Figure 5-6. Production Test Flow Figure 5-7. Timing Characteristics Diagram. 5-10 Figure 6-1. Failure Curve Semiconductors Figure 7-1. PQFP Packaging, Cross Sectional Figure 7-2. PBGA Packaging, Cross Sectional
Tables
Table 3-1. Environmental Test Parameters Table 6-1. Calculated Rate Current Products Table 7-1. Device Process Technology Table 7-2. Packaging Configuration. Table 7-3. Tray Loading
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Introduction
About this Handbook
Technology Reliability Test Handbook provides customers with understanding various measures used Technology ensure high quality product. Technology high degree confidence product that delivers customers. This handbook will into some detail about various reliability practices undertaken Technology. General Information about Reliability Programs
When manufacturing integrated circuits, reliability refers probability that circuit will satisfactorily perform intended function, under specific operating conditions, given time period. responsibility Technology's Quality/Reliability Engineering Department calculate measure probability product's successful operation. reliability engineers simulate environmental conditions, well develop testing methods that accelerate aging process circuit. simulation testing methods calculate reasonable results lifetime behavior analysis device. collection statistical data from various tests plays important role providing solid foundation failure analysis. this data that provides basis improvements needed) currently implemented processes that impact high quality product. There several types testing methods analyze integrity product. scope reliability program extends from external structure device internal circuitry. Areas such quality encapsulate packaging lead frames, internal bond wire interfaces, metal-line electromigration just some items monitored. reliability tests designed examine quality fabrication assembly processes ASIC products. reliability program roughly partitioned into three testing phases: Mechanical, Environmental Electrical. Mechanical testing involves testing mechanical integrity product's packaging, including wire bond attachments, termination integrity solderability, just name few. Environmental testing places devices under stressful conditions that accelerate so-called "life" device order provide reasonable data calculate failure rates other important reliability characteristics. Finally, electrical testing used verify product intended-operating environment. Testing programs developed characterizing specifications, timing characteristics that device must operate under. Figure shows various tests used reliability program.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Introduction
General Information about Test Programs
Reliability Testing
Environmental Testing Burn-In HTOL Temp. Cycle HAST Hight Temp. Storage 85°C/85% Autoclave Moisture Test Salt Atmosphere
Mechanical Testing
Electrical Testing
Bond Strength Shear Lead Integrity Solderability Salt Atmosphere
Latch-up Production Testing Characterization
Figure 1-1. Reliability Testing Structural Chart
General Information about Test Programs
Testing defined procedure which performance product measured under various conditions. Technology, responsibility Test Engineering Department develop production test programs characterization programs that effectively test device either normal operating conditions, worstcase operating conditions. measured results these tests then analyzed verify stability quality fabrication process.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Reliability Monitoring
Technology implemented internal monitoring program monitor finished product, shipped from subcontractors. system been place designed monitor quality reliability incoming product. monitors described detail below. Lead Scan
Technology performs lead scan testing monthly basis purpose monitoring quality package leads. Packaging leads scanned with laser scanning machines determine dimension measurements conform purposed packaging specification. Those that pass laser scan test documented sent reconditioning (pin correction). After device been reconditioned, that device re-tested. documentation relation lead scan test kept file closely monitored. addition routing cards provided lead scan service vendor, data kept containing relevant information from each months' monitor. Packing/Shipping Monitor
Internal monitoring performed, bi-monthly basis verify that shipping packaging procedures being followed accordance established internal specification. Randomly chosen packages opened inside properly controlled environment. Visual inspections performed noting items such damage, device placement trays, uniform device orientation, accurate shipping count. addition internal device inspections, external labeling packaging conformance monitored. discrepancies found noted recorded into inspection log. Quality Engineering Operations departments notified discrepancies. After inspections have been completed, proper actions taken correct noted discrepancies. Electrical Test
Electrical testing performed fixed sample size each month. This test performed with purpose monitoring conformance production product electrical functional parameters. sample size chosen test reflective most common individually packaged bundle size parts stock. parts used this test from Finished Goods Inventory (FGI). This gives some reference determining quality parts that being shipped customers. Industry standard Automated Test Equipment (ATE) testers used production test programs sampled devices. Numerous device parameters such current leakage, functional performance, VOL/VOH, measured verify overall performance each device. devices tested monthly monitoring program tested room temperature. Those devices that pass electrical testing placed back into stock while those that pass scrapped. test results kept file addition data that used recording important information about test. Subcontractors notified failures.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Reliability Monitoring
Characterization
Characterization
Device characterization performed specified number devices quarterly basis. Periodic characterization used method verifying stability quality device fabrication process, assembly process, other process controls. Figure 2-1, below, illustrates monitoring program flow.
Finished Goods Inventory (FGI)
Pack/Ship Monitor
Mechanical (Lead Scan)
Electrical Test
Characterization
Fail Pass Pass
Fail Pass
Fail Results
Inspection
Data Traveler/ Lead Scan
Electrical Test log/ record file
Characterization Record file/ Characterization
Figure 2-1. Monitoring Program Flow Diagram
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Environmental Testing
Burn-in Burn-in testing performed screening marginal devices. During manufacturing process, certain number devices will built with defects other shortcomings. Burn-in testing useful screening "infant mortality" failures. These failures occur early stages products lifetime manufacturing defects. Burn-in testing places devices high stress environment. stress conditions that applied devices during burn-in effective method aging devices. particular, burn-in testing used check internal metal migration metal expansion that effect device operation. Devices placed burn-in boards. Burn-in boards built from high temperature tolerant material that withstand constant temperature exposures 150°C. boards then placed into burn-in chambers. voltage bias higher than nominal voltage level applied devices order additional stress during this test. test performed 125°C hours. burn-in method used Technology referred dynamic burn-in. this method numerous driver/receiver boards generate vector patterns. vectors generated dynamic data stream patterns that keep signals switching high that maximum number internal nodes will exercised. Devices electrically tested prior entering burn-in ovens, also tested while burn-in process taking place. Once burn-in complete, devices submitted production testing verify functionality. Technology believes that three levels testing necessary order provide accurate assessment test failures. Failure mechanisms result burn-in test contamination, oxidation defects, metal line electromigration, refresh degradation silicon defects. High Temperature Operating Life (HTOL)
Technology performs HTOL testing monitor effects bias conditions high temperatures solid-state devices over extended period time. High Temperature Operating Life testing conducted 125°C with applied voltage bias higher than nominal voltage level. test duration 1000 hours. Test parameters, such time and/or temperature, altered order accelerate test. Intermediate measurements, using standard production test program, made devices 168, hours into test. Failures generated monitored analyzed long-term stress effects that products expected undergo. Metal electromigration, oxidation, other common high temperature voltage stress related failures noted test failures.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Environmental Testing
Autoclave
Temperature Cycle
Temperature cycle testing used method determining device's resistance high temperature extremes. This test exposes device packaging mechanical fatigue induced thermal expansion. Technology uses conditions this test stress attachments between bonding pads surface, well interface between surrounding solder attachment package. test results used reliability analysis assembly process. Before devices subjected temperature cycle testing, electrical testing performed check noticeable electrical problems. temperature cycle test involves placement device such that resistance airflow minimal. Devices cycled specified periods time (T_cyc minutes) between high temperatures +150°C (+15°C/-0°C), temperatures -65°C (+0°C/-10°C). typically runs 2-to-3 cycles hour during temperature cycle testing. temperature ranges used during test accordance with MIL-STD-883. test performed cycles within those specified temperature conditions. Once cycles completed, devices undergo another electrical test within hours, using standard production test program that device. Failure criteria consist physical defects die, packaging, leads, marking, provided damage caused result test itself. Post electrical testing performed conclusion Temperature Cycle Test. Autoclave
Autoclave test (also referred Pressure Pot) performed simulate highpressure environments. These high-pressure environments used determine whether device withstand high amounts thrust. test conducted 121°C, 100% Relative Humidity (RH) (atmospheres) pressure. Devices subjected this test left chambers hours. Standard production electrical testing performed devices once hours have been completed. Potential failures resulting from test might include device packaging implosion explosion. other physical defects resulting from this test considered test failures.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Highly Accelerated Stress Test (HAST)
Section Environmental Testing
85°C/85% (Relative Humidity/Temperature)
85°C/85% test method simulating potential storage conditions device. This test performed purpose evaluating reliability non-hermetic packaged device humid environment elevated temperature. main aspect this test place biased microcircuits environment 85°C relative humidity period 1000 hours. voltage applied accelerate stress levels. After 1000 hours, devices electrically tested verify functionality. Devices that cannot demonstrate full functionality electrical testing considered test failures. other mechanical failures physical defects resulting from this test shall also considered test failures. Highly Accelerated Stress Test (HAST)
HAST performed purpose evaluating reliability non-hermetic packaged solid-state device humid environments. extreme conditions used this test accelerate penetration external moisture through encapsulate packaging itself, through interface leads encapsulate package. Once equilibrium reached within test, results equivalent 1000 85°C/85% testing. This equivalency added stress provided increase temperature. HAST chambers must preconditioned specific humidity temperature conditions specified duration time. This preconditioning must completed prior placing HAST boards into test chambers. HAST testing performed 130°C relative humidity with voltage bias applied devices. bias typically higher than normal operating level provide high amount stress those devices. Devices placed into HAST chambers hours. After test completed, HAST boards removed from heating chambers allowed hour minimum, hour maximum. conclusion test, devices electrically tested verify continued functionality. Devices that cannot pass electrical testing also considered failures. Additionally, parts containing corrosion cracking also considered failures.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Environmental Testing
Moisture Induced Stress Testing
High Temperature Storage
High Temperature Storage performed evaluate effects high temperature storage conditions with electrical stress applied devices. This test used simulate potential storage conditions devices. test accomplished placing previously tested devices into temperature chamber, heating chamber temperature 150°C with uninterrupted exposure time 1000 hours. After 1000 hrs, devices electrically tested verify continued functionality. device does pass, considered failure. Other failure criteria shall include mechanical damage such packaging cracks. Moisture Induced Stress Testing
This test performed determine moisture level classification plastic surface mount devices (SMD) that they properly packaged, stored, handled order avoid various types mechanical damage. Mechanical damage incurred during assembly and/or solder reflow attachment process. This test used determine moisture class level device. Plastic encapsulates made moisture permeable materials. Moisture that inside packaging turns into steam expands, when devices exposed high temperature during vapor phase reflow infrared reflow processes. Moisture expansion cause internal delamination plastic from chip, leadframe, numerous other mechanical defects internal packaging. therefore necessary determine classify device's moisture sensitivity level. Moisture classification indication important package characteristics. First, indicates long device exposed moisture before device needs baked. Secondly, classifies amount baking time needed bring device back original state (dry) once that device reached moisture saturation. Moisture sensitivity testing performed first performing standard electrical test; therefore, verifying that devices fully functional. After functionality been verified, visual acoustic microscope inspections performed establish delamination criteria. devices then baked remove moisture from devices that they considered "dry". Devices then placed temperature/humidity chambers according specific soak requirements (level devices 30°C/60% hours). Once devices have been removed from chambers, they allowed specified amount time minutes tdry hours). After specified time, devices submitted cycles either vapor phase reflow reflow. reflow cycles have specific requirements rampup ramp-down heating rates, maximum temperatures. After reflow process, devices again inspected under microscope external cracking. Electrical testing once again performed verify continued device functionality. test requirements used Technology based moisture class levels.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Moisture Induced Stress Testing
Section Environmental Testing
Further analysis performed weight gain weight loss device. Devices weighed before after moisture testing. gain weight moisture absorption. Analysis this weight gain used determine floor life device. floor life refers amount time device removed from pack until sufficient amounts moisture absorbed place device risk during reflow process. weight loss desorption moisture provide useful information about baking time needed remove moisture from device. Failure criteria moisture test include external and/or internal cracks, room temperature electrical test failures. External cracking might include cracks packaging, while internal cracking occur bond wire/bond ball intersections, well leads, die, cracks from internal feature outside package. general summary environmental test parameters represented below Table 3-1. Table 3-1. Environmental Test Parameters Stress Test Burn-in HTOL Temperature Cycle Autoclave (Pressure Pot) 85°C/85 HAST Method MIL-STD-883, 1015 MIL-STD-883, 2003 MIL-STD-883, 1010.7 JESD22-A102-B Condition JESD-A101-A MIL-STD-883, 1003 JESD-A110-B Condition Duration
125°C, voltage bias, Dynamic data hours patterns 125°C, voltage bias From +150°C cycles/hour 121°C, 100% 85°C, voltage bias 130°C, voltage bias 150°C, voltage bias Class 30°C/60% Condition 35°C 1000 hours cycles hours 1000 hours hours 1000 hours hours hours
High Temperature JESD-A103-A Storage Moisture JEDEC J-STDInduced Stress 020A Test Salt Atmosphere MIL-STD-883, 1009
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Environmental Testing
Acceleration Stress Factors
Salt Atmosphere
Technology performs Salt Atmosphere test accelerated corrosion test. This test useful determining affects seacoast atmospheric conditions device packaging. salt solution composed de-ionized water sodium chloride, with between 6.5-7.2, used provide salt fog. special mounting fixture used hold devices such that contact made between adjacent devices and, that devices shield each other from exposure. devices placed into temperature chamber which devices submitted hours salt temperature 35°C. salt concentration velocity passage controlled test parameters, specified MIL-STD 883, Method 1009, Condition Inspections performed using magnification conclusion test. Failure criteria Salt Atmosphere testing includes corrosion defects exceed percent total surface area, flaking blistering. Additionally, blurs, fading missing mark also inspected. 3.10 Acceleration Stress Factors
Environmental testing makes high temperatures high voltage biases method stressing devices. testing temperature applied voltage have defined relation with amount stress added device. Both accelerating stress factors cause degrading device. burn-in temperatures' relation amount stress accrued device given following relationship: (NOTE: Acceleration factor applied temperature) AT(T) (Ea/k)(1/T0 1/Ts)
Boltzmann's constant (8.617x10-5 eV/K) Activation Energy (eV) normal operation temperature (Kelvin) stress temperature (Kelvin)
This relationship, taken from Arrhenius' equation, describes acceleration effects high stress temperature ranges. This relationship represented Figure 3-1, plot temperature acceleration factor temperature different levels activation energies. Temperature stress accelerate contamination defects metal electromigration.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Acceleration Stress Factors
Section Environmental Testing
100000 10000 Acceleration Factor (Relative Degrees 0.75
1000
Temperature Degrees
Figure 3-1. Temperature Acceleration Factor Temperature
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Environmental Testing
Acceleration Stress Factors
applied voltage used stress device related acceleration factor relationship: (NOTE: Acceleration factor applied voltage) AV(V)
constant derived experimentally normal applied voltage level stress level voltage
Typically, this voltage-stress relationship commonly used accelerating oxidation defects insulator breakdown. Oxide defects usually accelerated electric field strength. Figure 3-2, shows relationship voltage acceleration voltage stress, relative various experimentally derived beta values.
10000000 Beta Acceleration Factor (Relative 1000000 Beta 100000
10000 Beta 1000
7.25
5.25
5.75
6.75
7.75
6.25
8.25
8.75
Voltage
Figure 3-2. Stress Voltage Acceleration Factor Voltage
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Mechanical Testing
Lead Integrity Lead integrity testing useful determining integrity quality device leads, seals, welds. Various tests performed based criteria specified MILSTD-883, Method 2004.5. Lead bending type testing used determining lead integrity. Bending stress useful determining capability device leads, lead finish, seals withstand numerous stresses that expected occur actual handling assembly device. Technology requires that specified number random sampled PQFP devices have each individual leads bent angle then back original position. This process repeated second time. Once devices have been subjected this test, they inspected under magnification. Failure criteria this test include breakage, cracking, loosening, relative motion between lead device body. Another type testing used determining lead integrity tension test. Tension testing useful determining capability lead withstand straight pull. this test, force apparatus used pull each lead with force 2.5N timed duration seconds. devices inspected under magnification failure criteria similar those used bending stress test. Bond Strength (Destructive Bond Pull Test)
Destructive bond pull testing performed order determine bond strength magnitudes distributions, well determine compliance with bond strength specifications. Bond pull applied numerous bonding interfaces such wireto-die, wire-to-package lead, wire-to-substrate bonds. wire composition, wire diameters, bonding process itself used determining wire bond strengths. test condition used within Technology destructive bond strength testing MIL-STD-883, Method 2011.7 condition This particular method, which commonly referred wire pull, employed internal bonds substrate lead frame. Stress applied both interfaces bond wire simultaneously, wire-to-die wire-to-leadframe. This test involves insertion hook bond wire centered between leadframe. Applying force direction normal bond wires path stresses both interface attachments. amount force applied wire dependent composition diameter bond wire. Typical applied force ranges between 1.5-15.0 gram force. force applied until wire snaps bonds lift. criteria failure from this test bond lifting (failed bonds) either interface, lifted metallization from substrate, fracture substrate.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Mechanical Testing
Shear Strength
Shear Strength
Testing shear strength important determining integrity materials procedures used attaching packaging substrate. amount force needed separate from substrate depends size specified MIL-STD-883, Method 2019.5. contact tool used apply force die/substrate interface from sides die. tool then rotated make angle with substrate apply third force interface. contact tool used approximately same width being tested. This provides even distribution force along edge die. Figure demonstrates application applied force shear strength testing. Failure criteria shear testing are: separation with less than 1.25 times minimum amount force required, evidence less than left attach adhesive less than times minimum force with less than left attach adhesive.
View
Contact Tool
View
Contact Tool
Side View
Contact Tool
degree angle
Figure 4-1. Application Applied Force Shear Strength Testing
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
General Information Solder Solder Reflow Methods
Section Mechanical Testing
Solderability Testing
Typically, solderability testing performed order verify solderability device package terminations, which intended joined another surface using solder attachment. test designed answer question, "Will solder properly attach onto device leads?" Technology realizes that testing solderability useful identifying various problems before devices used solder reflow process. test solderability, terminations device held clamp force sensor. Prior solder submersion, device terminations dipped into specified type solder flux. device then immersed with terminations being perpendicular with solder, specified rate until terminations submerged. solder should least away from device package. solder contains least lbs. (4.4 molten solder 245°C. termination left there seconds then emmersed from solder specified rate. flux will then begin activate clean lead's surface, force pushing against lead will then reduced. force reduction recorded measured that data later compared results known "good" device. After test been completed, dipped portion termination manually examined using microscope. There several failure mechanisms when testing solderability. common failure type observed non-coverage total submersed surface area. dipped portion termination should less than percent covered with continuous solder coating. Some other common failure criteria non-wetting, dewetting, pinholes voids. lack solder certain areas referred nonwetting. Non-wetting typically degradation composite alloy layer around device terminations. that surrounding alloy that provides attachment solder lead terminations. De-wetting condition where molten solder coated surface receded leaving irregular shaped mounds solder. Voids pinholes refer imperfections that penetrate entirely through solder layer. General Information Solder Solder Reflow Methods
Reflow refers liquidus state solder. When solder this liquidus state, used attach devices onto printed circuit board (PCB). most common solder alloy used electronics tin/lead composite referred Sn63Pb37. This notation refers alloy's composition lead. This composition ratio chosen order reduce melting point solder down 183°C (Note: melting point (Sn) 232°C, melting point Lead (Pb) 327°C). There popular methods used bring solder liquidus state. method called Infrared reflow. Infrared (IR) reflow particular refers heating mechanism (infrared radiation) used bring solder paste liquidus state. advantage using infrared radiation reflow that well controlled. disadvantage using this method that when device direct exposure light only heats exposed area. area that shaded, such solder joint, does heat well. other method used bring solder liquidus state vapor phase. Vapor phase heats inactive solvent produce vapor through which passes through
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Mechanical Testing
General Information Solder Solder Reflow Methods
soldering. benefit vapor phase reflow that temperature maintained uniformly. risk oxidation contamination minimized inactive solvent. specific heating cooling times rates vapor phase reflow processes shown Figures respectively.
Peak Solder Liquidus (183 Temperature (degrees Wetting Time Preheat Soak Reflow Cooling C/sec C/sec within sec. C/sec
over sec.
within sec.
Time (seconds)
Figure 4-2. Infrared Reflow Temperature Profile
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
General Information Solder Solder Reflow Methods
Section Mechanical Testing
Temperature (degrees Wetting Time Preheat Soak Reflow Cooling over sec. within sec. C/sec C/sec Solder Liquidus (183 Peak within sec. C/sec
Time (seconds)
Figure 4-3. Vapor Phase Reflow Temperature Profile
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Electrical Testing
Latch-Up Testing Latch-Up defined generation impedance pathway CMOS chips between power ground rails interaction parasitic bipolar transistor structures sometimes triggered because input, output, supply overvoltages. Those interactions essentially short power ground rails through positive feedback mechanism thus causing excessive current flows, which turn cause damage internal circuitry. Technology performs latch-up testing order determine susceptibility products' internal CMOS circuitry formation latch-up. This test particularly effective method determining susceptibility latch-up long determined that damage caused latch-up formation. instance, device's quiescent power supply current specification supply voltage "collapsed", device should examined electrically determine whether device damaged without latch-up formation. basic test sequence consists first applying power supply voltage. constraint that (power supply current) limited 100mA. Next, functional pattern order input/output into desired state. trigger source then applied specified period time (10µs ttrigger depending whether trigger source being applied manually automated tester. After trigger source been applied, supply current measured. test limit, power supply should removed that device inspected electrical damage. inspect electrical damage, device electrically tested with particular attention placed checking levels current leakage. magnitude trigger source level required initiate latch-up reference used determining susceptibility. Latch-up testing performed different temperature supply voltage ranges. Worse case conditions latch-up formation high temperature/high voltage lowest value trigger current measured. Electrostatic Discharge Testing
Electrostatic discharge testing performed method classifying circuit's susceptibility damage degradation caused transfer electrostatic charge between circuit another body (Human Body Model Charged Device Model) different potentials. Electrostatic discharge most common reasons chip failures during manufacturing field operations. discharge caused either contact bodies static induction. protection networks that built into circuitry devices designed filter effects before they damage internal logic circuitry. order test susceptibility, various models have been designed simulate human-circuit interactions machine-circuit interactions. Human Body Model, commonly referred HBM, used simulate build static charge that occur human beings during everyday situations (i.e. walking synthetic carpet). MIL-STD-883, Method 3015, provides specification testing susceptibility.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Electrical Testing
Electrostatic Discharge Testing
devices classified withstand static voltage stresses greater than therefore classified class devices. test, which considered destructive test, performed room temperature. basic form test charging 100pF capacitor specified voltage level. Once capacitor charged high voltage relay connects charged capacitor circuit containing DUT. Once capacitor connected test circuit, discharges through resistor into DUT. After test performed, verified production electrical testing. test repeated increased voltage levels until failure verified electrical testing.
VESD
Figure 5-1. Human Body Model, Test Circuit Another model that used Charged Device Model. This model simulates discharge packaged integrated circuits. Devices accumulate charge during assembly process and/or shipping process. Charged device testing involves charging device through resistor, disconnecting charging supply discharging device ground. After testing Charged Device Model, electrical testing performed devices verify that damage caused test. Figure shows schematic Charged Device Model testing.
Discharging Probe
Charging Source
Figure Charge Device Model, Test Circuit
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Production Testing
Section Electrical Testing
Production Testing
order perform necessary electrical testing that production parts should subjected standard production test program been developed verify intended device requirements characteristics. Production testing involves testing numerous parameters well testing functional operability device. following describes detail various elements within production test flow. 5.3.1 Contact Test This test identifies whether contact made device's signal pins, well checking signal shorts. 5.3.1.1 Continuity Test supplied while this test running, pins tied ground. Current forced each pin, time using PMU, through protection diodes, then voltage drop across diodes measured. Forcing current 100µA protection diode that connected VDD, -100µA protection diode connected ground will forward bias each respective diode. Once diodes forward biased, voltage drops measured should result 0.7V each respective diode. measured voltage drop greater than parameter (usually voltage 1.2V) would indicate open circuit. Measured voltage drops levels less than equal 0.2V indicate short circuit. Figure Figure depict exactly what being tested during continuity testing.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Electrical Testing
Production Testing
Protection Diode P-Channel
Positive current flow from test system
Input
Signal
Internal Logic
Negative current flow from test system Channel Protection Diode
Measured Voltage Drop 0.7V 0.2V Connection Short Open
1.2V
Figure 5-3. Continuity Test Circuit Input Pins
Parasitic N-well Diode P-Channel
Positive current flow from test system
Output Signal
Internal Logic
Negative current flow from test system
Channel Parasitic P-substrate Diode
Measured Voltage Drop 0.7V 0.2V Connection Short Open
1.2V
Figure 5-4. Continuity Test Circuit Output Pins
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Production Testing
Section Electrical Testing
5.3.1.2 Functional Continuity Test This method testing protection diodes involves supplying with running preconditioning vector pattern. outputs tri-state mode. vector pattern will usually drive input pins ground, float each time, measuring diode voltage each output. output measured tristated, will pass. output measures low, shorted. output measures high, open. 5.3.2 Gross Gross test typically used check lines unacceptably large amounts current determine range supply current that device draws. supplied during this test. inputs either high low, switching circuits active. tester will then measure current flowing through lines into device. amount current less than specified amount (usually gross depending device), will pass. 5.3.3 Gross Functional This test used verify that accomplish necessary logical functions that intended perform. Gross functional testing usually performed lower speeds (1-10 MHz). This done because speed concern this point test flow, only device's functionality. Various test vectors verify that internal logic components working properly. Functional testing three different levels VDD, which reflective particular device's supply voltage level tolerance values. During gross functional test, VOL/VOH/VIL/VIH margins measured loosely. Later tests involve more restricted conditions noise margin. pass gross functional test, device must produce expected logical outputs corresponding input vector patterns that test system. 5.3.4 Static This test implemented measure current leakage during static conditions after device previously active switching circuits. Static test usually conducted after gross functional testing. specific test vector thus preconditioning device preferred state. Once that preferred state, vector pattern terminated leaving device static condition. This condition considered stand-by mode. signals pulled their inactive levels. this state, draws least amount IDD. Once test pattern stopped device held static specified amount time, currents flowing into pins measured. measured current below specified amount device will pass. sub-test that falls within this test description that IDDQ. IDDQ useful testing fabrication defects determining exactly which area chip high static current. IDDQ measurement static current within specific area chip. static current level specific circuit block known, that current
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Electrical Testing
Production Testing
measured compared with expected results. This method provides effective narrowing down possible regions erroneous operation, well determining bridging faults. 5.3.5 VIL/VIH VIL/VIH test test designed check noise margins inputs pins. test involves toggling output signals while sending input signal. input correctly viewed high low, depending anticipated input, will pass. noise generated toggling outputs interferes with proper interpretation signal, then will output incorrect response input, thus resulting test failure. 5.3.6 VOL/VOH purpose VOL/VOH test verify levels that being produced output pins, within proper ranges interpret signal logic-0 logic-1. method measuring VOL/VOH static method. this method, measure tester sinks specified amount current into each output pins, measures voltage that pin. measurements Compatible CMOS devices should typically less than 400mV. measure VOH, output sources specified amount current voltage that measured PMU. measurements should greater that 2.4V. Another method testing VOL/VOH functional test. This test accomplished re-running test vectors used during gross functional test, except that this circumstance noise margins outputs with more restricted level specifications. comparator with preset levels used check output values. test vectors used this test should test outputs both high levels. 5.3.7 Leakage Test (IIL/IIH) current leakage test used monitor amount current that leaks from line input line input line line device input pins. test performed only input pins. measure current leakage across p-channel transistor (IIL), input voltage needs high that p-type transistor turnedoff. drivers force inputs high (logic-1), then individually force each time. Once input been toggled low, current measured between input line line. This value should less than -10µA. measure current leakage across n-channel transistor (IIH), input voltage needs low. This sets n-channel transistor into "turned-off" state. Once input voltages driven low, each input toggled high individually. Current then measured between input ground lines. amount current measured depends numerous factors. instance, standard input like shown Figure will have leakage current range +/-10µA. input with pull-up pulldown resistor will have different level leakage current than standard input pin.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Production Testing
Section Electrical Testing
When low, measure leakage current across P-channel transistor
-10uA
P-Channel
Vout
10uA
Channel
When high, measure leakage current across N-channel transistor
Figure 5-5. Leakage Test Circuit
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Electrical Testing
Production Testing
production test flow represented Figure 5-6.
Start Test
Continuity/ Open-Shorts
Gross
Gross Functional
Static
VIL/VIH
VOL/VOH
Leakage Test
Good Part/
Figure 5-6. Production Test Flow
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Device Characterization
Section Electrical Testing
Device Characterization
What characterization? Technology uses device characterization method determining verifying specific information about performance characteristics product. Typically, high-speed CMOS designs need verified make sure that strict timing requirements met. Characterization validation specified timing level requirements given circuit. Once physical piece silicon produced, characterization performed verify that device meet worst-case timing requirements under given level parameter constraints. characterize device? Verify fabrication process. main benefits device characterization capability verifying fabrication process. information collected during characterization closely monitored significant changes. example drastic aspects device timing change significantly, steps taken make certain that fabrication process changed. Verify that device meets design specifications. Characterization data collected compared design specifications. Verifying input timing parameters such set-up time data-hold time useful determining speed device signaling. smallest amount time that input signal needs communicate data, faster that signal return perform other tasks. detailed description both input timing parameters will discussed following section. Characterizing delay timing output signals another important aspect device characterization. This information useful determining response time output signal.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Electrical Testing
Device Characterization
5.4.1 Parameters There three main timing parameters evaluated during characterization: setup time, data hold time output delay. Figure illustrates relationship between those signals with reference clock signal. 5.4.1.1 Setup Time purpose characterizing set-up time input signal check that device meet worst case (maximum) time signal needs setup before referencing clock edge switches high low. Setup time defined amount time signal needs into valid state before referenced clock reaches certain voltage level (typically 1.5V). prepare testing this parameter, setup defining appropriate timing values signal formats required timing specifications particular device. functional test vectors then order exercise necessary logical functions that appropriate measurements setup timing parameters then made. 5.4.1.2 Data Hold Time Characterizing this parameter useful identifying maximum amount time that input signal must hold onto data after referenced clock edge. Data hold time measured when referencing clock reaches certain voltage level (typically 1.5V). Data hold time verified meeting worst-case condition (maximum hold time). setup this test similar setup timing parameter test. Typically, parameters tested same time. 5.4.1.3 Output Delay Time Output delay timing measured order identify amount time between transition signal resulting transition another signal. amount delay large than timing system off. Output delay formally defined time takes output become valid after triggering edge referenced signal (triggering clock edge). After appropriate signal formats timing edges have been setup, test strobe programmed check valid levels time during tester cycle.
T_cyc
T_setup T_hold
INPUT
T_valid
OUTPUT
Valid Output
Valid Output
Valid Output
Valid Output
Parameter Set-Up Time Data Hold Time Output Delay Time
Symbol T_setup T_hold T_valid
Figure 5-7. Timing Characteristics Diagram
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
5-10
Device Characterization
Section Electrical Testing
5.4.2 Level Conditions During Characterization During characterization, input voltage levels controlled that worst-case levels determined. Input signals driven with VDD. determine maximum level, tester increments until incorrect output voltages produced. Minimum measured similar manner decreasing level until incorrect outputs produced. These settings used verify that signals being properly interpreted logic-0s logic-1s. same time, outputs have their high-Z state 1.5V. Anything greater than 1.5V will interpreted high anything less than 1.5V limit considered low. These settings used outputs, that input levels have flexible noise margins. 5.4.3 Characterization Temperatures characterize different temperatures? devices characterized various temperature ranges check signal degradation. Signal timing will degrade with increase temperature; therefore, devices characterized different temperatures variation timing monitored. there significant change timing temperature changes, then fabrication assembly process become suspect. characterizes devices three different temperature ranges. temperature levels defined follows: Cold Temperature Test: 0°C, -40°C Room Temperature Test: 25°C Temperature Test (worst case): 85°C 5.4.4 High Speed Digital Testers High-speed digital testers used specifically production testing, device characterization troubleshooting.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
5-11
Failure Analysis
Failure Mechanisms
physical chemical process that causes device fail termed failure mechanism. Failure mechanisms usually placed into three categories, chip-related failures, assembly-related failures, miscellaneous application related failures. Some examples chip related failures metal line electromigration, diffusion-related failures, oxide defects. Assembly related failures might chip mounting, wire bonding, packaging failures such cracked deformed device packaging. Failure Probabilities
device failure device-operating hours defined Failure Time (FIT). Failure rates, expressed units FITs, traditionally defined
F(t) [(Number device failures) (Number operating devices Operating time)]
failure rate F(t) represents instantaneous rate device failure device surviving time rates indicate probability that device will fail within given amount time during so-called "useful life" device. "useful life" device falls between early stages products life (early failure period) time towards products life (wear period). graph hazard rate device gives rise popular "bathtub" curve, shown Figure 6-1. rates give good indication operational reliability devices. lower rates, number defects specified number devices (typically measured parts million) must reduced small number possible.
F(t)
Instantaneous Failure Rate
Early Failures
Random Failures
Wear Failures
time Early Failure Period Useful Life Wear Period
Figure 6-1. Failure Curve Semiconductors
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section Failure Analysis
Rates
Rates
Table 6-1. Calculated Rate Current Products Device 9030 9050 9052 9054 9060 (series) 9080 Rate FITS FITS FITS FITS FITS FITS
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
General Product Information
This section provides general information specific current production devices produced Technology. Fabrication Process Technology
current production devices Complementary Metal Oxide Semiconductor (CMOS) circuits. Table gives comparison process technology given device. process technology typically refers minimum feature size particular integrated circuit. Table 7-1. Device Process Technology Device 9030 9050 9052 9054 9060-3A 9060ES 9060SD 9080-3 Process Technology (µm) 0.35 0.60 0.50 0.35 0.60 0.60 0.60 0.50 0.35
Device Packaging Terminology
There various package types that used products. These packages are: PQFP Plastic Quad Flat Package PBGA Plastic Ball Grid Array LBGA Profile Ball Grid Array
µBGA µ-Ball Grid Array (Micro-BGA)
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section General Product Information
Device Packaging Configurations
Device Packaging Configurations
Table 7-2. Packaging Configuration Part number PCI9030AA60PI PCI9030AA60BI PCI9050-1 PCI9052 PCI9054AA50PI PCI9054AA50BI PCI9054AB50PI PCI9054AB50BI PCI9060 (series) PCI9080-3 IOP480-AA66PI IOP480-AA66BI Package Type PQFP Lead/Ball Count Packaging Dimensions (mm) Lead/Ball Pitch (mm) 0.65 0.65
µBGA
PQFP PQFP PQFP PBGA PQFP PBGA PQFP PQFP PQFP PBGA
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Device Packaging Diagrams
Section General Product Information
Device Packaging Diagrams
Figure Figure show relationship between chip and/or encapsulate packaging PQFP PBGA packaging technologies respectively. drawings used illustrative purposes only scale.
Mold Compound
Plastic Quad Flat Package Attach Adhesive
Gold wire Copper Lead frame
Attach
Solder Interface
Figure 7-1. PQFP Packaging, Cross Sectional
Mold Compound
Plastic Ball Grig Array
Attach Adhesive Copper Signal Trace
Gold Wire
Solder Mask
Ground Ring Sn63/Pb37 Solder Balls
Attach
Solder Interface
Power Ring
Figure 7-2. PBGA Packaging, Cross Sectional
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Section General Product Information
Device Class Types
Part Number Definitions
7.5.1.1 Current Part Number Labeling Method XXXX XXXX
Device Class (i.e. PCI9054-AB50PI) Part Number (i.e. PCI9054-AB50PI) Device Revision I.D. (i.e. PCI9054-AB50PI) Maximum Local Operating Frequency MHz) (i.e. PCI9054-AB50PI) Packaging Technology (i.e. PCI9054-AB50PI) PQFP PBGA µBGA Operational Temperature Range (i.e. PCI9054-AB50PI) Industrial (-40°C 85°C) 7.5.1.2 Former Part Number Labeling Method XXXX Device Class (i.e PCI9080- Part Number (i.e. PCI9080- Revision Number (i.e PCI9080-
Device Class Types
Accelerator Bridge Device Input/Output Processor GigaBridgePort Switch Fabric Controller
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Tray Types
Section General Product Information
Tray Types
production-shipping trays used Technology high temperature (150°C) bakable trays. Furthermore, tray types adhere JEDEC standards. device count tray depends device packaging configuration. various part counts tray broken down illustrated Table 7-3.
Table 7-3. Tray Loading Package Type 160- PQFP 176- PQFP 208- PQFP 180- ball µBGA 225- ball PBGA Parts Tray Parts Parts Column
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
References
Sung-Mo Kung, Yusuf Leblebici. CMOS Digital Integrated Circuits: Analysis Design. McGraw-Hill: Francisco, 1999. Glaser/Subak-Sharpe, Integrated Circuit Engineering. Addison-Wesley Publishing Reading: Massachusetts, 1977. JEDEC Solid State Technology Association, "Latch-up CMOS Integrated Circuits" JEDEC Standard No.17, August 1998. "High Temperature Storage Life", JESD22-A103-A, July 1989. "Temperature Cycling", JESD22-A104-A, December 1989. "Bias Life", JESD22-A108-A, March 1991. "Highly Accelerated Temperature Humidity Stress Test", JESD22-A110-B, February 1999. Electronic Industries Association (EIA), JEDEC Solid State Technology Association. "Steady State Temperature Humidity Bias Life Test", EIA/JESD22-A101-B, April 1997. "Solderability Test Method", EIA/JESD22-B102-C, September 1998. IPC/JEDEC Standards, "Moisture/Reflow Sensitivity Classification Non-Hermetic Solid State Surface Mount Devices", IPC/JEDEC J-STD-020-A, April 1999. United States. Department Defense. MIL- STD- 883, Military Standards Test Methods Procedures Microelectronics, Solder Reflow Technology Handbook. Research International, Online, www.researchintl.com. Internet. 2000. Perry, Guy. Basic Test Technology, Rev. 1.2, Soft Test, Inc., Jose, 1994. "How Construct Highly Accurate SPICE Model Signal Integrity Simulation High Speed Ball Grid Array Burn-In Test Socket," Company, Tech Paper, #80-6106-0858-2, 1994. "Monitored Burn-in, Overview," Micro Control Company, Test Application Series, Publication# 990046, 1980.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Appendix Definition Terms
Input Pin: device that acts buffer between external signals internal logic. Output Pin: device that acts buffer between internal logic external signals. output provides IOL/IOH current. Positive current flow: current flowing from external environment device. Negative current flow: current flowing from device external environment. Tri-State Output: device output that capability going into high impedance state (high-Z state). PMU: precision measuring unit capable making accurate measurements either forcing voltage measuring current, forcing current measuring voltage. DUT: device under test. (Voltage input low): voltage value applied input when applying logic-0. maximum voltage value that applied still recognized logic-0. (Voltage input high): voltage value applied input when applying logic1. minimum voltage value that applied still recognized logic-1. (Voltage output low): voltage value produced output when driving logic-0. maximum value produced output when producing logic-0. (Voltage output high): voltage value produced output when driving logic-1. minimum value produced output when producing logic-1. (Current output low): amount current that flows from tester through output pins ground, "sink current", when output logic-0. output must supply specified amount current while maintaining correct voltage. (Current output high): amount current that must flow from device test system, "source current", while driving logic-1. output must supply specified amount current while maintaining correct voltage.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
Appendix Definition Terms
(Low input leakage current): maximum current allowed flow input when voltage forced onto pin. (High input leakage current): maximum current allowed flow input when high voltage forced onto pin. VDD: supply voltage device. IDD: supply current device.
Reliability Test Handbook 2000 Technology, Inc. rights reserved.
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