3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) Digitally programma
|
|
|
Top Searches for this datasheet
PDU13F
3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F)
Digitally programmable delay steps Monotonic delay-versus-address variation separate outputs: inverting non-inverting Precise stable delays Input outputs fully interfaced buffered fan-out capability Fits standard 14-pin socket Auto-insertable
OUT/
data delay devices, inc.
PACKAGES
OUT/
PDU13F-xx PDU13F-xxA2 PDU13F-xxB2 PDU13F-xxM
Gull-Wing J-Lead Military
PDU13F-xxMC3 Military Gull-Wing
FUNCTIONAL DESCRIPTION
PDU13F-series device 3-bit digitally programmable delay line. delay, TDA, from input (IN) output pins (OUT, OUT/) depends address code (A2-A0) according following formula: TINC
DESCRIPTIONS
OUT/ Delay Line Input Non-inverted Output Inverted Output Address Address Address Output Enable Volts Ground
where address code, TINC incremental delay device, inherent delay device. incremental delay specified dash number device range from 0.5ns through 50ns, inclusively. enable (EN/) held during normal operation. When this signal brought HIGH, OUT/ forced into HIGH states, respectively. address latched must remain asserted during normal operation.
SERIES SPECIFICATIONS
Total programmed delay tolerance: 1ns, whichever greater Inherent delay (TD0): typical (OUT) 5.5ns typical (OUT/) Setup time propagation delay: Address input setup (TAIS): Disable output delay (TDISO): typ. (OUT) Operating temperature: Temperature coefficient: 100PPM/°C (excludes TD0) Supply voltage VCC: 5VDC Supply current: ICCH 45ma ICCL 20ma Minimum pulse width: total delay
DASH NUMBER SPECIFICATIONS
Part Number PDU13F-.5 PDU13F-1 PDU13F-2 PDU13F-3 PDU13F-5 PDU13F-10 PDU13F-15 PDU13F-20 PDU13F-40 PDU13F-50 Incremental Delay Step (ns) Total Delay Change (ns) 14.0 17.5
NOTE: dash number between shown also available. 2004 Data Delay Devices
#97001
3/25/04
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
PDU13F
APPLICATION NOTES
ADDRESS UPDATE
PDU13F memory device. such, special precautions must taken when changing delay address order prevent spurious output signals. timing restrictions shown Figure After last signal edge delayed appeared pin, minimum time, TOAX, required before address lines change. This time given following relation: TOAX i-1) TINC where address codes, respectively. Violation this constraint may, depending history input signal, cause spurious signals appear pin. possibility spurious signals persists until required TOAX elapsed. similar situation occurs when using signal disable output while active. this case, unit must held disabled state until device able "clear" itself. This achieved holding signal high signal time given TDISH TINC Violation this constraint may, depending history input signal, cause spurious signals appear pin. possibility spurious signals persists until required TDISH elapsed.
INPUT RESTRICTIONS
There three types restrictions input pulse width period listed Characteristics table. recommended conditions those which delay tolerance specifications monotonicity guaranteed. suggested conditions those which signals will propagate through unit without significant distortion. absolute conditions those which unit will produce some type output given input. When operating unit between recommended absolute conditions, delays deviate from their values frequency. However, these deviations will remain constant from pulse pulse input pulse width period remain fixed. other words, delay unit exhibits frequency pulse width dependence when operated beyond recommended conditions. Please consult technical staff Data Delay Devices your application specific high-frequency requirements. Please note that increment tolerances listed represent design goal. Although most delay increments will fall within tolerance, they guaranteed throughout address range unit. Monotonicity however, guaranteed over addresses.
A2-A0 TAENS TENIS
TOAX TSKEW TDISO TAIS
TDISH
OUT/ Figure Timing Diagram
#97001
3/25/04
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU13F
DEVICE SPECIFICATIONS
TABLE CHARACTERISTICS
PARAMETER Total Programmable Delay Inherent Delay Output Skew Disable Output Delay Address Enable Setup Time Address Input Setup Time Enable Input Setup Time Output Address Change Disable Hold Time Absolute Input Period Suggested Recommended Absolute Input Pulse Width Suggested Recommended SYMBOL TSKEW TDISO TAENS TAIS TENIS TOAX TDISH PERIN PERIN PERIN PWIN PWIN PWIN UNITS TINC
Text Text
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
70C, 4.75V 5.25V) PARAMETER High Level Output Voltage Level Output Voltage High Level Output Current Level Output Current High Level Input Voltage Level Input Voltage Input Clamp Voltage Input Current Maximum Input Voltage High Level Input Current Level Input Current Short-circuit Output Current Output High Fan-out Output Fan-out SYMBOL IIHH 0.35 -1.0 20.0 -1.2 -0.6 -150 12.5 UNITS Unit Load NOTES MIN, MIN, MIN, MIN,
MIN, MAX, 7.0V MAX, 2.7V MAX, 0.5V
#97001
3/25/04
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
PDU13F
PACKAGE DIMENSIONS
.020 TYP.
.040 TYP.
.010 TYP.
Lead Material: Nickel-Iron alloy PLATE
.270 TYP.
.430 TYP.
.090
.280 MAX. .290 MAX.
.820 MAX.
.100 .600 .790 MAX.
.300 MAX.
.050 TYP.
Commercial Gull-Wing (PDU13F-xxA2)
.020 TYP.
.040 TYP. .270 TYP.
.050 TYP. .320 TYP.
.015 TYP. .018 TYP. .070 MAX. .600±.010 Equal spaces each .100±.010 Non-Accumulative
.010±.002
.350 MAX.
.110
.100 .600 .790 MAX.
.350 MAX.
.110 TYP.
Commercial (PDU13F-xx)
Commercial J-Lead (PDU13F-xxB2)
.410 TYP.
.020 TYP.
.040 TYP.
.010±.002
.820 MAX.
.020 .320 TYP. MAX.
.710 .590 ±.005 MAX.
.882 ±.005 .007 ±.005
.130 ±.030 .018 TYP. .600 TYP. .100 TYP.
.020 TYP. .300 TYP.
.090 .700 .880±.020
.100
.280 MAX.
.050 ±.010
Military (PDU13F-xxM)
Military Gull-Wing (PDU13F-xxMC3)
#97001
3/25/04
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU13F
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High 3.0V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.4V Pulse Width: PWIN Total Delay Period: PERIN Total Delay OUTPUT: Load: Cload: Threshold: FAST-TTL Gate 1.5V (Rising Falling)
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
PULSE GENERATOR TRIG DEVICE UNDER TEST (DUT) TRIG TIME INTERVAL COUNTER
Test Setup
PERIN TRISE INPUT SIGNAL
2.4V 1.5V 0.6V
TFALL
2.4V 1.5V 0.6V
TDAF
TDAR OUTPUT SIGNAL
1.5V
1.5V
Timing Diagram Testing
#97001
3/25/04
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
Other recent searches
UG385 - UG385 UG385 Datasheet
T67C - T67C T67C Datasheet
SX4487US - SX4487US SX4487US Datasheet
PC100 - PC100 PC100 Datasheet
HM5212165FTD - HM5212165FTD HM5212165FTD Datasheet
M68MP16PABUM - M68MP16PABUM M68MP16PABUM Datasheet
HSU119 - HSU119 HSU119 Datasheet
HP12062- - HP12062- HP12062- Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
