3-channel 8-bit 120MSPS Converter Amplifier Description CXA3506R
|
|
|
Top Searches for this datasheet
CXA3506R
3-channel 8-bit 120MSPS Converter Amplifier
Description CXA3506R 3-channel 8-bit 120MSPS converter with built-in amplifier developed projectors monitors. CXA3506R inputs graphics signals from personal computers others. After input levels controlled, conversion performed with clock generated PLL. digital output levels compatible with TTL. This operates maximum conversion rate 120MHz, support XGA. Control register supports both 3-wire bus. Features Supply voltage: 3.3V Power consumption: 1.7W typ. (120MSPS) 144-pin LQFP 3-ch eliminate design time mutual connections. Structure Bipolar silicon monolithic Applications monitors projectors Digital PDPs LQFP (Plastic)
Functions Performance Power save function Supports both 3-wire Amplifier block Clamp Main contrast: 8-bit contrast: 8-bit Main brightness: 8-bit CbCr offset: 6-bit Supports YCbCr input input systems monitor output/SW monitor output SYNCSEP function converter block Maximum conversion rate: 120MSPS Supports input Supports demultiplexed output Supports both in-phase alternate phase during demultiplexing Supports YUV4:2:2 output Output high impedance mode Built-in reference voltage block Sync input frequency: 10kHz 100kHz Clock delay: 1/32 64/32CLK counter: 12-bit clock jitter inversion 1/2CLK outputs Phase comparison hold Output high impedance mode
Sony reserves right change products specifications without prior notice. This information does convey license implication otherwise under patents other right. Application circuits shown, any, typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits.
E99Y22B1Z-PS
CXA3506R
Absolute Maximum Ratings 25°C) Item DVCCREG, AVCCADREF, DVCCADTTL, DVCCAD, DVCCPLLTTL, AVCCVCO, DVCCPLL, AVCCIR, AVCCAMPR, AVCCAMPG, AVCCAMPB AVCCAD3, DVCCAD3 ADDRESS, XPOWERSAVE, XSENABLE, 3WIRE/I2C, HOLD, XTLOAD, EVEN/ODD, XCLKIN, CLKIN, SYNCIN1, SYNCIN2, CLPIN, RC1, RC2, R/CrIN1, R/CrIN2, R/CrCLP, G/YCLP, B/CbCLP, SOGIN1, G/YIN1, SOGIN2, G/YIN2, B/CbIN1, B/CbIN2, RCrOUT, G/YOUT, B/CbOUT, DACTESTOUT SDA, Storage temperature Allowable power dissipation Tstg Maximum ratings Unit
Supply voltage
Input voltage
+150
Recommended Operating Conditions Item DVCCREG, AVCCADREF, DVCCADTTL, DVCCAD, DVCCPLLTTL, DVCCPLL, AVCCVCO, AVCCIR, AVCCAMPR, AVCCAMPG, AVCCAMPB AVCCAD3, DVCCAD3 input XPOWERSAVE, HOLD, XTLOAD, EVEN/ODD, SYNCIN1, SYNCIN2, CLPIN High level level High level PECL input CLKIN, XCLKIN level Straight mode Maximum conversion rate DMUX mode YUV4:2:2 mode YUV4:2:2 special mode Operating ambient temperature Min. 4.75 DVCCPLL -0.8 Typ. Max. 5.25 DVCCPLL -1.6 Unit MSPS MSPS MSPS MSPS
Supply voltage
CXA3506R
Configuration (Top View)
DSYNC/DIVOUT
DGNDPLLTTL
AGNDADREF
DGNDADTTL
DGNDADTTL
DVCCPLLTTL
DVCCADTTL
DVCCAD3
DVCCADTTL
EVEN/ODD
DGNDAD3
DGNDAD3
AGNDAD3
SOGOUT
AVCCAD3
UNLOCK
1/2XCLK
XTLOAD
DVCCAD
DPGND
1/2CLK
HOLD
XCLK
XCLKIN CLKIN SYNCIN1 SYNCIN2 CLPIN DVCCPLL DGNDPLL AVCCVCO AGNDVCO AVCCIR IREF DPGND AGNDIR G/YIN1 AVCCAMPG G/YIN2 AGNDAMPG G/YCLP B/CbCLP R/CrCLP DPGND SOGIN1 B/CbIN1 AVCCAMPB SOGIN2 B/CbIN2 AGNDAMPB DPGND R/CrIN1 AVCCAMPR R/CrIN2 AGNDAMPR G/YOUT DACTESTOUT B/CbOUT ADDRESS R/CrOUT XPOWER SAVE DGNDREG DVCCREG 3WIRE/I2C DVCCADTTL AVCCADREF DGNDADTTL DVCCADTTL XSENABLE DVCCAD3 AVCCAD3 SEROUT DGNDADTTL DPGND DGNDAD3 AGNDAD3 DGNDAD3 DGNDADTTL DGNDAD3 DVCCADTTL GNDAD3 DGNDADTTL DVCCADTTL DGNDAD3 DGNDADTTL DGNDAD3 DVCCADTTL
Block Diagram
CLPIN R/CrOUT G/YOUT B/CbOUT
R/CrIN1 Offset
Contrast Brightness
R/CrIN2
R/CrCLP Contrast Brightness
G/YIN1
G/YCLP Contrast Brightness Offset XCLK COUNTER (12) REGISTER 1/2DIV Width COARSE DELAY 1/2CLK 1/2XCLK DSYNC/DIVOUT
HOLD
SOGOUT
SEROUT
ADDRESS
3WIRE/I2C
UNLOCK
XTLOAD
XPOWER SAVE
XSENABLE
EVEN/ODD
FINE DELAY SOGT SOGO
B/CbIN1
B/CbIN2
B/CbCLP
VHYS Main Contrast
SOGP
SYNCSEP
SYNCIN1
SYNCIN2
SYNCIN
SOGIN1
SYNCSEP
SOGIN2
SYNCTIP
SYNCSEP
DATA MODE
G/YIN2
CXA3506R
Amplifier Block Diagram
CLPIN 1bit Brightness Offset 8bit 6bit Contrast 8bit CLPOFF 1bit 1bit R/CrCLP R/CrOUT
RGB/YUV 1bit
R/CrIN1
R/CrIN2
G/YCLP
G/YOUT
Brightness 8bit Contrast 8bit
G/YIN1
G/YIN2
B/CbCLP B/CbOUT Brightness Offset 8bit 6bit Contrast 8bit Main Contrast 8bit SYNC SYNC SOGP SYNC 4bit VHYS 2bit
POWER SAVE
1bit
B/CbIN1
B/CbIN2
SYNC POWER SAVE
SOGIN1
SYNC
SYNC GREEN SEPARATOR
1bit
SYNC
SOGIN2
SYNC GREEN SYNCT1 SYNC GREEN SYNCT2 SYNC GREEN SYNCP DACTEST DACTEST
CXA3506R
Block Diagram
Coarse Delay 2bit DSYNC By-pass 1bit TTLIN DIVOUT Delay DIVOUT WIDTH 1bit 2bit DIVOUT Delay Reset Pulse Generator DIVOUT Pulse Width Polarity TTLOUT Coarse Delay EVEN/ODD (TTL)
CLKIN (PECL) XCLKIN (PECL)
PECLIN
DSYNC Enable 1bit DSYNC/DIVOUT (TTL) DSYNC 1bit Enable 1bit DSYNC HOLD 1bit DSYNC HOLD TTLOUT XCLK Enable 1bit (TTL)
Enable 1bit
SOGOUT (TTL)
TTLOUT
1bit
RGBIN1/2SEL
SYNC GREEN SYNCT1 SYNC GREEN SYNCT2 Phase Detector Charge Pump 3bit 6bit 1bit Programmable Counter 1bit By-pass 2bit RESET Fine Delay
Polarity
1bit 1bit SYNC Polarity
TTLOUT
XCLK (TTL) (ADC) 1/2CLK Enable 1bit TTLOUT 1/2CLK (TTL)
SYNC GREEN SYNCP SYNCIN1 (TTL) 1bit SYNC
12bit 1/256 1/4096 Polarity HOLD 1bit Polarity 1bit TTLIN Power Save 1bit Clamp Pulse XTLOAD (TTL)
TTLIN
SYNCIN2 (TTL)
TTLIN
1bit SYNCP/HSYNC
UNLOCK Enable 1bit UNLOCK Detect
1bit HSYNC1/2
1/2XCLK Enable 1bit TTLOUT 1/2XCLK (TTL) 1/2CLK (ADC)
HOLD (TTL)
TTLIN
UNLOCK
CLPIN (TTL)
TTLIN
IREF
CXA3506R
SYNC Block Diagram
SYNCP1 SYNCT SYNC SOGT SOGO SYNCT1
R/CrIN1
BLOCK
BLOCK
G/YIN1 SYNC 1bit 1bit
PEDESTAL CLAMP
B/CbIN1
SOGIN1
SYNC CLAMP
SYNCIN1
1bit Enable
SOGOUT
SOGP SYNC SYNCIN SYNCT2 SYNC 1bit HSYNC1/2 4bit 2bit VHYS 1bit Select
R/CrIN2
G/YIN2
PEDESTAL CLAMP SYNCP2
1bit 1bit SYNC SYNCP/HSYNC
B/CbIN2
SOGIN2
SYNC CLAMP
SYNCIN2
CXA3506R
Block Diagram
MODE
1/2CLK
CONT DATA FORMAT DATA 1bit 3bit CXA3506R
Power Save 1bit
CXA3506R
Description Symbol B/CbOUT ADDRESS R/CrOUT XPOWER SAVE DGNDREG DVCCREG XSENABLE SEROUT 3WIRE/I2C AVCCADREF AVCCAD3 DVCCAD3 Typical signal 1.83V 1.83V 3.3V 2.9V 3.3V 1.9V Description Amplifier output signal monitor slave address setting Amplifier output signal monitor used used Power save setting Register Register power supply Control register data input Control register input Enable signal input 3-wire control register 3-wire control register data readout Selection input between 3-wire Reference power supply converter Analog power supply converter reference voltage output converter Digital power supply converter output power supply converter output converter Data output R-channel port side Digital converter Analog converter Data output R-channel port side Data output B-channel port side Data output B-channel port side Data output G-channel port side Data output G-channel port side Digital power supply converter Bottom reference voltage output converter Reference voltage converter
DVCCADTTL DGNDADTTL
DGNDAD3 AGNDAD3 DVCCAD AGNDADREF
CXA3506R
Symbol DVCCPLLTTL
Typical signal
Description output power supply output Inverted output output Inverted 1/2CLK output 1/2CLK output DSYNC DIVOUT signal output
DGNDPLLTTL XCLK 1/2XCLK 1/2CLK DSYNC/ DIVOUT UNLOCK SOGOUT HOLD XTLOAD EVEN/ODD XCLKIN CLKIN SYNCIN1 SYNCIN2 CLPIN DVCCPLL DGNDPLL AVCCVCO AGNDVCO AVCCIR IREF AGNDIR G/YIN1 AVCCAMPG G/YIN2 AGNDAMPG G/YCLP B/CbCLP R/CrCLP SOGIN1 B/CbIN1
Open collector Unlock signal output PECL PECL 2.1V 4.5V 1.2V 2.8V Output SYNC GREEN Input phase comparison disable signal Programmable counter reset setting Inverted pulse input sampling Inverted input testing input testing Sync input Sync input Clamp pulse input Digital power supply Digital Analog power supply Analog External loop filter External loop filter Analog power supply IREF Current setup Analog IREF signal input Power supply amplifier block signal input amplifier block Clamp capacitor brightness Clamp capacitor brightness Clamp capacitor brightness SYNC GREEN signal input B/Cb signal input
CXA3506R
Symbol AVCCAMPB SOGIN2 B/CbIN2 AGNDAMPB R/CrIN1 AVCCAMPR R/CrIN2 AGNDAMPR G/YOUT TEST
Typical signal 2.8V 1.83V
Description Power supply B/Cb amplifier block SYNC GREEN signal input B/Cb signal input B/Cb amplifier block R/Cr signal input Power supply R/Cr amplifier block R/Cr signal input R/Cr amplifier block Monitor amplifier output signal testing output amplifier block control register
102, 122, DPGND 131,
CXA3506R
Description Equivalent Circuit Symbol Typical signal Equivalent circuit Description Amplifier output signal monitor. Each monitor output either entered signal immediately before converter signal after switching between types input signals. types input signals selected control register output. These pins emitter follower outputs, internal bias current small that resistor should connected between these pins monitor high frequency signals. When used, connect AVCCAMP.
R/CrOUT
1.83V
AVCCAMP
G/YOUT
1.83V
280µ AGNDAMP
B/CbOUT
1.83V
AVCCAMPR AVCCAMPG AVCCAMPB AGNDAMPR AGNDAMPG AGNDAMPB
DVCCPLL
Power supply amplifier block.
amplifier block.
DVCCPLLTTL
100k
SOGOUT
DGNDPLLTTL DGNDPLL
Sync separated SYNC signal output. Separates outputs SYNC signal from SYNC GREEN input signal. (SYNC signal input from SYNCIN1 SYNCIN2 pins output.) Both positive negative polarity outputs supported. polarity selected control register.
SOGIN1
2.8V
AVCCAMPG
SOGIN2
2.8V
AGNDAMPG
100µ
SYNC GREEN signal inputs. Input 0.1µF capacitor. When used, connect AVCC. SYNC clamp level approximately 2.0V (0.8V) approximately 2.8V. this time, voltage lowered, these pins impedance current flows from When these pins SYNC level higher, clamp circuit only input base current approximately 1.2µA flows.
CXA3506R
Symbol
Typical signal
Equivalent circuit
Description
Amplifier block Analog input signal. Input 0.1µF ceramic capacitor. typical signal level 0.7V. Signals from 0.5V (min.) 1.0V (max.) supported. selected control register. Leave these pins open when used. input YCbCr input selected control register. clamp level typical values follows. case input 2.2V (0.8V) approximately case YCbCr input G/YIN: 2.2V (0.8V) approximately R/CrIN, B/CbIN: 2.7V (0.8V) approximately 3.5V Clamp period: clamp current ±1.2mA (max.) flows. Signal period: base current 0.5µA flows Clamp capacitor connector brightness. Connect 0.1µF ceramic capacitors between these pins GND. Typical levels clamp follows. case input BRIGHTNESS 00H: 2.68V 80H: 2.81V FFH: 2.94V case YCbCr input G/YCLP same above. R/Cr, B/CbCLP follows. CbCr Offset 00H: 3.04V 20H: 3.07V 3FH: 3.102V Clamp period: clamp current ±1.2mA (max.) flows. Signal period: base current 0.5µA flows
R/CrIN1
R/CrIN2
AVCCAMP
G/YIN1
G/YIN2
AGNDAMP
400µ 100µ
B/CbIN1
B/CbIN2
R/CrCLP
AVCCAMP AGNDAMP 100µ 100k
G/YCLP
B/CbCLP
CXA3506R
Symbol
Typical signal
Equivalent circuit
DVCCPLL 1.5k
Description Clamp pulse input signal analog input clamp brightness clamp. Both positive negative polarity inputs supported. polarity selected control register. input pulse width should 200ns more.
CLPIN
1.5V
DGNDPLL
converter block
DVCCPLLTTL
XCLK
100k
output. Output same frequency that sampling. These complemental levels. These pins independently controlled (power save) control register. 1/2CLK output. Output half frequency that sampling. These complemental levels. These pins independently controlled (power save) control register. Data output R-channel port side.
1/2CLK
DGNDPLLTTL DGNDPLL
1/2XCLK
DVCCADTTL
Data output R-channel port side. Data output G-channel port side. Data output G-channel port side.
100k
AVCCADREF AGNDADREF AVCCAD3 AGNDAD3 DVCCAD3 DVCCAD
DGNDADTTL DGNDAD3
3.3V 3.3V
Data output B-channel port side. Data output B-channel port side. Reference power supply converter. Reference converter. Analog power supply converter. Analog converter. Digital power supply converter. Digital power supply converter.
CXA3506R
Symbol
Typical signal
Equivalent circuit
Description
DGNDAD3 DVCCADTTL DGNDADTTL
Digital converter.
output power supply converter.
output converter.
AVCCADREF
2.9V
reference voltage output converter input dynamic range. Connect AVCCAD3 ceramic capacitor.
AGNDADREF
AVCCADREF
1.9V
AGNDADREF
Bottom reference voltage output converter input dynamic range. Connect AVCCAD3 ceramic capacitor.
CXA3506R
block
Symbol
Typical signal
Equivalent circuit
Description
SYNCIN1
Input SYNC signal level. input polarity switched control register. Leave this open when used. Input SYNC signal level. input polarity switched control register. Leave this open when used. Input signal phase comparison HOLD. Phase comparison stopped, oscillation frequency held. When hold, follows. When HOLDPOL register "1", this level. When HOLDPOL register "0", leave this open high level.
1.5V
SYNCIN2
DVCCPLL
HOLD
EVEN/ODD
DGNDPLL
Input signal used invert converter sampling CLK. Low: EVEN mode High: mode Normally level. Programmable counter reset. Normally high level leave open. programmable counter test mode, level call register contents. When used, leave this open high level.
XTLOAD
DVCCPLL
CLKIN
PECL
input operation check. Input PECL level signal complementally. When using this pin, external input control register. Leave this open when used.
XCLKIN
PECL
DGNDPLL
CXA3506R
Symbol
Typical signal
Equivalent circuit
DVCCPLL DVCCPLLTTL
Description
DSYNC/ DIVOUT
100k
This output either DSYNC signal DIVOUT signal. selected control register. addition, output polarity selected control register.
DGNDPLLTTL DGNDPLL DVCCPLLTTL
UNLOCK
100k
DGNDPLLTTL DGNDPLL
UNLOCK signal output. Make discrimination between lock unlock analog manner connecting external circuit. Leave this open when used. connect this neither power supply GND.
AVCCIR
2.1V
External loop filter.
4.5V
AGNDIR
AVCCIR
External loop filter.
DPGND
IREF
1.2V
AGNDIR DPGND
Connect external resistor (3k) supply stabilized current inside (charge pump current, etc.) Connect this 0.1µF ceramic capacitor connected close possible. band voltage output.
DVCCPLL DGNDPLL DVCCPLLTTL
Digital power supply PLL. Digital PLL. output power supply PLL.
CXA3506R
Symbol DGNDPLLTTL AVCCIR AGNDIR AVCCVCO AGNDVCO
Typical signal
Equivalent circuit
Description output PLL. Analog power supply IREF. Analog IREF. Analog power supply VCO. Analog VCO.
Control register block
DVCCREG 200k
Input control register data. Switching between 3-wire mode performed 3WIRE/I2C pin.
DGNDREG DVCCREG 200k
Input control register CLK. Switching between 3-wire mode performed 3WIRE/I2C pin.
DGNDREG
DVCCREG
slave address when using mode. Slave address: 3/4VCC 3/4VCC 2/4VCC 2/4VCC 1/4VCC 1/4VCC
DGNDREG
Connect this during 3-wire mode.
CXA3506R
Symbol
Typical signal
Equivalent circuit
DVCCREG 200k
Description
XSENABLE
Inputs enable signal 3-wire bus. High level: Control disabled level: Control enabled Connect this when using I2C.
DGNDREG DVCCREG 100k 100k
Selection input between 3-wire bus. 2/3VCC 2/3VCC 1/3VCC 1/3VCC 3-wire mode mode mode
3WIRE/I2C
100k DGNDREG DVCCREG
SEROUT
100k
When using read mode 3-wire mode, register information written once output series order from setting address data.
DGNDREG
DGNDREG DVCCREG
DVCCREG
register. Power supply register.
XPOWER SAVE
Power save functions including control register block. High level: Normal operation level: Power save
DGNDREG
CXA3506R
Symbol
Typical signal
Equivalent circuit
DVCCREG
Description
TEST
test output control register amplifier block. Current output open collector. Normally connect AVCC.
DGNDREG
102, 122, 131, DPGND
This connected pad. Connect specified Application Circuit. used. Leave this open connect GND. used. Leave this open connect GND.
CXA3506R
Electrical Characteristics 25°C, AVCC, DVCC AVCC3, DVCC3 3.3V) Supply Current Item Current during operating current consumption 3.3V current consumption ICC5 ICC3 Symbol Measurement conditions Min. Typ. Max. Unit
Register control power save current power save current consumption 3.3V power save current consumption ICC5PS ICC3PS
XPOWER SAVE control power save current power save current consumption 3.3V power save current consumption ICC5XPS ICC3XPS
Register Item Symbol Measurement conditions Min. Typ. Max. Unit
3-wire control (SDA, SCL, SENABLE) High level input voltage level input voltage High level input current level input current Threshold voltage High Threshold voltage High Input capacitance clock frequency XSENABLE setup time XSENABLE hold time XSENABLE high level pulse width setup time hold time delay time VTHHL1 VTHLH1 FSCL1 TENS TENH TENPW WRITE/READ mode WRITE/READ mode WRITE/READ mode WRITE/READ mode WRITE/READ mode WRITE/READ mode READ mode -2.0 -5.0 1.65
CXA3506R
Register (Cont.) Item control (SDA, SCL) High level input voltage (High) mode level input voltage -2.0 -5.0 -1.0 -5.0 START condition: After this period, first clock generated. 1.95 1.65 0.15 Symbol Measurement conditions Min. Typ. Max. Unit
High level input current level input current Threshold voltage High Threshold voltage High VTHHL2 VTHLH2
High level input voltage (Low) mode level input voltage
High level input current level input current Threshold voltage High Threshold voltage High VTHHL3 VTHLH3
level output voltage Input capacitance clock frequency free-time STOP START Hold time (resend) Hold time clock state Hold time clock High state Setup time under resend START condition Data hold time Data setup time Rise time Fall time Setup time under STOP condition Capacitive load each line FSCL2 TBUF
THD;STA
TLOW THIGH TSU;STA THD;DAT TSU;DAT TSU;STO
5000
1000
CXA3506R
Item Brightness characteristics Brightness level (ADC OUT) Brightness level Brightness level Brightness level Brightness level side variable range Brightness level High side variable range Clamp characteristics clamp level (ADC OUT) clamp level clamp level clamp level clamp level side variable range clamp level High side variable range Clamp pulse minimum width TWCLP Contrast characteristics Main Contrast Contrast 1.2Vp-p RGB/YUV mode, Main Contrast Contrast 0.6Vp-p RGB/YUV mode, Main Contrast Contrast 0.45Vp-p RGB/YUV mode, Main Contrast Contrast 0.85Vp-p RGB/YUV mode, VCLMAD VCLL VCLM VCLH offset output conversion level offset voltage offset voltage offset voltage VCLL VCLM VCLH VCLM 1.94 1.99 2.03 2.23 2.28 2.34 2.46 2.51 2.58 VBRHAD VBRL VBRM VBRH Brightness output conversion level Brightness voltage Brightness voltage Brightness voltage VBRL VBRM VBRH VBRM 1.388 1.63 1.86 1.588 1.83 2.06 -242 1.788 2.03 2.26 Symbol Measurement conditions Min. Typ. Max. Unit
Main contrast control
VMCL
0.62
0.78
0.94
times
Main contrast control
VMCM
1.23
1.53
1.84
times
Main contrast control
VMCH
1.79
2.24
2.69
times
contrast control
VSCL
0.96
1.44
times
CXA3506R
(Cont.) Item Symbol Measurement conditions Main Contrast Contrast 0.55Vp-p RGB/YUV mode, Main Contrast Contrast 0.6Vp-p RGB/YUV mode, Min. Typ. Max. Unit
contrast control
VSCH
1.48
1.85
2.22
times
Gain difference among
Gain
Frequency response
Main Contrast Contrast 0.6Vp-p RGB/YUV mode,
Cross talk characteristics Cross talk between channels Main Contrast Contrast 100MHz, 0.6Vp-p Main Contrast Contrast 100MHz, 0.6Vp-p
Cross talk among
SYNCSEP Item Symbol Measurement conditions Min. Typ. Max. Unit
SYNC input characteristics SYNC input minimum amplitude SYNC input minimum duty SYNC threshold voltage SYNC hysteresis voltage VSYN DSYN VHYS SYNC 1000 SYNC VHYS SYNC 1000 SYNC VHYS Vp-p
CXA3506R
Item Hold characteristics leak current Ileak Symbol Measurement conditions Min. Typ. Max. Unit
SYNC signal input characteristics SYNC signal input frequency range characteristics Clock frequency Clock frequency Clock frequency Clock frequency lock range gain gain gain gain Jitter characteristics SYNC input signal Clock output jitter (NTSC) SYNC input signal Clock output jitter (VGA) SYNC input signal Clock output jitter (SVGA) SYNC input signal Clock output jitter (XGA) Delay sync Clock output jitter Triggered SYNC Fsync 15.73kHz Fclk 12.27MHz Triggered SYNC Fsync 31.47kHz Fclk 25.18MHz Triggered SYNC Fsync 48.08kHz Fclk 50.00MHz 1040 Triggered SYNC Fsync 56.48kHz Fclk 75.00MHz 1328 Triggered DSYNC FCLK1 FCLK2 FCLK3 FCLK4 Vlock KVCO1 frequency divider KVCO2 frequency divider KVCO3 frequency divider KVCO4 frequency divider frequency divider frequency divider frequency divider frequency divider 37.5 62.5 Mrad/sv Mrad/sv Mrad/sv Mrad/sv FSYNC
Tj1p-p
Tj2p-p
Tj3p-p
Tj4p-p
Tj7p-p
CXA3506R
Item Resolution characteristics Integral linearity error Differential linearity error Reference voltage reference voltage Bottom reference voltage Input dynamic range characteristics Maximum conversion frequency Straight Data Mode Maximum conversion frequency DMUX Parallel Data Mode Maximum conversion frequency DMUX Interleaved Data Mode Maximum conversion frequency 4:2:2 Data Mode Maximum conversion frequency 4:2:2 Data Special Mode MSPS AVccAD3 reference AVccAD3 reference -0.3 -1.3 -0.4 -1.4 -0.6 -1.6 Symbol Measurement conditions Min. Typ. Max. Unit
MSPS
MSPS
MSPS
MSPS
CXA3506R
Item Digital input (PECL) Digital input voltage: Digital input voltage: Digital input current: Digital input current: Digital input (TTL) Digital input voltage: Digital input voltage: Threshold voltage Digital input current: Digital input current: Digital output (TTL) VOH1 Digital output voltage: VOH2 VOH3 VOH4 Digital output voltage: -2mA -2mA -2mA -2mA 2.05 1.85 2.95 2.45 2.75 VIH2 VIL2 IIH2 IIL2 3.5V 0.2V VIH1 VIL1 IIH1 IIL1 DVccPLL reference DVccPLL reference VIH1 DVCCPLL 0.8V VIL1 DVCCPLL 1.6V -1.15 -100 -200 -1.5 Symbol Measurement conditions Min. Typ. Max. Unit
CXA3506R
Timing Characteristics Item Clock output rise time Clock output fall time Delay sync output rise time Delay sync output fall time Data output rise time Data output fall time HOLD signal setup time HOLD signal hold time Delay sync delay time coarse delay Delay sync delay time fine delay Clock output delay from SYNC input signal Delay time between clock output DSYNC/DIVOUT signal DIVOUT signal output delay time Clock clock clock Data Clock Data Symbol TR_CLK TF_CLK TR_DSYNC TF_DSYNC TR_DATA TF_DATA Td_1 Td_2 Td_3 Measurement conditions 2.0V (CLK, 1/2CLK) 0.8V (CLK, 1/2CLK) 2.0V (DSYNC, DIVOUT, SOGOUT) 0.8V (DSYNC, DIVOUT, SOGOUT) 2.0V 0.8V Min. 1/32 Typ. Max. 64/32 Unit
Td_4
Difference between delay sync signal DIVOUT signal
Td_5 Td_6 Td_7 Td_8
Electrical Characteristics Measurement Circuit (3-wire Control)
AGNDADREF AVCCAD3
DVCCAD
DVCCADTTL
DGNDADTTL
DGNDAD3
AGNDAD3
DGNDAD3
DGNDADTTL DVCCADTTL DGNDADTTL DGNDAD3 DVCCADTTL GNDAD3 DGNDADTTL DVCCADTTL DGNDAD3 DGNDADTTL DGNDAD3 DVCCADTTL
EVEN/ODD
XTLOAD
HOLD
SOGOUT
UNLOCK
DSYNC/DIVOUT
DPGND
1/2CLK
1/2XCLK
XCLK
DGNDPLLTTL
SEROUT DVCCREG DGNDREG XSENABLE XPOWER SAVE R/CrOUT B/CbOUT ADDRESS DPGND AVCCAD3 DVCCAD3 3WIRE/I2C DGNDAD3 AGNDAD3 DVCCADTTL DGNDAD3 AVCCADREF DVCCADTTL DGNDADTTL DGNDADTTL
XCLK
XCLKIN
CLKIN
HSYNC
SYNCIN1
CLAMP PULSE
SYNCIN2
CLPIN
DVCCPLL
DGNDPLL
AVCCVCO
AGNDVCO
330p
3.3k
0.33µ
AVCCIR
ANALOG SIGNAL
100p
IREF
DPGND
AGNDIR
0.1µ
G/YIN1
AVCCAMPG
4.7k
4.7k
CONTROLER
0.1µ
G/YIN2
AGNDAMPG
G/YCLP
B/CbCLP
R/CrCLP
ANALOG SIGNAL
0.1µ
DPGND
SOGIN1
0.1µ 0.1µ
B/CbIN1
AVCCAMPB
SOGIN2
0.1µ
B/CbIN2
ANALOG SIGNAL
AGNDAMPB
DPGND
0.1µ
R/CrIN1
AVCCAMPR
0.1µ
R/CrIN2
AGNDAMPR
G/YOUT
DACTESTOUT
DVCCPLLTTL
DVCCAD3
AVCC5V
DVCC5V
3.3V
CXA3506R
DGND
AGND
Control Register Functions Table Register Name Control Range (typ.) Register Data
Block
Function
Feedback programmable counter control
Frequency division ratio
DIV1,
frequency divider control
000000: 1/32CLK 111111: 64/32CLK
FINE DELAY
Delay control (lower order)
Delay control (higher order) COARSE DELAY
3CLK 4CLK 5CLK 6CLK
Charge.Pump 000: 100µA 001: 200µA 010: 300µA 011: 400µA 100: 500µA 101: 600µA 110: 700µA 111: 800µA 1CLK 2CLK DIVOUT WIDTH 4CLK 8CLK DIVOUT DELAY DSYNC HOLD 4CLK 5CLK NEGATIVE POSITIVE NEGATIVE POSITIVE
Charge pump current control
DIVOUT signal pulse width control
DIVOUT signal delay control
CXA3506R
Delay sync output polarity control
Hold input polarity control
Block SYNC By-pass DIVOUT DSYNC By-pass DSYNC DSYNC Hold SYNC SYNCP/ HSYNC HSYNC Enable XCLK Enable 1/2CLK Enable 1/2XCLK Enable DSYNC Enable SYNC1 SYNC2 SYNCP HSYNC1, SYNCT SYNCP/HSYNC NORMAL HOLD NEGATIVE POSITIVE NEGATIVE POSITIVE NEGATIVE POSITIVE NEGATIVE POSITIVE
Function
Register Name
Control Range (typ.)
Register
Data
Phase comparison input positive/negative control
Sync input polarity control
polarity control
Clamp pulse input polarity control
External clock/internal switching
Delay sync output/DIVOUT switching
Delay sync hold function
Output SOG/HSYNC switching
HSYNC1, input/SOGA switching
HSYNC1 input/HSYNC2 input switching
output function (clock)
output function (inverse clock)
output function (1/2 clock)
output function (inverse clock)
CXA3506R
output function (delay sync)
Block Register Name UNLOCK Enable Enable SEROUT Enable MAIN CONTRAST CONTRAST CONTRAST CONTRAST 00000000: 61LSB BRIGHTNESS 11111111: 61LSB 00000000: 61LSB BRIGHTNESS 11111111: 61LSB 00000000: 61LSB BRIGHTNESS 11111111: 61LSB Offset Offset YCbCr mode 00000000: 128LSB 16LSB 11111111: 128LSB 16LSB 00000000: 128LSB 16LSB 11111111: 128LSB 16LSB YCbCr 00000000: Mgain 0.79 11111111: Mgain 1.21 00000000: Mgain 0.79 11111111: Mgain 1.21 00000000: Mgain 0.79 11111111: Mgain 1.21 00000000: Mgain 0.78 11111111: Mgain 2.24 Control Range (typ.)
Function
Register
Data
output function (UNLOCK)
output function (SOG OUT)
REGISTER
output function (SER OUT)
Main contrast
contrast
contrast
contrast
Select Select
brightness
brightness
brightness
input clamp level adjustment mode
input clamp level adjustment mode
YCbCr input mode clamp level switching
output signal selection output output
CXA3506R
RGB2 input selection
Block Brightness
Function
Register Name
Control Range (typ.)
Register
Data
Brightness clamp
SYNC SYNC VHYS
SYNC hysteresis level setting during SYNC GREEN
20mV 45mV 70mV 0000: 75mV 10mV step 1111: 215mV
SYNC SYNC 0(NEGATIVE) DATA 1(POSITIVE)
SYNC threshold level setting during SYNC GREEN
DATA output polarity control
DATA output mode switching DATA MODE
000: Straight 001: DMUX Parallel 010: DMUX Interleaved 011: YUV4:2:2 111: YUV4:2:2 Special active power save active power save active power save active power save
SYNC Power Save Power Save Power Save Power Save TTLOUT 2.20V 2.45V 2.70V 2.95V
power save
power save
power save
SYNC
SYNC power save
TTLOUT TTLOUT LEVEL
CXA3506R
Register Assignment
Data Address VCODIV Bit1 VCODIV Bit9 Fine Delay Bit1 Fine Delay Bit0 VCODIV Bit8 VCODIV Bit0 VCODIV Bit2 VCODIV Bit10 Fine Delay Bit2 code code VCODIV Bit6 DIV1, Bit1 Fine Delay Bit5 DIVOUT DELAY SOGOUT SYNC SYNCP/ HSYNC DSYNC Enable 1/2XCLK Enable 1/2CLK Enable SYNC DSYNC Hold DSYNC By-pass XCLK Enable HOLD HSYNC1/2 Enable UNLOCK Enable Fine Delay Bit4 Fine Delay Bit3 DIV1, Bit0 VCODIV Bit11 VCODIV Bit5 VCODIV Bit4 VCODIV Bit3
Register
Register Name
Register
VCODIV1
VCODIV Bit7
Reference
Register
VCODIV2
Reference
Register
DELAY
Coarse Delay Coarse Delay Bit0 Bit1
Reference
Register
DIVOUT Width DIVOUT Width Charge Pump Charge Pump Charge Pump Bit2 Bit1 Bit0 Bit1 Bit0 DSYNC By-pass Enable
Reference
Register
POLARITY
Reference
Register
SYNC
Reference
Register
TTLOUT ENABLE
SEROUT Enable
Reference
Register
MAIN CONTRAST
Main Contrast Main Contrast Main Contrast Main Contrast Main Contrast Main Contrast Main Contrast Main Contrast Bit6 Bit5 Bit2 Bit1 Bit0 Bit4 Bit3 Bit7
Reference
Register
CONTRAST
Contrast Contrast Contrast Contrast Contrast Contrast Contrast Contrast Bit5 Bit7 Bit6 Bit4 Bit3 Bit2 Bit1 Bit0
Reference
Register
CONTRAST
Contrast Contrast Contrast Contrast Contrast Contrast Contrast Contrast Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reference
CXA3506R
Register
CONTRAST
Contrast Contrast Contrast Contrast Contrast Contrast Contrast Contrast Bit5 Bit7 Bit6 Bit4 Bit3 Bit2 Bit1 Bit0
Reference
Data code code
Address
Register
Register Name
Register BRIGHTNESS Reference Brightness Bit6 Brightness Bit6 Offset Bit5 Offset Bit5 Brightness In1/2 Select Select Offset Bit4 Offset Bit1 Offset Bit3 Offset Bit2 Offset Bit0 YCbCr mode DATA MODE Bit0 TTLOUT TTLOUT Bit1 Bit0 Sync Power Save Power Save Power Save DATA Power Save Offset Bit4 Offset Bit1 Offset Bit3 Offset Bit2 Offset Bit0 Brightness Bit5 Brightness Brightness Bit4 Bit3 Brightness Bit1 Brightness Bit2 Brightness Bit0 Brightness Bit5 Brightness Bit4 Brightness Bit1 Brightness Bit0 Brightness Bit3 Brightness Bit2
Brightness Bit7
Brightness Bit6
Brightness Bit5
Brightness Brightness Bit4 Bit3 Brightness Brightness Bit1 Bit0
Brightness Bit2
Register BRIGHTNESS Reference
Brightness Bit7
Register BRIGHTNESS Reference
Brightness Bit7
Register
CbOFFSET
Reference
Register
CrOFFSET
Reference
SYNC
POWER SAVE
DATA DATA MODE MODE Bit2 Bit1
Register
MODE
Reference
Register
SYNCSEP
Sync Sync Sync Sync Sync VHYS Sync VHYS Bit3 Bit2 Bit1 Bit0 Bit1 Bit0
Reference
Register
OUTPUT MODE
Reference
Register
POWER SAVE
Reference
CXA3506R
CXA3506R
Description Operation Control Register Programmable control performed many functions this Mode selection Both 3-wire mode supported, either these modes selected 3WIRE/I2C (Pin 13). 3WIRE/I2C voltage Setting mode (High) 1/2VCC (Low) (5V) 3-wire
threshold voltages 1/3VCC 2/3VCC. Threshold voltage mode, both (Pin (Pin input. These input logic signals have threshold voltages 3-wire/I2C. These threshold voltages have following hysteresis. SDA, threshold voltages Threshold voltage (Low High) (High) mode 1.95V Threshold voltage (Low High) (Low) mode 1.65V Threshold voltage (High Low) 1.6V Threshold voltage (High Low) 1.3V
3-wire mode, threshold voltages logic signal input SDA, XSENABLE pins have following hysteresis. SDA, XSENABLE threshold voltages Threshold voltage (Low High) 3-wire mode 1.65V Threshold voltage (High Low) 1.3V
CXA3506R
3-wire Mode Various control performed setting internal control register values serial interface comprised three pins (Pin (Pin XSENABLE (Pin 11). Data accepted when XSENABLE level. When XSENABLE high level, data cannot accepted. pins multiple also connected same line each controlled independently XSENABLE. XSENABLE change state when high level. Write mode 8-bit control data consisting 7-bit address 1-bit READ/WRITE setting input series from pin. When READ/WRITE setting "1", data written register. When this used 3-wire mode, address bits, always bits "0". Input clock pin. Data loaded rising edge this clock. data register rising edge XSENABLE. pins also used control mode.
TENPW XSENABLE ADDRESS DATA
READ/WRITE
READ/WRITE READ Mode WRITE Mode
TENS XSENABLE
TENH
post-stage frequency divider (DIV1, programmable counter (VCODIV) following order. data when Register1 sent. Register0 (SUB ADDRESS (H): Register1 (SUB ADDRESS (H):
CXA3506R
Read mode Input 7-bit address 1-bit READ/WRITE setting pin. When READ/WRITE setting "0", 8-bit internally data output series from SEROUT (Pin 12). While data being output from SEROUT pin, don't care what data input pin. read function check whether data correctly inside
TENPW XSENABLE SEROUT ADDRESS READ/WRITE READ/WRITE READ Mode WRITE Mode TENS XSENABLE SEROUT TENH DATA
SEROUT output. When using READOUT function, output circuit turned control register. Register: SEROUT ENABLE SEROUT output status
Function Function
Power-on Reset When power supply rises, power-on reset circuit operates control register data "1". AMP, ADC, SYNCSEP power save mode, output pins high impedance mode. Therefore, possible share same interface with other digital outputs having high impedance modes.
CXA3506R
Mode Various control performed setting internal control register values serial interface comprised (Pin (Pin 10). This mode only write mode setting data, there read mode. Therefore, address "S0" READ/WRITE always "0". SLAVE ADDRESS
Four different kinds slave address address) externally setting ADDRESS (Pin specific voltage. ADDRESS voltage SLAVE ADDRESS 1/3VCC 2/3VCC (5V)
1001 1000 1001 1100 1001 1110 1001 1010
threshold voltages 1/4VCC, 1/2VCC 3/4VCC.
8-bit slave address address), 8-bit address, number 8-bit data strings input series from pin. When this used mode, address bits, bits side always "0". signal returned from confirm that data been received each 8-bit data. address designated optionally. address auto-incremented order from designated address, data strings loaded succession. data specific separated address, either send stop condition then reset address, also send data unchanged portions that data continuous. Only auto-increment mode supported, address data address data mode where only specific addresses designated supported.
SLAVE ADDRESS
ADDRESS
DATA
DATA
START CONDITION
STOP CONDITION
START CONDITION When high level, signal input falling edge, there START CONDITION. STOP CONDITION When high level, signal input rising edge, there STOP CONDITION.
CXA3506R
Control Signals
TBUF TLOW TR_REG TF_REG THD;STA
THD;STA THD;DAT THIGH TSU;DAT TSU;STA TSU;STO
Power-on Reset When power supply rises, power-on reset circuit operates control register data "1". AMP, ADC, SYNCSEP power save mode, output pins high impedance mode. Therefore, possible share same interface with other digital outputs having high impedance modes.
CXA3506R
Amplifier This 3-channel that optimizes coupled analog input signals YCbCr analog input signals input. Switch input mode between input YCbCr input with control register. coupled analog input signals synchronously clamped externally input clamp pulse pedestal level. input capacitor 0.1µF recommended. Allowing lines input selected analog input signal, includes high frequency, cross talk video switch circuit input switching. Switching performed using control register. When using only line, leave unused line open. input band analog input signal 220MHz -3dB bandwidth range. There main contrast sub-contrast gain used adjust analog input signal full scale typ.) ADC. Each adjusted levels using control registers. Main contrast controlled moving gain channels. each gain channels controlled independently. input mode, clamp level used black level adjustment adjusted independently channels levels using sub-brightness. pin1 connected hold capacitor clamp circuit sub-brightness. hold capacitor 0.1µF recommended. pins2 output signal immediately before input signal after switching between lines input select switch. Either them selected control register. emitter follower output, since internal bias current small, sure connect resistor between pins2 AGND order view signal with high frequency. driver cannot supported. addition, load capacitance should less. When SYNC GREEN signal monitored pins2 after lines select switch, sync amplitude maximum 0.3V, limiter applied amplifier input stage. YCbCr signal input mode, adjusted levels using sub-brightness while adjusted levels using offset. detailed description above registers given below. pins: Overall naming R/Cr (Pin 130), (Pin 128), B/Cb (Pin 129) pins: Overall naming R/Cr (Pin (Pin 143), B/Cb (Pin Analog input signal mode switching Analog input signal supports both analog input signal YCbCr analog input signal. This register switches clamp level input clamp block amplifier output block each mode. However, G/Ych perform same processing both input mode YCbCr input mode. Register: YCbCr mode Analog input signal mode input YCbCr input
Input channel switching Input supports 2-channel input, input selected internal switch. Register: Select Analog input signal channel switching
Clamp pulse input polarity clamp pulse input polarity selected internal switch. Register: Clamp pulse polarity NEGATIVE POSITIVE
CXA3506R
Brightness clamp function Clamp operation mode where only post-stage brightness clamp does operate even clamp pulse input CLPIN (Pin 113). this time, three channels pins1 high impedance simultaneously, signal black level varied analog manner setting voltages externally. However, voltage value here related (Pin (Pin voltages OUT2 monitor signal output levels. Therefore value should while monitoring data output data after that. Register: Brightness Clamp operation Clamp operation Clamp
Monitor signal output selection monitor signal outputs (OUT pins2) amplifier selected internal switch. amplifier output signal immediately before input ADC, other after switching between lines select switch. Register: select Monitor output switching
Amplifier output Switch output
Main contrast channel gains collectively 8-bit setting. Register: MAIN CONTRAST Amplifier gain (typ.) CONTRAST 0.78 1.53 2.24
contrast contrast amplifier gain) adjusted independently within range ±21% relative main contrast 8-bit setting. Register: CONTRAST gain adjustment (typ.) -21% +21%
contrast contrast amplifier gain) adjusted independently within range ±21% relative main contrast 8-bit setting. Register: CONTRAST gain adjustment (typ.) -21% +21%
contrast contrast amplifier gain) adjusted independently within range ±21% relative main contrast 8-bit setting. Register: CONTRAST gain adjustment (typ.) -21% +21%
CXA3506R
brightness mode brightness (black level voltage) 8-bit during signal input. brightness varied within range ±25% input dynamic range (approximately centering (Pin (approximately 1.9V). Register: BRIGHTNESS Level shift amount (typ.) Register: YCbCr mode Input signal mode -61LSB 0LSB +61LSB
brightness mode brightness (black level voltage) 8-bit during signal input. brightness varied within range ±25% input dynamic range (approximately centering (Pin (approximately 1.9V). Register: BRIGHTNESS Level shift amount (typ.) Register: YCbCr mode Input signal mode -61LSB 0LSB +61LSB
brightness mode brightness (black level voltage) 8-bit during signal input. brightness varied within range ±25% input dynamic range (approximately centering (Pin (approximately 1.9V). Register: BRIGHTNESS Level shift amount (typ.) Register: YCbCr mode Input signal mode -61LSB 0LSB +61LSB
Cbch black level shift YCbCr mode Cbch black level voltage 6-bit during YCbCr signal input. Cbch black level voltage varied within range ±16LSB centering input dynamic range center ((VRT VRB)/2). Register: Offset Level shift amount (typ.) Register: YCbCr mode Input signal mode 112LSB YCbCr 128LSB 144LSB
Crch black level shift YCbCr mode Crch black level voltage 6-bit during YCbCr signal input. Crch black level voltage varied within range ±16LSB centering input dynamic range center ((VRT VRB)/2). Register: Offset Level shift amount (typ.) Register: YCbCr mode Input signal mode 112LSB YCbCr 128LSB 144LSB
CXA3506R
Input signal connection method Input Symbol G/YIN1 G/YIN2 B/CbIN1 B/CbIN2 R/CrIN1 R/CrIN2 Output Symbol
When inputting both YCbCr, input according table above. SYNCSEP connected G/YIN. When inputting using SYNCSEP, there difference between three channels input order optional. When inputting sure input according table above. possible only R/Cr B/Cb pins clamped center input dynamic range.
CXA3506R
SYNCSEP SYNCSEP function used separate output SYNC signal that superimposed SYNC GREEN signal (including SYNC signal). There major SYNCSEP circuits. circuit creating SYNC signal input PLL, other circuit outputting SYNC signal from SOGOUT (Pin 105) that clamp pulse created externally. These SYNCSEP circuits perform processing entirely different channels. (See block diagram SYNCSEP operational description.) SYNCSEP circuit SYNC signal case SYNC GREEN signal, SYNC GREEN signal coupled G/YIN1 (Pin 124) G/YIN2 (Pin 126) sync component separated used reference. input capacitor 0.1µF recommended. When signal input this pin, pedestal level clamped clamp pulse input CLPIN (Pin 113). After this, signal split into signal amplifier circuit signal SYNCSEP circuits, SYNC signal sent through lines input select switch SOGP) SYNC signal separated SYNCSEP circuits. this time, possible minimize jitter SYNC signal sent using control register select threshold level (VTH) hysteresis level (VHYS) SYNCSEP circuit according type noise superimposed SYNC signal. SYNC threshold (Versus pedestal level) Register: SYNC Threshold SYNC hysteresis Register: SYNC VHYS Hysteresis 20mV 45mV 70mV 0000 75mV 9.3mV step 1111 215mV
VHYS SYNC signal Pedestal level
SYNC signal separated SYNCSEP circuits switched circuit with externally input SYNC signal (the SYNC signal input from SYNCIN1 SYNCIN2 pin) using control registers (SYNCP/HSYNC). selected signal input block. Selecting between sync separated SYNC signal externally input SYNC signal Register: SYNCP/HSYNC SYNC signal type SYNC signal input Sync separated signal G/YIN1 G/YIN2 Externally input SYNC signal SYNCIN1 SYNCIN2
CXA3506R
SYNCSEP circuits SYNC signal clamp pulse SYNC GREEN signal input SOGIN1 (Pin 132) SOGIN2 (Pin 135). coupled signal internally sync clamped minimum level (bottom sync) turned into internally-set level (approximately 2.8V). sync clamped input signal separated from threshold 165mV SYNC DUTY above from bottom sync SYNCSEP circuit. After this, signal output level from SOGOUT used reference signal generating clamp pulse. Since clamp pulse required sync clamp, possible output SYNC signal from SOGOUT even when there external clamp pulse present such when power supply turned input capacitor 0.1µF recommended. control register used select output either SYNC signal separated from signal input from SOGIN1 SOGIN2 previously described SYNC signal output from circuit. Output from SOGOUT SYNCT1, SYNCT2/SYNCP1, SYNCP2/SYNCIN1, SYNCIN2 output selection SYNCT1, SYNCT2: SYNC signal sync clamped separated from SOGIN1 SOGIN2 pins SYNCP1, SYNCP2: SYNC signal pedestal clamped separated from G/YIN1 G/YIN2 pins SYNCIN1, SYNCIN2: SYNC signal input from SYNCIN1 SYNCIN2 pins Register: SYNC
Output from SOGOUT SYNCT1, SYNCT2 SYNCP1, SYNCP2 SYNCIN1, SYNCIN2
SOGIN1, SOGIN2 previously described G/YIN1, G/YIN2 interlocked 2-ch selection (Register: Select). Input channel selection Register: Select G/YIN selection SOGIN selection
polarity signals output from SOGOUT using registers. Register: SOGOUT SOGOUT output polarity Negative Positive
SYNC GREEN output enable When SOGOUT used, possible turn output using control register. cannot high impedance. Register: Enable SOGOUT output status
CXA3506R
SYNC signal input SYNC (HSYNC) used input from SYNC signal input pins. There sets input pins, SYNCIN1 (Pin 111) SYNCIN2 (Pin 112), which switched control register. SYNCIN1 input, SYNCIN2 input switching Register: HSYNC1/2 SYNC signal input SYNCIN1 SYNCIN2
SYNC signals within range from 10kHz 100kHz input. input supports both positive negative polarity. SYNC signal input polarity Register: SYNC SYNC signal input polarity Negative Positive
register accordance with polarity externally input SYNC. When SYNC positive polarity, SYNC "1". (Clock generated sync with rising edge SYNC.) When SYNC negative polarity, SYNC "0". (Clock generated sync with falling edge SYNC.) When there SYNC input, oscillates random random pulse output from output.
SYNC signal
Programmable counter
Point oscillation frequency Point Clock frequency
Phase detector (PD) phase detector compares phase SYNC signal with that programmable counter output signal. phase comparison performed edge, phase difference between compared signals output pulse. There hysteresis function input pins SYNC signal (SYNCIN1 SYNCIN2) input phase detector. necessary external waveform shaping should done jitter results when noisy signal input. control register, POL, input polarity phase detector. Hold function hold function holds input voltage generates oscillation itself without performing phase comparison. oscillation frequency held during this period without performing phase comparison, inputting HOLD signal from HOLD (Pin 106). HOLD signal polarity using control register: HOLD POL. Register: HOLD HOLD signal input polarity Held while HOLD signal Held while HOLD signal High
details, hold timing diagram.
CXA3506R
Charge pump (CP) charge pump sets charge pump current flow amount time corresponding pulse width output from phase detector. phase detector gain determined charge pump current. amount current varied using control register. This used charge pump current value according oscillation frequency given below. Setting Matrix] oscillation frequency: 40MHz 85MHz: 85MHz 110MHz: 110MHz 140MHz: 140MHz 155MHz: 155MHz 165MHz:
setting values 200µA 300µA 400µA 500µA 600µA
oscillation frequency that Point diagram. Register: Charge Pump Bit2 Register: Charge Pump Bit1 Register: Charge Pump Bit0 Charge pump current 100µA 200µA 300µA 400µA 500µA 600µA 700µA 800µA
Loop filter (LPF) control voltage input pulse current output from charge pump circuit that smoothed integrating circuit (loop filter). resistor capacitor values integrating circuit follows. (For circuit configuration, application circuit.) 0.33µF 330pF 3.3k resistor capacitors, metal film chip resistor with little temperature variation ceramic chip capacitors. particular, 0.33µF capacitor should equivalent high dielectric constant series capacitor type better. (Electrostatic capacitance change ratio ±10%: +85°C) case using resistors capacitors except those given above, guaranteed. oscillation frequency range covers from 40MHz 165MHz.
CXA3506R
frequency dividers (DIV oscillation frequency divided 1/1, 1/2, 1/4, according control register setting. Depending combination oscillation frequency frequency divider, Point clock frequency covers operating range 5MHz 120MHz. matrix frequency divider setting follows. [VCO Frequency Divider Setting Matrix] Clock frequency: setting value 5MHz 14MHz: 14MHz 40MHz: 40MHz 80MHz: 80MHz 120MHz: Register: Bit1 Register: Bit0 Counter frequency
Programmable counter clock frequency Point divided programmable counter output signal generated. frequency division ratio optionally using 12-bit control register. This determined using lower order bits upper order bits following formula. Frequency division ratio bits (VCO bits (VCO Register Register Register Register Name VCODIV1 VCODIV2 Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data0
After value frequency division ratio changed, that value loaded into programmable counter when output value programmable counter becomes "all Clock output When input polarity SYNC signal positive, clock output synchronized rising edge SYNC signal available complementary signals (Pin XCLK (Pin 98). delay time clock output varied range 1/32CLK 64/32CLK using control register (see timing diagram). Although clock output turned independently using control register, cannot high impedance. operational frequency clock 100MHz. Register: Enable, XCLK Enable Clock output status
CXA3506R
clock output clock signal signal that resets clock using reset pulse created from internal delay sync signal divides clock half. complementary signal output from 1/2CLK (Pin 101) 1/2XCLK (Pin 100). (See timing diagram). Although clock output also independently turned control register, cannot high impedance. Register: 1/2CLK Enable, 1/2XCLK Enable Clock Output Status
Delay sync output types delay sync signal (DSYNC DIVOUT) output from DSYNC/DIVOUT (Pin 103). This selected switching control register. DSYNC signal output input SYNC signal undergone timing control. DIVOUT signal output programmable counter output undergone timing control. Both used reset signals connected such scaling Delay sync output signal (DSYNC/DIVOUT (Pin 103)) Register: DSYNC By-pass Signal output from DSYNC/DIVOUT
DIVOUT signal DSYNC signal
DSYNC signal SYNC signal input that been timing controlled clock generated output. Although only forward edge completely managed this time with delay settings, etc., back edge undefined width clock cycle because latches outputs input SYNC signal. DIVOUT signal timing controlled programmable counter output signal output. addition COARSE DELAY that been using DSYNC signal, delay time setting output with delay clocks. pulse width also managed clock. [Function Correspondence Table DSYNC Signal/DIVOUT Signal] Function COARSE DELAY FINE DELAY Pulse width DIVOUT DELAY Output polarity Output enable Output during HOLD DSYNC signal 3CLK 6CLK 1/32CLK 64/32CLK Fixed (depends input SYNC signal width) On/Off On/Off On/Off DIVOUT signal 3CLK 6CLK 1/32CLK 64/32CLK 8CLK 5CLK On/Off On/Off On/Off Register COARSE DELAY FINE DELAY DIVOUT WIDTH DIVOUT DELAY DSYNC DSYNC Enable DSYNC Hold
CXA3506R
Delay time setting (Fine Delay/Coarse Delay) delay sync output, clock output, clock output make delay time setting (Fine Delay/Coarse Delay) input signal. amount delay time from 3CLK Delay 6CLK Delay Coarse Delay from 1/32CLK 64/32CLK Fine Delay. delay time (Fine Delay/Coarse Delay) using control registers shown below. Register: FINE DELAY Delay time Register: COARSE DELAY Delay time 000000 1/32CLK 3CLK 000001 2/32CLK 4CLK 5CLK 6CLK 111111 64/32CLK
DIVOUT signal output pulse width pulse width DIVOUT signal output clock pulse widths using control register. Register: DIVOUT WIDTH DSYNC signal width 1CLK 2CLK 4CLK 8CLK
DIVOUT signal output delay time setting DIVOUT signal output with clock delay based delay time (Fine Delay/ Coarse Delay) described above. clock delay time using control register. Register: DIVOUT DELAY Delay time 4CLK 5CLK
Delay sync output polarity polarity delay sync signal output from DSYNC/DIVOUT selected either negative positive using control register. Register: DSYNC Delay sync output polarity Negative Positive
Delay sync output status Although possible turn signal output from DSYNC/DIVOUT using control register, cannot high impedance. Register: DSYNC Enable Delay sync output status
CXA3506R
Delay sync output status during hold Register: delay sync output during hold period controlled with DSYNC Hold register HOLD signal. Register: DSYNC Hold Delay sync output status Using HOLD signal logic DSYNC signal/DIVOUT signal
output status resulting from this setting differs based status DSYNC By-pass register. HOLD signal logic (When HOLD register
Register: DSYNC Hold
Register: DSYNC By-pass
Delay sync output DIVOUT signal DSYNC signal DIVOUT signal DIVOUT signal DSYNC signal DSYNC signal
values given above table when DSYNC register "1". delay sync output status reversed when DSYNC "0". XTLOAD signal (reset signal) This input forces reset divider function programmable counter. Since this signal normally used, leave open high level. When used, this signal conjunction with HOLD signal. note given later regarding combined these signals. XTLOAD Programmable counter status Forcible reset Count
CXA3506R
Register: DSYNC Hold register HOLD signal used control delay sync output during hold period. relationship between delay sync output SYNC signal shown below. (For each CASE DSYNC register "1". addition, DSYNC signal output DIVOUT signal output switched using DSYNC By-pass register.) CASE
SYNC signal (SYNC
HOLD signal
DSYNC Hold
DSYNC signal
DIVOUT signal
DSYNC Hold
DSYNC signal
DIVOUT signal
CXA3506R
CASE
SYNC signal (SYNC
HOLD signal
DSYNC Hold
DSYNC signal
DIVOUT signal
DSYNC Hold
DSYNC signal
DIVOUT signal
CXA3506R
CASE
SYNC signal (SYNC
HOLD signal
DSYNC Hold
DSYNC signal
DIVOUT signal
DSYNC Hold
DSYNC signal
DIVOUT signal
CXA3506R
Notes Using HOLD Signal XTLOAD Signal (Reset Signal) cycle SYNC signal lost, phase difference between SYNC signal programmable counter output phase detector will increase, will cause unlock. this time, HOLD signal input HOLD (Pin 106), phase comparison stopped while signal high level (when HOLD register "1"), clock stably oscillated holding oscillation frequency. Note, however, correspondence differs depending whether number locations where SYNC signal period changes (the 0.5H region diagram) even.
SYNC signal
Clock output
Programmable counter
Case When 0.5H region even (correspondence with HOLD signal only)
SYNC signal (SYNC Programmable counter output signal HOLD signal 0.5H 0.5H 0.5H 0.5H
When number 0.5H period even, possible hold period programmable counter output stable applying HOLD signal before frequency changes. This corresponds vertical blanking period composite sync (computer signal). Case When 0.5H region (correspondence with HOLD signal XTLOAD signal (reset signal))
SYNC signal (SYNC Programmable counter output signal HOLD signal 8CLK XTLOAD signal (reset signal) (min) 100ns "HSYNC" "XTLOAD" synchronized
0.5H 0.5H 0.5H
When number 0.5H period odd, only HOLD signal used, phase difference between SYNC signal programmable counter output signal will increase extra 0.5H region lock will lost momentarily. this case, 0.5H region held HOLD signal, possible XTLOAD signal (reset signal) backward official counter period resetting/setting counter value. Although there particular restrictions setup time hold time XTLOAD signal (reset signal), pulse width XTLOAD signal (reset signal) restricted while HOLD signal high. (When HOLD register "1".) rising edge XTLOAD signal (reset signal) delayed 8CLK from falling edge SYNC signal, counter output will obtained synchronizing with falling edge next SYNC signal. diagram details timing.
CXA3506R
HOLD signal timing
SYNC signal (when SYNC
SYNC signal (when SYNC
DIVOUT signal (when DSYNC HOLD signal (when HOLD Thold oscillation frequency held without performing phase comparison. Clock output
HOLD signal setup time (Ths) time from rising edge HOLD signal falling edge DIVOUT signal. HOLD signal hold time (Thh) time from falling edge DIVOUT signal rising edge HOLD signal. above timing diagram details relationship with SYNC POL. frequency variation while held calculated given below.
Ileak
Ileak Thold Loop filter capacitance Varying voltage leak current Ileak: Leak current internal amplifier Thold: Hold time Ileak Thold/C KVCO Ileak Thold/C KVCO example, Assuming 100MHz, Ileak 1nA, Thold 1ms, 0.33µF, KVCO [MHz/V], 10-9 10-3/(0.1 10-6) 10-6 10-9 10-3/(0.1 10-6) 1050 [Hz]
CXA3506R
UNLOCK timing phase difference between SYNC signal input programmable counter output signal phase detector (PD) increases, becomes impossible maintain stable oscillation. This status converted into UNLOCK signal output. possible perform analog lock/unlock connecting external circuit this pin.
internal Signal from phase detector UNLOCK detect signal external signal UNLOCK signal
100k 0.01µF
UNLOCK output open collector. connecting external circuit shown above this output pin, possible adjust sensitivity signal varying constants (The constants above reference values. resistor should should series. operations three cases described below. Case When there phase difference (PLL locked status) signal signal high. UNLOCK signal low.
signal signal UNLOCK signal Threshold level inverter
Case When there phase difference, signal will goes high shown figure below. this time, falling edge slew rate signal determined current flowing into this open collector. falling edge slew rate signal will therefore delayed resistor increases. addition, since rising edge slew rate signal determined current rising edge slew rate signal will become faster resistor decreases. integrated signal does fall below threshold level next inverter, UNLOCK signal will remain low. This will therefore judged locked even there phase difference.
signal signal UNLOCK signal Threshold level inverter
Case However, even same phase difference described above assumed, decreasing resistor will increase current flowing into open collector. falling edge slew rate signal will therefore become faster. addition, resistor increased, rising edge slew rate signal will become slower. integrated signal under threshold level next inverter, UNLOCK signal will from high will judged unlocked.
signal signal UNLOCK signal Threshold level inverter
CXA3506R
CXA3506R's charge pump constant-current output type shown below.
When constant-current output charge pump circuit used inside PLL, phase detector (PD) output acts current source, dimension transmittance A/rad. Also, when considering input voltage, transmittance dimension must expressed ohms V/A). Therefore, transmittance when constant-current output charge pump circuit used follows.
(A/rad)
KVCO (rad/S/V)
counter
closed loop transmittance obtained following formula. KVCO KVCO .(1)
Here, KPD, F(S) KVCO are: KPD: Phase comparator gain (A/rad) F(S): Loop filter transmittance KVCO: gain (rad/s/V) reason inside phase detector follows. (t)/N (t)/Ndt 0)/N: (t)/N (t)/Ndt: Performing Laplace conversion: (S)/N (S)/N:
CXA3506R
loop filter F(S) described below. loop filter smoothes output pulse from phase detector (PD) inputs component VCO. addition this, however, loop filter also functions important element determining response characteristics. Typical examples loop filters include filters, lag-lead filters, active filters, etc. However, CXA3506R's current input type active filter shown below, following calculations show actual example deriving closed loop transmittance when using this type filter then using this transmittance create formula setting filter constants. Current input type active filter
filter transmittance follows.
Bode diagram formula follows.
Gain [dB] scale
Phase [deg]
Here, assuming then: .(2)
-45deg
Next, substituting into obtaining overall closed loop transmittance PLL: KVCO KVCO
KVCO
.(3)
KVCO
.(4)
KVCO
.(5)
.(6)
CXA3506R
Here, follows. characteristic angular frequency: oscillatory angular frequency when oscillation assumed have been maintained loop filter individual loop gains called characteristic angular frequency: damping factor: This transient response characteristic, serves measure stability. determined loop gain loop filter. capacitor added actual loop filter. This added capacitor used reduce noise, value around 1/10 1/1000 should selected necessary. Current input type active filter with added capacitor
filter transmittance follows. ((C1
Bode diagram formula follows.
Gain [dB] scale
.(3)
Phase [deg]
-45deg
Here, assuming C1/100, then: C1/100 C1/100
CXA3506R
Next, various parameters inside actual CXA3506R obtained. CXA3506R's charge pump output block circuit follows.
100µA 100µA step 800µA 100µA 100µA step 800µA CXA3506R
First, follows. 100µ/2 200µ/2 300µ/2 400µ/2 500µ/2 600µ/2 700µ/2 800µ/2 (A/rad) Typical KVCO characteristics curves CXA3506R's internal follows.
frequency [MHz]
input voltage
Therefore, KVCO follows. KVCO 27.5 13.75 6.875 (rad/s/V)
CXA3506R
calculated various types computer signals shown below. Here, various parameters follows. FSYNC: Input sync frequency, FCLK: Output clock frequency Phase comparator gain (KPD 800) KVCO/2: gain (when 1/1, KVCO/2 (when 1/2, KVCO/2 55/2) (when 1/4, KVCO/2 55/4) (when 1/8, KVCO/2 55/8) Counter value, Loop filter capacitance value, Loop filter resistance value
MODE Resolution FSYNC FCLK NTSC NTSC NTSC NTSC 480p 1080i 720p 15.73 15.73 15.73 15.73 15.63 15.63 15.63 15.63 31.47 33.75 45.00 31.47 35.00 12.27 18.41 24.55 27.00 14.69 22.03 29.38 27.00 72.00 74.25 74.25 21.05 25.18 30.24 31.50 36.00 40.00 49.51 50.00 56.25 57.28 65.00 75.01 78.75 80.00 94.50 C.Pump setting KVCO setting setting oscillation frequency 1.54 98.18 1.45 73.64 1.54 98.18 1.47 108.00 1.62 58.75 1.62 88.13 1.62 117.50 1.46 108.00 2.32 144.01 2.37 148.50 2.74 148.50 1.71 84.19 2.15 100.70 2.39 120.96 2.44 126.00 2.46 144.02 2.65 160.01 2.65 99.01 2.67 100.01 3.07 112.49 2.93 114.55 2.71 129.99 3.05 150.01 3.36 157.49 3.34 160.00 3.28 94.50
bit2 bit1 bit0 M/(SV) bit1 bit0
kHzrad 2.83 2.67 2.83 2.70 2.98 2.98 2.98 2.69 4.27 4.35 5.03 3.13 3.95 4.39 4.48 4.51 4.87 4.87 4.90 5.64 5.38 4.98 5.60 6.17 6.14 6.03 0.45 0.42 0.45 0.43 0.47 0.47 0.47 0.43 0.68 0.69 0.80 0.50 0.63 0.70 0.71 0.72 0.77 0.77 0.78 0.90 0.86 0.79 0.89 0.98 0.98 0.96
55/8 55/4 55/4 55/4 55/4 55/4 55/4 55/4 55/2 55/2 55/2 55/4 55/4 55/4 55/4 55/4 55/4 55/2 55/2 55/2 55/2 55/2 55/2 55/2 55/2 55/1
0.33
1170 0.33 1560 0.33 1716 0.33 0.33 1410 0.33 1880 0.33 1728 0.33 2288 0.33 2200 0.33 1650 0.33 0.33 0.33 0.33 0.33
PC-98 24.82
VESA 37.86 SVGA 35.16 SVGA 37.88 SVGA 46.88 SVGA 48.08 SVGA 53.67 49.72 1024 48.36 1024 56.48 1024 60.02 1024 68.68
1024 0.33 1056 0.33 1056 0.33 1040 0.33 1048 0.33 1152 0.33 1344 0.33 1328 0.33 1312 0.33 1328 0.33 1376 0.33
1024 60.24
setting matrix setting matrix Internal oscillation frequency: setting value Output oscillation frequency: setting value 40MHz 85MHz: 200µA 5MHz 14MHz: 85MHz 110MHz: 300µA 14MHz 40MHz: 110MHz 140MHz: 400µA 40MHz 80MHz: 140MHz 155MHz: 500µA 80MHz 120MHz: 155MHz 165MHz: 600µA
CXA3506R
Jitter Evaluation Method generated obtained inputting Hsync CXA3506R. Apply this digital oscilloscope observe waveform using Hsync trigger.
trigger Digital oscilloscope
Pulse generator
Hsync signal
CXA3506R
Clock
Back sync porch
Active video
Front porch
Computer signal Tsync Hsync signal Tsync 1/fsync
Clock
Trigger
Enlarge
Enlarge
Enlarge
Enlarge
Clock
jitter measured peak peak long-term write mode digital oscilloscope shown figure. jitter size varies according difference relative position with respect Hsync. Therefore, when observation point changed, jitter that point observed. figure below shows typical example jitter CXA3506R. jitter increases slightly rising edge Hsync case positive polarity), then settles down thereafter. However, this problem active pixels start after about cycle passed from rising edge Hsync.
Jitter amount
Tsync
Tsync Observation points
Tsync
Tsync
CXA3506R
Converter Analog input signal analog input signal YCbCr analog input signal converted digital signals output. sure adjust input dynamic range pre-stage amplifier block performing contrast brightness settings analog signal input ADC. (See item amplifier details setting procedure.) Sampling clock Although sampling clock created (internal CLK), also possible externally input clock (external CLK) directly checking operations. this case, sure make register settings below order input PECL level clock from CLKIN (Pin 110) XCLKIN (Pin 109). Register: By-pass clock External Internal
Note, however, that even external input under above settings, impossible input clock frequency unless PLL's frequency divider 1/1. Running external done order check operations ADC. Normally, should internal generated PLL. Reference voltage input dynamic range determined based reference voltage from (Pin (Pin 93). Since this reference voltage created using internal band voltage, there need external reference voltage circuit. voltage voltage approximately 0.4V lower than voltage coming from AVCCAD3 power pin. Also, voltage approximately 1.0V lower than that pin. Capacitors more should connected between AVCCAD3 power supply pins these reference voltage pins (VRT pin). value capacitor capacitor attached, reference voltage circuit will cause oscillation that results noise malfunction because faithfully samples this oscillation. impossible apply external voltage reference voltage pin. Note that also impossible voltage generated reference voltage external voltage source. Operational mode output data this supports five types operational mode. Each operational mode using control register. Register: DATA MODE Straight Data Mode DMUX Parallel Data Mode DMUX Interleaved Data Mode 4:2:2 Data Mode 4:2:2 Data special Mode
description each operational mode, next page.
CXA3506R
Description operational modes (Straight Data Mode) analog input signal coupled optimized using 3-ch signal input ADC. analog input signal input sampled using clock generated PLL. identical signal with sampling clock analog input signal output from (Pin 99). sampled analog input signal output from port side data output with 3-clock pipeline delay. Note that output port side turned this time cannot high impedance. data output output with propagation delay (Td_8) ranges from 2.2ns (min.) 3.8ns (max.) versus clock output from pin. operational frequency Straight Data Mode 100MHz sampling clock frequency. Also, note, when operating Straight Data Mode, that output port side (RB0 RB7, GB7, BB7) turned cannot high impedance. output high impedance only when this into power save mode. following type interface possible when this operated Straight Data Mode.
CXA3506R XCLK 1/2CLK 1/2XCLK max. min. Td_8 2.2ns (min.) 3.8ns (max.)
Scaling
(min.)
hold time post-stage scaling using interface shown above (min.) 2.2ns
CXA3506R
(DMUX Parallel Data Mode) analog input signal coupled optimized using 3-ch signal input ADC. analog signal input sampled using clock generated PLL. identical signal with sampling clock analog input signal output from (Pin 99). each clock cycle, sampled data divided into pins port side port side. data output port side possesses 3-clock pipeline delay versus sampling clock, while data output port side possesses 2-clock pipeline delay. output timing same data output from both ports. Data maintained cycles (2T) sampling clock. data output with propagation delay (Td_7) ranges from 2.3ns (min.) 3.2ns (max.) versus clock output from 1/2XCLK (Pin 100). interface following type possible when this DMUX Parallel Data Mode.
CXA3506R XCLK 1/2CLK 1/2XCLK max. min.
Td_7 2.3ns (min.) 3.2ns (max.)
Scaling
With interface shown above, post-stage scaling acquire data using clock signal output from 1/2CLK ADC. case this interface, setup time post-stage scaling (min.) 3.2ns While hold time (min.) 2.3ns
CXA3506R
(DMUX Interleaved Data Mode) analog input signal coupled optimized using 3-ch signal input ADC. analog signal input sampled using clock generated PLL. identical signal with sampling clock analog input signal output from (Pin 99). each clock cycle, sampled data divided into pins port port data output port side possesses 2-clock pipeline delay versus sampling clock, while data output port side also possesses 2-clock pipeline delay. Although data output from both ports maintained cycles (2T) sampling clock, there cycle difference between output timing port side port side. Data output port side possesses propagation delay (Td_7) ranges from 1.3ns (min.) 2.2ns (max.) versus clock output from 1/2XCLK (Pin 100), while data output port side possesses propagation delay (Td_1/2clk data) ranges from 2.3ns (min.) 3.2ns (max.) versus clock output from 1/2CLK (Pin 101). interface following type possible when this DMUX Interleaved Data Mode.
CXA3506R XCLK 1/2CLK 1/2XCLK max. min. max. min.
Scaling
Td_7 2.3ns (min.) 3.2ns (max.)
With interface shown above, port data acquired into post-stage scaling using clock signal output from 1/2CLK ADC, while port data acquired using clock signal output from 1/2XCLK pin. case this interface, setup time post-stage scaling (min.) 3.2ns While hold time (min.) 2.3ns
CXA3506R
(4:2:2 Data Mode) YCbCr analog input signal coupled optimized using 3-ch signal input ADC. analog signal input sampled using clock generated PLL. identical signal with sampling clock analog input signal output from (Pin 99). 4:2:2 Data Mode, only signal converted just Straight Data Mode output data output ports GA7. signals simultaneously converted half sampling rate compared with signal, then multiplexed within output data output ports order (Cb) (Cr). When SYNC signal input, necessary separate SYNC signal superimposed signal. operational description SYNCSEP details. Data output possesses propagation delay (Td_8) ranges from 2.2ns (min.) 3.8ns (max.) versus clock output from pin. operating frequency 4:2:2 Data Mode 100MHz sampling clock frequency. Although RA7, RB7, GB7, into output mode when operates 4:2:2 Data Mode, they cannot high impedance. output high impedance when this into power save mode. interface following type possible when this 4:2:2 Data Mode.
CXA3506R XCLK Td_8 2.2ns (min.) 3.8ns (max.) max. min.
Scaling
1/2CLK 1/2XCLK
hold time post-stage scaling using interface shown above (min.) 2.2ns
CXA3506R
(4:2:2 Data special Mode) YCbCr analog input signal coupled optimized using 3-ch signal input ADC. analog input signal sampled using clock generated PLL. identical signal with sampling clock analog input signal output from (Pin 99). 4:2:2 Data special Mode, only signal converted just Straight Data Mode output data output ports GA7. signals converted every other sampling half sampling rate signal, then multiplexed within output data output ports order (Cb) (Cr). When SYNC signal input, necessary separate SYNC signal superimposed signal. operational description SYNCSEP details. data output possesses propagation delay (Td_8) ranges from 2.2ns (min.) 3.8ns (max.) versus clock output from pin. operating frequency 4:2:2 Data special Mode 100MHz sampling clock frequency. addition, although RA7, RB7, GB7, into output mode when operates 4:2:2 Data Special Mode, they cannot high impedance. output high impedance when this into power save mode. interface following type possible when this 4:2:2 Data Mode.
CXA3506R XCLK 1/2CLK 1/2XCLK max. min. Td_8 2.2ns (min.) 3.8ns (max.)
Scaling
hold time post-stage scaling using interface shown above (min.) 2.2ns
CXA3506R
EVEN/ODD function When toggle signal created dividing Vsync signal half input EVEN/ODD (Pin 108), sampling clock inverted every Vsync signal. This function used configure single frame screen from fields converting analog input signal that requires high speed high resolution, such UXGA 60Hz (162MHz) more signal, half frequency original sampling rate. There particular control register settings when using EVEN/ODD function. sampling clock inverted based polarity signal input EVEN/ODD pin. sure input signal EVEN/ODD level. EVEN/ODD Operational mode EVEN
Example Using EVEN/ODD Function
Analog input signal EVEN field field
Hsync Sampling
Vsync Toggle signal (EVEN/ODD pin)
EVEN/ODD frame
CXA3506R
Output High Level Setting output pins high level control register. output pins simultaneously. output pins follows. RA0, RB0, GA0, GB0, BA0, BB0, SEROUT, SOGOUT, Delay Sync Output, 1/2CLK, 1/2XCLK, XCLK Register: TTLOUT High level (typ.) 2.2V 2.45V 2.7V 2.95V
output input directly power supply without level conversion. high level accordance with supply voltage.
Power Save Power save functions functions chip stopped save power XPOWER SAVE (Pin control register also power save mode this time. XPOWER SAVE Operating status input level level. Power save every block using control register blocks except registers also power save mode control register. Selects according using state. Register Power Save Power Save Power Save SYNC Power Save Power Power Power Power Power save Power save Power save Power save Power save Power
CXA3506R
Output Mode during Power Save Mode output pins high impedance when into power save mode. Since this supports power reset, AMP, ADC, PLL, SYNCSEP power save mode when power turned output pins high impedance. However, note that output pins don't change into high impedance, when control register used each output disable mode separately. Even though there also modes which data output ports output mode based operational mode, cannot high impedance. Data Output Modes XPOWER Straight SAVE Power Save mode mode mode Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DATA DATA DATA DMUX Parallel mode DATA DATA DATA DATA DATA DATA DMUX 4:2:2 4:2:2 Interleaved Special mode mode mode DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA
Other Output Modes XPOWER XCLK 1/2CLK SAVE Power Save Disable Disable Disable mode mode Hi-Z Hi-Z Signal Signal Hi-Z Hi-Z Signal Signal Hi-Z Hi-Z Signal Signal Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal 1/2XCLK Disable Signal Signal Signal Signal Signal Signal Signal DSYNC SOGOUT SEROUT UNLOCK Disable Disable Disable Disable Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal
XCLK 1/2CLK 1/2XCLK DSYNC/ DIVOUT SOGOUT SEROUT UNLOCK
dash indicates output status that cannot high impedance.
CXA3506R
Supply Current default value current consumption control register-based power save current (ICC5PS, ICC3PS), power save current (ICC5XPS, ICC3XPS) when XPOWER SAVE function used, indicated each block follows. (The current consumption values given here typical values when clock frequency 80MSPS.) Current Register current current Supply consumption consumption voltage consumption (typ.) 3.3V 17.2mA 80.0mA 16.0mA 41.4mA 6.8mA 73.2mA 180mA 17.2mA 0.7mA 2.0mA 0.4mA 6.0mA 3.0mA 1.2mA 0.7mA 1.0mA 0.4mA 6.0mA 3.0mA
Block Register
Supply names
DVCCREG (SYNCSEP) AVCCAMP AVCCVCO AVCCIR DVCCPLL DVCCPLLTTL AVCCADREF DVCCAD DVCCADTTL AVCCAD3 DVCCAD3
AVCCAMP AVCCAMPR AVCCAMPG AVCCAMPB
Timing Chart (Td1 3CLK)
6CLK
Analog input
Td_3 (typ. 7ns)
SYNCIN1 (Pin 111) SYNCIN2 (Pin 112)
1CLK
(Pin
Td_2 1/32 64/32CLK Td_1 3CLK Td_4 (typ. 1.0ns)
DSYNC signal (Pin 103) (DSYNC By-pass
Td_5 4CLK 8CLK Td_5 5CLK Td_6 (typ. 1.2ns) Td_6 (typ. 1.2ns)
RESET (Internal Signal)
DIVOUT signal (Pin 103) (DSYNC By-pass DIVOUT Delay
DIVOUT signal (Pin 103) (DSYNC By-pass DIVOUT Delay
8CLK
1/2CLK (Pin 101) EVEN)
1/2CLK (Pin 101) ODD)
Data Output (Straight Mode)
CXA3506R
Timing Chart (Td1 4CLK)
6CLK
Analog input
Td_3 (typ. 7ns)
SYNCIN1 (Pin 111) SYNCIN2 (Pin 112)
1CLK
(Pin
Td_2 1/32 64/32CLK Td_1 4CLK Td_4 (typ. 1.0ns)
DSYNC signal (Pin 103) (DSYNC By-pass
Td_5 4CLK Td_5 5CLK Td_6 (typ. 1.2ns) Td_6 (typ. 1.2ns)
RESET (Internal Signal)
DIVOUT signal (Pin 103) (DSYNC By-pass DIVOUT Delay
8CLK
DIVOUT signal (Pin 103) (DSYNC By-pass DIVOUT Delay
8CLK
1/2CLK (Pin 101) EVEN)
1/2CLK (Pin 101) ODD)
Data Output (Straight Mode)
CXA3506R
Timing Chart (Td1 5CLK)
6CLK
Analog input
Td_3 (typ. 7ns)
SYNCIN1 (Pin 111) SYNCIN2 (Pin 112)
1CLK
(Pin
Td_2 1/32 64/32CLK Td_1 5CLK Td_4 (typ. 1.0ns)
DSYNC signal (Pin 103) (DSYNC By-pass
Td_5 4CLK Td_5 5CLK Td_6 (typ. 1.2ns) Td_6 (typ. 1.2ns)
RESET (Internal Signal)
DIVOUT signal (Pin 103) (DSYNC By-pass DIVOUT Delay
8CLK
DIVOUT signal (Pin 103) (DSYNC By-pass DIVOUT Delay
8CLK
1/2CLK (Pin 101) EVEN)
1/2CLK (Pin 101) ODD)
Data Output (Straight Mode)
CXA3506R
Timing Chart (Td1 6CLK)
6CLK
Analog input
Td_3 (typ. 7ns)
SYNCIN1 (Pin 111) SYNCIN2 (Pin 112)
1CLK
(Pin
Td_2 1/32 64/32CLK Td_1 6CLK Td_4 (typ. 1.0ns)
DSYNC signal (Pin 103) (DSYNC By-pass
Td_5 4CLK Td_5 5CLK Td_6 (typ. 1.2ns) Td_6 (typ. 1.2ns)
RESET (Internal Signal)
DIVOUT signal (Pin 103) (DSYNC By-pass DIVOUT Delay
8CLK
DIVOUT signal (Pin 103) (DSYNC By-pass DIVOUT Delay
8CLK
1/2CLK (Pin 101) EVEN)
1/2CLK (Pin 101) ODD)
Data Output (Straight Mode)
CXA3506R
CXA3506R
Timing Diagram
Clock XCLK 2.0V 0.8V Td_6 min. typ. max. 0.9ns 1.2ns 1.6ns min. 0.8ns 1.0ns typ. 1.4ns 1.5ns max. 2.3ns 2.8ns
TR_CLK TF_CLK
1/2CLK clock 1/2XCLK TR_CLK TF_CLK 2.0V 0.8V min. 0.8ns 1.0ns typ. 1.4ns 1.5ns max. 2.3ns 2.8ns
Data
2.0V 0.8V Td_8 min. typ. max. 2.2ns 2.8ns 3.8ns min. 0.9ns 0.9ns typ. 1.2ns 1.2ns max. 2.0ns 2.0ns
TR_DATA TF_DATA
timing diagram above supposes that data cycle represents same amount time clock cycle concerning three modes follows: Straight Data Mode, 4:2:2 Data Mode, 4:2:2 Data special Mode.
CXA3506R
Timing Diagram
Clock XCLK 2.0V 0.8V Td_6 min. typ. max. 0.9ns 1.2ns 1.6ns min. 0.8ns 1.0ns typ. 1.4ns 1.5ns max. 2.3ns 2.8ns
TR_CLK TF_CLK
1/2CLK clock 1/2XCLK 2.2ns min. 1.3ns min. TR_CLK TF_CLK 2.0V 0.8V min. 0.8ns 1.0ns typ. 1.4ns 1.5ns max. 2.3ns 2.8ns
Data
2.0V 0.8V Td_7 min. typ. max. 2.3ns 2.6ns 3.2ns min. 0.9ns 0.9ns typ. 1.2ns 1.2ns max. 2.0ns 2.0ns
TR_DATA TF_DATA
timing diagram above supposes DMUX Parallel Data Mode. possible post-stage scaling acquire data using clock. output delay time this mode same that DMUX Interleaved Data Mode.
CXA3506R
Timing Diagram (Straight Data Mode)
Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) pin) XCLK pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data
CXA3506R
Timing Diagram (DMUX Parallel Data Mode)
Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) pin) XCLK pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data
CXA3506R
Timing Diagram (DMUX Interleaved Data Mode)
Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) pin) XCLK pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data
CXA3506R
Timing Diagram (4:2:2 Data Mode)
Analog input RIN1 (139 pin) RIN2 (141 pin)
GIN1 (124 pin) GIN2 (126 pin)
BIN1 (133 pin) BIN2 (136 pin)
SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) pin) XCLK pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data
(U3) (V3) (U5) (V5)
(U7) (V7)
CXA3506R
Timing Diagram (4:2:2 Data special Mode)
Analog input RIN1 (139 pin) RIN2 (141 pin)
GIN1 (124 pin) GIN2 (126 pin)
Cr10
BIN1 (133 pin) BIN2 (136 pin)
SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) pin) XCLK pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data
(V3) (U3) (V4) (U5) (V6)
(U7) (V8)
CXA3506R
Timing Diagram (Straight Data Mode, EVEN/ODD) EVEN
Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) pin) XCLK pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data
Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) pin) XCLK pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data
CXA3506R
Timing Diagram (DMUX Parallel Data Mode, EVEN/ODD) EVEN
Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) pin) XCLK pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data
Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) pin) XCLK pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data
CXA3506R
Timing Diagram (DMUX Interleaved Data Mode, EVEN/ODD) EVEN
Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) pin) XCLK pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data
Analog input RIN1 (139 pin) RIN2 (141 pin) GIN1 (124 pin) GIN2 (126 pin) BIN1 (133 pin) BIN2 (136 pin) SYNCIN1 (111 pin) SYNCIN2 (112 pin) DSYNC (103 pin) pin) XCLK pin) 1/2CLK (101 pin) 1/2XCLK (100 pin) Data
CXA3506R
Main Contrast Control Characteristics
Contrast Control Characteristics
Gain adjustment ratio
Gain [dB]
contrast
Main contrast
Main Contrast register
Contrast register
Brightness Level Control Characteristics
output conversion level (LSB) output conversion level (LSB) Brightness register
CbCr Clamp Level Control Characteristics
CbCr offset register
SYNC Control Characteristics
register
SYNC VHYS Control Characteristics
VHYS [mV]
[mV]
VHYS register
CXA3506R
Frequency Response
Gain [dB] Main contrast contrast Gain fluctuation ratio Frequency [MHz]
Gain Temperature Characteristics
Main contrast contrast
Ambient temperature [°C]
Gain Supply Voltage Characteristics
Gain fluctuation ratio -0.5 -1.0 -1.5 -2.0 4.75 Main contrast contrast output fluctuation (LSB)
Brightness Level Temperature Characteristics
-0.1 Brightness -0.2
Supply voltage
5.25
-0.3
Ambient temperature [°C]
Brightness Supply Voltage Characteristics
CbCr Clamp Level Temperature Characteristics
output level fluctuation (LSB)
output level fluctuation (LSB)
-0.5
-0.2 CbCr offset register -0.4
-1.0 Brightness -1.5 4.75 Supply voltage 5.25
-0.6
Ambient temperature [°C]
CXA3506R
CbCr Clamp Level Supply Voltage Characteristics
KVCO Characteristics
output level fluctuation (LSB)
Output frequency [MHz]
-0.2 CbCr offset register -0.4
-0.6 4.75
Supply voltage
5.25
control voltage
Fine Delay Control
Fine delay [1/32CLK] Fine delay register control [1/32CLK]
Jitter Peak-Peak Output Frequency
Jitter peak-peak [ns] Output frequency [MHz] NTSC, VGA, SVGA, XGA, 1/8, 1/4, 1/4, 1/2, 1/2, 010, 010, 010, 100, 011,
CXA3506R
Current Consumption Temperature Characteristics
Current Consumption Supply Voltage Fluctuation
Current consumption [mA]
Current consumption [mA]
ICC5 ICC3
ICC5 ICC3 4.75
Supply voltage
5.25
VCC3 VCC5
Ambient temperature [°C]
Current Consumption Frequency Response
Operational mode: DMUX parallel Data Load capacitance: 10pF Current consumption [mA]
ICC5 ICC3
FCLK Clock frequency [MHz]
Application Circuit (I2C (High) mode)
AGNDADREF AVCCAD3
DVCCAD
DVCCADTTL
DGNDADTTL
DGNDAD3
AGNDAD3
DGNDAD3
DGNDADTTL DVCCADTTL DGNDADTTL DGNDAD3 DVCCADTTL GNDAD3 DGNDADTTL DVCCADTTL DGNDAD3 DGNDADTTL DGNDAD3 DVCCADTTL
EVEN/ODD
XTLOAD
HOLD
SOGOUT
UNLOCK
DSYNC/DIVOUT
DPGND
1/2CLK
1/2XCLK
XCLK
DGNDPLLTTL
XCLKIN
DVCCPLLTTL
DVCCAD3
CLKIN
This application circuit which controls this with (High) mode supports RGB2 channel input. operational mode supports DMUX Parallel mode DMUX Interleaved mode. (I2C slave address 10011000.)
SYNCIN1
SYNCIN2
CLPIN
DVCCPLL
DGNDPLL
100p
AVCCVCO
AGNDVCO
330p
3.3k 0.33µ
AVCCIR
100p
IREF
DPGND
AGNDIR
0.1µ
G/YIN1
AVCCAMPG
DPGND AVCCAD3 DVCCAD3 DGNDAD3 AGNDAD3 DGNDAD3
R/CrOUT
B/CbOUT
ADDRESS
DVCCREG
SEROUT
DGNDREG
XSENABLE
3WIRE/I2C
DVCCADTTL
AVCCADREF
DGNDADTTL
DVCCADTTL
XPOWER SAVE
4.7k
4.7k
DGNDADTTL
0.1µ
G/YIN2
AGNDAMPG
0.1µ
G/YCLP
0.1µ
B/CbCLP
0.1µ
R/CrCLP
0.1µ
DPGND
SOGIN1
B/CbIN1
0.1µ 0.1µ
AVCCAMPB
SOGIN2
0.1µ
B/CbIN2
AGNDAMPB
DPGND
0.1µ
R/CrIN1
AVCCAMPR
0.1µ
R/CrIN2
AGNDAMPR
G/YOUT
DACTESTOUT
Application circuits shown typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits infringement third party patent other right same.
AVCC5V DVCC5V
3.3V
CXA3506R
DGND
AGND
Application Circuit (3-wire mode)
This application circuit which controls this with 3-wire mode operates with 4:2:2 Data mode with respect YcbCr analog input signal.
AGNDADREF AVCCAD3
DVCCAD
DVCCADTTL
DGNDADTTL
DGNDAD3
AGNDAD3
DGNDAD3
DGNDADTTL DVCCADTTL DGNDADTTL DGNDAD3 DVCCADTTL GNDAD3 DGNDADTTL DVCCADTTL DGNDAD3 DGNDADTTL DGNDAD3 DVCCADTTL
EVEN/ODD
XTLOAD
HOLD
SOGOUT
UNLOCK
DSYNC/DIVOUT
DPGND
1/2CLK
1/2XCLK
XCLK
DGNDPLLTTL
SEROUT DVCCREG DGNDREG XSENABLE R/CrOUT B/CbOUT ADDRESS DPGND AVCCAD3 DVCCAD3 3WIRE/I2C DGNDAD3 AGNDAD3 DGNDAD3 AVCCADREF
XCLKIN
CLKIN
SYNCIN1
SYNCIN2
CLPIN
DVCCPLL
DGNDPLL
100p
AVCCVCO
AGNDVCO
330p
3.3k 0.33µ
AVCCIR
100p
IREF
DPGND
AGNDIR
0.1µ
G/YIN1
AVCCAMPG
DVCCADTTL
DVCCADTTL
DGNDADTTL
XPOWER SAVE
4.7k
4.7k
DGNDADTTL
TP-B TP-R
G/YIN2
AGNDAMPG
0.1µ
G/YCLP
0.1µ
B/CbCLP
0.1µ
R/CrCLP
0.1µ
DPGND
SOGIN1
0.1µ
B/CbIN1
AVCCAMPB
SOGIN2
B/CbIN2
AGNDAMPB
DPGND
0.1µ
R/CrIN1
AVCCAMPR
R/CrIN2
AGNDAMPR
G/YOUT
DACTESTOUT
TP-G
DVCCPLLTTL
DVCCAD3
Application circuits shown typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits infringement third party patent other right same.
AVCC5V DVCC5V
3.3V
CXA3506R
DGND
AGND
CXA3506R
Notes Operation board, prepare solid ground pattern having large area possible, placing center, divide this area into analog region digital region. loop filter area block plays important role terms performance. therefore located close possible pins periphery guarded with AGND. Also, sure capacitors resistors loop filter that should temperature compensated change values. sure metal film resistor resistor connected IREF (Pin 121). wiring SYNCIN1 (Pin 111) SYNCIN2 (Pin 112) should short possible each needs shielded ground. 0.1µF ceramic chip capacitor bypass capacitor attached between power supply ground. capacitor should attached close possible. ceramic chip capacitor capacitor attached (Pin (Pin connect AVCCAD3 (Pin close possible. Equalize shorten lines analog input signals, possible. Each line needs shielded ground. (This same R/CrCLP, G/YCLP, B/CbCLP pins.) 0.1µF capacitor recommended attachment analog input pins. less capacitance becomes, more leak current becomes. more capacitance becomes, more start time takes case putting power source into (This same R/CrCLP, G/YCLP, B/CbCLP pins.) Design boards that wiring R/CrIN, G/YIN, B/CbIN R/CrOUT, G/YOUT, B/CbOUT pins separated possible. pattern width that takes characteristic impedance into account signal wires terminated There particular restrictions power-on sequence. Although there AVCCAD3 DVCCAD3 3.3V power supply, same 3.3V analog power supply each board. AGNDAD3 DGNDAD3 ground AVCCAD3 DVCCAD3, respectively. same ground AGNDAD3 DGNDAD3. Although AGND ground recommended AGNDAD3 DGNDAD3, there problems terms operation even connected DGND. (The special evaluation board Application Circuit connected DGND.) Although power supply divided into both analog digital power supply lines, sure wire boards that potential difference arises between these power supplies. Load capacitance data output wires causes change worse slew rate noise. sure short layouts with finest wires possible. this into power save mode when making connection between data output another (High impedance cannot when pins disabled separately.)
CXA3506R
CXA3506R Evaluation Board Overview CXA3506R Evaluation Board special board designed easy evaluation CXA3506R developed projector monitor that performance maximized. DSUB 15-pin connector used input connector that allows direct input video signal from input video signal converted CXA3506R monitoring designed onto board that output data checked directly. 10-bit high speed converters built onto board that performance easily checked. Picture quality easily evaluated using monitor since D/A-converted video signal output from DSUB 15-pin connector output addition DSYNC output CXA3506R. Features Single power supply (with built-in 3.3V regulator) Allows two-line video signal input Data output port also used output data monitoring CXA3506R output converted easily monitored Supports types control registers (3-wire I2C) Operating Conditions Supply voltage: (typ.) Current consumption: 830mA (typ.) Input signal: Separated sync video signal
CXA3506R Block Diagram
Power supply pins CXA2016P Clamp pulse generation
CLPIN analog input signal 0.1µF Control signal
SOGOUT
Video
CON1 analog input signal 0.1µF CXA3506R
Video signal Hsync signal Vsync signal
digital output data
Output data monitoring pins data output ports
Video signal input pins
Vsync signal select analog output signal 10µF Power save 3WIRE/I2C logic 3Wire CON5 CON4 Control register pins
Video
Video signal Hsync signal
CON2
Vsync signal CXA3197R
Video
Video signal output pins
Video signal output Hsync output Vsync output
CON3
CXA3506R
CXA3506R
Using CXA3506R Evaluation Board CXA3506R Evaluation Board used easily evaluate just connecting power supply, video signals, control register signals. procedure described below. Connect power supply power connection pin. (GND/+5V) apply power supply this state. Check direction SW1. power save control switch. CXA3506R into power save mode when rear position forward position when using CXA3506R. connected XPOWER SAVE pin. Connect special control register signal cable. Connect cable CON4 when using control. forward position. While, connect cable CON5 when using 3-wire control. rear position. addition, check that short (I2C) "00" position case using control. Input analog signals from CON1 (Video XGA60 recommended initial signal because control program default value XGA60. XGA60: Vsync 60Hz Hsync: Video signal 48kHz 1344 analog signal simple picture quality evaluations output from CON3 (Video Out). sure connect CON3 monitor that process signal XGA60 more. Turn power. Check current about 360mA flows through power supply. there much more current than this, immediately turn power check that there misconnections. control program. Click "re-load" bottom right control program screen, check current about 830mA flows through power supply. everything works normally, processed image picture quality evaluation appears monitor. Reconfirm above items from beginning processed image does appear.
CXA3506R
3-wire Control Program Installation Startup Method [Operating Environment] Windows95 Windows98 [Program Installation Startup] installation program configured from following four files stored floppy disks. setup.exe, A3506_1.cab, A3506_2.cab, Setup.lst Copy four files from floppy disk onto Click setup.exe. installer will start. Follow on-screen instructions. Once installation complete, folder titled "Project1" will created Program files folder. following control window will open when A3506.exe file starts. this window make board settings response printer port address sure address from pull-down menu port top-left control screen. There types addresses: 3BC.
CXA3506R
Control Program Installation Startup Method [Operating Environment] Windows95 Windows98 [Program Installation Startup] installation program consists following four files stored floppy disks. setup.exe, A3506_1.cab, A3506_2.cab, Setup.lst Copy these four files from floppy disk onto Click setup.exe. installer will start. Follow on-screen instructions. Once installation complete, folder titled "Project1" will created Program files folder. following control window will open when A3506.exe file starts. this window make board settings response printer port address sure address from pull-down menu port top-left control screen. There types addresses: 3BC.
CXA3506R
Notes Using CXA3506R analog signals input from CON1 CON2 converted. digital signals converted. addition, analog signals output coupling. Therefore, output analog signals output from CON3. this reason, when analog signals output from CON3 undergo picture quality evaluation using monitor, note that on-screen evaluation cannot confirmed about functions BRIGHTNESS Cb/Cr OFFSET. This fact that component disappears because analog signals output coupled after output converter, even offset changed. current consumption this board immediately after turning board's power approximately 360mA. Board current 830mA when CXA3506R control register started after this. When turning power board, sure check board current make sure that connections correct. Although this board equipped with power supply pin, operate using single 0/+5V power supply. sure leave power supply open.
Notes Regarding Control Program When program accurately installed sure re-check items operational procedures above when does move. CXA3506R does move even after item above checked, possible that control signals control register output from printer board. this case, sure re-check board settings listed item under "Program Installation Startup".
CXA3506R
CXA3506R Evaluation Board Parts List Parts IC3, CON1, CON4 CON5 R17, R20, R24, R26, R28, R30, R38, R47, R49, 3.3k 2.2k Product name CXA3506R CXA2016S CXA3197R SN74LS04N SN74LS32N SN74LS08N LT1086CM-3.3 D02-N15SAG-13L9 53053-0510 53053-0610 G-12AP G-13AP G-22AP ZBF503D-00 Chip resistor Chip resistor Chip metal film resistor Lead metal film resistor Chip resistor Chip resistor Chip resistor Chip resistor Lead metal film resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor Chip resistor SONY SONY SONY Texas Instruments Texas Instruments Texas Instruments Linear Technology SANSHIN ELECTRONICS Molex Molex NIHON KAIHEIKI IND. NIHON KAIHEIKI IND. NIHON KAIHEIKI IND. C11, C13, C48, 2.2µ 100µ 0.1µ 100p 0.1µ 330p 0.33µ 0.1µ 0.1µ 0.1µ 0.22µ 0.1µ 0.22µ 0.1µ 0.01µ 3300p 0.1µ 0.1µ Tantalum capacitor Tantalum capacitor Tantalum capacitor Electrolytic capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Chip capacitor Manufacturer
CLAMP
DSYNC
VSYNC2 VSYNC1
SOGOUT
1/2CLK 1/2XCLK XCLK
AGND
Video Signal Data
EVEN/ODD XTLOAD DGND
UNLOCK
DVcc 0.1µ 0.1µ 0.1µ 0.1µ
3.3k 0.1µ 100p 330p 100p DVcc DGND AVcc AGND 0.1µ
EVEN/ODD XTLOAD HOLD SOGOUT UNLOCK DSYNC/DIVOUT DPGND 1/2CLK 1/2XCLK XCLK DGNDPLLTTL DVccPLLTTL AGNDADREF AVccAD3 DVccAD3 DVccAD DVccADTTL DGNDADTTL DGNDAD3 AGNDAD3 DGNDAD3 DGNDADTTL DVccADTTL
AVcc
AGND
0.1µ
CON1 0.1µ AVcc CXA3506R 0.1µ
AVcc 0.33µ 0.1µ 0.1µ AGND
0.1µ
0.1µ
AGND
AGND
AGND
GOUT AGND
ROUT BOUT
0.1µ
0.1µ
0.1µ
10010 10010 10010
Slave address 10010
XPOWER SAVE
3-Wire/I2C
0.1µ
0.1µ
B/CbOUT ADDRESS R/CrOUT XPOWER SAVE DGNDREG DVccREG XSENABLE SEROUT 3WIRE/I2C DPGND AVccADREF AVccAD3 DVccAD3 DVccADTTL DGNDADTTL DGNDAD3 AGNDAD3 DGNDAD3 DVccADTTL DGNDADTTL
CXA3506R
DGND DVcc
DVcc
DGND
DGND DVcc SENABLE SEROUT
AGND AVcc
DGND Register
0.1µ AGND 0.1µ 0.1µ 0.1µ 0.1µ AVcc 0.1µ 0.1µ 0.1µ AGND 0.1µ 0.1µ AGND AVcc AVcc 0.1µ
Video
AGND
CON2
0.1µ
XCLKIN CLKIN SYNCIN1 SYNCIN2 CLPIN DVccPLL DGNDPLL AVccVCO AGNDVCO AVccIR IREF DPGND AGNDIR G/YIN1 AVccAMPG G/YIN2 AGNDAMPG G/YCLP B/CbCLP R/CrCLP DPGND SOGIN1 B/CbIN1 AVvAMPB SOGIN2 B/CbIN2 AGNDAMPB DPGND R/CrIN1 AVccAMPR R/CrIN2 AGNDAMPR G/YOUT TEST
Video
DGNDADTTL DGNDAD3 DVccADTTL GNDAD3 DGNDADTTL DVccADTTL DGNDAD3 DGNDADTTL DGNDAD3 DVccADTTL
2.2µ CLAMP DSYNC 1/2CLK 1/2XCLK XCLK 3300p 0.1µ AGND AGND 0.22µ 0.22µ CXA2016S AVcc DVcc 0.1µ CLKP/E CLKN/E AGND DGND XCLK 0.1µ
SOGOUT
Data
Video Signal
0.1µ 0.22µ
VSIN AVcc Vssin CSIN Vssout 2.2k Videoin 0.1µ HDsel clpsel xclpout clpout 0.01µ AGND VssREF
DSYNC 1/2CLK 1/2XCLK XCLK
DGND
DGND
DGND
CXA3197R DVcc DVcc
0.1µ
0.1µ
CXA3197R
CXA3197R
0.1µ DVcc
1/2CLK CLK/T CLKP/E CLKN/E DGND1 DVcc1 RPOLARITY VOCLP AGND2 DGND2 DVcc2 AVccO AOUTN AOUTP AGND2 VREF VSET AVcc2 DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E AVcc2
DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E
DGND2
DGND1 DVcc1 RPOLARITY VOCLP AGND2
1/2CLK CLK/T CLKP/E CLKN/E
1/2CLK CLK/T CLKP/E CLKN/E
DGND1 DVcc1 RPOLARITY VOCLP AGND2
DVcc2 AVccO
VSYNC1
VSYNC2
DSYNC
0.1µ 0.1µ
0.1µ 0.1µ
0.1µ 0.1µ
0.1µ
0.1µ
DGND2 DVcc2 AVccO 0.1µ AOUTN AOUTP AGND2 VREF VSET 0.1µ AVcc2
Video Vsync
Video Vsync
DGND DGND 100µ
DGND
AOUTN AOUTP AGND2 VREF VSET
0.1µ
0.1µ
100µ
AVcc
CON3
AGND
AVEE
100µ
Video
AGND
CXA3506R
LT1086CM-3.3 Vout AVcc AGND AVEE DGND
DVcc
SEROUT SENABLE
3-Wire/I2C
IC6A IC6B IC6C IC6D 74AS04 74AS04 74AS04 IC7A 74AS32
Register
74AS04 IC8A 74AS08
DVcc
74AS08 IC8B
IC6E 74AS04 IC6F 74AS04
CON4 DGND DGND SENABLE SEROUT DVcc CON5 3-WIRE
0.1µ DGND CXA3506R 0.1µ 0.1µ
CXA3506R
CXA3506R
CXA3506R
CXA3506R
CXA3506R
Package Outline
Unit:
144PIN LQFP (PLASTIC)
22.0 20.0
0.05 0.08 0.20 0.03
(21.0)
DETAIL
0.15
DETAIL
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L01 LQFP144-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY
0.125 0.04
Sony Corporation
Other recent searches
TLV2361 - TLV2361 TLV2361 Datasheet
TLV2362 - TLV2362 TLV2362 Datasheet
SR730CSDP - SR730CSDP SR730CSDP Datasheet
S75WS-N - S75WS-N S75WS-N Datasheet
LD14706-17 - LD14706-17 LD14706-17 Datasheet
LD14706-18 - LD14706-18 LD14706-18 Datasheet
LA4275 - LA4275 LA4275 Datasheet
DBS27P - DBS27P DBS27P Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
