3.3V CMOS 16-BIT IDT74LVCH162374A EDGE TRIGGERED D-TYPE FLIPFLOP WITH

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3.3V CMOS 16-BIT IDT74LVCH162374A EDGE TRIGGERED D-TYPE FLIPFLOP WITH

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IDT74LVCH162374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
3.3V CMOS 16-BIT IDT74LVCH162374A EDGE TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, VOLT TOLERANT I/O, BUS-HOLD
Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP 0.40mm pitch TVSOP packages Extended commercial range -40°C +85°C 3.3V ±0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs Volt tolerant Supports insertion
DESCRIPTION:
LVCH162374A 16-bit edge-triggered D-type flip-flop built using advanced dual metal CMOS technology. This high-speed, low-power register ideal buffer register data synchronization storage. output enable (OE) clock (CLK) controls organized operate each device 8-bit registers 16-bit register with common clock. Flow-through organization signal pins simplifies layout. inputs designed with hysteresis improved noise margin. pins LVCH162374A driven from either 3.3V devices. This feature allows this device translator mixed 3.3V/5V supply system. LVCH162374A series resistors device output structure which will significantly reduce line noise when used with light loads. This driver been developed drive 12mA designated thresholds. LVCH162374A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
Drive Features LVCH162374A: Balanced Output Drivers: ±12mA switching noise
APPLICATIONS:
3.3V mixed voltage systems Data communication telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
SEVEN OTHER CHAN NELS
SEVEN OTHER CHAN NELS
1999 Integrated Device Technology, Inc.
AUGUST 1999
DSC-4678/-
IDT74LVCH162374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Unit
Link
SO48-1 SO48-2 SO48-3
Symbol VTERM(2) VTERM(3) TSTG IOUT
Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each
Max. +6.5 +6.5 +150 ±100
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25OC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
Link
NOTE: applicable device type.
FUNCTION TABLE (each flip-flop)
Inputs xCLK Outputs
SSOP/ TSSOP/ TVSOP VIEW
DESCRIPTION
Names xCLK Description Data Inputs Clock Inputs 3-State Outputs 3-State Output Enable Inputs (Active LOW)
NOTE: These pins have "Bus-hold". other pins standard inputs, outputs, I/Os.
NOTE: HIGH Voltage Level Voltage Level Don't Care High-Impedance Level before indicated steady-state input conditions were established.
1998 Integrated Device Technology, Inc.
DSC-123456
IDT74LVCH162374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40OC +85OC
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, 18mA 3.3V 3.6V 5.5V(2) Quiescent Power Supply Current Variation input 0.6V other inputs
Link
Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 5.5V 5.5V
Min.
Typ.(1)
Max.
Unit
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
Link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
IDT74LVCH162374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 2.7V 3.0V Output Voltage 2.3V 3.6V 2.3V 2.7V 3.0V 12mA 0.1mA 12mA Min. Max. 0.55 0.55
Link
Unit
2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C +85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance flip-flop Outputs enabled Power Dissipation Capacitance flip-flop Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
SWITCHING CHARACTERISTICS
Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xCLK Output Enable Time Output Disable Time Set-up Time HIGH LOW, before xCLK Hold Time HIGH LOW, after xCLK xCLK Pulse Width HIGH Output Skew(2)
2.7V Min. Max. 3.3V±0.3V Min. Max. Unit
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH162374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) 2.7V VCC(2)= 2.5V ±0.2V Unit
Link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
Link
TEST CIRCUITS OUTPUTS
Pulse Generator D.U.T. LOAD Open
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT OUTPUT ITCH NORMALLY tPZH OUTPUT ITCH NORMALLY OPEN HIGH LOAD/2 tPHZ DISABLE LOAD/2
Link
Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator.
NOTE: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
Open
Link
OUTPUT SKEW
INPUT tPLH1 PHL1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
OUTPUT
OUTPUT PLH2 tPHL2
tPLH2 tPLH1 tPHL2
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
Link
IDT74LVCH162374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
ORDERING INFORMATION
Bus-Hold Family XXXX Device Type Package Temp. Range
374A
Shrink Small Outline Package (SO48-1) Thin Shrink Small Outline Package (SO48-2) Thin Very Small Outline Package (SO48-3) 16-Bit Edge Triggered -Type Flip-Flop Double-D ensity with Resistors, ±12m
Bus-hold -40°C +85°C
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3.3V CMOS 16-BIT IDT74LVCH162374A EDGE TRIGGERED D-TYPE FLIPFLOP WITH

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