8-bit 120MSPS Flash Converter Description CXA3246Q 8-bit high-spe
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CXA3246Q
8-bit 120MSPS Flash Converter
Description CXA3246Q 8-bit high-speed flash converter capable digitizing analog signals maximum rate 120MSPS. ECL, PECL selected digital input level accordance with application. digital output level allows demultiplexed output. Features Differential linearity error: ±0.5LSB less Integral linearity error: ±0.5LSB less High-speed operation with maximum conversion rate 120MSPS input capacitance: 10pF Wide analog input bandwidth: 250MHz power consumption: 500mW demultiplexed output frequency-divided clock output (with reset function) Compatible with ECL, PECL digital input levels output levels: 2.8V (Typ.) +3.3V line CMOS direct connecting available Single power supply operation available Surface mounting package (48-pin QFP) Configuration (Top View)
DGND3 AVCC DVEE3
RESETN/E RESET/E RESETN/T SELECT CLKOUT DVCC2 DGND2 PBD7 PBD6 PBD5 PBD4
(Plastic)
LEAD TREATMENT: PALLADIUM PLATING
Structure Bipolar silicon monolithic Applications Magnetic recording (PRML) Communications (QPSK, QAM) LCDs Digital oscilloscopes
AGND
CLK/E CLKN/E CLK/T N.C. N.C. N.C. DVCC2 DGND2 PAD0 PAD1 PAD2 PAD3
AGND
AVCC
VRM3
VRM2
VRM1
DGND2
DGND1
PBD1
PAD7
PAD5
DVCC1
PBD0
PAD4
PAD6
Sony reserves right change products specifications without prior notice. This information does convey license implication otherwise under patents other right. Application circuits shown, any, typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits.
DVCC2
PBD2
PBD3
E97902A8X-PS
CXA3246Q
Absolute Maximum Ratings 25°C) Unit AVCC, DVCC1, DVCC2 -0.5 +7.0 DGND3 -0.5 +7.0 DVEE3 -7.0 +0.5 DGND3 DVEE3 -0.5 +7.0 AVCC Analog input voltage Reference input voltage AVCC AVCC |VRT VRB| Digital input voltage ECL/PECL input DVEE3 DGND3 input DGND1 DVCC1 VID1 (|/E N/E|) Storage temperature Tstg +150 Allowable power dissipation (when mounted two-layer glass fabric base epoxy board with dimentions 50mm 50mm, 1.6mm thick) Supply voltage Recommended Operating Conditions With single power supply With dual power supply Unit Min. Typ. Max. Min. Typ. Max. Supply voltage DVCC1, DVCC2, AVCC +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 DGND1, DGND2, AGND -0.05 +0.05 -0.05 +0.05 DGND3 +4.75 +5.0 +5.25 -0.05 +0.05 DVEE3 -0.05 +0.05 -5.5 -5.0 -4.75 Analog input voltage Reference input voltage +2.9 +4.1 +2.9 +4.1 +1.4 +2.6 +1.4 +2.6 |VRT VRB| Digital input voltage ECL/PECL input DVEE3 DGND3 DVEE3 DGND3 DVEE3 DVEE3 input VID1 (|/E N/E|) Maximum conversion rate (Straight mode) MSPS (DMUX mode) MSPS Ambient temperature
VID: Input Voltage Differential PECL switching level
DGND3 (max.) (DGND3 1.2V) (min.)
CXA3246Q
Description [Symbol] DVEE3 AGND VRM1 AVCC VRM2 AVCC VRM3 AGND DGND3 CLK/E CLKN/E CLK/T N.C. DVCC2 DGND2 PAD0 PAD7 DGND1 DVCC1 DVCC2 DGND2 PBD0 PBD7 DGND2 DVCC2 CLKOUT SELECT RESETN/T RESET/E RESETN/E [Pin No.] [Description] Digital power supply Bottom reference voltage Analog ground Reference voltage point Analog power supply Analog signal input Reference voltage point Analog power supply Reference voltage point Analog ground Reference voltage (typ.) Digital power supply ECL/PECL clock input ECL/PECL clock input clock input connected Digital power supply Digital ground side data output Digital ground Digital power supply Digital power supply Digital ground side data output Digital ground Digital power supply Clock output Data output polarity inversion Output mode selection reset input ECL/PECL reset input ECL/PECL reset input Typical voltage level with single power supply 2.6V 4.1V PECL PECL PECL PECL Typical voltage level with dual power supply -5.0V 2.6V 4.1V
CXA3246Q
Block Diagram
AVCC
DVCC1
DVCC2
DGND3
(MSB) PBD7 PBD6
VRM3
6bit
PBD5
LATCH
TTLOUT
8bit
PBD4 PBD3 PBD2
6bit
PBD1
6bit LATCH ENCODER
VRM2
ENCODER
PBD0 (LSB)
(MSB) PAD7 PAD6 PAD5
VRM1
6bit
LATCH
LATCH
TTLOUT
PAD4 PAD3 PAD2 PAD1
8bit 6bit
CLK/T CLK/E CLKN/E
PAD0 (LSB) N.C. N.C. N.C. Select CLKOUT
RESETN/T RESETN/E RESET/E AGND
SELECT
DGND1
DGND2
DVEE3
CXA3246Q
Description Equivalent Circuit Symbol AGND Standard voltage level (typ.) (typ.) (typ.) (With single power supply) (With dual power supply) (With single power supply) (typ.) (With dual power supply) N.C. Equivalent circuit Description Analog ground. Separated from digital ground. Analog power supply. Separated from digital power supply. Digital ground. Digital power supply.
AVCC
DGND1 DGND2 DVCC1 DVCC2
DGND3
Digital power supply. Ground input. PECL inputs.
DVEE3
Digital power supply. input. Ground PECL inputs.
connected pin. connected with internal circuits.
CXA3246Q
Symbol CLK/E
Standard voltage level
Equivalent circuit Clock input.
Description
CLKN/E
DGND3
ECL/ PECL RESETN/E
CLK/E complementary input. When left open, this goes threshold voltage. Only CLK/E used operation, complementary inputs recommended attain fast stable operation. Reset signal input. When level, built-in frequency divider circuit reset. RESETN/E complementary input. When left open, this goes threshold voltage. Only RESETN/E used operation. Clock input.
DVEE3
RESET/E
CLK/T
DVCC1
RESETN/T
Reset signal input. When left open, this goes high level. When level, built-in frequency divider circuit reset. Data output polarity inversion input. When left open, this input goes high level. (See Table Correspondence Table.) Data output mode selection. (See Table Operation Mode Table.)
DGND1 DVEE3
1.5V
SELECT
CXA3246Q
Symbol
Standard voltage level 4.0V (typ.)
Equivalent circuit
Description reference voltage. By-pass AGND with tantal capacitor 0.1µF chip capacitor. Reference voltage point. By-pass AGND with 0.1µF chip capacitor. Reference voltage point. By-pass AGND with 0.1µF chip capacitor. Reference voltage point. By-pass AGND with 0.1µF chip capacitor. Bottom reference voltage. By-pass AGND with tantal capacitor 0.1µF chip capacitor.
VRM3
(VRT VRB)
Comparator
Comparator Comparator
VRM2
(VRT VRB)
Comparator Comparator
VRM1
(VRT VRB)
Comparator Comparator
Comparator
2.0V (typ.)
AVCC
Comparator AVCC
Analog input.
Vref
DVEE3
AGND
PAD0 PAD7 PBD0 PBD7
DVCC1 DVCC2
Port side data output. output; high level clamped approximately 2.8V. Port side data output. output; high level clamped approximately 2.8V. Clock output. (See Table Operation Mode Table.) output; high level clamped approximately 2.8V.
100k
DGND2 DVEE3
DGND1
CLKOUT
CXA3246Q
Electrical Characteristics (AVCC, DVCC1, DGND3 +5V, AGND, DGND1, DVEE3 25°C) Item Resolution characteristics Integral linearity error Differential linearity error Analog input Analog input capacitance Analog input resistance Analog input current Reference input Reference resistance Reference current Offset voltage side side Digital input (ECL, PECL) Digital input voltage: High Threshold voltage Digital input current High Digital input capacitance Digital input (TTL) Digital input voltage: High Threshold voltage Digital input current High Digital input capacitance Digital output (TTL) Digital output voltage High Switching characteristics Maximum conversion rate Aperture jitter Sampling delay Clock high pulse width Clock pulse width Reset signal setup time Reset signal hold time Clock output delay Data output delay Output rise time Output fall time Rref2 Iref3 Symbol Conditions Min. Typ. ±0.5 ±0.5 Max. Unit bits
2Vp-p, 5MSPS
+3.0V 0.07Vrms DVEE3 DVEE3
DGND3
DGND3
DGND3 0.8V DGND3 1.6V
3.5V 0.2V
Tpw1 Tpw0 T_rs T_rh Td_clk Tdo1 Tdo2
-2mA DMUX mode
-0.5
MSPS
RESETN RESETN DMUX mode 2.0V 2.0V 5pF) 5pF) 5pF) 5pF) 5pF)
These characteristics PECL input unless otherwise specified.
CXA3246Q
Item Dynamic characteristics Input bandwidth ratio
Symbol
Conditions 2Vp-p, -3dB 120MSPS, 1kHz DMUX mode 120MSPS, 29.999MHz DMUX mode 120MSPS, 1kHz DMUX mode Error 16LSB 120MSPS, 29.999MHz DMUX mode Error 16LSB 100MSPS, 24.999MHz Straight mode Error 16LSB
Min.
Typ.
Max.
Unit
TPS5
Error rate
AICC DICC1 DICC2
10-12
10-9
10-9
Power supply Supply current AVcc supply current DVcc1 supply current DVcc2 supply current DGND3 supply current Power consumption
Rref: Resistance value between Iref Rref TPS: Times Sample (ICC IEE) (VRT VRB) Rref
CXA3246Q
Step
VRM2
Table Correspondence Table
CXA3246Q
Electrical Characteristics Measurement Circuit Current Consumption Measurement Circuit
AVCC DVCC1 DVCC2 DGND3
Sampling Delay Measurement Circuit Aperture Jitter Measurement Circuit
100MHz OSC1 Variable CXA3246Q Logic Analizer 1024 samples Buffer
1.95V
CLK/E
5MHz PECL OSC2
DGND2 DGND1 AGND
DVEE3
100MHz
Integral Linearity Error Measurement Circuit Differential Linearity Error Measurement Circuit
Aperture Jitter Measurement Method
VRM2 when when
Comparator CXA3246Q Controller Buffer
(LSB)
Sampling timing fluctuation aperture jitter)
Where (LSB) deviation output codes when largest slew rate point sampled clock which exactly same frequency analog input signal, aperture jitter Comparator Pulse Counter
Error Rate Measurement Circuit
Signal Source CXA3246Q Latch
1kHz 2Vp-p Sine Wave
Latch
16LSB Signal Source
CXA3246Q
Description Operation Modes CXA3246Q types operation modes which selected with (SELECT). Operation mode DMUX mode Straight mode SELECT Maximum conversion rate 120MSPS 100MSPS Data output Demultiplexed output 60Mbps Straight output 100Mbps Clock output input clock frequency divided output. 60MHz input clock inverted output. 100MHz
Table Operation Mode Table
DMUX mode (See Application Circuit 1-(1), (3).) SELECT this mode. this mode, clock frequency divided data output after being demultiplexed this frequency-divided clock. frequency-divided clock, which adequate setup time hold time output data, output from clock output pin. When using multiple CXA3246Q DMUX mode, start timing frequency-divided clocks becomes phase, producing operation such that shown example next page. countermeasure, CXA3246Q function that resets frequency-divided clocks. When resetting this frequency-divided clock, level reset signal should input RESETN (Pin 48). reset signal requires setup time (T_rs 1.0ns) hold time (T_rh -0.5ns) clock rising edge because synchronized with taken clock. reset period extended making level period reset signal longer because clock output fixed (reset) during level period clock rising edge. reset start timing regarded important, timing where reset signal from high consequence. However, when reset released timing where reset signal from high must become significant because timing used commence frequency-divided clock. this case, setup time (T_rs) also necessary. timing chart detail. (This chart shows example reset 2T.) converter operate (min.) 120MSPS this mode.
CXA3246Q
When reset signal used
CXA3246Q
CLKOUT 8bit DATA
RESETN
CXA3246Q
CLKOUT 8bit DATA
RESETN
When reset signal used
Reset signal CXA3246Q
RESETN
CLKOUT 8bit DATA
(Reset period)
CXA3246Q
CLKOUT 8bit DATA
(Reset period)
Reset signal
RESETN
Straight mode (See Application Circuits 1-(4), (6).) SELECT this mode. this mode, data output obtained accordance with clock frequency applied converter applications which clock applied converter system clock. converter operate (min.) 100MSPS this mode. Digital input level supply voltage settings logic input level CXA3246Q supports ECL, PECL levels. power supplies (DVEE3, DGND3) logic input block must match logic input (CLK reset signals) level. Digital input level PECL DVEE3 DGND3 Supply voltage Application circuits
Table Logic Input Level Power Supply Settings
CXA3246Q
Application Circuit DMUX input
RESET signal
+5V(D)
+5V(A) -5V(D)
PAD0 PAD7 Digital Data Latch PBD0 PBD7 Digital Data Latch
Digital Data
+5V(D)
+5V(A)
Digital Data
ECL-CLK +5V(D)
DMUX PECL input
PECL RESET signal
+5V(A)
+5V(D)
PBD0 PBD7 Digital Data
Digital Data Latch
+5V(D)
+5V(D)
+5V(A)
Digital Data PAD0 PAD7 Digital Data Latch
PECL-CLK +5V(D)
DMUX input
+5V(D) RESET signal
PBD0 PBD7 Digital Data Latch
Digital Data
+5V(A)
+5V(D)
+5V(D) +5V(A)
Digital Data PAD0 PAD7 Digital Data Latch
TTL-CLK +5V(D)
CXA3246Q
Straight input
+5V(D)
-5V(D)
PBD0 PBD7 8-bit Digital Data
8-bit Digital Data Latch
+5V(A)
+5V(D)
+5V(A)
ECL-CLK +5V(D)
Straight PECL input
+5V(D)
+5V(A)
PBD0 PBD7 8-bit Digital Data Latch
8-bit Digital Data
+5V(D)
+5V(D)
+5V(A)
PECL-CLK PECL +5V(D)
Straight input
+5V(D)
+5V(A)
PBD0 PBD7 8-bit Digital Data
8-bit Digital Data Latch
+5V(D)
+5V(D)
+5V(A)
TTL-CLK
+5V(D)
CXA3246Q
Application Circuit
DMUX Mode (When single power supply used)
Analog input
10µF short short 10µF
DGND3
AGND
CLK/E
RESETN/E RESET/E RESETN/T SELECT CLKOUT DVCC2 DGND2 PBD7 PBD6 PBD5
CLKN/E CLK/T N.C. N.C. N.C. DVCC2 DGND2 PAD0 PAD1 PAD2
DGND1
DGND2
DVCC1
DVCC2
PAD3
DVEE3
PBD4
AGND
VRM3
AVCC
VRM2
AVCC
VRM1
PBD0
PBD1
PAD4
PAD5
PAD6
PAD7
PBD2
PBD3
Short analog system digital system point immediately under converter. Notes Operation. chip capacitor 0.1µF. Also, important suppress noise generated during output circuit operating. Place fixed position between pins with shortest distance.
Application circuits shown typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits infringement third party patent other right same.
(MSB) PAD7
PBD6 (MSB) PBD7
(LSB) PAD0 PAD1
(LSB) PBD0
PAD2 PAD3
PAD5
PBD1
PBD2
PAD4
PBD3
PBD4 PBD5
PAD6
CXA3246Q
DMUX Mode Timing Chart (Select VCC)
(Pin 1.4ns (typ.)
(Pin Tpw1 Tpw0 Tdo2; 5.0ns (typ.) 3.5ns (min) 7.5ns (max) PAD0 (Pins 2.0V 0.8V
PBD0 (Pins Td_clk; 4.5ns (typ.) 7.0ns (max) 3.0ns (min) (Pin 2.0V 0.8V 2.0V 0.8V
Tdo1 0.5ns (typ.)
2.0V 0.8V
(Reset period)
2.0V 0.8V
T_rh RESETN (Pin
T_rs
T_rh
T_rs
CXA3246Q
Straight Mode Timing Chart (Select GND)
(Pin 1.4ns (typ.)
(Pin Tpw1 Tpw0
Tdo2; 5.0ns (typ.) 3.5ns (min) 7.5ns (max) PAD0 (Pins 2.0V 0.8V
PBD0 (Pins
2.0V 0.8V
Td_clk; 4.5ns (typ.) 3.0ns (min) 7.0ns (max) (CLK inverted output.) (Pin 2.0V 0.8V
CXA3246Q
Notes Operation CXA3246Q PECL input pins clock reset input pins. When clock input PECL level, inputting reset signal PECL level recommended. Also, when clock input level, inputting reset signal recommended. impedance input signal should properly matched ensure CXA3246Q's stable operation high speed. power supply grounding have profound influence converter performance. power supply grounding method particularly important during high-speed operation. General points caution follows. ground pattern should large possible. recommended make power supply ground patterns wider inner layer using multi-layer board. prevent interference between AGND DGND between AVcc DVcc, make sure respective patterns separated. prevent offset power supply pattern, connect AVcc DVcc lines point each ferrite-bead filter, etc. Shorting AGND DGND patterns place immediately under converter improves converter performance. sure turn analog digital power supplies simultaneously. simultaneously, does operate correctly. Ground power supply pins (AVcc, DVcc1, DVcc2, DVEE3) close each possible with 0.1µF larger ceramic chip capacitor. (Connect AVcc AGND pattern DVcc1, DVcc2 DVEE3 pins DGND pattern.) recommended place ceramic chip capacitor 0.1µF more, particular, between DVcc2 DGND2 with shortest distance. This effect suppress noise generated when CXA3246Q output circuit operates. digital output wiring should short possible. digital output wiring long, wiring capacitance will increase, deteriorating output slew rate resulting reflection output waveform since original output slew rate quite fast. analog input input capacitance approximately 10pF. drive converter with proper frequency response, necessary prevent performance deterioration parasitic capacitance parasitic inductance using large capacity drive circuit, keeping wiring short possible, using chip parts resistors capacitors, etc. pins must have adequate by-pass protect them from high-frequency noise. By-pass them AGND with approximately tantal capacitor 0.1µF chip capacitor short possible. CLKN/E used, by-pass this DGND with approximately 0.1µF capacitor. this time, approximately DGND3 1.2V voltage generated. However, this recommended threshold voltage because weak. When digital input level PECL level, pins should used pins left open. When digital input level TTL, pins should used pins left open. CXA3246Q output high level clamped approximately 2.8V This makes possible directly interface with 3.5V system CMOS CXA3026Q output pins However, CXA3246Q, these symbols changed PAand this time, side CXA3026Q changed side CXA3246Q; side CXA3026Q side CXA3246Q. pipeline delay CXA3246Q smaller clock, compared that CXA3026Q.
CXA3246Q
Example Representative Characteristics
Current consumption Ambient temperature characteristics
Current consumption Conversion rate characteristics
Current consumption [mA]
Current consumption [mA]
fCLK 1kHz
DMUX mode
Ambient temperature [°C]
Conversion rate [MSPS]
Analog input current Analog input voltage characteristics
Reference current Ambient temperature characteristics
Analog input current [µA]
Reference current [mA]
Ambient temperature [°C] Analog input voltage
CXA3246Q
Input frequency response
Error rate Conversion rate characteristics
10-6 fCLK 1kHz
10-7
Error Rate [TPS]
Error 16LSB 10-8
[dB]
120MSPS
10-9
10-10 Conversion rate [MSPS]
Input frequency [MHz]
Maximum conversion rate Ambient temperature characteristics
Maximum conversion rate [MSPS]
fCLK 1kHz Error 16LSB Error rate: 10-9
Ambient temperature [°C]
CXA3246Q
Package Outline
Unit:
48PIN (PLASTIC)
15.3 12.0 0.15 0.05 0.15
0.15
0.24
0.35 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 QFP048-P-1212 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PALLADIUM PLATING 42/COPPER ALLOY 0.7g
NOTE PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
13.5
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