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Am29F032B
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Publication Number 21610 Revision
Amendment Issue Date December 2000
Am29F032B
Megabit 8-Bit) CMOS Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
10%, single power supply operation Minimizes system level power requirements Manufactured 0.32 process technology High performance Access times fast power consumption typical active read current typical program/erase current typical standby current (standard access time active mode) Flexible sector architecture uniform sectors Kbytes each combination sectors erased. Supports full chip erase Group sector protection: hardware method locking sector groups prevent program erase operations within that sector group Temporary Sector Group Unprotect allows code changes previously locked sectors Embedded Algorithms Embedded Erase algorithm automatically preprograms erases entire chip combination designated sectors Embedded Program algorithm automatically writes verifies bytes specified addresses Minimum 1,000,000 write/erase cycles guaranteed 20-year data retention 125°C Reliable operation life system Package options 40-pin TSOP 44-pin Compatible with JEDEC standards Pinout software compatible with single-power-supply Flash standard Superior inadvertent write protection Data# Polling toggle bits Provides software method detecting program erase cycle completion Ready/Busy output (RY/BY#) Provides hardware method detecting program erase cycle completion Erase Suspend/Resume Suspends sector erase operation read data from, program data non-erasing sector, then resumes erase operation Hardware reset (RESET#) Resets internal state machine read mode
This Data Sheet states AMD's current technical specifications regarding Product described herein. This Data Sheet revised subsequent versions modifications changes technical specifications.
Publication# 21610 Rev: Amendment/+1 Issue Date: December 2000
GENERAL DESCRIPTION
Am29F032B Mbit, volt-only Flash memory organized 4,194,304 bytes bits each. Mbytes data divided into sectors Kbytes each flexible erase capability. bits data appear DQ0-DQ7. Am29F032B offered 40-pin TSOP 44-pin packages. Am29F032B manufactured using AMD's 0.32 process technology. This device designed programmed in-system with standard system volt supply. 12.0 volt required program erase operations. device also programmed standard EPROM programmers. standard device offers access times 120, allowing high-speed microprocessors operate without wait states. eliminate contention, device separate chip enable (CE#), write enable (WE#), output enable (OE#) controls. device entirely command compatible with JEDEC single-power-supply Flash standard. Commands written command register using standard microprocessor write timings. Register contents serve input internal state machine that controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from 12.0 volt Flash EPROM devices. device programmed executing program command sequence. This invokes Embedded Program algorithm-an internal algorithm that automatically times program pulse widths verifies proper cell margin. device erased executing erase command sequence. This invokes Embedded Erase algorithm-an internal algorithm that automatically preprograms array already programmed) before executing erase operation. During erase, device automatically times erase pulse widths verifies proper cell margin. sector erase architecture allows memory sectors erased reprogrammed without affecting data contents other sectors. sector typically erased verified within second. device erased when shipped from factory. hardware sector group protection feature disables both program erase operations combination eight sector groups memory. sector group consists four adjacent sectors. Erase Suspend feature enables system erase hold period time read data from, program data sector that being erased. True background erase thus achieved. device requires only single volt power supply both read write functions. Internally generated regulated voltages provided program erase operations. detector automatically inhibits write operations during power transitions. host system detect whether program erase cycle complete using RY/BY# pin, (Data# Polling) (toggle) status bits. After program erase cycle been completed, device automatically returns read mode. hardware RESET# terminates operation progress. internal state machine reset read mode. RESET# tied system reset circuitry. Therefore, system reset occurs during either Embedded Program Embedded Erase algorithm, device automatically reset read mode. This enables system's microprocessor read boot-up firmware from Flash memory. AMD's Flash technology combines years Flash memory manufacturing experience produce effectiveness. device electrically erases bits within sector simultaneously Fowler-Nordheim tunneling. bytes programmed byte time using programming mechanism electron injection.
Am29F032B
TABLE CONTENTS
Product Selector Guide Block Diagram Connection Diagrams Configuration Logic Symbol Ordering Information Device Operations Requirements Reading Array Data Writing Commands/Command Sequences Program Erase Operation Status Standby Mode RESET#: Hardware Reset Output Disable Mode. DQ3: Sector Erase Timer
Figure Toggle Algorithm. Table Write Operation Status.
Absolute Maximum Ratings.
Figure Maximum Negative Overshoot Waveform Figure Maximum Positive Overshoot Waveform.
Table Am29F032B Device Operations
Operating Ranges Characteristics TTL/NMOS Compatible CMOS Compatible. Test Conditions.
Figure Test Setup. Table Test Specifications
Table Am29F032B Sector Address Table.
Autoselect Mode.
Table Am29F032B Autoselect Codes
Switching Waveforms Characteristics Read-only Operations.
Figure Read Operation Timings
Sector Group Protection/Unprotection.
Table Sector Group Addresses.
Hardware Reset (RESET#)
Figure RESET# Timings
Temporary Sector Group Unprotect
Figure Temporary Sector Group Unprotect Operation.
Write (Erase/Program) Operations
Figure Program Operation Timings. Figure Chip/Sector Erase Operation Timings Figure Data# Polling Timings (During Embedded Algorithms). Figure Toggle Timings (During Embedded Algorithms). Figure DQ6.
Hardware Data Protection
Write Inhibit. Write Pulse "Glitch" Protection Logical Inhibit Power-Up Write Inhibit
Temporary Sector Unprotect
Figure Temporary Sector Group Unprotect Timings
Command Definitions Reading Array Data Reset Command. Autoselect Command Sequence Byte Program Command Sequence. Chip Erase Command Sequence
Figure Program Operation
Write (Erase/Program) Operations-Alternate Controlled Writes
Figure Alternate Controlled Write Operation Timings
Sector Erase Command Sequence Erase Suspend/Erase Resume Commands.
Figure Erase Operation.
Command Definitions
Table Am29F032B Command Definitions.
Write Operation Status DQ7: Data# Polling.
Figure Data# Polling Algorithm
RY/BY#: Ready/Busy# DQ6: Toggle DQ2: Toggle Reading Toggle Bits DQ6/DQ2 DQ5: Exceeded Timing Limits
Erase Programming Performance Latchup Characteristic TSOP Capacitance Data Retention. Physical Dimensions 044-44-Pin Small Outline Package. 040-40-Pin Standard Thin Small Outline Package. TSR040-40-Pin Reversed Thin Small Outline Package Revision Summary Revision (June 1998) Revision (July 1998). Revision (January 1999) Revision (April 1999). Revision (November 1999) Revision (December 2000)
Am29F032B
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options access time, (tACC) access time, (tCE) access time, (tOE) -120 -150 Am29F032B
Note: Characteristics" full specifications.
BLOCK DIAGRAM
DQ0-DQ7 RY/BY# RESET# State Control Command Register Sector Switches Erase Voltage Generator Input/Output Buffers
Voltage Generator Chip Enable Output Enable Data Latch
Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A21
Am29F032B
CONNECTION DIAGRAMS
RESET# RY/BY#
40-Pin Standard TSOP
RY/BY#
40-Pin Reverse TSOP
RESET#
RESET#
RY/BY#
Am29F032B
CONFIGURATION
A0-A21 RESET# RY/BY# Addresses Data Inputs/Outputs Chip Enable Write Enable Output Enable Hardware Reset Pin, Active Ready/Busy Output DQ0-DQ7
LOGIC SYMBOL
A0-A21 DQ0-DQ7
RESET# RY/BY#
+5.0 single power supply (see Product Selector Guide device speed ratings voltage supply tolerances) Device Ground Connected Internally
Am29F032B
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination following: Am29F032B
TEMPERATURE RANGE Commercial (0°C +70°C) Industrial (-40°C +85°C) Extended (-55°C +125°C) PACKAGE TYPE 40-Pin Thin Small Outline Package (TSOP) Standard Pinout 040) 40-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR040) 44-Pin Small Outline Package 044) SPEED OPTION Product Selector Guide Valid Combinations DEVICE NUMBER/DESCRIPTION Am29F032B Megabit 8-Bit) CMOS Volt-only Sector Erase Flash Memory Read, Program, Erase
Valid Combinations AM29F032B-75 AM29F032B-90 AM29F032B-120 AM29F032B-150
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am29F032B
DEVICE OPERATIONS
This section describes requirements device operations, which initiated through internal command register. command register itself does occupy addressable memory location. register composed latches that store commands, along with address data information needed execute command. contents register serve inputs internal state machine. state machine outputs dictate function device. appropriate device operations table lists inputs control levels required, resulting output. following subsections describe each these operations further detail.
Table
Operation Read Write CMOS Standby Standby Output Disable Hardware Reset Temporary Sector Unprotect (See Note)
Am29F032B Device Operations
RESET# A0-A21 DQ0-DQ7 DOUT High-Z High-Z High-Z High-Z
Legend: Logic VIL, Logic High VIH, 12.0 Don't Care, Data DOUT Data Out, Address Note: sections Sector Group Protection Temporary Sector Unprotect more information.
Requirements Reading Array Data
read array data from outputs, system must drive pins VIL. power control selects device. output control gates array data output pins. should remain VIH. internal state machine reading array data upon device power-up, after hardware reset. This ensures that spurious alteration memory content occurs during power transition. command necessary this mode obtain array data. Standard microprocessor read cycles that assert valid addresses device address inputs produce valid data device data outputs. device remains enabled read access until command register contents altered. "Reading Array Data" more information. Refer Read Operations table timing specifications Read Operations Timings diagram timing waveforms. ICC1 Characteristics table represents active current specification reading array data.
sectors memory), system must drive VIL, VIH. erase operation erase sector, multiple sectors, entire device. Sector Address Tables indicate address space that each sector occupies. "sector address" consists address bits required uniquely select sector. "Writing specific address data commands sequences into command register initiates device operations. Command Definitions table defines valid register command sequences. Writing incorrect address data values writing them improper sequence resets device reading array data." section details erasing sector entire chip, suspending/resuming erase operation. After system writes autoselect command sequence, device enters autoselect mode. system then read autoselect codes from internal register (which separate from memory array) DQ7-DQ0. Standard read cycle timings apply this mode. Refer "Autoselect Mode" "Autoselect Command Sequence" sections more information. ICC2 Characteristics table represents active current specification write mode.
Writing Commands/Command Sequences
write command command sequence (which includes programming data device erasing
Am29F032B
Characteristics" section contains timing specification tables timing diagrams write operations.
Program Erase Operation Status
During erase program operation, system check status operation reading status bits DQ7-DQ0. Standard read cycle timings read specifications apply. Refer "The Erase Resume command valid only during Erase Suspend mode." more information, each Characteristics section timing diagrams.
drives RESET# least period tRP, device immediately terminates operation progress, tristates data output pins, ignores read/write attempts duration RESET# pulse. device also resets internal state machine reading array data. operation that interrupted should reinitiated once device ready accept another command sequence, ensure data integrity. Current reduced duration RESET# pulse. When RESET# held VIL, device enters standby mode; RESET# held device enters CMOS standby mode. RESET# tied system reset circuitry. system reset would thus also reset Flash memory, enabling system read boot-up firmware from Flash memory. RESET# asserted during program erase operation, RY/BY# remains (busy) until internal reset operation complete, which requires time tREADY (during Embedded Algorithms). system thus monitor RY/BY# determine whether reset operation complete. RESET# asserted when program erase operation executing (RY/BY# "1"), reset operation completed within time tREADY (not during Embedded Algorithms). system read data after RESET# returns VIH. Refer Characteristics tables RESET# parameters timing diagram.
Standby Mode
When system reading writing device, place device standby mode. this mode, current consumption greatly reduced, outputs placed high impedance state, independent input. device enters CMOS standby mode when RESET# pins both held (Note that this more restricted voltage range than VIH.) device enters standby mode when RESET# pins both held VIH. device requires standard access time (tCE) read access when device either these standby modes, before ready read data. device also enters standby mode when RESET# driven low. Refer next section, "RESET#: Hardware Reset Pin". device deselected during erasure programming, device draws active current until operation completed. Characteristics tables, ICC3 represents standby current specification.
Output Disable Mode
When input VIH, output from device disabled. output pins placed high impedance state.
RESET#: Hardware Reset
RESET# provides hardware method resetting device reading array data. When system
Am29F032B
Table
Sector SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43
Am29F032B Sector Address Table
Sector Size Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh
Am29F032B
Table
Sector SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63
Am29F032B Sector Address Table (Continued)
Sector Size Address Range 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh
Note: sectors Kbytes size.
Autoselect Mode
autoselect mode provides manufacturer device identification, sector group protection verification, through identifier codes output DQ7-DQ0. This mode primarily intended programming equipment automatically match device programmed with corresponding programming algorithm. However, autoselect codes also accessed in-system through command register. When using programming equipment, autoselect mode requires (11.5 12.5 address Address pins must shown Table addition, when verifying sector group proTable
Description Manufacturer Device Am29F032B Sector Group Protection Verification A21-A18 Sector Group Address A17-A10
tection, sector group address must appear appropriate highest order address bits (see Table Table also shows remaining address bits that don't care. When necessary bits have been required, programming equipment then read corresponding identifier code DQ7-DQ0. access autoselect codes in-system, host system issue autoselect command command register, shown Table This method does require address line. Refer Autoselect Command Sequence section more information.
Am29F032B Autoselect Codes
A8-A7 A5-A2 Identifier Code DQ7-DQ0 (protected) (unprotected)
Note: Identifier codes manufacturer device exhibit parity with defined parity bit.
Am29F032B
Sector Group Protection/Unprotection
hardware sector group protection feature disables both program erase operations sector group. Each sector group consists four adjacent sectors. Table shows sectors grouped, address range that each sector group contains. hardware sector group unprotection feature re-enables both program erase operations previously protected sector groups. Sector group protection/unprotection must implemented using programming equipment. procedure requires high voltage (VID address control pins. Details this method provided supplement, publication number 22184. Contact representative obtain copy appropriate document. device shipped with sector groups unprotected. offers option programming protecting sector groups factory prior shipping device through AMD's ExpressFlashService. Contact representative details. possible determine whether sector group protected unprotected. "Autoselect Mode" details. Table
Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15
Temporary Sector Group Unprotect
This feature allows temporary unprotection previously protected sector groups change data in-system. Sector Group Unprotect mode activated setting RESET# (11.5 12.5 During this mode, formerly protected sector groups programmed erased selecting sector group addresses. Once removed from RESET# pin, previously protected sector groups protected again. Figure shows algorithm, Figure shows timing diagrams, this feature.
START
RESET# (Note Perform Erase Program Operations
RESET#
Sector Group Addresses
Sectors SA0-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA63
Temporary Sector Group Unprotect Completed (Note
Notes: protected sector groups unprotected. previously protected sector groups protected once again.
Figure
Temporary Sector Group Unprotect Operation
Am29F032B
Hardware Data Protection
command sequence requirement unlock cycles programming erasing provides data protection. addition, following hardware data protection measures prevent accidental erasure programming, which might otherwise caused spurious system level signals during power-up power-down transitions, from system noise. Write Inhibit When less than VLKO (see Characteristics voltage levels), device does accept write cycles. This protects data during power-up power-down. command register internal program/erase circuits disabled. Under this condition device resets read mode. Subsequent writes ignored until level greater
than VLKO. system must ensure that control pins logically correct prevent unintentional writes when above VLKO. Write Pulse "Glitch" Protection Noise pulses less than (typical) OE#, initiate write cycle. Logical Inhibit Write cycles inhibited holding VIL, VIH. initiate write cycle, must while VIH. Power-Up Write Inhibit during power device does accept commands rising edge WE#. internal state machine automatically reset read mode power-up.
COMMAND DEFINITIONS
Writing specific address data commands sequences into command register initiates device operations. Command Definitions table defines valid register command sequences. Writing incorrect address data values writing them improper sequence resets device reading array data. addresses latched falling edge CE#, whichever happens later. data latched rising edge CE#, whichever happens first. Refer appropriate timing diagrams Characteristics" section. also "Requirements Reading Array Data" "Device Operations" section more information. Read Operations table provides read parameters, Read Operation Timings diagram shows timing diagram.
Reset Command
Writing reset command device resets device reading array data. Address bits don't care this command. reset command written between sequence cycles erase command sequence before erasing begins. This resets device reading array data. Once erasure begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles program command sequence before programming begins. This resets device reading array data (also applies programming Erase Suspend mode). Once programming begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles autoselect command sequence. Once autoselect mode, reset command must written return reading array data (also applies autoselect during Erase Suspend). goes high during program erase operation, writing reset command returns device reading array data (also applies during Erase Suspend).
Reading Array Data
device automatically reading array data after device power-up. commands required retrieve data. device also ready read array data after completing Embedded Program Embedded Erase algorithm. After device accepts Erase Suspend command, device enters Erase Suspend mode. system read array data using standard read timings, except that reads address within erasesuspended sectors, device outputs status data. After completing programming operation Erase Suspend mode, system once again read array data with same exception. "Erase Suspend/Erase Resume Commands" more information this mode. system must issue reset command re-enable device reading array data goes high, while autoselect mode. "Reset Command" section, next.
Am29F032B
Autoselect Command Sequence
autoselect command sequence allows host system access manufacturer devices codes, determine whether sector protected. Command Definitions table shows address data requirements. This method alternative that shown Autoselect Codes (High Voltage Method) table, which intended PROM programmers requires address autoselect command sequence initiated writing unlock cycles, followed autoselect command. device then enters autoselect mode, system read address number times, without initiating another command sequence. read cycle address XX00h retrieves manufacturer code. read cycle address XX01h returns device code. read cycle containing sector address (SA) address returns that sector protected, unprotected. Refer Sector Address tables valid sector addresses. system must write reset command exit autoselect mode return reading array data.
hardware reset immediately terminates programming operation. program command sequence should reinitiated once device reset reading array data, ensure data integrity. Programming allowed sequence across sector boundaries. cannot programmed from back "1". Attempting halt operation "1", cause Data# Polling algorithm indicate operation successful. However, succeeding read will show that data still "0". Only erase operations convert "1".
Chip Erase Command Sequence
Chip erase six-bus-cycle operation. chip erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed chip erase command, which turn invokes Embedded Erase algorithm. device does require system preprogram prior erase. Embedded Erase algorithm automatically preprograms verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. Command Definitions table shows address data requirements chip erase command sequence. commands written chip during Embedded Erase algorithm ignored. Note that hardware reset during chip erase operation immediately terminates operation. Chip Erase command sequence should reinitiated once device returned reading array data, ensure data integrity. system determine status erase operation using DQ7, DQ6, DQ2, RY/BY#. "The Erase Resume command valid only during Erase Suspend mode." information these status bits. When Embedded Erase algorithm complete, device returns reading array data addresses longer latched. Figure illustrates algorithm erase operation. Erase/Program Operations tables Characteristics" parameters, Chip/Sector Erase Operation Timings timing waveforms.
Byte Program Command Sequence
Programming four-bus-cycle operation. program command sequence initiated writing unlock write cycles, followed program set-up command. program address data written next, which turn initiate Embedded Program algorithm. system required provide further controls timings. device automatically provides internally generated program pulses verify programmed cell margin. Command Definitions take shows address data requirements byte program command sequence. When Embedded Program algorithm complete, device then returns reading array data addresses longer latched. system determine status program operation using DQ7, DQ6, RY/BY#. "Write Operation Status" information these status bits. commands written device during Embedded Program Algorithm ignored. Note that
Am29F032B
START
Write Program Command Sequence
Embedded Program algorithm progress
Data Poll from System
otherwise last address command might accepted, erasure begin. recommended that processor interrupts disabled during this time ensure commands accepted. interrupts re-enabled after last Sector Erase command written. time between additional sector erase commands assumed less than system need monitor DQ3. command other than Sector Erase Erase Suspend during time-out period resets device reading array data. system must rewrite command sequence additional sector addresses commands. system monitor determine sector erase timer timed out. (See "DQ3: Sector Erase Timer" section.) time-out begins from rising edge final pulse command sequence.
Verify Data?
Increment Address
Last Address?
Once sector erase operation begun, only Erase Suspend command valid. other commands ignored. Note that hardware reset during sector erase operation immediately terminates operation. Sector Erase command sequence should reinitiated once device returned reading array data, ensure data integrity. When Embedded Erase algorithm complete, device returns reading array data addresses longer latched. system determine status erase operation using DQ7, DQ6, DQ2, RY/BY#. Refer "The Erase Resume command valid only during Erase Suspend mode." information these status bits. Figure illustrates algorithm erase operation. Refer Erase/Program Operations tables Characteristics" section parameters, Sector Erase Operations Timing diagram timing waveforms.
Programming Completed
Note: Table program command sequence.
Figure
Program Operation
Sector Erase Command Sequence
Sector erase cycle operation. sector erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed address sector erased, sector erase command. Command Definitions table shows address data requirements sector erase command sequence. device does require system preprogram memory prior erase. Embedded Erase algorithm automatically programs verifies sector zero data pattern prior electrical erase. system required provide controls timings during these operations. After command sequence written, sector erase time-out begins. During time-out period, additional sector addresses sector erase commands written. Loading sector erase buffer done sequence, number sectors from sector sectors. time between these additional cycles must less than
Erase Suspend/Erase Resume Commands
Erase Suspend command allows system interrupt sector erase operation then read data from, program data sector selected erasure. This command valid only during sector erase operation, including time-out period during sector erase command sequence. Erase Suspend command ignored written during chip erase operation Embedded Program algorithm. Writing Erase Suspend command during Sector Erase time-out immediately terminates time-out period suspends erase operation. Addresses "don't-cares" when writing Erase Suspend command. When Erase Suspend command written during sector erase operation, device requires maximum suspend erase operation. However, when Erase Suspend command written during sector erase time-out, device immediately ter-
Am29F032B
minates time-out period suspends erase operation. After erase operation been suspended, system read array data from program data sector selected erasure. (The device "erase suspends" sectors selected erasure.) Normal read write timings command definitions apply. Reading address within erase-suspended sectors produces status data DQ7-DQ0. system DQ7, together, determine sector actively erasing erase-suspended. "The Erase Resume command valid only during Erase Suspend mode." information these status bits. After erase-suspended program operation complete, system once again read array data within non-suspended sectors. system determine status program operation using status bits, just standard program operation. "The Erase Resume command valid only during Erase Suspend mode." more information. system also write autoselect command sequence when device Erase Suspend mode. device allows reading autoselect codes even addresses within erasing sectors, since codes stored memory array. When device exits autoselect mode, device reverts Erase Suspend mode, ready another valid operation. "Autoselect Command Sequence" more information. system must write Erase Resume command (address bits "don't care") exit erase suspend mode continue sector erase operation. Further writes Resume command ignored. Another
Erase Suspend command written after device resumed erasing.
START
Write Erase Command Sequence
Data Poll from System
Embedded Erase algorithm progress
Data FFh?
Erasure Completed
Notes: appropriate Command Definitions table erase command sequence. "DQ3: Sector Erase Timer" more information.
Figure
Erase Operation
Am29F032B
Command Definitions
Table
Cycles
Am29F032B Command Definitions
Cycles (Notes 2-4)
Command Sequence (Note Read (Note Reset (Note Manufacturer
First Addr Data
Second Addr Data
Third Addr
Fourth Data Addr Data
Fifth Addr Data
Sixth Addr Data
Autoselect Device (Note
Sector Group Protect Verify (Note Program Chip Erase Sector Erase Erase Suspend (Note Erase Resume (Note
XX00 XX01
Legend: Don't care Address memory location read. Data read from location during read operation. Address memory location programmed. Addresses latch falling edge pulse, whichever happens later.
Data programmed location Data latches rising edge pulse, whichever happens first. Address sector verified autoselect mode) erased. Address bits A21-A16 select unique sector. Address sector group verified. Address bits A21-A18 select unique sector group.
Notes: Table description operations. values hexadecimal. Except when reading array autoselect data, cycles write operations. Address bits A21-A11 don't cares unlock command cycles, unless required. unlock command cycles required when reading array data. Reset command required return reading array data when device autoselect mode, goes high (while device providing status data).
fourth cycle autoselect command sequence read cycle. data unprotected sector group protected sector group.See "Autoselect Command Sequence" more information. system read program non-erasing sectors, enter autoselect mode, when Erase Suspend mode. Erase Suspend command valid only during sector erase operation. Erase Resume command valid only during Erase Suspend mode.
Am29F032B
WRITE OPERATION STATUS
device provides several bits determine status write operation: DQ2, DQ3, DQ5, DQ6, DQ7, RY/BY#. Table following subsections describe functions these bits. DQ7, RY/BY#, each offer method determining whether program erase operation complete progress. These three bits discussed first. rithms) figure Characteristics" section illustrates this. Table shows outputs Data# Polling DQ7. Figure shows Data# Polling algorithm.
DQ7: Data# Polling
Data# Polling bit, DQ7, indicates host whether Embedded Algor ithm progress completed, whether device Erase Suspend. Data# Polling valid after rising edge final pulse program erase command sequence. During Embedded Program algorithm, device outputs complement datum programmed DQ7. This status also applies programming during Erase Suspend. When Embedded Program algorithm complete, device outputs datum programmed DQ7. system must provide program address read valid status information DQ7. program address falls within protected sector, Data# Polling active approximately then device returns reading array data. During Embedded Erase algorithm, Data# Polling produces DQ7. When Embedded Erase algorithm complete, device enters Erase Suspend mode, Data# Polling produces DQ7. This analogous complement/true datum output described Embedded Program algorithm: erase function changes bits sector "1"; prior this, device outputs "complement," "0." system must provide address within sectors selected erasure read valid status information DQ7. After erase command sequence written, sectors selected erasing protected, Data# Polling active approximately then device returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. When system detects changed from complement true data, read valid data DQ7-DQ0 following read cycles. This DQ0-DQ6 while Output Enable (OE#) asserted low. Data# Polling Timings (During Embedded Algo-
START
Read DQ7-DQ0 Addr
Data?
Read DQ7-DQ0 Addr
Data?
FAIL PASS
Notes: Valid address programming. During sector erase operation, valid address address within sector selected erasure. During chip erase, valid address non-protected sector address. should rechecked even because change simultaneously with DQ5.
Figure
Data# Polling Algorithm
Am29F032B
RY/BY#: Ready/Busy#
RY/BY# dedicated, open-drain output that indicates whether Embedded Algorithm progress complete. RY/BY# status valid after rising edge final pulse command sequence. Since RY/BY# open-drain output, several RY/BY# pins tied together parallel with pull-up resistor VCC. output (Busy), device actively erasing programming. (This includes programming Erase Suspend mode.) output high (Ready), device ready read array data (including during Erase Suspend mode), standby mode. Table shows outputs RY/BY#. timing diagrams read, reset, program, erase shows relationship RY/BY# other signals.
Write Operation Status table shows outputs Toggle DQ6. Refer Figure toggle algorithm, Toggle Timings figure Characteristics" section timing diagram. figure shows differences between graphical form. also subsection "DQ2: Toggle II".
DQ2: Toggle
"Toggle DQ2, when used with DQ6, indicates whether particular sector actively erasing (that Embedded Erase algorithm progress), whether that sector erase-suspended. Toggle valid after rising edge final pulse command sequence. toggles when system reads addresses within those sectors that have been selected erasure. (The system either control read cycles.) cannot distinguish whether sector actively erasing erase-suspended. DQ6, comparison, indicates whether device actively erasing, Erase Suspend, cannot distinguish which sectors selected erasure. Thus, both status bits required sector mode information. Refer Table compare outputs DQ6. Figure shows toggle algorithm flowchart form, section "DQ2: Toggle explains algorithm. also "DQ6: Toggle subsection. Refer Toggle Timings figure toggle timing diagram. figure shows differences between graphical form.
DQ6: Toggle
Toggle indicates whether Embedded Program Erase algorithm progress complete, whether device entered Erase Suspend mode. Toggle read address, valid after rising edge final pulse command sequence (prior program erase operation), during sector erase time-out. During Embedded Program Erase algorithm operation, successive read cycles address cause toggle. (The system either control read cycles.) When operation complete, stops toggling. After erase command sequence written, sectors selected erasing protected, toggles approximately then returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. system together determine whether sector actively erasing erasesuspended. When device actively erasing (that Embedded Erase algorithm progress), toggles. When device enters Erase Suspend mode, stops toggling. However, system must also determine which sectors erasing erase-suspended. Alternatively, system (see subsection "DQ7: Data# Polling"). program address falls within protected sector, toggles approximately after program command sequence written, then returns reading array data. also toggles during erase-suspend-program mode, stops toggling once Embedded Program algorithm complete.
Reading Toggle Bits DQ6/DQ2
Refer Figure following discussion. Whenever system initially begins reading toggle status, must read DQ7-DQ0 least twice determine whether toggle toggling. Typically, system would note store value toggle after first read. After second read, system would compare value toggle with first. toggle toggling, device completed program erase operation. system read array data DQ7-DQ0 following read cycle. However, after initial read cycles, system determines that toggle still toggling, system also should note whether value high (see section DQ5). system should then determine again whether toggle toggling, since toggle have stopped toggling just went high. toggle longer toggling, device successfully completed program erase operation. still toggling, device complete operation successfully,
Am29F032B
system must write reset command return reading array data. remaining scenario that system initially determines that toggle toggling gone high. system continue monitor toggle through successive read cycles, determining status described previous paragraph. Alternatively, choose perform other system tasks. this case, system must start beginning algorithm when returns determine status operation (top Figure
erase command. high second status check, last command might have been accepted. Table shows outputs DQ3.
START
Read DQ7-DQ0
DQ5: Exceeded Timing Limits
indicates whether program erase time exceeded specified internal pulse count limit. Under these conditions produces "1." This failure condition that indicates program erase cycle successfully completed. failure condition appear system tries program location that previously programmed "0." Only erase operation change back "1." Under this condition, device halts operation, when operation exceeded timing limits, produces "1." Under both these conditions, system must issue reset command return device reading array data.
Read DQ7-DQ0
(Note
Toggle Toggle?
DQ3: Sector Erase Timer
After writing sector erase command sequence, system read determine whether erase operation begun. (The sector erase timer does apply chip erase command.) additional sectors selected erasure, entire timeout also applies after each additional sector erase command. When time-out complete, switches from "1." system ignore system guarantee that time between additional sector erase commands will always less than also "Sector Erase Command Sequence" section. After sector erase command sequence written, system should read status (Data# Polling) (Toggle ensure device accepted command sequence, then read DQ3. "1", internally controlled erase cycle begun; further commands (other than Erase Suspend) ignored until erase operation complete. "0", device will accept additional sector erase commands. ensure command been accepted, system software should check status prior following each subsequent sector
Read DQ7-DQ0 Twice
(Notes
Toggle Toggle?
Program/Erase Operation Complete, Write Reset Command Program/Erase Operation Complete
Notes: Read toggle twice determine whether toggling. text. Recheck toggle because stop toggling changes "1". text.
Figure
Toggle Algorithm
Am29F032B
Table
Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program
Write Operation Status
Toggle Toggle toggle Data Toggle (Note Data Data (Note toggle Toggle Toggle Data RY/BY#
(Note DQ7# Data DQ7#
Notes: require valid address when reading status information. Refer appropriate subsection further details. switches when Embedded Program Embedded Erase operation exceeded maximum timing limits. "DQ5: Exceeded Timing Limits" more information.
Am29F032B
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages -65°C +150°C Ambient Temperature with Power Applied. -55°C +125°C Voltage with Respect Ground (Note -2.0 OE#, RESET# (Note -2.0 13.0 other pins (Note -2.0 Output Short Circuit Current (Note
Notes: Minimum voltage input pins -0.5 During voltage transitions, inputs overshoot -2.0 periods Figure Maximum voltage output pins During voltage transitions, outputs overshoot periods Figure Minimum input voltage OE#, RESET# pins -0.5V. During voltage transitions, OE#, RESET# pins overshoot -2.0 periods Figure Maximum input voltage OE#, RESET# 13.0 which overshoot 13.5 periods more than output shorted time. Duration short circuit should greater than second. Stresses greater than those listed this section cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Exposure device absolute maximum rating conditions extended periods affect device reliability.
+2.0 +0.5 -0.5 -2.0 +0.8
Figure Maximum Negative Overshoot Waveform
Figure Maximum Positive Overshoot Waveform
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) +70°C Industrial Devices Ambient Temperature (TA) -40°C +85°C Extended Devices Ambient Temperature (TA) -55°C +125°C Supply Voltages devices .+4.75 +5.25 devices .+4.50 +5.50
Operating ranges define those limits between which functionality device guaranteed.
Am29F032B
CHARACTERISTICS TTL/NMOS Compatible
Parameter Symbol ILIT ICC1 ICC2 ICC3 ICC4 VLKO Parameter Description Input Load Current Input Load Current Output Leakage Current Read Current (Note Write Current (Notes Standby Current (CE# Controlled) Standby Current (RESET# Controlled) Input Level Input High Level Voltage Autoselect Sector Protect Output Voltage Output High Level Lock-out Voltage -2.5 Test Description VCC, Max, 12.0 VOUT VCC, VIL, VIL, VIH, RESET# Max, RESET# -0.5 11.5 ±1.0 ±1.0 12.5 0.45 Unit
CMOS Compatible
Parameter Symbol ILIT ICC1 ICC2 ICC3 ICC4 VOH1 VOH2 VLKO Parameter Description Input Load Current Input Load Current Output Leakage Current Read Current (Note Write Current (Notes Standby Current (CE# Controlled) Standby Current (RESET# Controlled) Input Level Input High Level Voltage Autoselect Sector Protect Output Voltage Output High Voltage Lock-out Voltage -2.5 -100 0.85 Test Description VCC, Max, 12.0 VOUT VCC, VIL, VIL, RESET# RESET# -0.5 0.7x 11.5 ±1.0 ±1.0 12.5 0.45 Unit
Notes Characteristics (both tables): current typically less than mA/MHz, with VIH. active while Embedded Program Embedded Erase algorithm progress. 100% tested.
Am29F032B
TEST CONDITIONS
Table
Test Condition
Test Specifications
others gate 0.0-3.0 0.45-2.4 Unit
Device Under Test
Output Load Output Load Capacitance, (including capacitance) Input Rise Fall Times Input Pulse Levels Input timing measurement reference levels
Note: Diodes IN3064 equivalent
Figure
Test Setup
Output timing measurement reference levels
SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from Changing from Don't Care, Change Permitted Does Apply Changing, State Unknown Center Line High Impedance State (High OUTPUTS
Am29F032B
CHARACTERISTICS Read-only Operations
Parameter Symbol JEDEC tAVAV tAVQV tELQV tGLQV tACC Parameter Description Read Cycle Time (Note Address Output Delay Chip Enable Output Delay Output Enable Output Delay Read tOEH Output Enable Hold Time (Note Toggle Data# Polling Test Setup Speed Options -120 -150 Unit
tEHQZ tGHQZ tAXQX
tReady
Chip Enable Output High (Note Output Enable Output High (Note Output Hold Time From Addresses Whichever Occurs First RESET# Read Mode (Note
Notes: 100% tested. Refer Figure Table test specifications.
Addresses tOEH HIGH Outputs RESET# RY/BY# Output Valid HIGH Addresses Stable tACC
Figure
Read Operation Timings
Am29F032B
CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC tREADY tREADY Description RESET# (During Embedded Algorithms) Read Write (See Note) RESET# (NOT During Embedded Algorithms) Read Write (See Note) RESET# Pulse Width RESET# High Time Before Read (See Note) RY/BY# Recovery Time Test Setup Speed Options Unit
Note: 100% tested.
RY/BY#
CE#, RESET# tReady
Reset Timings during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# CE#,
RESET#
Figure
RESET# Timings
Am29F032B
CHARACTERISTICS Write (Erase/Program) Operations
Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tGHWL tWPH tWHWH1 tWHWH2 tVCS tBUSY Parameter Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recover Time Before Write (OE# high low) Setup Time Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation (Note Sector Erase Operation (Note Time (Note RY/BY# Valid Speed Options -120 -150 Unit
Notes: 100% tested. "Erase Programming Performance" section more information.
Am29F032B
CHARACTERISTICS
Program Command Sequence (last cycles) Addresses 555h Data tBUSY RY/BY# tVCS Status DOUT tWPH tWHWH1 Read Status Data (last cycles)
Note: program address, program data, DOUT true data program address.
Figure
Program Operation Timings
Am29F032B
CHARACTERISTICS
Addresses 2AAh
555h chip erase
tWPH
tWHWH2
Data
Chip Erase Progress Complete
tBUSY RY/BY# tVCS
Note: Sector Address. Valid Address reading status data.
Figure
Chip/Sector Erase Operation Timings
Am29F032B
CHARACTERISTICS
Addresses tACC tOEH
High
Complement
Complement
True
Valid Data
High
DQ0-DQ6 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: Valid address. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
Figure
Data# Polling Timings (During Embedded Algorithms)
Addresses tACC tOEH DQ6/DQ2 tBUSY RY/BY#
High
Valid Status (first read)
Valid Status (second read)
Valid Status (stops toggling)
Valid Data
Note: Valid address; required DQ6. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
Figure
Toggle Timings (During Embedded Algorithms)
Am29F032B
CHARACTERISTICS
Enter Embedded Erasing Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
Note: system toggle DQ6. toggles only when read address within erase-suspended sector.
Figure
Temporary Sector Unprotect
Parameter JEDEC tVIDR tRSP Description Rise Fall Time (See Note) RESET# Setup Time Temporary Sector Unprotect Speed Options Unit
Note: 100% tested.
RESET# tVIDR Program Erase Command Sequence tVIDR
tRSP RY/BY#
Figure
Temporary Sector Group Unprotect Timings
Am29F032B
CHARACTERISTICS Write (Erase/Program) Operations-Alternate Controlled Writes
Parameter Symbol JEDEC tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 tGHEL tCPH tWHWH1 tWHWH2 Parameter Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Address Hold Time Read Recover Time Before Write Setup Time Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation (Note Sector Erase Operation (Note Speed Options -120 -150 Unit
Notes: 100% tested. "Erase Programming Performance" section more information.
Am29F032B
CHARACTERISTICS
program erase program sector erase chip erase
Data# Polling
Addresses tGHEL tCPH Data
program erase program sector erase chip erase
tWHWH1
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: Program Address, Program Data, Sector Address, DQ7# Complement Data Input, DOUT Array Data. Figure indicates last cycles command sequence.
Figure
Alternate Controlled Write Operation Timings
Am29F032B
ERASE PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time (Note (Note 28.8 86.4 (Note Unit Comments Excludes programming prior erasure (Note Excludes system-level overhead (Note
Notes: Typical program erase times assume following conditions: 25°C, VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. Under worst case conditions 90°C, 1,000,000 cycles (4.75 -75). typical chip programming time considerably less than maximum chip programming time listed, since most bytes program faster than maximum byte program time listed. maximum byte program time given exceeded, only then does device section further information. pre-programming step Embedded Erase algorithm, bytes programmed before erasure. System-level overhead time required execute four-bus-cycle sequence programming. Table further information command definitions. device minimum erase program cycle endurance 1,000,000 cycles.
LATCHUP CHARACTERISTIC
Description Input Voltage with respect pins Current -1.0 -100 +100
Note: Includes pins except VCC. Test conditions: Volt, time.
TSOP CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance VOUT Test Conditions Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
DATA RETENTION
Parameter Minimum Pattern Data Retention Time 125°C Years Test Conditions 150°C Unit Years
Am29F032B
PHYSICAL DIMENSIONS 044-44-Pin Small Outline Package
10/99
Am29F032B
PHYSICAL DIMENSIONS 040-40-Pin Standard Thin Small Outline Package
10/99
Am29F032B
PHYSICAL DIMENSIONS TSR040-40-Pin Reversed Thin Small Outline Package
10/99
Am29F032B
REVISION SUMMARY Revision (June 1998)
Initial release. Data Retention Added table.
Revision (July 1998)
Distinctive Characteristics Changed typical active read current match Characteristics table. Operating Ranges Corrected temperature range descriptions "ambient."
Revision (November 1999)
Characteristics-Figure Program Operations Timing Figure Chip/Sector Erase Operations Deleted tGHWL changed waveform start high. Physical Dimensions Replaced figures with more detailed illustrations.
Revision (January 1999)
Distinctive Characteristics Added 20-year data retention subbullet.
Revision (December 2000)
Added table contents. Ordering Information
Revision (April 1999)
Deleted duplicate sections full data sheet.
Deleted burn-in option.
Trademarks
Copyright 2000 Advanced Micro Devices, Inc. rights reserved. AMD, logo, combinations thereof registered trademarks Advanced Micro Devices, Inc. ExpressFlash trademark Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
Am29F032B
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