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Publication Number 25685 Revision
Amendment Issue Date July 2002
PRELIMINARY
Am29PDL128G
Megabit 16-Bit/4 32-Bit) CMOS Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIOControl
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
128Mbit Page Mode device
Word (16-bit) double word (32-bit) mode selectable WORD# input Page size words/4 double words: Fast page read access from random locations within page
SOFTWARE FEATURES
Software command-set compatible with JEDEC 42.4 standard
Backward compatible with Am29F Am29LV families
(Common Flash Interface) complaint
Provides device-specific information system, allowing host software easily reconfigure different Flash devices
Single power supply operation
Full Voltage range: volt read, erase, program operations battery-powered applications
Erase Suspend Erase Resume
Suspends erase operation allow read program operations other sectors same bank
Simultaneous Read/Write Operation
Data continuously read from bank while executing erase/program functions another bank Zero latency switching from write read operations
Unlock Bypass Program command
Reduces overall programming time when issuing multiple program command sequences
FlexBank Architecture
separate banks, with simultaneous operations device Organized Mbit banks (Bank Mbit banks (Bank
HARDWARE FEATURES
Ready/Busy# (RY/BY#)
Provides hardware method detecting program erase cycle completion
VersatileI/O
(VIO) Control
Output voltage generated input voltages tolerated device determined voltage
Hardware reset (RESET#)
Hardware method reset device reading array data
SecSi (Secured Silicon) Sector region
words double words) accessible through command sequence
(Write Protect) input
VIL, protects bottom sectors, regardless sector protect/unprotect status VIH, allows removal sector protection internal pull provided
Both bottom boot blocks device Manufactured 0.17 process technology 20-year data retention 125°C Minimum million write cycle guarantee sector
Persistent Sector Protection
command sector protection method lock combinations individual sectors sector groups prevent program erase operations within that sector Sectors locked unlocked in-system level
PERFORMANCE CHARACTERISTICS
High Performance
Page access times fast Random access times fast
Password Sector Protection
sophisticated sector protection method lock combinations individual sectors sector groups prevent program erase operations within that sector using user-defined 64-bit password
Power consumption (typical values MHz)
active read current program/erase current typical standby mode current
(Acceleration) input provides faster programming times factory setting Package options
80-ball Fortified
This document contains information product under development Advanced Micro Devices. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice.
Publication# 25685 Rev: Amendment/+2 Issue Date: July 2002
Refer AMD's Website (www.amd.com) latest information.
GENERAL DESCRIPTION
Am29PDL128G Mbit, volt-only Page Mode Simultaneous Read/Write Flash memory device organized Mwords double words (One word equal bytes). device offered 80-ball Fortified package. word-wide data (x16) appears DQ15-DQ0; double word mode data (x32) appears DQ31-DQ0. This device programmed in-system standard EPROM programmers. 12.0 required write erase operations. device offers fast page access times with corresponding random access times respectively, allowing high speed microprocessors operate without wait states. eliminate contention device separate chip enable (CE#), write enable (WE#) output enable (OE#) controls.
Standard Flash Memory Features
device requires single volt power supply (2.7 both read write functions. Internally generated regulated voltages provided program erase operations. device entirely command compatible with JEDEC 42.4 single-power-supply Flash standard. Commands written command register using standard microprocessor write timing. Register contents serve inputs internal state-machine that controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from other Flash EPROM devices. Device programming occurs executing program command sequence. Unlock Bypass mode facilitates faster programming times requiring only write cycles program data instead four. Device erasure occurs executing erase command sequence. host system detect whether program erase operation complete reading (Data# Polling) (toggle) status bits. After program erase cycle been completed, device ready read array data accept another command. sector erase architecture allows memory sectors erased reprogrammed without affecting data contents other sectors. device fully erased when shipped from factory. Hardware data protection measures include detector that automatically inhibits write operations during power transitions. hardware sector protection feature disables both program erase operations combination sectors memory. This achieved in-system programming equipment. Erase Suspend/Erase Resume feature enables user erase hold period time read data from, program data sector that selected erasure. True background erase thus achieved. read needed from SecSi Sector area (One Time Program area) after erase suspend, then user must proper command sequence enter exit this region. device offers power-saving features. When addresses have been stable specified amount time, device enters automatic sleep mode. system also place device into standby mode. Power consumption greatly reduced both these modes. AMD's Flash technology combined years Flash memory manufacturing experience produce highest levels quality, reliability cost effectiveness. device electrically erases bits within sector simultaneously Fowler-Nordheim tunneling. data programmed using electron injection.
Simultaneous Read/Write Operation with Zero Latency
Simultaneous Read/Write architecture provides simultaneous operation dividing memory space into banks, which considered four separate memory arrays certain operations concerned. device improve overall system performance allowing host system program erase bank, then immediately simultaneously read from another bank with zero latency (with simultaneous operations operating time). This releases system from waiting completion program erase operation, greatly improving system performance. device organized both bottom sector configurations (see Table Bank/Sector Sizes Number Sectors Sector Size (Word/Dbl. Word) 32/16 32/16 32/16 32/16
Bank
Bank Size Mbit Mbit Mbit Mbit
Page Mode Features
device timing, input/output, package compatible with Mbit page mode mask ROM. page size words double words. After initial page access accomplished, page mode operation provides fast read access speed random locations within that page.
Am29PDL128G
July 2002
TABLE CONTENTS
Product Selector Guide Block Diagram Simultaneous Operation Block Diagram Connection Diagrams Description. Logic Symbol Ordering Information Device Operations
Table Am29PDL128G Device Operations Table System Interface String.
Word/Double Word Configuration. Requirements Reading Array Data Random Read (Non-Page Read) Page Mode Read
Table Page Select, Double Word Mode Table Page Select, Word Mode
Table Device Geometry Definition. Table Primary Vendor-Specific Extended Query. Command Definitions. Reading Array Data Reset Command Autoselect Command Sequence Enter SecSi Sector/Exit SecSi Sector Command Sequence Double Word/Word Program Command Sequence Unlock Bypass Command Sequence
Figure Program Operation
Chip Erase Command Sequence Sector Erase Command Sequence Erase Suspend/Erase Resume Commands
Figure Erase Operation.
Simultaneous Operation
Table Bank Select
Writing Commands/Command Sequences Accelerated Program Operation Autoselect Functions Standby Mode Automatic Sleep Mode RESET#: Hardware Reset Output Disable Mode
Table Sector Address Table Table SecSi Sector Addresses
Autoselect Mode.
Table Autoselect Codes (High Voltage Method) Table Sector Block Addresses Protection/Unprotection
Sector Protection Persistent Sector Protection Persistent Protection (PPB) Persistent Protection Lock (PPB Lock) Dynamic Protection (DYB)
Table Sector Protection Schemes
Password Program Command Password Verify Command Password Protection Mode Locking Program Command Persistent Sector Protection Mode Locking Program Command SecSi Sector Protection Program Command Lock Command Write Command Password Unlock Command Program Command Erase Command Write Command Lock Command Lock Status Command Sector Protection Status Command Command Definitions Tables.
Table Memory Array Command Definitions (x32 Mode) Table Sector Protection Command Definitions (x32 Mode) Table Memory Array Command Definitions (x16 Mode) Table Sector Protection Command Definitions (x16 Mode)
Persistent Sector Protection Mode Locking Password Protection Mode Password Password Mode Locking 64-bit Password Write Protect (WP#) Persistent Protection Lock High Voltage Sector Protection
Figure In-System Sector Protection/ Sector Unprotection Algorithms
Write Operation Status DQ7: Data# Polling
Figure Data# Polling Algorithm
RY/BY#: Ready/Busy#. DQ6: Toggle
Figure Toggle Algorithm.
Temporary Sector Unprotect
Figure Temporary Sector Unprotect Operation.
SecSi(Secured Silicon) Sector Flash Memory Region SecSi Sector Protection Utilizing Password SecSi Sector Concurrently Hardware Data Protection Write Inhibit Write Pulse "Glitch" Protection Logical Inhibit Power-Up Write Inhibit Common Flash Memory Interface (CFI) Table Query Identification String
DQ2: Toggle Reading Toggle Bits DQ6/DQ2 DQ5: Exceeded Timing Limits DQ3: Sector Erase Timer
Table Write Operation Status
Absolute Maximum Ratings.
Figure Maximum Negative Overshoot Waveform Figure Maximum Positive Overshoot Waveform.
Characteristics Test Conditions.
Figure Test Setup. Figure Input Waveforms Measurement Levels
Characteristics Read-Only Operations
Figure Read Operation Timings Figure Page Read Operation Timings.
July 2002
Am29PDL128G
Hardware Reset (RESET#)
Figure Reset Timings Figure Sector/Sector Block Protect Unprotect Timing Diagram
Word/Double Word Configuration (WORD#)
Figure WORD# Timings Read Operations. Figure WORD# Timings Write Operations.
Alternate Controlled Erase Program Operations
Figure Alternate Controlled Write (Erase/Program) Operation Timings.
Erase Program Operations
Figure Program Operation Timings. Figure Accelerated Program Timing Diagram. Figure Chip/Sector Erase Operation Timings Figure Back-to-back Read/Write Cycle Timings Figure Data# Polling Timings (During Embedded Algorithms). Figure Toggle Timings (During Embedded Algorithms). Figure DQ6.
Temporary Sector Unprotect
Figure Temporary Sector Unprotect Timing Diagram
Erase Programming Performance. Latchup Characteristics TSOP Package Capacitance Data Retention. Physical Dimensions LAB080-80-Ball Fortified Ball Grid Array package Revision Summary
Am29PDL128G
July 2002
PRODUCT SELECTOR GUIDE
Part Number Speed Option Voltage Range: 3.0-3.6 Voltage Range: 2.7-3.6 Access Time, (tACC) Access, (tCE) Page Access, (tPACC) Access, (tOE) Note: Characteristics section full specifications. Am29PDL128G
BLOCK DIAGRAM
DQ31-DQ0 RY/BY# (Note Sector Switches
RESET# Erase Voltage Generator State Control Command Register Voltage Generator
Input/Output Buffers
Chip Enable Output Enable Logic
Data Latch
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
A21-A2
X-Decoder
Cell Matrix
A1-A0 (A-1)
Notes: double word mode, input/outputs DQ31-DQ0, address range A21-A0. word mode, input/outputs DQ15-DQ0, address range A21-A-1. RY/BY# open drain output.
July 2002
Am29PDL128G
SIMULTANEOUS OPERATION BLOCK DIAGRAM
DW/W#
A21-A0
Bank Address
Bank Y-gate X-Decoder
A21-A0
RY/BY#
Bank Address
Bank X-Decoder DQ31-DQ0
A21-A0 RESET# DW/W# DQ0-DQ15 X-Decoder A21-A0
Bank Address
STATE CONTROL COMMAND REGISTER
Status DQ31-DQ0 Control DQ31-DQ0
Bank Y-gate
X-Decoder A21-A0
Bank Address
Bank
Am29PDL128G
DQ31-DQ0
DQ31-DQ0
July 2002
CONNECTION DIAGRAMS
80-Ball Fortified View, Balls Facing Down
WORD# RY/BY#
DQ30 DQ15
DQ28 DQ13 DQ12 RESET# DQ19
DQ11 DQ26 DQ27 DQ20 DQ21
DQ25 DQ10 DQ22
DQ24 DQ23
DQ31/A-1 DQ14 DQ16 DQ17 DQ29 DQ18
Special Handling Instructions Packages
Special handling required Flash Memory products molded packages (TSOP, BGA, PLCC, PDIP,
SSOP). package and/or data integrity compromised package body exposed temperatures above 150°C prolonged periods time.
July 2002
Am29PDL128G
DESCRIPTION
A21-A0 Addresses Data Inputs/Outputs DQ31 (Data Input/Output, double word mode), (LSB Address Input, word mode) Chip Enable Output Enable Write Enable DQ30-DQ0 DQ31/A-1
LOGIC SYMBOL
A21-A0 DQ31-DQ0 (A-1)
RESET# WORD#
Hardware Write Protect Input Acceleration Input Hardware Reset Pin, Active Word Enable Input VIL, selects 16-bit mode, VIH, selects 32-bit mode Ready/Busy Output Volt-only Single Power Supply (see Product Selector Guide speed options voltage supply tolerances) Output Buffer Power Supply Device Ground Connected Internally Reserved Future
RESET# WORD# RY/BY#
RY/BY#
Am29PDL128G
July 2002
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination following: Am29PDL128G
OPTIONAL PROCESSING Blank Standard Processing 16-byte devices (Contact representative more information) TEMPERATURE RANGE Industrial (-40°C +85°C) Extended (-55°C +125°C) PACKAGE TYPE 80-Ball Fortified Ball Grid Array (FBGA) pitch, package (LAB080) SPEED OPTION Product Selector Guide Valid Combinations DEVICE NUMBER/DESCRIPTION Am29PDL128G Megabit 16-Bit/4 32-Bit) CMOS Flash Memory Volt-only Read, Program, Erase Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Valid Combinations Packages Order Number Am29PDL128G70R Am29PDL128G70 Am29PDL128G80 Am29PDL128G90 PEI, Package Marking PD128G70R PD128G70V PD128G80V PD128G90V
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Am29PDL128G
DEVICE OPERATIONS
This section describes requirements device operations, which initiated through internal command register. command register itself does occupy addressable memory location. register latch used store commands, along with address data information needed execute command. contents Table register serve inputs internal state machine. state machine outputs dictate function device. Table lists device operations, inputs control levels they require, resulting output. following subsections describe each these operations further detail.
Am29PDL128G Device Operations
DQ31-DQ16
Operation Read Write Standby Output Disable Reset Temporary Sector Unprotect (High Voltage)
RESET#
Addresses (Note
WORD# DOUT High-Z High-Z High-Z
WORD# DQ30-DQ16 High-Z, DQ31 High-Z High-Z High-Z
DQ15- DOUT High-Z High-Z High-Z
Legend: Logic VIL, Logic High VIH, 11.5-12.5 Don't Care, Sector Address, Address Data DOUT Data Notes: Addresses A21-A0 double word mode (WORD# VIH), A21-A-1 word mode (WORD# VIL). sector protect sector unprotect functions also implemented programming equipment. "Sector Protection" section.
Word/Double Word Configuration
WORD# controls whether device data pins operate word double word configuration. WORD# VIH, device double word configuration, DQ31-DQ0 active controlled OE#. WORD# VIL, device word configuration, only data pins DQ15-DQ0 active controlled OE#. data pins DQ30-DQ16 tri-stated, DQ31 used input least significant address (LSB) function, which named A-1.
internal state machine reading array data upon device power-up, after hardware reset. This ensures that spurious alteration memory content occurs during power transition. command necessary this mode obtain array data. Standard microprocessor read cycles that assert valid addresses device address inputs produce valid data device data outputs. Each bank remains enabled read access until command register contents altered. Refer Read-Only Operations table timing specifications Figure timing diagram. ICC1 Characteristics table represents active current specification reading array data. Random Read (Non-Page Read) Address access time (tACC) equal delay from stable addresses valid output data. chip enable access time delay from stable addresses stable valid data output inputs. output enable access time delay from falling edge valid data output
Requirements Reading Array Data
read array data from outputs, system must drive pins VIL. power control selects device. output control gates array data output pins. should remain WORD# determines whether device outputs array data words double words.
Am29PDL128G
July 2002
inputs (assuming addresses have been stable least tACC-tOE time). Page Mode Read device capable fast page mode read compatible with page mode Mask read operation. This mode provides faster read access speed random locations within page. page size device words, double words, with appropriate page being selected higher address bits A21-A2 bits A1-A0 double word mode) word mode) determining specific word/double word within that page. This asynchronous operation with microprocessor supplying specific word double word location. random initial page access equal tACC subsequent page read accesses long locations specified microprocessor falls within that page) equivalent tPACC. When deasserted reasserted subsequent access, access time tACC tCE. Here again, selects device output control should used gate data output inputs device selected. Fast page mode accesses obtained keeping A21-A2 constant changing select specific double word, changing select specific word, within that page. Table
Word Double Word Double Word Double Word Double Word
Simultaneous Operation
device capable reading data from bank memory while program erase operation progress another bank memory (simultaneous operation), addition conventional features (read, program, erase-suspend read, erase-suspend program). bank selected selected bank addresses (A21-A19) with zero latency. simultaneous operation execute multi-function mode same bank. Table
Bank Bank Bank Bank Bank
Bank Select
A21-A19 001, 010, 100, 101,
Writing Commands/Command Sequences
write command command sequence (which includes programming data device erasing sectors memory), system must drive VIL, VIH. program operations, WORD# determines whether device accepts program data double words words. Refer "Word/Double Word Configuration" more information. device features Unlock Bypass mode facilitate faster programming. Once bank enters Unlock Bypass mode, only write cycles required program double word word, instead four. "Double Word/Word Program Command Sequence" section details programming data device using both standard Unlock Bypass command sequences.
Page Select, Double Word Mode
Table
Word Word Word Word Word Word Word Word Word
Page Select, Word Mode
erase operation erase sector, multiple sectors, entire device. Table indicates address space that each sector occupies. "bank address" address bits required uniquely select bank. Similarly, "sector address" refers address bits required uniquely select sector. "Command Definitions" section details erasing sector entire chip, suspending/resuming erase operation. ICC2 Characteristics table represents active current specification write mode. Characteristics section contains timing specification tables timing diagrams write operations.
July 2002
Am29PDL128G
Accelerated Program Operation device offers accelerated program operations through function. This function primarily intended allow faster manufacturing throughput factory. system asserts this pin, device automatically enters aforementioned Unlock Bypass mode, temporarily unprotects protected sectors, uses higher voltage reduce time required program operations. system would two-cycle program command sequence required Unlock Bypass mode. Removing from returns device normal operation. Note that must asserted operations other than accelerated programming, device damage result. Autoselect Functions system writes autoselect command sequence, device enters autoselect mode. system then read autoselect codes from internal register (which separate from memory array) DQ15-DQ0. Standard read cycle timings apply this mode. Refer Autoselect Mode Autoselect Command Sequence sections more information. this mode when addresses remain stable tACC automatic sleep mode independent CE#, WE#, control signals. Standard address access timings provide data when addresses changed. While sleep mode, output data latched always available system. Note that during automatic sleep mode, must before device reduces current stated sleep mode specification. ICC5 Characteristics table represents automatic sleep mode current specification.
RESET#: Hardware Reset
RESET# provides hardware method resetting device reading array data. When RESET# driven least period tRP, device immediately terminates operation progress, tristates output pins, ignores read/write commands duration RESET# pulse. device also resets internal state machine reading array data. operation that interrupted should reinitiated once device ready accept another command sequence, ensure data integrity. Current reduced duration RESET# pulse. When RESET# held VSS±0.3 device draws CMOS standby current (ICC4). RESET# held within VSS±0.3 standby current will greater. RESET# tied system reset circuitry. system reset would thus also reset Flash memory, enabling system read boot-up firmware from Flash memory. RESET# asserted during program erase operation, RY/BY# remains (busy) until internal reset operation complete, which requires time READY (during Embedded Algorithms). system thus monitor RY/BY# determine whether reset operation complete. RESET# asserted when program erase operation executing (RY/BY# "1"), reset operation completed within time tREADY (not during Embedded Algorithms). system read data after RESET# returns VIH. Refer Characteristics tables RESET# parameters Figure timing diagram.
Standby Mode
When system reading writing device, place device standby mode. this mode, current consumption greatly reduced, outputs placed high impedance state, independent input. device enters CMOS standby mode when RESET# pins both held (Note that this more restricted voltage range than VIH.) RESET# held VIH, within device will standby mode, standby current will greater. device requires standard access time read access when device either these standby modes, before ready read data. device deselected during erasure programming, device draws active current until operation completed. ICC3 Characteristics table represents CMOS standby current specification.
Output Disable Mode
When input VIH, output from device disabled. output pins (except RY/BY#) placed high impedance state.
Automatic Sleep Mode
automatic sleep mode minimizes Flash device energy consumption. device automatically enables
Am29PDL128G
July 2002
Table
Sector Address (A21-A11) 00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 00000100XXX 00000101XXX 00000110XXX 00000111XXX 00001000XXX 00001001XXX 00001010XXX 00001011XXX 00001100XXX 00001101XXX 00001110XXX 00001111XXX 00010000XXX 00010001XXX 00010010XXX 00010011XXX 00010100XXX 00010101XXX 00010110XXX 00010111XXX 00011000XXX 00011001XXX 00011010XXX 00011011XXX 00011100XXX 00011101XXX 00011110XXX 00011111XXX
Sector Address Table
Sector Size (Kwords/ Kdoublewords) 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Address Range (x16) 00000h-00FFFh 01000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-04FFFh 05000h-05FFFh 06000h-06FFFh 07000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-FFFFFh Address Range (x32) 000000h-0007FFh 000800h-000FFFh 001000h-0017FFh 001800h-001FFFh 002000h-0027FFh 002800h-002FFFh 003000h-0037FFh 003800h-003FFFh 004000h-007FFFh 008000h-00BFFFh 00C000h-00FFFFh 010000h-013FFFh 014000h-017FFFh 018000h-01BFFFh 01C000h-01FFFFh 020000h-023FFFh 024000h-027FFFh 028000h-02BFFFh 02C000h-02FFFFh 030000h-033FFFh 034000h-037FFFh 038000h-03BFFFh 03C000h-03FFFFh 040000h-043FFFh 044000h-047FFFh 048000h-04BFFFh 04C000h-04FFFFh 050000h-053FFFh 054000h-057FFFh 058000h-05BFFFh 05C000h-05FFFFh 060000h-063FFFh 064000h-067FFFh 068000h-06BFFFh 06C000h-06FFFFh 070000h-073FFFh 074000h-077FFFh 078000h-07BFFFh 07C000-07FFFFh
Bank
Sector SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17
Bank
SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
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Am29PDL128G
Table
Sector Address (A21-A11) 00100000XXX 00100001XXX 00100010XXX 00100011XXX 00100100XXX 00100101XXX 00100110XXX 00100111XXX 00101000XXX 00101001XXX 00101010XXX 00101011XXX 00101100XXX 00101101XXX 00101110XXX 00101111XXX 00110000XXX 00110001XXX 00110010XXX 00110011XXX 00110100XXX 00110101XXX 00110110XXX 00110111XXX 00111000XXX 00111001XXX 00111010XXX 00111011XXX 00111100XXX 00111101XXX 00111110XXX 00111111XXX 01000000XXX 01000001XXX 01000010XXX 01000011XXX 01000100XXX 01000101XXX 01000110XXX 01000111XXX 01001000XXX 01001001XXX
Sector Address Table (Continued)
Sector Size (Kwords/ Kdoublewords) 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Address Range (x16) 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh Address Range (x32) 080000h-083FFFh 084000h-087FFFh 088000h-08BFFFh 08C000h-08FFFFh 090000h-093FFFh 094000h-097FFFh 098000h-09BFFFh 09C000h-09FFFFh 0A0000h-0A3FFFh 0A4000h-0A7FFFh 0A8000h-0ABFFFh 0AC000h-0AFFFFh 0B0000h-0B3FFFh 0B4000h-0B7FFFh 0B8000h-0BBFFFh 0BC000h-0BFFFFh 0C0000h-0C3FFFh 0C4000h-0C7FFFh 0C8000h-0CBFFFh 0CC000h-0CFFFFh 0D0000h-0D3FFFh 0D4000h-0D7FFFh 0D8000h-0DBFFFh 0DC000h-0DFFFFh 0E0000h-0E3FFFh 0E4000h-0E7FFFh 0E8000h-0EBFFFh 0EC000h-0EFFFFh 0F0000h-0F3FFFh 0F4000h-0F7FFFh 0F8000h-0FBFFFh 0FC000h-0FFFFFh 100000h-103FFFh 104000h-107FFFh 108000h-10BFFFh 10C000h-10FFFFh 110000h-113FFFh 114000h-117FFFh 118000h-11BFFFh 11C000h-11FFFFh 120000h-123FFFh 124000h-127FFFh
Bank
Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58
Bank
SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80
Am29PDL128G
July 2002
Table
Sector Address (A21-A11) 01001010XXX 01001011XXX 01001100XXX 01001101XXX 01001110XXX 01001111XXX 01010000XXX 01010001XXX 01010010XXX 01010011XXX 01010100XXX 01010101XXX 01010110XXX 01010111XXX 01011000XXX 01011001XXX 01011010XXX 01011011XXX 01011100XXX 01011101XXX 01011110XXX 01011111XXX 01100000XXX 01100001XXX 01100010XXX 01100011XXX 01100100XXX 01100101XXX 01100110XXX 01100111XXX 01101000XXX 01101001XXX 01101010XXX 01101011XXX 01101100XXX 01101101XXX 01101110XXX 01101111XXX 01110000XXX
Sector Address Table (Continued)
Sector Size (Kwords/ Kdoublewords) 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Address Range (x16) 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh Address Range (x32) 128000h-12BFFFh 12C000h-12FFFFh 130000h-133FFFh 134000h-137FFFh 138000h-13BFFFh 13C000h-13FFFFh 140000h-143FFFh 144000h-147FFFh 148000h-14BFFFh 14C000h-14FFFFh 150000h-153FFFh 154000h-157FFFh 158000h-15BFFFh 15C000h-15FFFFh 160000h-163FFFh 164000h-167FFFh 168000h-16BFFFh 16C000h-16FFFFh 170000h-173FFFh 174000h-177FFFh 178000h-17BFFFh 17C000h-17FFFFh 180000h-183FFFh 184000h-187FFFh 188000h-18BFFFh 18C000h-18FFFFh 190000h-193FFFh 194000h-197FFFh 198000h-19BFFFh 19C000h-19FFFFh 1A0000h-1A3FFFh 1A4000h-1A7FFFh 1A8000h-1ABFFFh 1AC000h-1AFFFFh 1B0000h-1B3FFFh 1B4000h-1B7FFFh 1B8000h-1BBFFFh 1BC000h-1BFFFFh 1C0000h-1C3FFFh
Bank
Sector SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97
Bank (continued)
SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119
July 2002
Am29PDL128G
Table
Sector Address (A21-A11) 01110001XXX 01110010XXX 01110011XXX 01110100XXX 01110101XXX 01110110XXX 01110111XXX 01111000XXX 01111001XXX 01111010XXX 01111011XXX 01111100XXX 01111101XXX 01111110XXX 01111111XXX 10000000XXX 10000001XXX 10000010XXX 10000011XXX 10000100XXX 10000101XXX 10000110XXX 10000111XXX 10001000XXX 10001001XXX 10001010XXX 10001011XXX 10001100XXX 10001101XXX 10001110XXX 10001111XXX 10010000XXX 10010001XXX 10010010XXX 10010011XXX 10010100XXX 10010101XXX 10010110XXX 10010111XXX
Sector Address Table (Continued)
Sector Size (Kwords/ Kdoublewords) 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Address Range (x16) 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh 400000h-407FFFh 408000h-40FFFFh 410000h-417FFFh 418000h-41FFFFh 420000h-427FFFh 428000h-42FFFFh 430000h-437FFFh 438000h-43FFFFh 440000h-447FFFh 448000h-44FFFFh 450000h-457FFFh 458000h-45FFFFh 460000h-467FFFh 468000h-46FFFFh 470000h-477FFFh 478000h-47FFFFh 480000h-487FFFh 488000h-48FFFFh 490000h-497FFFh 498000h-49FFFFh 4A0000h-4A7FFFh 4A8000h-4AFFFFh 4B0000h-4B7FFFh A48000h-4BFFFFh Address Range (x32) 1C4000h-1C7FFFh 1C8000h-1CBFFFh 1CC000h-1CFFFFh 1D0000h-1D3FFFh 1D4000h-1D7FFFh 1D8000h-1DBFFFh 1DC000h-1DFFFFh 1E0000h-1E3FFFh 1E4000h-1E7FFFh 1E8000h-1EBFFFh 1EC000h-1EFFFFh 1F0000h-1F3FFFh 1F4000h-1F7FFFh 1F8000h-1FBFFFh 1FC000h-1FFFFFh 200000h-203FFFh 204000h-207FFFh 208000h-20BFFFh 20C000h-20FFFFh 210000h-213FFFh 214000h-217FFFh 218000h-21BFFFh 21C000h-21FFFFh 220000h-223FFFh 224000h-227FFFh 228000h-22BFFFh 22C000h-22FFFFh 230000h-233FFFh 234000h-237FFFh 238000h-23BFFFh 23C000h-23FFFFh 240000h-243FFFh 244000h-247FFFh 248000h-24BFFFh 24C000h-24FFFFh 250000h-253FFFh 254000h-257FFFh 258000h-25BFFFh 25C000h-25FFFFh
Bank
Sector SA120 SA121 SA122 SA123 SA124
Bank (continued)
SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145
Bank
SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158
Am29PDL128G
July 2002
Table
Sector Address (A21-A11) 10011000XXX 10011001XXX 10011010XXX 10011011XXX 10011100XXX 10011101XXX 10011110XXX 10011111XXX 10100000XXX 10100001XXX 10100010XXX 10100011XXX 10100100XXX 10100101XXX 10100110XXX 10100111XXX 10101000XXX 10101001XXX 10101010XXX 10101011XXX 10101100XXX 10101101XXX 10101110XXX 10101111XXX 10110000XXX 10110001XXX 10110010XXX 10110011XXX 10110100XXX 10110101XXX 10110110XXX 10110111XXX 10111000XXX 10111001XXX 10111010XXX 10111011XXX 10111100XXX 10111101XXX 10111110XXX
Sector Address Table (Continued)
Sector Size (Kwords/ Kdoublewords) 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Address Range (x16) 4C0000h-4C7FFFh 4C8000h-4CFFFFh 4D0000h-4D7FFFh 4D8000h-4DFFFFh 4E0000h-4E7FFFh 4E8000h-4EFFFFh 4F0000h-4F7FFFh 4F8000h-4FFFFFh 500000h-507FFFh 508000h-50FFFFh 510000h-517FFFh 518000h-51FFFFh 520000h-527FFFh 528000h-52FFFFh 530000h-537FFFh 538000h-53FFFFh 540000h-547FFFh 548000h-54FFFFh 550000h-557FFFh 558000h-55FFFFh 560000h-567FFFh 568000h-56FFFFh 570000h-577FFFh 578000h-57FFFFh 580000h-587FFFh 588000h-58FFFFh 590000h-597FFFh 598000h-59FFFFh 5A0000h-5A7FFFh 5A8000h-5AFFFFh 5B0000h-5B7FFFh 5B8000h-5BFFFFh 5C0000h-5C7FFFh 5C8000h-5CFFFFh 5D0000h-5D7FFFh 5D8000h-5DFFFFh 5E0000h-5E7FFFh 5E8000h-5EFFFFh 5F0000h-5F7FFFh Address Range (x32) 260000h-263FFFh 264000h-267FFFh 268000h-26BFFFh 26C000h-26FFFFh 270000h-273FFFh 274000h-277FFFh 278000h-27BFFFh 27C000h-27FFFFh 280000h-283FFFh 284000h-287FFFh 288000h-28BFFFh 28C000h-28FFFFh 290000h-293FFFh 294000h-297FFFh 298000h-29BFFFh 29C000h-29FFFFh 2A0000h-2A3FFFh 2A4000h-2A7FFFh 2A8000h-2ABFFFh 2AC000h-2AFFFFh 2B0000h-2B3FFFh 2B4000h-2B7FFFh 2B8000h-2BBFFFh 2BC000h-2BFFFFh 2C0000h-2C3FFFh 2C4000h-2C7FFFh 2C8000h-2CBFFFh 2CC000h-2CFFFFh 2D0000h-2D3FFFh 2D4000h-2D7FFFh 2D8000h-2DBFFFh 2DC000h-2DFFFFh 2E0000h-2E3FFFh 2E4000h-2E7FFFh 2E8000h-2EBFFFh 2EC000h-2EFFFFh 2F0000h-2F3FFFh 2F4000h-2F7FFFh 2F8000h-2FBFFFh
Bank
Sector SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175
Bank (continued)
SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197
July 2002
Am29PDL128G
Table
Sector Address (A21-A11) 10111111XXX 11000000XXX 11000001XXX 11000010XXX 11000011XXX 11000100XXX 11000101XXX 11000110XXX 11000111XXX 11001000XXX 11001001XXX 11001010XXX 11001011XXX 11001100XXX 11001101XXX 11001110XXX 11001111XXX 11010000XXX 11010001XXX 11010010XXX 11010011XXX 11010100XXX 11010101XXX 11010110XXX 11010111XXX 11011000XXX 11011001XXX 11011010XXX 11011011XXX 11011100XXX 11011101XXX 11011110XXX 11011111XXX
Sector Address Table (Continued)
Sector Size (Kwords/ Kdoublewords) 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Address Range (x16) 5F8000h-5FFFFFh 600000h-607FFFh 608000h-60FFFFh 610000h-617FFFh 618000h-61FFFFh 620000h-627FFFh 628000h-62FFFFh 630000h-637FFFh 638000h-63FFFFh 640000h-647FFFh 648000h-64FFFFh 650000h-657FFFh 658000h-65FFFFh 660000h-667FFFh 668000h-66FFFFh 670000h-677FFFh 678000h-67FFFFh 680000h-687FFFh 688000h-68FFFFh 690000h-697FFFh 698000h-69FFFFh 6A0000h-6A7FFFh 6A8000h-6AFFFFh 6B0000h-6B7FFFh 6B8000h-6BFFFFh 6C0000h-6C7FFFh 6C8000h-6CFFFFh 6D0000h-6D7FFFh 6D8000h-6DFFFFh 6E0000h-6E7FFFh 6E8000h-6EFFFFh 6F0000h-6F7FFFh 6F8000h-6FFFFFh Address Range (x32) 2FC000h-2FFFFFh 300000h-303FFFh 304000h-307FFFh 308000h-30BFFFh 30C000h-30FFFFh 310000h-313FFFh 314000h-317FFFh 318000h-31BFFFh 31C000h-31FFFFh 320000h-323FFFh 324000h-327FFFh 328000h-32BFFFh 32C000h-32FFFFh 330000h-333FFFh 334000h-337FFFh 338000h-33BFFFh 33C000h-33FFFFh 340000h-343FFFh 344000h-347FFFh 348000h-34BFFFh 34C000h-34FFFFh 350000h-353FFFh 354000h-357FFFh 358000h-35BFFFh 35C000h-35FFFFh 360000h-363FFFh 364000h-367FFFh 368000h-36BFFFh 36C000h-36FFFFh 370000h-373FFFh 374000h-377FFFh 378000h-37BFFFh 37C000h-37FFFFh
Bank
Sector SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211
Bank (continued)
SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230
Am29PDL128G
July 2002
Table
Sector Address (A21-A11) 11100000XXX 11100001XXX 11100010XXX 11100011XXX 11100100XXX 11100101XXX 11100110XXX 11100111XXX 11101000XXX 11101001XXX 11101010XXX 11101011XXX 11101100XXX 11101101XXX 11101110XXX 11101111XXX 11110000XXX 11110001XXX 11110010XXX 11110011XXX 11110100XXX 11110101XXX 11110110XXX 11110111XXX 11111000XXX 11111001XXX 11111010XXX 11111011XXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 11111111100 11111111101 11111111110 11111111111
Sector Address Table (Continued)
Sector Size (Kwords/ Kdoublewords) 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Address Range (x16) 700000h-707FFFh 708000h-70FFFFh 710000h-717FFFh 718000h-71FFFFh 720000h-727FFFh 728000h-72FFFFh 730000h-737FFFh 738000h-73FFFFh 740000h-747FFFh 748000h-74FFFFh 750000h-757FFFh 758000h-75FFFFh 760000h-767FFFh 768000h-76FFFFh 770000h-777FFFh 778000h-77FFFFh 780000h-787FFFh 788000h-78FFFFh 790000h-797FFFh 798000h-79FFFFh 7A0000h-7A7FFFh 7A8000h-7AFFFFh 7B0000h-7B7FFFh 7B8000h-7BFFFFh 7C0000h-7C7FFFh 7C8000h-7CFFFFh 7D0000h-7D7FFFh 7D8000h-7DFFFFh 7E0000h-7E7FFFh 7E8000h-7EFFFFh 7F0000h-7F7FFFh 7F8000h-7F8FFFh 7F9000h-7F9FFFh 7FA000h-7FAFFFh 7FB000h-7FBFFFh 7FC000h-7FCFFFh 7FD000h-7FDFFFh 7FE000h-7FEFFFh 7FF000h-7FFFFFh Address Range (x32) 380000h-383FFFh 384000h-387FFFh 388000h-38BFFFh 38C000h-38FFFFh 390000h-393FFFh 394000h-397FFFh 398000h-39BFFFh 39C000h-39FFFFh 3A0000h-3A3FFFh 3A4000h-3A7FFFh 3A8000h-3ABFFFh 3AC000h-3AFFFFh 3B0000h-3B3FFFh 3B4000h-3B7FFFh 3B8000h-3BBFFFh 3BC000h-3BFFFFh 3C0000h-3C3FFFh 3C4000h-3C7FFFh 3C8000h-3CBFFFh 3CC000h-3CFFFFh 3D0000h-3D3FFFh 3D4000h-3D7FFFh 3D8000h-3DBFFFh 3DC000h-3DFFFFh 3E0000h-3E3FFFh 3E4000h-3E7FFFh 3E8000h-3EBFFFh 3EC000h-3EFFFFh 3F0000h-3F3FFFh 3F4000h-3F7FFFh 3F8000h-3FBFFFh 3FC000h-3FC7FFh 3FC800h-3FCFFFh 3FD000h-3FD7FFh 3FD800h-3FDFFFh 3FE000h-3FE7FFh 3FE800h-3FEFFFh 3FF000h-3FF7FFh 3FF800h-3FFFFFh
Bank
Sector SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248
Bank
SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
Note: address range A21:A-1 word mode (WORD#=VIL) A21:A0 double word mode (WORD#=VIH). Address bits A21:A11 uniquely select sector; address bits A21:A19 uniquely select bank.
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Am29PDL128G
Table
Device Am29PDL128G
SecSi Sector Addresses
Sector Size words/64 double words (x32) Address Range 000000h-00003Fh (x16) Address Range 000000h-00007Fh
Autoselect Mode
autoselect mode provides manufacturer device identification, sector protection verification, through identifier codes output DQ7-DQ0. This mode primarily intended programming equipment automatically match device programmed with corresponding programm algorithm. However, autoselect codes also accessed in-system through command register. When using programming equipment, autoselect mode requires address Address pins must shown Table addition, when verifying sector protection, sector address must appear appropriate highest order address bits (see Table Table shows remaining address bits that don't care. When necessary bits have been required, programming equipment then Table
read corresponding identifier code DQ7-DQ0. However, autoselect codes also accessed in-system through command register, instances when device erased programmed system without access high voltage pin. command sequence illustrated Tables Note that Bank Address (BA) address bits A21, A20, asserted during third write cycle autoselect command, host system read autoselect data that bank then immediately read array data from other bank, without exiting autoselect mode. access autoselect codes in-system, host system issue autoselect command command register, shown Tables This method does require VID. Refer Autoselect Command Sequence section more information.
Autoselect Codes (High Voltage Method)
DQ31
(Word/Double Word)
Description Manufacturer Read Cycle Read Cycle Read Cycle Sector Protection Verification SecSi Indicator (DQ7)
(protected), (unprotected) (factory locked), (not factory locked)
000000h 22h/ 222222h 22h/ 222222h 22h/ 222222h 00h/ 000000h 00h/ 000000h
Device
Legend: Logic VIL, Logic High VIH, Bank Address, Sector Address, Don't care. Note: autoselect codes also accessed in-system command sequences.
Am29PDL128G
July 2002
Table
Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7
Sector Block Addresses Protection/Unprotection
SA11 SA14 SA15 SA18 SA19 SA22 SA23 SA26 SA27 SA30 SA31 SA34 SA35 SA38 SA39 SA42 SA43 SA46 SA47 SA50 SA51 SA54 SA55 SA58 SA59 SA62 SA63 SA66 SA67 SA70 SA71 SA74 SA75 SA78 SA79 SA82 SA83 SA86 SA87 SA90 SA91 SA94 SA95 SA98 SA99 SA102 SA10 Sectors
SGA8
SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31
July 2002
Am29PDL128G
Table
Sector Group SGA32 SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 SGA48 SGA49 SGA50 SGA51 SGA52 SGA53 SGA54 SGA55 SGA56 SGA57 SGA58 SGA59 SGA60 SGA61 SGA62 SGA63 SGA64 SGA65
Sector Block Addresses Protection/Unprotection (Continued)
Sectors SA103 SA106 SA107 SA110 SA111 SA114 SA115 SA118 SA119 SA122 SA123 SA126 SA127 SA130 SA131 SA134 SA135 SA138 SA139 SA142 SA143 SA146 SA147 SA150 SA151 SA154 SA155 SA158 SA159 SA162 SA163 SA166 SA167 SA170 SA171 SA174 SA175 SA178 SA179 SA182 SA183 SA186 SA187 SA190 SA191 SA194 SA195 SA198 SA199 SA202 SA203 SA206 SA207 SA210 SA211 SA214 SA215 SA218 SA219 SA222 SA223 SA226 SA227 SA230 SA231 SA234 SA235 SA238
Am29PDL128G
July 2002
Table
Sector Group SGA66 SGA67 SGA68 SGA69 SGA70
Sector Block Addresses Protection/Unprotection (Continued)
SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 SA259 SA261 Sectors SA239 SA242 SA243 SA246 SA247 SA250 SA251 SA254 SA255 SA258
SGA71
SGA72 SGA73 SGA74 SGA75 SGA76 SGA77 SGA78 SGA79
SECTOR PROTECTION
Am29PDL128G features several levels sector protection, which disable both program erase operations certain sectors sector groups: Persistent Sector Protection command sector protection method that replaces controlled protection method. Password Sector Protection highly sophisticated protection method that requires password before changes certain sectors sector groups permitted Hardware Protection write protect that prevent program erase operations sectors 268, 269. parts default operate Persistent Sector Protection mode. customer must then choose Persistent Password Protection method most desirable. There one-time programmable non-volatile bits that define which sector protection method will used. customer decides continue using Persistent Sector Protection method, they must Persistent Sector Protection Mode Locking Bit. This will permanently part operate only using Persistent Sector Protection. customer decides password method, they must Password Mode Locking Bit. This will permanently part operate only using password sector protection. important remember that setting either Persistent Sector Protection Mode Locking Password Mode Locking permanently selects protection mode. possible switch between methods once locking been set. important that mode explicitly selected when device first programmed, rather than relying default mode alone. This that possible system program virus later Password Mode Locking Bit, which would cause unexpected shift from default Persistent Sector Protection Mode into Password Protection Mode. Hardware Protection feature always available, independent software managed protection method chosen. device shipped with sectors unprotected. offers option programming protecting sectors factory prior shipping device through AMD's ExpressFlashService. Contact representative details.
July 2002
Am29PDL128G
possible determine whether sector protected unprotected. Autoselect Mode details. When device first powered DYBs power cleared (sectors protected). Protection State each sector determined logical related that sector. sectors that have PPBs cleared, DYBs control whether sector protected unprotected. issuing Write command sequences, DYBs will cleared, thus placing each sector protected unprotected state. These so-called Dynamic Locked Unlocked states. They called dynamic states because very easy switch back forth between protected unprotected conditions. This allows software easily protect sectors against inadvertent changes does prevent easy removal protection when changes needed. DYBs maybe cleared often needed. PPBs allow more static, difficult change, level protection. PPBs retain their state across power cycles because they Non-Volatile. Individual PPBs with command must cleared group through complex sequence program erasing commands. PPBs also limited erase cycles. Lock adds additional level protection. Once PPBs programmed desired settings, Lock "1". Setting Lock disables program erase commands Non-Volatile PPBs. effect, Lock locks PPBs into their current state. only clear Lock through power cycle. System boot code determine changes needed e.g. allow system code downloaded. changes needed then boot code Lock disable further changes PBBs during system operation. protects bottom sectors when VIL. These sectors generally hold system boot code. prevent changes boot code that could override choices made while setting sector protection during system initialization. possible have sectors that have been persistently locked, sectors that left dynamic state. sectors dynamic state unprotected. there need protect some them, simple Write command sequence that necessary. write command dynamic sectors switch DYBs signify protected unprotected, respectively. there need change status persistently locked sectors, more steps required. First, Lock must disabled either putting device through power-cycle, hardware reset. PPBs then changed reflect desired settings. Setting
Persistent Sector Protection
Persistent Sector Protection method replaces controlled protection method while same time enhancing flexibility providing three different sector protection states: Persistently Locked-A sector protected cannot changed. Dynamically Locked-The sector protected changed simple command Unlocked-The sector unprotected changed simple command order achieve these states, three types "bits" going used: Persistent Protection (PPB) single Persistent (non-volatile) Protection assigned maximum four sectors (see sector address tables specific sector protection groupings). Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) greater flexibility. Each individually modifiable through Write Command. Note: requires erasure, sector PPBs must first preprogrammed prior erasing. PPBs erase parallel, unlike programming where individual PPBs programmable. responsibility user perform preprogramming operation. Otherwise, already erased sector PPBs potential being over-erased. There over-erasure. Persistent Protection Lock (PPB Lock) global volatile bit. When "1", PPBs cannot changed. When cleared ("0"), PPBs changeable. There only Lock device. Lock cleared after power-up hardware reset. There command sequence unlock Lock. Dynamic Protection (DYB) volatile protection assigned each sector. After power-up hardware reset, contents DYBs "0". Each individually modifiable through Write Command. When parts first shipped, PPBs cleared, DYBs cleared, Lock defaulted power cleared state meaning PPBs changeable.
Am29PDL128G
July 2002
lock once again will lock PPBs, device operates normally again. Note: achieve best protection, it's recommended execute lock command early boot code, protect boot code holding VIL. Table
locking bit. This guarantees that hacker could place device password protection mode.
Password Protection Mode
Password Sector Protection Mode method allows even higher level security than Persistent Sector Protection Mode. There main differences between Persistent Sector Protection Password Sector Protection Mode: When device first powered comes reset cycle, Lock locked state, rather than cleared unlocked state. only means clear Lock writing unique 64-bit Password device. Password Sector Protection method otherwise identical Persistent Sector Protection method. 64-bit password only additional tool utilized this method. password stored first eight bytes SecSi Sector. Once Password Mode Locking set, password permanently with means read, program, erase password used clear Lock bit. Password Unlock command must written flash, along with password. flash device internally compares given password with pre-programmed password. they match, Lock cleared, PPBs altered. they match, flash device does nothing. There built-in delay each "password check." This delay intended thwart efforts program that tries possible combinations order crack password. Because password occupies first eight bytes SecSi Sector, password must programmed before either password protection mode selected SecSi Sector protection programmed both SecSi Sector Password Protection same time). Utilizing Password SecSi Sector Concurrently more information.
Sector Protection Schemes
Lock Protected-PPB changeable, changeable Protected-PPB changeable Sector State Unprotected-PPB changeable Unprotected-PPB changable, changable
Table contains possible combinations DYBDYB, PPB, lock relating status sector. summary, set, lock set, sector protected protection removed until next power cycle clears lock. cleared, sector dynamically locked unlocked. then controls whether sector protected unprotected. user attempts program erase protected sector, device ignores command returns read mode. program command protected sector enables status polling approximately before device returns read mode without having modified contents protected sector. erase command protected sector enables status polling approximately after which device returns read mode without having erased protected sector. programming DYB, PPB, lock given sector verified writing DYB/PPB/PPB lock verify command device.
Password Password Mode Locking
order select Password sector protection scheme, customer must first program password. recommends that password somehow correlated unique Electronic Serial Number (ESN) particular flash device. Each different every flash device; therefore each password should different every flash device. While programming password region, customer perform Password Verify operations. Once desired password programmed customer must then Password Mode Locking Bit. This operation achieves objectives:
Persistent Sector Protection Mode Locking
Like password mode locking bit, Persistent Sector Protection mode locking exists guarantee that device remain software sector protection. Once set, Persistent Sector Protection locking prevents programming password protection mode
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Am29PDL128G
permanently sets device operate using Password Protection Mode. possible reverse this function. also disables further commands password region. program, read operations ignored. Both these objectives important, carefully considered, lead unrecoverable errors. user must sure that Password Protection method desired when setting Password Mode Locking Bit. More importantly, user must sure that password correct when Password Mode Locking set. fact that read operations disabled, there means verify what password afterwards. password lost after setting Password Mode Locking Bit, there will clear Lock bit. Password Mode Locking Bit, once set, prevents reading 64-bit password further password programming. Password Mode Locking erasable. Once Password Mode Locking programmed, Persistent Sector Protection Locking disabled from programming, guaranteeing that changes protection scheme allowed. system asserts pin, device disables program erase functions sectors 268, independent whether previously protected unprotected using High Voltage Sector Protection. system asserts pin, device reverts whether sectors 268, were last protected unprotected. That sector protection unprotection these sectors depends whether they were previously protected unprotected using High Voltage Sector Protection. Persistent Protection Lock Persistent Protection (PPB) Lock volatile that reflects state Password Mode Locking after power-up reset. Password Mode Lock also after hardware reset (RESET# asserted) power-up reset. ONLY means clearing Lock Password Protection Mode issue Password Unlock command. Successful execution Password Unlock command clears Lock Bit, allowing sector PPBs modifications. Asserting RESET#, taking device through power-on reset, issuing Lock command sets Lock when Password Mode Lock set. Password Mode Locking set, including Persistent Protection Mode, Lock cleared after power-up hardware reset. Lock issuing Lock command. Once only means clearing Lock issuing hardware power-up reset. Password Unlock command ignored Persistent Protection Mode.
64-bit Password
64-bit Password located memory space accessible through Password Program Verify commands (see "Password Verify Command"). password function works conjunction with Password Mode Locking Bit, which when set, prevents Password Verify command from reading contents password pins device.
Write Protect (WP#)
Write Protect feature provides hardware method protecting sectors 268, without using VID. This function provided overrides previously discussed Sector Protection/Unprotection method.
High Voltage Sector Protection
Sector protection unprotection also implemented using programming equipment. procedure requires high voltage (VID) placed RESET# pin. Refer Figure details this procedure. Note that sector unprotect, unprotected sectors must first protected prior first sector write cycle.
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START PLSCNT RESET# Wait Protect sectors: indicated portion sector protect algorithm must performed unprotected sectors prior issuing first sector unprotect address START PLSCNT RESET# Wait
Temporary Sector Unprotect Mode
First Write Cycle 60h? sector address Sector Protect: Write sector address with A6-A0 0111010 Wait Verify Sector Protect: Write sector address with A6-A0 0111010 Read from sector address with A6-A0 0111010
First Write Cycle 60h? sectors protected? first sector address Sector Unprotect: Write sector address with A6-A0 1111010
Temporary Sector Unprotect Mode
Increment PLSCNT
Reset PLSCNT
Wait Verify Sector Unprotect: Write sector address with A6-A0 1111010
PLSCNT Data 01h?
Increment PLSCNT
Read from sector address with A6-A0 1111010 next sector address
Device failed
Protect another sector? Remove from RESET#
PLSCNT 1000?
Data 00h?
Device failed Write reset command
Last sector verified?
Sector Protect Algorithm
Sector Protect complete
Sector Unprotect Algorithm
Remove from RESET#
Write reset command Sector Unprotect complete
Figure In-System Sector Protection/ Sector Unprotection Algorithms
Note:These algorithms valid only Persistent Sector Protection mode. They valid Password Protection Mode.
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Temporary Sector Unprotect
This feature allows temporary unprotection previously protected sectors change data in-system. Sector Unprotect mode activated setting RESET# VID. During this mode, formerly protected sectors programmed erased selecting sector addresses. Once removed from RESET# pin, previously protected sectors protected again. Figure shows algorithm, Figure shows timing diagrams, this feature.
offers device with SecSi Sector either ctor able factory-locked version always protected when shipped from factory, SecSi Sector Indicator permanently "1." customer-lockable version shipped with SecSi Sector unprotected, allowing customers utilize that sector manner they choose. customer-lockable version SecSi Sector Indicator permanently "0." Thus, SecSi Sector Indicator prevents customer-lockable devices from being used replace devices that factory locked. system accesses SecSi Sector through command sequence (see Enter SecSi Sector/Exit SecSi Sector Command Sequence). After system written Enter SecSi Sector command sequence, read SecSi Sector using addresses normally occupied boot sectors. This mode operation continues until system issues Exit SecSi Sector command sequence, until power removed from device. power-up, following hardware reset, device reverts sending commands normal address space. Factory Locked: SecSi Sector Programmed Protected Factory factory locked device, SecSi Sector protected when device shipped from factory. SecSi Sector cannot modified way. device preprogrammed with both random number secure ESN. SecSi Sector located 000000h-00003Fh double word mode). device available preprogrammed with following: random, secure only Customer code through ExpressFlash service Both random, secure customer code through ExpressFlash service. Customers have their code programmed through ExpressFlash service. programs customer's code, with without random ESN. devices then shipped from AMD's factory with SecSi Sector permanently locked. Contact representative details using AMD's ExpressFlash service. Customer Lockable: SecSi Sector Programmed Protected Factory security feature required, SecSi Sector treated additional Flash memory space. SecSi Sector read number times, programmed locked only once. Note that accelerated programming (ACC) unlock bypass functions available when programming SecSi Sector.
START
RESET# (Note Perform Erase Program Operations
RESET#
Temporary Sector Unprotect Completed (Note
Notes: protected sectors unprotected VIL, sectors 268, will remain protected). previously protected sectors protected once again.
Figure
Temporary Sector Unprotect Operation
SecSi(Secured Silicon) Sector Flash Memory Region
SecSi (Secured Silicon) Sector feature provides Flash memory region that enables permanent part identification through Electronic Serial Number (ESN). SecSi Sector words double words) length, uses SecSi Sector Indicator (DQ7) indicate whether SecSi Sector locked when shipped from factory. This permanently factory cannot changed, which prevents cloning factory locked part. This ensures security once product shipped field.
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SecSi Sector area protected using following procedures: Write three-cycle Enter SecSi Sector Region command sequence, then follow in-system sector protect algorithm shown Figure except that RESET# either VID. This allows in-system protection SecSi Sector Region without raising device high voltage. Note that this method only applicable SecSi Sector. Write three-cycle Enter SecSi Sector Secure Region command sequence, then alternate method sector protection described Sector Protection section. Once SecSi Sector locked verified, system must write Exit SecSi Sector Region command sequence return reading writing remainder array. SecSi Sector lock must used with caution since, once locked, there procedure available unlocking SecSi Sector area none bits SecSi Sector memory space modified way. SecSi Sector Protection SecSi Sector Protection prevents programming SecSi Sector memory area. Once set, SecSi Sector memory area contents non-modifiable. Utilizing Password SecSi Sector Concurrently password must stored first eight bytes SecSi Sector. Once device permanently locked into Password Protection Mode, erase, program, read operation longer work those eight bytes password SecSi Sector. Once SecSi Sector protection programmed, location SecSi Sector programmed. both Password Protection SecSi Sector concurrently, user must always program password into first eight bytes SecSi Sector before either Password Protection Mode selected SecSi Sector protection programmed. Method Enter SecSi Sector issuing SecSi Sector Entry command. Program 64-bit password issuing Password Program Password Verify commands Lock password issuing Password Protection Mode Locking Program command. Program SecSi Sector, excluding bytes 0-7. Lock SecSi Sector issuing SecSi Sector Protection Program command. Exit SecSi Sector issuing SecSi Sector Exit Reset command
Note: Step performed prior step
Method Enter SecSi Sector issuing SecSi Sector Entry command. Program entire SecSi Sector, including first eight bytes contain 64-bit password. Lock password issuing Password Protection Mode Locking Program command. Lock SecSi Sector issuing SecSi Sector Protection Program command. Exit SecSi Sector issuing SecSi Sector Exit Reset command
Note: Step performed prior step
Hardware Data Protection
command sequence requirement unlock cycles programming erasing provides data protection against inadvertent writes. addition, following hardware data protection measures prevent accidental erasure programming, which might otherwise caused spurious system level signals during power-up power-down transitions, from system noise. Write Inhibit When less than LKO, device does accept write cycles. This protects data during power-up power-down. command register internal program/erase circuits disabled, device resets read mode. Subsequent writes ignored until greater than VLKO. system must provide proper signals control pins prevent unintentional writes when greater than VLKO. Write Pulse "Glitch" Protection Noise pulses less than (typical) OE#, initiate write cycle. Logical Inhibit Write cycles inhibited holding VIL, initiate write cycle, must logical zero while logical one. Power-Up Write Inhibit during power device does accept commands rising edge WE#. internal state machine automatically reset read mode power-up.
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COMMON FLASH MEMORY INTERFACE (CFI)
Common Flash Interface (CFI) specification outlines device host system software interrogation handshake, which allows specific vendor-specified software algorithms used entire families devices. Software support then device-independent, JEDEC ID-independent, forward- backward-compatible specified flash device families. Flash vendors standardize their existing interfaces long-term compatibility. This device enters Query mode when system writes Query command, 98h, address word mode address byte mode), time device ready read array data. system read information addresses given Tables 10-13. terminate reading data, Table
Addresses (Double Word Mode) Addresses (Word Mode)
system must write reset command. Query mode accessible when device executing Embedded Program embedded Erase algorithm. system also write query command when device autoselect mode. device enters query mode, system read data addresses given Tables 10-13. system must write reset command return device reading array data. further information, please refer Specification Publication 100, available World Wide http://www.am Alternatively, contact representative copies these documents.
Query Identification String
Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
Description Query Unique ASCII string "QRY"
Primary Command Address Primary Extended Table Alternate Command (00h none exists) Address Alternate Extended Table (00h none exists)
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Table
Addresses (Double Word Mode) Addresses (Word Mode)
System Interface String
Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h
Description Min. (write/erase) D7-D4: volt, D3-D0: millivolt Max. (write/erase) D7-D4: volt, D3-D0: millivolt Min. voltage (00h present) Max. voltage (00h present) Typical timeout single byte/word write Typical timeout Min. size buffer write (00h supported) Typical timeout individual block erase Typical timeout full chip erase (00h supported) Max. timeout byte/word write times typical Max. timeout buffer write times typical Max. timeout individual block erase times typical Max. timeout full chip erase times typical (00h supported)
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Table
Addresses (Double Word Mode) Addresses (Word Mode)
Device Geometry Definition
Data 0018h 0005h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Device Size byte
Description
Flash Device Interface description (refer publication 100) Max. number byte multi-byte write (00h supported) Number Erase Block Regions within device Erase Block Region Information (refer specification publication 100)
Erase Block Region Information (refer specification publication 100)
Erase Block Region Information (refer specification publication 100)
Erase Block Region Information (refer specification publication 100)
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Table
Addresses (Double Word Mode) Addresses (Word Mode)
Primary Vendor-Specific Extended Query
Data 0050h 0052h 0049h 0031h 0033h 0004h
Description Query-unique ASCII string "PRI" Major version number, ASCII (reflects modifications silicon) Minor version number, ASCII (reflects modifications table) Address Sensitive Unlock (Bits 1-0) Required, Required Silicon Revision Number (Bits 7-2)
0002h 0001h 0001h
Erase Suspend Supported, Read Only, Read Write Sector Protect Supported, Number sectors group Sector Temporary Unprotect Supported, Supported Sector Protect/Unprotect scheme =29F040 mode, 29F016 mode, 29F400, 29LV800 mode Simultaneous Operation Supported, Number Sectors excluding Bank Burst Mode Type Supported, Supported Page Mode Type Supported, Word Page, Word Page (Acceleration) Supply Minimum Supported, D7-D4: Volt, D3-D0: (Acceleration) Supply Maximum Supported, D7-D4: Volt, D3-D0: Top/Bottom Boot Sector Flag
0007h
00E7h 0000h 0002h 00B5h
0005h
0001h
Uniform device, Uniform, Kbit Bottom, Bottom Boot Device, Boot Device, Both Bottom Program Suspend supported, Supported Bank Organization Data zero, Number Banks Bank Region Information Number Sectors Bank Bank Region Information Number Sectors Bank Bank Region Information Number Sectors Bank Bank Region Information Number Sectors Bank
0000h
0004h
*0027h
*0060h
*0060h
0027h
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Am29PDL128G
COMMAND DEFINITIONS
Writing specific address data commands sequences into command register initiates device operations. Tables 14-17 define valid register command sequences. Writing incorrect address data values writing them improper sequence resets device reading array data. addresses latched falling edge CE#, whichever happens later. data latched rising edge CE#, whichever happens first. Refer Characteristics section timing diagrams. which system writing read mode. program command sequence written bank that Erase Suspend mode, writing reset suspend-read mode. Once programming begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles autoselect command sequence. Once autoselect mode, reset command must written return read mode. bank entered autoselect mode while Erase Suspend mode, writing reset command returns that bank erase-suspend-read mode. goes high during program erase operation, writing reset command returns banks read mode erase-suspend-read mode that bank Erase Suspend).
Reading Array Data
device automatically reading array data after device power-up. commands required retrieve data. Each bank ready read array data after completing Embedded Program Embedded Erase algorithm. After device accepts Erase Suspend command, corresponding bank enters eras e-sus pend-read mode, after which system read data from non-erase-suspended sector within same bank. system read array data using standard read timing, except that reads address within erase-suspended sectors, device outputs status data. After completing programming operation Erase Suspend mode, system once again read array data with same exception. Erase Suspend/Erase Resume Commands section more information. system must issue reset command return bank read erase-suspend-read) mode goes high during active program erase operation, bank autoselect mode. next section, Reset Command, more information. also Requirements Reading Array Data Device Operations section more information. Read-Only Operations table provides read parameters, Figure shows timing diagram.
Autoselect Command Sequence
autoselect command sequence allows host system access manufacturer device codes, determine whether sector protected. autoselect command sequence written address within bank that either read erase-suspend-read mode. autoselect command written while device actively programming erasing other bank. autoselect command sequence initiated first writing unlock cycles. This followed third write cycle that contains bank address autoselect command. bank then enters autoselect mode. system read number autoselect codes without reinitiating command sequence. Tables show address data requirements. determine sector protection information, system must write appropriate bank address (BA) sector address (SA). Table shows address range bank number associated with each sector. system must write reset command return read mode erase-suspend-read mode bank previously Erase Suspend).
Reset Command
Writing reset command resets banks read erase-suspend-read mode. Address bits don't cares this command. reset command written between sequence cycles erase command sequence before erasing begins. This resets bank which system writing read mode. Once erasure begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles program command sequence before programming begins. This resets bank
Enter SecSi Sector/Exit SecSi Sector Command Sequence
SecSi Sector region provides secured data area containing random, eight word/four double word electronic serial number (ESN). system access SecSi Sector region issuing three-cycle Enter SecSi Sector command sequence. device continues access SecSi Sector region
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until system issues four-cycle Exit SecSi Sector command sequence. Exit SecSi Sector comm operation. SecSi Sector accessible when device executing Embedded Program embedded Erase algorithm. Tables show address data requirements both command sequences. also "SecSi(Secured Silicon) Sector Flash Memory Region" further information. data still "0." Only erase operations convert "1." Unlock Bypass Command Sequence unlock bypass feature allows system program data bank faster than using standard program command sequence. unlock bypass command sequence initiated first writing unlock cycles. This followed third write cycle containing unlock bypass command, 20h. That bank then enters unlock bypass mode. two-cycle unlock bypass program command sequence that required program this mode. first cycle this sequence contains unlock bypass program command, A0h; second cycle contains program address data. Additional data programmed same manner. This mode dispenses with initial unlock cycles required standard program command sequence, resulting faster total programming time. Tables show requirements command sequence. During unlock bypass mode, only Unlock Bypass Program Unlock Bypass Reset commands valid. exit unlock bypass mode, system must issue two-cycle unlock bypass reset command sequence. first cycle must contain bank address data 90h. second cycle need only contain data 00h. bank then returns read mode. device offers accelerated program operations through pin. When system asserts pin, device automatically enters Unlock Bypass mode. system then write two-cycle Unlock Bypass program command sequence. device uses higher voltage accelerate operation. Note that must operation other than accelerated programming, device damage result. addition, must left floating unconnected; inconsistent behavior device result. Figure illustrates algorithm program operation. Refer Erase Program Operations table Characteristics section parameters, Figure timing diagrams.
Double Word/Word Program Command Sequence
system program device double word word, depending state WORD# pin. Programming four-bus-cycle operation. program command sequence initiated writing unlock write cycles, followed program set-up command. program address data written next, which turn initiate Embedded Program algorithm. system required provide further controls timings. device automatically provides internally generated program pulses verifies programmed cell margin. Tables show address data requirements program command sequence. When Embedded Program algorithm complete, that bank then returns read mode addresses longer latched. system determine status program operation using DQ7, DQ6, RY/BY#. Refer Write Operation Status section information these status bits. commands written device during Embedded Program Algorithm ignored. Note that hardware reset immediately terminates program operation. program command sequence should reinitiated once that bank returned read mode, ensure data integrity. Programming allowed sequence across sector boundaries. cannot programmed from back "1." Attempting cause that bank cause status bits indicate operation successful. However, succeeding read will show that
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commands written during chip erase operation ignored. However, note that hardware reset immediately terminates erase operation. that occurs, chip erase command sequence should reinitiated once that bank returned reading array data, ensure data integrity. Figure illustrates algorithm erase operation. Refer Erase Program Operations tables Characteristics section parameters, Figure section timing diagrams.
START
Write Program Command Sequence
Embedded Program algorithm progress
Data Poll from System
Sector Erase Command Sequence
Sector erase cycle operation. sector erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock cycles written, then followed address sector erased, sector erase command. Tables show address data requirements sector erase command sequence. device does require system preprogram prior erase. Embedded Erase algorithm automatically programs verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. After command sequence written, sector erase time-out occurs. During time-out period, additional sector addresses sector erase commands written. Loading sector erase buffer done sequence, number sectors from sector sectors. time between these additional cycles must less than otherwise erasure begin. sector erase address command following exceeded time-out accepted. recommended that processor interrupts disabled during this time ensure commands accepted. interrupts re-enabled after last Sector Erase command written. command other than time-out period resets that bank read mode. system must rewrite command sequence additional addresses commands. system monitor determine sector erase timer timed (See section DQ3: Sector Erase Timer.). time-out begins from rising edge final pulse command sequence. When Embedded Erase algorithm complete, bank returns reading array data addresses longer latched. Note that while Embedded Erase operation progress, system read data from non-erasing bank. system determine status erase operation reading
Verify Data?
Increment Address
Last Address?
Programming Completed
Note: Tables program command sequence.
Figure
Program Operation
Chip Erase Command Sequence
Chip erase cycle operation. chip erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed chip erase command, which turn invokes Embedded Erase algorithm. device does require system preprogram prior erase. Embedded Erase algorithm automatically preprograms verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. Tables show address data requirements chip erase command sequence. When Embedded Erase algorithm complete, that bank returns read mode addresses longer latched. system determine status erase operation using DQ7, DQ6, DQ2, RY/BY#. Refer Write Operation Status section information these status bits.
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DQ7, DQ6, DQ2, RY/BY# erasing bank. Refer Write Operation Status section information these status bits. Once sector erase operation begun, only Erase Suspend command valid. other commands ignored. However, note that hardware reset immediately terminates erase operation. that occurs, sector erase command sequence should reinitiated once that bank returned reading array data, ensure data integrity. Figure illustrates algorithm erase operation. Refer Erase Program Operations tables Characteristics section parameters, Figure section timing diagrams. erase-suspend-read mode, system also issue autoselect command sequence. device allows reading autoselect codes even addresses within erasing sectors, since codes stored memory array. When device exits autoselect mode, device reverts Erase Suspend mode, ready another valid operation. Refer Autoselect Mode Autoselect Command Sequence sections details. resume sector erase operation, system must write Erase Resume command (address bits don't care). bank address erase-suspended bank required when writing this command. Further writes Resume command ignored. Another Erase Suspend command written after chip resumed erasing.
Erase Suspend/Erase Resume Commands
Erase Suspend command, B0h, allows system interrupt sector erase operation then read data from, program data sector selected erasure. bank address required when writing this command. This command valid only during sector erase operation, including time-out period during sector erase command sequence. Erase Suspend command ignored written during chip erase operation Embedded Program algorithm. When Erase Suspend command written during sector erase operation, device requires maximum suspend erase operation. However, when Erase Suspend command written during sector erase time-out, device immediately terminates time-out period suspends erase operation. Addresses "don't-cares" when writing Erase suspend command. After erase operation been suspended, bank enters erase-suspend-read mode. system read data from program data sector selected erasure. (The device "erase suspends" sectors selected erasure.) Reading address within erase-suspended sectors produces status information DQ7-DQ0. system DQ7, together, determine sector actively erasing erase-suspended. Refer Write Operation Status section information these status bits. After erase-suspended program operation complete, bank returns erase-suspend-read mode. system determine status program operation using status bits, just standard Double Word/Word Program operation. Refer Write Operation Status section more information.
START
Write Erase Command Sequence (Notes
Data Poll Erasing Bank from System
Embedded Erase algorithm progress
Data FFh?
Erasure Completed
Notes: Tables erase command sequence. section information sector erase timer.
Figure
Erase Operation
Password Program Command
Password Program Command permits programming password that used part hardware protection scheme. actual password 64-bits long. Depending upon state WORD# pin, multiple Password Program Commands required. data bus, Password Program commands required program password.
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Am29PDL128G
data bus, Password Program commands required. user must enter unlock cycle, password program command (38h) program address/data each portion password when programming. There special addressing order required programming password. Also, when password undergoing programming, Simultaneous Operation disabled. Read operations memory location will return programming status. Once prog issu Read/Reset command return device normal operation. Once Password written verified, Password Mode Locking must order prevent verification. Password Program Command only capable programming "0"s. Programming after cell programmed results time-out Embedded Program Algorithmwith cell remaining "0". password when shipped from factory. 64-bit password combinations valid password. Password Programming permitted SecSi sector enabled. Password Protection Mode Locking Program command permitted SecSi sector enabled.
Persistent Sector Protection Mode Locking Program Command
Persistent Sector Protection Mode Locking Program Command programs Persistent Sector Protection Mode Locking Bit, which prevents Password Mode Locking from ever being programmed. Persistent Sector Protection Mode Locking verified programmed without margin, Persistent Sector Protection Mode Locking Program Command should reissued improve program margin. disabling program circuitry Password Mode Locking Bit, device forced remain Persistent Sector Protection mode operation, once this set. Exiting Persistent Protection Mode Locking Program command accomplished writing Read/Reset command. Persistent Sector Protection Mode Locking Program command permitted SecSi sector enabled.
Password Verify Command
Password Verify Command used verify Password. Password verifiable only when Password Mode Locking programmed. Password Mode Locking programmed user attempts verify Password, device will always drive onto data bus. Password Verify command permitted SecSi sector enabled. Also, device will operate Simultaneous Operation when Password Verify command executed. Only password returned regardless bank address. lower address bits (A0:A-1) valid during Password Verify. Writing Read/Reset command returns device back normal operation.
SecSi Sector Protection Program Command
SecSi Sector Protection Program Command programs SecSi Sector Protection Bit, which prevents SecSi sector memory from being cleared. SecSi Sector Protection verified programmed without margin, SecSi Sector Protection Program Command should reissued improve program margin. Exiting VCC-level SecSi Sector Protection Program Command accomplished writing Read/Reset command. SecSi Sector Protection Program command permitted SecSi sector enabled.
Lock Command
Lock command used Lock cleared either reset Password Unlock command successfully executed. There Lock Clear command. Once Lock set, cannot cleared unless device taken through power-on clear Password Unlock command executed. Upon setting Lock Bit, PPBs latched into DYBs. Password Mode Locking set, Lock status reflected set, even after power-on reset cycle. Persistent Sector Protection mode, exiting Lock command accomplished writing Read/Reset command. Lock command permitted SecSi sector enabled.
Password Protection Mode Locking Program Command
Password Protection Mode Locking Program Command programs Password Protection Mode Locking Bit, which prevents further verifies updates Password. Once programmed, Password Protection Mode Locking cannot erased! Password Protection Mode Locking verified program without margin, Password Protection Mode Locking Program command executed improve program margin. Once Password Protection Mode Locking programmed, Persistent Sector Protection Locking program circuitry disabled, thereby forcing device remain Password Protection mode. Exiting Mode Locking Program command accomplished writing Read/Reset command.
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Write Command
Write command used clear given sector. high order address bits (A21-A11) issued same time code DQ7-DQ0. other data pins ignored during data write cycle. DYBs modifiable time, regardless state Lock Bit. DYBs cleared power-up hardware reset.Exiting Write command accomplished writing Read/Reset command. Write command permitted SecSi sector enabled.
Program Command
Program command used program, set, given PPB. Each individually programmed (but bulk erased with other PPBs). specific sector address (A21-A11) written same time program command with Lock corresponding sector, Program command will execute command will time-out without programming PPB. After programming PPB, additional cycles needed determine whether been programmed with margin. been programmed without margin, program command should reissued improve program margin. Program command permitted SecSi sector enabled. Program command does follow Embedded Program algorithm.
Password Unlock Command
Password Unlock command used clear Lock that PPBs unlocked modification, thereby allowing PPBs become accessible modification. exact password must entered order unlocking function occur. This command cannot issued faster than time prevent hacker from running through 64-bit combinations attempt correctly match password. command issued before execution window each portion unlock, command will ignored. Password Unlock function accomplished writing Password Unlock command data device perform clearing Lock Bit. password bits long, user must write Password Unlock command times data times data bus. Once Password Unlock command entered, RY/BY# goes indicating that device busy. Approximately required each portion unlock. Once first portion password unlock completes (RY/BY# driven does toggle when read), Password Unlock command issued again, only this time with next part password. WORD# second Password Unlock command final command before Lock cleared (assuming valid password). WORD# this fourth Password Unlock command. mode, four Password Unlock commands required successfully clear Lock Bit. with first Password Unlock command, RY/BY# signal goes reading device results toggling successive read operations until complete. responsibility microprocessor keep track number Password Unlock commands bus), order, when read Lock confirm successful password unlock Password Unlock command permitted SecSi sector enabled.
Erase Command
Erase command used erase PPBs bulk. There means individually erasing specific PPB. Unlike program, specific sector address required. However, when erase command written (60h) Sector PPBs erased parallel. Lock Erase command will execute command will time-out without erasing PPBs. After erasing PPBs, additional cycles needed determine whether been erased with margin. PPBs been erased without margin, erase command should reissued improve program margin. responsibility user preprogram PPBs prior issuing Erase command. user attempts erase cleared PPB, over-erasure occur making difficult program later time. Also note that total number program/erase cycles limited cycles. Cycling PPBs beyond cycles guaranteed. Erase command permitted SecSi sector enabled.
Write Command
Write command used setting DYB, which volatile that cleared hardware reset. There sector. set, sector protected regardless value DYB. cleared, setting protects sector from programs erases. Since this volatile bit, removing power resetting device will clear DYBs. bank address latched when command written.
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Am29PDL128G
Write command permitted SecSi sector enabled.
Sector Protection Status Command
programming either given sector sector group verified writing Sector Protection Status command device. Note that there single command independently verify programming given sector group.
Lock Command
Lock command used setting lock bit. During Password Protection mode, only Password Unlock command reset Lock Otherwise, power-up hardware reset resets Lock
Lock Status Command
programming Lock verified writing Lock status verify command device.
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Command Definitions Tables
Table
Command (Notes) Read Reset Manufacturer Autoselect (Note Device (10) SecSi Sector Factory Protect Sector Group Protect Verify Program Chip Erase Sector Erase Program/Erase Suspend (11) Program/Erase Resume (12) Query (13) Accelerated Program (15) Configuration Register Verify Configuration Register Write (16) Unlock Bypass Entry (17) Unlock Bypass Program (17) Unlock Bypass Erase (17) Unlock Bypass (13, Unlock Bypass Reset (17) Cycles
Memory Array Command Definitions (x32 Mode)
Cycles (Notes 1-4) Addr Data Addr Data Addr Data (BA)5 (BA)XX (BA)X00 (BA)X01 SA02 (see Note XX00/ XX01 (BA)X0E (BA)X0F Addr Data Addr Data Addr Data
Legend: Address bank switching autoselect mode, bypass mode, erase operation. Determined A21:A19, Tables more detail. Program Address (A21:A0). Addresses latch falling edge pulse, whichever happens later. Program Data (DQ15:DQ0) written location Data latches rising edge pulse, whichever happens first. Notes: Table description operations. values hexadecimal. Shaded cells table denote read cycles. other cycles write operations. During unlock command cycles, when lower address bits 2AAh shown table, address bits higher than (except where required) data bits higher than don't cares. unlock command cycles required when bank reading array data. Reset command required return reading array erase-suspend-read mode previously Erase Suspend) when bank autoselect mode, goes high (while bank providing status information). Cycle autoselect command sequence read cycle. Autoselect Command Sequence section more information. data factory locked factory locked.
Read Address (A21:A0). Read Data (DQ15:DQ0) from location Sector Address (A21:A12) verifying autoselect mode) erasing. Write Data. "Configuration Register" definition specific write data. Data latched rising edge WE#. Don't care
data unprotected sector group protected sector group.
Device must read across cycles System read program non-erasing sectors, enter autoselect mode, when Program/Erase Suspend mode. Program/Erase Suspend command valid only during sector erase operation, requires bank address. Program/Erase Resume command valid only during Erase Suspend mode, requires bank address. Command valid when device ready read array data when device autoselect mode. must during entire operation command. Command ignored during Embedded Program, Embedded Erase, Suspend operation. Unlock Bypass Entry command required prior Unlock Bypass operation. Unlock Bypass Reset command required return reading array.
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Am29PDL128G
Table
Command (Notes) Reset SecSi Sector Entry SecSi Sector Exit SecSi Protection Program Password Program Password Verify Password Unlock Program Erase (13, Lock Lock Status (15) Write Erase Status PPMLB Program (6,12) PPMLB Status SPMLB Program (6,12) SPMLB Status Cycles
Sector Protection Command Definitions (x32 Mode)
Cycles (Notes 1-4) Addr Data Addr Data (BA)555 (BA)555 (BA)555 RD(1) RD(0) RD(0) RD(0) RD(0) RD(0) XX[0-1] PD[0-1] RD(0) Addr Data Addr Data Addr Data Addr Data
PWA[0-1] PWD[0-1] PWA[0-1] PWD[0-1] (SA)WP (SA)EP (SA)WP (SA)EP (SA)WP RD(0) (SA)WP RD(0)
Legend: Dynamic Protection SecSi Sector Address (A6:A0) (0011010). PD[1:0] Program Data. Password written portions. Persistent Protection Password Address. selects portion password. Password Data being verified. Password Protection Mode Lock Address (A5:A0) (001010) RD(0) Read Data protection indicator bit.
RD(1) Read Data Lock status. Sector Address where security command applies. Address bits A21:A11 uniquely select sector. Persistent Protection Mode Lock Address (A5:A0) (010010) Address (A6:A0) (0111010) (Note Erase Address (A6:A0) (1111010) Don't care PPMLB Password Protection Mode Locking SPMLB Persistent Protection Mode Locking Command sequence returns PPMLB set.
Table description operations.
values hexadecimal. Shaded cells table denote read cycles. other cycles write operations. During unlock command cycles, when lower address bits 2AAh shown table, address bits higher than (except where required) data bits higher than don't cares. Reset command returns device reading array. Cycle programs addressed locking bit. Cycles validate been fully programmed when cycle entire command sequence must issued verified again. Data latched rising edge WE#. Entire command sequence must executed each portion password.
Password written over four consecutive cycles addresses 0-3. timeout required between portions password. timeout required between cycles timeout required between cycles Cycle erases PPBs. Cycles validate bits have been fully erased when cycle entire command sequence must issued verified again. Before issuing erase command, PPBs should programmed prevent PPBs overerasure. locked, unlocked. other parts that Persistant Protection (axcluding PDL640G), address 000010.
Am29PDL128G
July 2002
Table
Command (Notes) Read Reset Manufacturer Device (10) Autoselect (Note SecSi Sector Factory Protect Sector Group Protect Verify Program Chip Erase Sector Erase Program/Erase Suspend (11) Program/Erase Resume (12) Query (13) Accelerated Program (15) Configuration Register Verify Configuration Register Write (16) Unlock Bypass Entry (17) Unlock Bypass Program (17) Unlock Bypass Erase (17) Unlock Bypass (13, Unlock Bypass Reset (17) Cycles
Memory Array Command Definitions (x16 Mode)
Cycles (Notes 1-4) Addr Data Addr Data (BA)AAA (BA)XX (BA)X00 (BA)X01 SA02 (see Note XX00/ XX01 (BA)X0E (BA)X0F Addr Data Addr Data Addr Data Addr Data
Legend: Address bank switching autoselect mode, bypass mode, erase. Determined A21:A19, Tables more detail. Program Address (A21:A-1). Addresses latch falling edge pulse, whichever happens later. Program Data (DQ15:DQ0) written location Data latches rising edge pulse, whichever happens first. Read Address (A21:A-1). Notes: Table description operations. values hexadecimal. Shaded cells table denote read cycles. other cycles write operations. During unlock command cycles, when lower address bits AAAh shown table, address bits higher than (except where required) data bits higher than don't cares. unlock command cycles required when bank reading array data. Reset command required return reading array erase-suspend-read mode previously Erase Suspend) when bank autoselect mode, goes high (while bank providing status information). Cycle autoselect command sequence read cycle. Autoselect Command Sequence section more information. data factory locked factory locked.
Read Data (DQ15:DQ0) from location Sector Address (A21:A12) verifying autoselect mode) erasing. Write Data. "Configuration Register" definition specific write data. Data latched rising edge WE#. Don't care
data unprotected sector group protected sector group.
Device must read across cycles System read program non-erasing sectors, enter autoselect mode, when Program/Erase Suspend mode. Program/Erase Suspend command valid only during sector erase operation, requires bank address. Program/Erase Resume command valid only during Erase Suspend mode, requires bank address. Command valid when device ready read array data when device autoselect mode. must during entire operation this command. Command ignored during Embedded Program, Embedded Erase, Suspend operation. Unlock Bypass Entry command required prior Unlock Bypass operation. Unlock Bypass Reset command required return reading array.
July 2002
Am29PDL128G
Table
Command (Notes) Reset SecSi Sector Entry SecSi Sector Exit SecSi Protection Program Password Program Password Verify Password Unlock Program Erase (13, Lock Lock Status (15) Write Erase Status PPMLB Program PPMLB Status SPMLB Program SPMLB Status Cycles
Sector Protection Command Definitions (x16 Mode)
Cycles (Notes 1-4) Addr Data Addr Data (BA)AAA (BA)AAA (BA)AAA RD(1) RD(0) RD(0) RD(0) RD(0) RD(0) XX[0-3] PD[0-3] RD(0) Addr Data Addr Data Addr Data Addr Data
PWA[0-3] PWD[0-3] PWA[0-3] PWD[0-3] (SA)WP (SA)EP (SA)WP (SA)EP (SA)WP RD(0) (SA)WP RD(0)
Legend: Dynamic Protection SecSi Sector Address (A6:A0) (0011010). PD[3:0] Program Data. Password written four 16-bit sections. Persistent Protection Password Address. A0:A-1 selects portion password. Password Data being verified. Password Protection Mode Lock Address (A5:A0) (001010) RD(0) Read Data protection indicator bit.
RD(1) Read Data Lock status. Sector Address where security command applies. Address bits A21:A11 uniquely select sector. Persistent Protection Mode Lock Address (A5:A0) (010010) Address (A6:A0) (0111010) (Note Erase Address (A6:A0) (1111010) Don't care PPMLB Password Protection Mode Locking SPMLB Persistent Protection Mode Locking Command sequence returns PPMLB set.
Table description operations.
values hexadecimal. Shaded cells table denote read cycles. other cycles write operations. During unlock command cycles, when lower address bits AAAh shown table, address bits higher than (except where required) data bits higher than don't cares. Reset command returns device reading array. Cycle programs addressed locking bit. Cycles validate been fully programmed when cycle program command must issued verified again. Data latched rising edge WE#. Entire command sequence must executed each portion password.
Password written over four consecutive cycles, addresses 0-3. timeout required between portions password. timeout required between cycles timeout required between cycles Cycle erases PPBs. Cycles validate bits have been fully erased when cycle erase command must issued verified again. Before issuing erase command, PPBs should programmed order prevent overerasure. locked, unlocked. other parts that Persistant Protection (excluding PDL640G), address 000010.
Am29PDL128G
July 2002
WRITE OPERATION STATUS
device provides several bits determine status program erase operation: DQ2, DQ3, DQ5, DQ6, DQ7. Table following subsections describe function these bits. each offer method determining whether program erase operation complete progress. device also provides hardware-based output signal, RY/BY#, determine whether Embedded Program Erase operation progress been completed. vice completed program erase operation Q31- Valid DQ31-DQ0 DQ15-DQ0 word mode) will appear successive read cycles. Table shows outputs Data# Polling DQ7. Figure shows Data# Polling algorithm. Figure Characteristics section shows Data# Polling timing diagram.
DQ7: Data# Polling
Data# Polling bit, DQ7, indicates host system whether Embedded Program Erase algorithm progress completed, whether bank Erase Suspend. Data# Polling valid after rising edge final pulse command sequence. During Embedded Program algorithm, device outputs complement datum programmed DQ7. This status also applies programming during Erase Suspend. When Embedded Program algorithm complete, device outputs datum programmed DQ7. system must provide program address read valid status information DQ7. program address falls within protected sector, Data# Polling active approximately then that bank returns read mode. During Embedded Erase algorithm, Data# Polling produces DQ7. When Embedded Erase algorithm complete, bank enters Erase Suspend mode, Data# Polling produces DQ7. system must provide address within sectors selected erasure read valid status information DQ7. After erase command sequence written, sectors selected erasing protected, Data# Polling active approximately then bank returns read mode. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. However, system reads address within protected sector, status valid. When system detects changed from complement true data, read valid data DQ31-DQ0 DQ15-DQ0 word mode) following read cycles. Just prior completion Embedded Program Erase operation, change asynchronously with DQ31-DQ16 (DQ15-DQ0 word mode) while Output Enable (OE#) asserted low. That device change from providing status information valid data DQ7. Depending when system samples output, read status valid data. Even deNo START
Read DQ7-DQ0 Addr
Data?
Read DQ7-DQ0 Addr
Data?
FAIL PASS
Notes: Valid address programming. During sector erase operation, valid address sector address within sector being erased. During chip erase, valid address non-protected sector address. should rechecked even because change simultaneously with DQ5.
Figure
Data# Polling Algorithm
July 2002
Am29PDL128G
RY/BY#: Ready/Busy#
RY/BY# dedicated, open-drain output which indicates whether Embedded Algorithm progress complete. RY/BY# status valid after rising edge final pulse command sequence. Since RY/BY# open-drain output, several RY/BY# pins tied together parallel with pull-up resistor VCC. output (Busy), device actively erasing programming. (This includes programming Erase Suspend mode.) output high (Ready), device read mode, standby mode, banks erase-suspend-read mode. Table shows outputs RY/BY#.
also toggles during erase-suspend-program mode, stops toggling once Embedded Program algorithm complete. Table shows outputs Toggle DQ6. Figure shows toggle algorithm. Figure Characteristics" section shows toggle timing diagrams. Figure shows differences between graphical form. also subsection DQ2: Toggle
START
DQ6: Toggle
Toggle indicates whether Embedded Program Erase algorithm progress complete, whether device entered Erase Suspend mode. Toggle read address, valid after rising edge final pulse command sequence (prior program erase operation), during sector erase time-out. During Embedded Program Erase algorithm operation, successive read cycles address cause toggle. system either control read cycles. When operation complete, stops toggling. After erase command sequence written, sectors selected erasing protected, toggles approximately then returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. system together determine whether sector actively erasing erase-suspended. When device actively erasing (that Embedded Erase algorithm progress), toggles. When device enters Erase Suspend mode, stops toggling. However, system must also determine which sectors erasing erase-suspended. Alternatively, system (see subsection DQ7: Data# Polling). program address falls within protected sector, toggles approximately after program command sequence written, then returns reading array data.
Read Byte (DQ0-DQ7) Address Read Byte (DQ0-DQ7) Address
Toggle Toggle?
Read Byte Twice (DQ0-DQ7) Address
Toggle Toggle?
Program/Erase Operation Complete, Write Reset Command Program/Erase Operation Complete
Note: system should recheck toggle even because toggle stop toggling changes "1." subsections more information.
Figure
Toggle Algorithm
Am29PDL128G
July 2002
DQ2: Toggle
"Toggle DQ2, when used with DQ6, indicates whether particular sector actively erasing (that Embedded Erase algorithm progress), whether that sector erase-suspended. Toggle valid after rising edge final pulse command sequence. toggles when system reads addresses within those sectors that have been selected erasure. (The system either control read cycles.) cannot distinguish whether sector actively erasing erase-suspended. DQ6, comparison, indicates whether device actively erasing, Erase Suspend, cannot distinguish which sectors selected erasure. Thus, both status bits required sector mode information. Refer Table compare outputs DQ6. Figure shows toggle algorithm flowchart form, section "DQ2: Toggle explains algorithm. also DQ6: Toggle subsection. Figure shows toggle timing diagram. Figure shows differences between graphical form.
gone high. system continue monitor toggle through successive read cycles, determining status described previous paragraph. Alternatively, choose perform other system tasks. this case, system must start beginning algorithm when returns determine status operation (top Figure
DQ5: Exceeded Timing Limits
indicates whether program erase time exceeded specified internal pulse count limit. Under these conditions produces "1," indicating that program erase cycle successfully completed. device output system tries program location that previously programmed "0." Only erase operation change back "1." Under this condition, device halts operation, when timing limit been exceeded, produces "1." Under both these conditions, system must write reset command return read mode erase-suspend-read mode bank previously erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing sector erase command sequence, system read determine whether erasure begun. (The sector erase timer does apply chip erase command.) additional sectors selected erasure, entire time-out also applies after each additional sector erase command. When time-out period complete, switches from "1." time between additional sector erase commands from system assumed less than system need monitor DQ3. also Sector Erase Command Sequence section. After sector erase command written, system should read status (Data# Polling) (Toggle ensure that device accepted command sequence, then read DQ3. "1," Embedded Erase algorithm begun; further commands (except Erase Suspend) ignored until erase operation complete. "0," device will accept additional sector erase commands. ensure command been accepted, system software should check status prior following each subsequent sector erase command. high second status check, last command might have been accepted. Table shows status relative other status bits.
Reading Toggle Bits DQ6/DQ2
Refer Figure following discussion. Whenever system initially begins reading toggle status, must read DQ31-DQ0 DQ15-DQ0 word mode) least twice determine whether toggle toggling. Typically, system would note store value toggle after first read. After second read, system would compare value toggle with first. toggle toggling, device completed program erase operation. system read array data DQ31-DQ0 DQ15-DQ0 word mode) following read cycle. However, after initial read cycles, system determines that toggle still toggling, system also should note whether value high (see section DQ5). system should then determine again whether toggle toggling, since toggle have stopped toggling just went high. toggle longer toggling, device successfully completed program erase operation. still toggling, device completed operation successfully, system must write reset command return reading array data. remaining scenario
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