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Am50DL9608G
There change this datasheet result offering device Spansion product. changes that have been made result normal datasheet improvement noted document revision summary, where supported. Future routine revisions will occur when appropriate, changes will noted revision summary.
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Fujitsu continue support existing part numbers beginning with "Am" "MBM". order these products, please only Ordering Part Numbers listed this document.
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Publication Number 27025 Revision
Amendment Issue Date 2003
PRELIMINARY
Am50DL9608G
Stacked Multi-Chip Package (MCP) Flash Memory Pseudo SRAM
Megabit 16-Bit) Megabit 16-Bit) CMOS Volt-only, Simultaneous Operation Flash Memories, Mbit (512 16-Bit) Pseudo Static DISTINCTIVE CHARACTERISTICS
Features
Power supply voltage volt High performance
Flash access time fast Pseudo SRAM access time fast Access time fast Program time: µs/word typical utilizing Accelerate function
Ultra power consumption (typical values)
active read current active read current standby automatic sleep mode
Package
73-Ball FBGA
Minimum million erase cycles guaranteed sector year data retention 125°C
Reliable operation life system
Operating Temperature
-40°C +85°C
SOFTWARE FEATURES
Supports Common Flash Memory Interface (CFI) Program/Erase Suspend/Erase Resume
Suspends program/erase operations allow programming/erasing same bank
Flash Memory Features (Am29DL640G/Am29DL320G)
Features apply Am29DL640G Am29DL320G independently.
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
Data continuously read from bank while executing erase/program functions another bank. Zero latency between read write operations
Data# Polling Toggle Bits
Provides software method detecting status program erase cycles
HARDWARE FEATURES
combination sectors erased Ready/Busy# output (RY/BY#)
Hardware method detecting program erase cycle completion
Flexible Bank architecture
Read occur three banks being written erased. Four banks grouped customer achieve desired bank divisions.
Hardware reset (RESET#)
Hardware method resetting internal state machine read mode
Manufactured 0.17 process technology SecSi(Secured Silicon) Sector
Extra byte sector Am29DL640G Extra byte sector Am29DL320G Factory locked identifiable: bytes available secure, random factory Electronic Serial Number; verifiable factory locked through autoselect function. ExpressFlash option allows entire sector available factory-secured data Customer lockable: Sector one-time programmable. Once sector locked, data cannot changed.
WP#/ACC input
Write protect (WP#) protects sectors 140, Am29DL640G, outermost boot sectors Am29DL320G Acceleration (ACC) function accelerates program timing
Sector protection
Hardware method locking sector, either in-system using programming equipment, prevent program erase operation within that sector Temporary Sector Unprotect allows changing data protected sectors in-system
Zero Power Operation
Sophisticated power management circuits reduce power consumed during inactive periods nearly zero.
Boot sectors
bottom boot sectors Am29DL640G bottom boot options Am29DL320G
Pseudo SRAM Features
Power dissipation
Operating: maximum Standby: maximum
Compatible with JEDEC standards
Pinout software compatible with single-power-supply flash standard
CE1s# CE2s Chip Select Power down features using CE1s# CE2s Data retention supply voltage: volt Byte data control: LB#s (DQ7-DQ0), UB#s (DQ15-DQ8)
PERFORMANCE CHARACTERISTICS
High performance
This document contains information product under development Advanced Micro Devices. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice. 5/19/03
Publication# 27025 Rev:A Amendment/+4 Issue Date: 2003
Refer AMD's Website (www.amd.com) latest information.
GENERAL DESCRIPTION
Am50DL9608G consists flash memory devices (one 64-Mbit Am29DL640G 32-Mbit Am29DL320G), Mbit pseudo SRAM device. Bottom boot configuration shown following table.
Bank Bank Bank Bank Bank Megabits Sector Sizes Eight Kword Twenty-four Kword Twenty-four Kword Eight Kword, Seven Kword
Am29DL640G Am29DL320G Features
Am29DL640G megabit, volt-only flash memory device, organized 4,194,304 words. Am29DL320G megabit, volt-only flash memory device, organized 2,097,152 words. Word mode data appears DQ15-DQ0. device designed programmed in-system with standard volt supply, also programmed standard EPROM programmers. device available with access time offered 73-ball FBGA package. Standard control pins-chip enable (CE#fx), write enable (WE#), output enable (OE#)-control normal read write operations, avoid contention issues. device requires only single volt power supply both read write functions. Internally generated regulated voltages provided program erase operations.
Available Am29DL640G Am29DL320G, SecSi(Secured Silicon) Sector extra byte sector capable being permanently locked customers. Secure SectorSecSi Indicator (DQ7) permanently part factory locked, customer lockable. This way, customer lockable parts never used replace factory locked part. Factory locked parts provide several options. Secure SectorSecSi Sector store secure, random byte (Electronic Serial Number), customer code (programmed through AMD's ExpressFlash service), both. Customer Lockable parts utilize Secure SectorSecSi Sector one-time programmable area. (Data Management Software) manages data programming, enables EEPROM emulation, eases historical sector erase flash limitations. more information obtain software, contact authorized representative. device offers complete compatibility with JEDEC single-power-supply Flash command standard. Commands written command register using standard microprocessor write timings. Reading data device similar reading from other Flash EPROM devices. host system detect whether program erase operation complete using device status bits: RY/BY# pin, (Data# Polling) DQ6/DQ2 (toggle bits). After program erase cycle been completed, device automatically returns read mode. sector erase architecture allows memory sectors erased reprogrammed without affecting data contents other sectors. device fully erased when shipped from factory. Hardware data protection measures include detector that automatically inhibits write operations during power transitions. hardware sector protection feature disables both program erase operations combination sectors memory. This achieved in-system programming equipment. device offers power-saving features. When addresses have been stable specified amount time, device enters automatic sleep mode. system also place device into standby mode. Power consumption greatly reduced both modes.
Simultaneous Read/Write Operations with Zero Latency
Simultaneous Read/Write architecture provides simultaneous operation dividing memory space into four banks. Sector addresses fixed, system software used form user-defined bank groups. During Erase/Program operation, three non-busy banks read from. Note that only banks operate simultaneously. device improve overall system performance allowing host stem program erase bank, then immediately simultaneously read from other bank, with zero latency. This releases system from waiting completion program erase operations. Am29DL640G organized both bottom boot sector configuration.
Bank Bank Bank Bank Bank Megabits Sector Sizes Eight Kword, Fifteen Kword Forty-eight Kword Forty-eight Kword Eight Kword, Fifteen Kword
Am29DL320G organized either bottom boot sector configuration. boot configuration shown following table.
Bank Bank Bank Bank Bank Megabits Sector Sizes Eight Kword, Seven Kword Twenty-four Kword Twenty-four Kword Eight Kword
Am50DL9608G
2003
TABLE CONTENTS
Product Selector Guide Block Diagram Flash Memory Block Diagram Connection Diagram Special Package Handling Instructions Ordering Information Device Operations
Table Device Operations-Flash Word Mode Figure Erase Operation.
Erase Suspend/Erase Resume Commands
Table Am29DL640G Am29DL320G Command Definitions
Flash Write Operation Status DQ7: Data# Polling
Figure Data# Polling Algorithm
DQ6: Toggle
Figure Toggle Algorithm.
Flash Device Operations Requirements Reading Array Data Writing Commands/Command Sequences Simultaneous Read/Write Operations with Zero Latency Automatic Sleep Mode RESET#: Hardware Reset Output Disable Mode
Table Am29DL640G Sector Architecture Table Am29DL640G Bank Address Table Am29DL640G SecSi Sector Addresses Table Am29DL320G Boot Sector Addresses Table Am29DL320G Boot SecSiSector Addresses Table Am29DL320G Bottom Boot Sector Addresses Table Am29DL320G Bottom Boot SecSiSector Addresses Table Am29DL640G Boot Sector/Sector Block Addresses Protection/Unprotection Table Am29DL320G Boot Sector/Sector Block Addresses Protection/Unprotection Table Am29DL320G Bottom Boot Sector/Sector Block Addresses Protection/Unprotection
DQ2: Toggle Reading Toggle Bits DQ6/DQ2 DQ5: Exceeded Timing Limits DQ3: Sector Erase Timer
Table Write Operation Status
Absolute Maximum Ratings
Figure Maximum Negative Overshoot Waveform Figure Maximum Positive Overshoot Waveform.
Flash Characteristics CMOS Compatible
Figure ICC1 Current Time (Showing Active Automatic Sleep Currents) Figure Typical ICC1 Frequency
Pseudo SRAM Operating Characteristics
Figure Standby Current CMOS
Test Conditions
Figure Test Setup. Figure Input Waveforms Measurement Levels
Write Protect (WP#)
Table WP#/ACC Modes
Flash Characteristics Pseudo SRAM CE#s Timing
Figure Timing Diagram Alternating Between Pseudo SRAM Flash.
Temporary Sector Unprotect
Figure Temporary Sector Unprotect Operation. Figure In-System Sector Protect/Unprotect Algorithms
Read-Only Operations
Figure Read Operation Timings
SecSi(Secured Silicon) Sector SectorFlash Memory Region
Table SecSi Sector Programming Figure SecSi Sector Protect Verify.
Hardware Reset (RESET#)
Figure Reset Timings
Erase Program Operations
Figure Program Operation Timings. Figure Accelerated Program Timing Diagram. Figure Chip/Sector Erase Operation Timings Figure Back-to-back Read/Write Cycle Timings Figure Data# Polling Timings (During Embedded Algorithms). Figure Toggle Timings (During Embedded Algorithms). Figure DQ6.
Hardware Data Protection Common Flash Memory Interface (CFI)
Table Am29DL640G Query Identification String Table Am29DL640G System Interface String Table Am29DL640G Device Geometry Definition. Table Am29DL640G Primary Vendor-Specific Extended Query Table Am29DL320G Query Identification String Table Am29DL320G System Interface String Table Am29DL320G Device Geometry Definition. Table Am29DL320G Primary Vendor-Specific Extended Query
Temporary Sector Unprotect
Figure Temporary Sector Unprotect Timing Diagram Figure Sector/Sector Block Protect Unprotect Timing Diagram
Alternate CE#f Controlled Erase Program Operations
Figure Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings.
Flash Command Definitions Reading Array Data Reset Command Autoselect Command Sequence Enter SecSiSector/Exit SecSi Sector Command Sequence Program Command Sequence
Figure Program Operation
Pseudo SRAM Characteristics Power Time Read Cycle
Figure Pseudo SRAM Read Cycle-Address Controlled. Figure Pseudo SRAM Read Cycle.
Write Cycle
Figure Pseudo SRAM Write Cycle-WE# Control Figure Pseudo SRAM Write Cycle-CE1#s Control Figure Pseudo SRAM Write Cycle-
Chip Erase Command Sequence Sector Erase Command Sequence
2003
Am50DL9608G
UB#s LB#s Control.
Flash Erase Programming Performance Latchup Characteristics Package Capacitance Flash Data Retention
Physical Dimensions FTA073-73-Ball Fine-Pitch Grid Array 11.6 Revision Summary
Am50DL9608G
2003
PRODUCT SELECTOR GUIDE
Part Number Speed Options Standard Voltage Range: 2.7-3.3 Am50DL9608G Flash Memory (Am29DL640G, Am29DL320G) Pseudo SRAM
Access Time (ns) Access (ns) Access (ns)
BLOCK DIAGRAM
VCCf
RY/BY#
CE#f1
MBit Flash Memory
DQ15
VCCf
RY/BY#
RESET# WP#/ACC CE#f2
MBit Flash Memory
VCCs
LB#s UB#s CE1#s CE2s MBit pseudo Static
DQ15
2003
Am50DL9608G
FLASH MEMORY BLOCK DIAGRAM
A21*-A0
Bank Address
Bank
Y-gate
X-Decoder
A21*-A0
RY/BY#
Bank Address
Bank X-Decoder
DQ15-DQ0
A21*-A0 RESET# WP#/ACC STATE CONTROL COMMAND REGISTER Status
DQ15-DQ0
DQ15-DQ0 Control
DQ15-DQ0
A21*-A0
X-Decoder
Bank Address
Bank
Y-gate
X-Decoder A21*-A0
Bank Address
Bank
Addresses Am29DL640G A21-A0. Address Am29DL320G A20-A0.
Am50DL9608G
DQ15-DQ0
2003
CONNECTION DIAGRAM
73-Ball FBGA View
Flash only
Pseudo SRAM only Shared
RY/BY#
WP#/ACC
RESET# CE2s
CE#f2
CE#f1
DQ13
DQ15
CE1#s
DQ10
VCCf
VCCs
DQ12
DQ11
DQ14
Special Package Handling Instructions
Special handling required Flash Memory products molded packages (BGA). package and/or data
integrity compromised package body exposed temperatures above 150°C prolonged periods time.
2003
Am50DL9608G
DESCRIPTION
A18-A0 Address Inputs (Common) A21-A19, Address Inputs (Flash) DQ15-DQ0 CE#f1 CE#f2 CE#1s CE2s RY/BY# UB#s LB#s RESET# WP#/ACC VCCf Data Inputs/Outputs (Common) Flash Chip Enable (Am29DL640G) Flash Chip Enable (Am29DL320G) Pseudo SRAM Chip Enable Pseudo SRAM Chip Enable Output Enable (Common) Write Enable (Common) Ready/Busy Output Upper Byte Control (Pseudo SRAM) Lower Byte Control (Pseudo SRAM) Hardware Reset Pin, Active Hardware Write Protect/ Acceleration (Flash) Flash volt-only single power supply (see Product Selector Guide speed options voltage supply tolerances) Pseudo SRAM Power Supply Device Ground (Common) Connected Internally
LOGIC SYMBOL
A18-A0
A21-A19 CE#f1 CE#f2 CE1#s CE2s WP#/ACC RESET# UB#s LB#s RY/BY# DQ15-DQ0
VCCs
Am50DL9608G
2003
ORDERING INFORMATION
order number (Valid Combination) formed following:
Am50DL960
TAPE REEL inches inches TEMPERATURE RANGE Industrial (-40°C +85°C) SPEED OPTION Flash pSRAM Flash pSRAM (See page BOOT SECTOR ARCHITECTURE Boot Am29DL320G Flash Bottom Boot Am29DL320G Flash PROCESS TECHNOLOGY 0.17 PSEUDO SRAM DEVICE DENSITY Mbits DEVICE NUMBER/DESCRIPTION Am50DL9608G Stacked Multi-Chip Package (MCP) Flash Memory Pseudo SRAM Am29DL640G Megabit (8/4 16-Bit) Am29DL320G Megabit (4/2 16-Bit) CMOS Volt-only, Simultaneous Operation Flash Memory Mbit (152 16-Bit) Pseudo Static
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Valid Combinations Order Number Am50DL9608GT70I Am50DL9608GB70I Am50DL9608GT75I Am50DL9608GB75I Package Marking M500000010 M500000011 M500000012 M500000013
DEVICE OPERATIONS
This section describes requirements device operations, which initiated through internal command register. command register itself does occupy addressable memory location. register latch used store commands, along with address data information
needed execute command. contents register serve inputs internal state machine. state machine outputs dictate function device. Tables lists device operations, inputs control levels they require, resulting output. following subsections describe each these operations further detail.
2003
Am50DL9608G
Table
Operation (Notes Read from Flash
Device Operations-Flash Word Mode
Addr. LB#s UB#s RESET# WP#/ (Note DQ7- DOUT High-Z DQ15- DOUT High-Z
CE#f1 CE1#s CE2s CE#f2 (Note (Note (Note
SADD, SADD,
Write Flash
(Note
Standby
Output Disable Flash Hardware Reset Sector Protect (Note
High-Z
High-Z
High-Z
High-Z
Sector Unprotect (Note Temporary Sector Unprotect Read from Pseudo SRAM
(Note
(Note
DOUT
High-Z DOUT DOUT High-Z High-Z
High-Z DOUT
Write Pseudo SRAM
High-Z
Legend: Logic VIL, Logic High VIH, 11.5-12.5 Don't Care, SADD Flash Sector Address, Address Data DOUT Data Notes: Other operations except those indicated this column inhibited. apply CE#fx VIL, CE1#s CE2s same time. Don't care open LB#s UB#s. WP#/ACC VIL, boot sectors will protected. WP#/ACC boot sectors protection will removed. WP#/ACC VACC (9V), program time will reduced 40%. sector protect sector unprotect functions also implemented programming equipment. "Sector/Sector Block Protection Unprotection" section. WP#/ACC VIL, outermost boot sectors remain protected. WP#/ACC VIH, outermost boot sector protection depends whether they were last protected unprotected using method described "Sector/Sector Block Protection Unprotection". WP#/ACC VHH, sectors will unprotected. Only flash device should accessed time. Am29DL640G flash access, CE#f1 VIL, CE#f2 VIH. Am29DL320G flash access, CE#f1 VIH, CE#f2 ViL. CE#1s= VIL, CE2s= VIH, CE#f1=VIH CE#f2=VIH when accessing pseudo SRAM.
Am50DL9608G
2003
FLASH DEVICE OPERATIONS Requirements Reading Array Data
read array data from outputs, system must drive CE#f pins VIL. CE#f power control selects device. output control gates array data output pins. should remain VIH. internal state machine reading array data upon device power-up, after hardware reset. This ensures that spurious alteration memory content occurs during power transition. command necessary this mode obtain array data. Standard microprocessor read cycles that assert valid addresses device address inputs produce valid data device data outputs. Each bank remains enabled read access until command register contents altered. Refer Read-Only Operations table timing specifications Figure timing diagram. ICC1 Characteristics table represents active current specification reading array data. provided WP#/ACC pin. This function primarily intended allow faster manufacturing throughput factory. system asserts this pin, device automatically enters aforementioned Unlock Bypass mode, temporarily unprotects protected sectors, uses higher voltage reduce time required program operations. system would two-cycle program command sequence required Unlock Bypass mode. Removing from WP#/ACC returns device normal operation. Note that must asserted WP#/ACC operations other than accelerated programming, device damage result. addition, WP#/ACC must left floating unconnected; inconsistent behavior device result. "Write Protect (WP#)" page related information. Autoselect Functions system writes autoselect command sequence, device enters autoselect mode. system then read autoselect codes from internal register (which separate from memory array) DQ15-DQ0. Standard read cycle timings apply this mode. Refer Sector/Sector Block Protection Unprotection Autoselect Command Sequence sections more information.
Writing Commands/Command Sequences
write command command sequence (which includes programming data device erasing sectors memory), system must drive CE#f VIL, VIH. device features Unlock Bypass mode facilitate faster programming. Once bank enters Unlock Bypass mode, only write cycles required program word byte, instead four. "Byte/Word Program Command Sequence" section details programming data device using both standard Unlock Bypass command sequences. erase operation erase sector, multiple sectors, entire device. Table indicates address space that each sector occupies. Similarly, "sector address" address bits required uniquely select sector. "Flash Command Definitions" section details erasing sector entire chip, suspending/resuming erase operation. device address space divided into four banks. "bank address" address bits required uniquely select bank. ICC2 Characteristics table represents active current specification write mode. Flash Characteristics section contains timing specification tables timing diagrams write operations. Accelerated Program Operation device offers accelerated program operations through function. This functions
Simultaneous Read/Write Operations with Zero Latency
This device capable reading data from bank memory while programming erasing other bank memory. erase operation also suspended read from program another location within same bank (except sector being erased). Figure shows read write cycles initiated simultaneous operation with zero latency. ICC6f ICC7f table represent current specifications read-while-program read-while-erase, respectively.
Standby Mode
When system reading writing device, place device standby mode. this mode, current consumption greatly reduced, outputs placed high impedance state, independent input. device enters CMOS standby mode when CE#f RESET# pins both held (Note that this more restricted voltage range than CE#f RESET# held within device will standby mode, standby current will greater.
2003
Am50DL9608G
vice requires standard access time (tCE) read access when device either these standby modes, before ready read data. device deselected during erasure programming, device draws active current until operation completed. ICC3f table represents standby current specification. ready accept another command sequence, ensure data integrity. Current reduced duration RESET# pulse. When RESET# held VSS±0.3 device draws CMOS standby current (ICC4 RESET# held within VSS±0.3 standby current will greater. RESET# tied system reset circuitry. system reset would thus also reset Flash memory, enabling system read boot-up firmware from Flash memory. RESET# asserted during program erase operation, RY/BY# remains (busy) until internal reset operation complete, which requires time READY (during Embedded Algorithms). system thus monitor RY/BY# determine whether reset operation complete. RESET# asserted when program erase operation executing (RY/BY# "1"), reset operation completed within time tREADY (not during Embedded Algorithms). system read data after RESET# returns VIH. Refer Flash Characteristics tables RESET# parameters Figure timing diagram.
Automatic Sleep Mode
automatic sleep mode minimizes Flash device energy consumption. device automatically enables this mode when addresses remain stable tACC automatic sleep mode independent CE#f, WE#, control signals. Standard address access timings provide data when addresses changed. While sleep mode, output data latched always available system. ICC5f table represents automatic sleep mode current specification.
RESET#: Hardware Reset
RESET# provides hardware method resetting device reading array data. When RESET# driven least period tRP, device immediately terminates operation progress, tristates output pins, ignores read/write commands duration RESET# pulse. device also resets internal state machine reading array data. operation that interrupted should reinitiated once device
Output Disable Mode
When input VIH, output from device disabled. output pins placed high impedance state.
Am50DL9608G
2003
Table
Bank Sector SA10 Bank SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22
Am29DL640G Sector Architecture
Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x16) Address Range 00000h-00FFFh 01000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-04FFFh 05000h-05FFFh 06000h-06FFFh 07000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh
Sector Address A21-A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001xxx 0000010xxx 0000011xxx 0000100xxx 0000101xxx 0000110xxx 0000111xxx 0001000xxx 0001001xxx 0001010xxx 0001011xxx 0001100xxx 0001101xxx 0001101xxx 0001111xxx
2003
Am50DL9608G
Table
Bank Sector SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 Bank SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
Am29DL640G Sector Architecture (Continued)
Sector Address A21-A12 0010000xxx 0010001xxx 0010010xxx 0010011xxx 0010100xxx 0010101xxx 0010110xxx 0010111xxx 0011000xxx 0011001xxx 0011010xxx 0011011xxx 0011000xxx 0011101xxx 0011110xxx 0011111xxx 0100000xxx 0100001xxx 0100010xxx 0101011xxx 0100100xxx 0100101xxx 0100110xxx 0100111xxx 0101000xxx 0101001xxx 0101010xxx 0101011xxx 0101100xxx 0101101xxx 0101110xxx 0101111xxx 0110000xxx 0110001xxx 0110010xxx 0110011xxx 0100100xxx 0110101xxx 0110110xxx 0110111xxx 0111000xxx 0111001xxx 0111010xxx 0111011xxx 0111100xxx 0111101xxx 0111110xxx 0111111xxx Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x16) Address Range 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-FFFFFh F9000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh
Am50DL9608G
2003
Table
Bank Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 Bank SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118
Am29DL640G Sector Architecture (Continued)
Sector Address A21-A12 1000000xxx 1000001xxx 1000010xxx 1000011xxx 1000100xxx 1000101xxx 1000110xxx 1000111xxx 1001000xxx 1001001xxx 1001010xxx 1001011xxx 1001100xxx 1001101xxx 1001110xxx 1001111xxx 1010000xxx 1010001xxx 1010010xxx 1010011xxx 1010100xxx 1010101xxx 1010110xxx 1010111xxx 1011000xxx 1011001xxx 1011010xxx 1011011xxx 1011100xxx 1011101xxx 1011110xxx 1011111xxx 1100000xxx 1100001xxx 1100010xxx 1100011xxx 1100100xxx 1100101xxx 1100110xxx 1100111xxx 1101000xxx 1101001xxx 1101010xxx 1101011xxx 1101100xxx 1101101xxx 1101110xxx 1101111xxx Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x16) Address Range 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-28FFFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2FFFFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh
2003
Am50DL9608G
Table
Bank Sector SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 Bank SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 Note: address range A21:A0
Am29DL640G Sector Architecture (Continued)
Sector Address A21-A12 1110000xxx 1110001xxx 1110010xxx 1110011xxx 1110100xxx 1110101xxx 1110110xxx 1110111xxx 1111000xxx 1111001xxx 1111010xxx 1111011xxx 1111100xxx 1111101xxx 1111110xxx 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x16) Address Range 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F8FFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh
Table
Bank
Am29DL640G Bank Address
A21-A19 001, 010, 100, 101,
Table
Device Am29DL640G
Am29DL640G SecSi Sector Addresses
Sector Size bytes (x16) Address Range 00000h-0007Fh
Am50DL9608G
2003
Table
Sector Bank SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Bank SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
Bank
Am29DL320G Boot Sector Addresses
Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x16) Address Range 000000h-07FFFh 008000h-0FFFFh 010000h-17FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh
Sector Address A20-A12 000000xxx 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx
SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47
2003
Am50DL9608G
Table
Sector SA48 Bank (continued) SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 Bank SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Note: address range A20:A0.
Am29DL320G Boot Sector Addresses (Continued)
Sector Address A20-A12 110000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x16) Address Range 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F8FFFh 1F9000h-1F9FFFh 1FA000h-1FAFFFh 1FB000h-1FBFFFh 1FC000h-1FCFFFh 1FD000h-1FDFFFh 1FE000h-1FEFFFh 1FF000h-1FFFFFh
Table
Device Am29DL320GT
Am29DL320G Boot SecSiSector Addresses
Sector Address A20-A12 111111xxx Sector Size (Bytes/Words) 256/128 (x16) Address Range 1FF000h-1FF07Fh
Am50DL9608G
2003
Table
Sector Bank SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 Bank SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41
Bank
Am29DL320G Bottom Boot Sector Addresses
Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x16) Address Range 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh
Sector Address A20-A12 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx
SA42 SA43 SA44 SA45 SA46 SA47
2003
Am50DL9608G
Table
Sector SA48 SA49 SA50 SA51 Bank (continued) SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 Bank SA66 SA67 SA68 SA69 SA70
Am29DL320G Bottom Boot Sector Addresses (Continued)
Sector Address A20-A12 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 111000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111xxx Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x16) Address Range 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh
Note: address range A20:A0
Table
Device Am29DL320GB
Am29DL320G Bottom Boot SecSiSector Addresses
Sector Address A20-A12 000000xxx Sector Size (Bytes/Words) 256/128 (x16) Address Range 00000h-00007Fh
Am50DL9608G
2003
Sector/Sector Block Protection Unprotection
(Note: following discussion, term "sector" applies both sectors sector blocks. sector block consists more adjacent sectors that protected unprotected same time (see Table hardware sector protection feature disables both program erase operations sector. hardware sector unprotection feature re-enables both program erase operations previously protected sectors. Sector protection/unprotection implemented methods. Table Am29DL640G Boot Sector/Sector Block Addresses Protection/Unprotection
Sector SA8-SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 A21-A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX, 0000010XXX, 0000011XXX, 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX Sector/ Sector Block Size Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes (3x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes
Sector SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 SA87-SA90 SA91-SA94 SA95-SA98 SA99-SA102 SA103-SA106 SA107-SA110 SA111-SA114 SA115-SA118 SA119-SA122 SA123-SA126 SA127-SA130 SA131-SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
A21-A12 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX, 1111101XXX, 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111101 1111111111
Sector/ Sector Block Size (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (3x64) Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes
2003
Am50DL9608G
Table Am29DL320G Boot Sector/Sector Block Addresses Protection/Unprotection
Sector SA1-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 A20-A12 000000XXX 000001XXX, 000010XXX 000011XXX 0001XXXXX 0010XXXXX 0011XXXXX 0100XXXXX 0101XXXXX 0110XXXXX 0111XXXXX 1000XXXXX 1001XXXXX 1010XXXXX 1011XXXXX 1100XXXXX 1101XXXXX 1110XXXXX 111100XXX, 111101XXX, 111110XXX 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111 Sector/ Sector Block Size Kbytes (3x64) Kbytes SA69-SA67 (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (3x64) Kbytes SA10-SA8 Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes SA66-SA63 SA62-SA59 SA58-SA55 SA54-SA51 SA50-SA47 SA46-SA43 SA42-SA39 SA38-SA35 SA34-SA31 SA30-SA27 SA26-SA23 SA22-SA19 SA18-SA15 SA14-SA11
Table Am29DL320G Bottom Boot Sector/Sector Block Addresses Protection/Unprotection
Sector SA70 A20-A12 111111XXX 111110XXX, 111101XXX, 111100XXX 1110XXXXX 1101XXXXX 1100XXXXX 1011XXXXX 1010XXXXX 1001XXXXX 1000XXXXX 0111XXXXX 0110XXXXX 0101XXXXX 0100XXXXX 0011XXXXX 0010XXXXX 0001XXXXX 000011XXX, 000010XXX, 000001XXX 000000111 000000110 000000101 000000100 000000011 000000010 000000001 000000000 Sector/Sector Block Size Kbytes (3x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (3x64) Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes
Am50DL9608G
2003
Sector protection/unprotection requires RESET# only, implemented either in-system programming equipment. Figure shows algorithms Figure shows timing diagram. sector unprotect, unprotected sectors must first protected prior first sector unprotect write cycle. Note that sector unprotect algorithm unprotects sectors parallel. previously protected sectors must individually re-protected. change data protected sectors efficiently, temporary sector unprotect function available. "Temporary Sector Unprotect". device shipped with sectors unprotected. offers option programming protecting sectors factory prior shipping device through AMD's ExpressFlashService. Contact representative details. possible determine whether sector protected unprotected. Sector/Sector Block Protection Unprotection section details. Note that WP#/ACC must left floating unconnected; inconsistent behavior device result. Table
Input Voltage
WP#/ACC Modes
Am29DL640G Disables programming erasing SA0, SA1, SA140, SA141 Enables programming erasing SA0, SA1, SA140, SA141
Am29DL320G Disables programming erasing SA69 SA70 Enables programming erasing SA60 SA70
Enables accelerated programming (ACC). "Accelerated Program Operation" page
Temporary Sector Unprotect
(Note: following discussion, term "sector" applies both sectors sector blocks. sector block consists more adjacent sectors that protected unprotected same time (see Table This feature allows temporary unprotection previously protected sectors change data in-system. Sector Unprotect mode activated setting RESET# VID. During this mode, formerly protected sectors programmed erased selecting sector addresses. Once removed from RESET# pin, previously protected sectors protected again. Figure shows algorithm, Figure shows timing diagrams, this feature. WP#/ACC while Am29DL640G enabled, sectors 140, that device will remain protected during Temporary sector Unprotect mode. Similarly, WP#/ACC while Am29DL320G enabled, outermost boot sectors (SA0 bottom boot devices SA69 boot devices) that device will remain protected during Temporary sector Unprotect mode.
Write Protect (WP#)
Write Protect function provides hardware method protecting without using VID. This function provided WP#/ACC pin. system asserts WP#/ACC while Am29DL640G enabled (CE#f1), device disables program erase functions sectors 140, 141, independently whether those sectors were protected unprotected using method described "Sector/Sector Block Protection Unprotection". Similarly, outermost boot sectors (SA0 bottom boot devices SA69 boot devices) Am29DL320G protected when asserted WP#/ACC while Am29DL320G enabled (CE#f2). system asserts WP#/ACC pin, device reverts whether aforementioned sectors were last protected unprotected. That sector protection unprotection these sectors depends whether they were last protected unprotected using method described "Sector/Sector Block Protection Unprotection".
2003
Am50DL9608G
START
RESET# (Note Perform Erase Program Operations
RESET#
Temporary Sector Unprotect Completed (Note
Notes: protected sectors unprotected WP#/ACC VIL, following sectors will remain protected: sectors 140, (Am29DL640G), sectors (Am29DL320GB), sectors (Am29DL320GT). previously protected sectors protected once again.
Figure
Temporary Sector Unprotect Operation
Am50DL9608G
2003
START PLSCNT RESET# Wait Protect sectors: indicated portion sector protect algorithm must performed unprotected sectors prior issuing first sector unprotect address
START PLSCNT RESET# Wait
Temporary Sector Unprotect Mode
First Write Cycle 60h? sector address Sector Protect: Write sector address with Wait Verify Sector Protect: Write sector address with Read from sector address with
First Write Cycle 60h? sectors protected? first sector address Sector Unprotect: Write sector address with
Temporary Sector Unprotect Mode
Increment PLSCNT
Reset PLSCNT
Wait Verify Sector Unprotect: Write sector address with
PLSCNT Data 01h?
Increment PLSCNT
Read from sector address with next sector address
Device failed
Protect another sector? Remove from RESET#
PLSCNT 1000?
Data 00h?
Device failed Write reset command
Last sector verified?
Sector Protect Algorithm
Sector Protect complete
Sector Unprotect Algorithm
Remove from RESET#
Write reset command Sector Unprotect complete
Figure
In-System Sector Protect/Unprotect Algorithms
2003
Am50DL9608G
SecSi(Secured Silicon) Sector SectorFlash Memory Region
SecSi (Secured Silicon) Sector feature provides Flash memory region that enables permanent part identification through Electronic Serial Number (ESN). SecSi Sector bytes length, uses SecSi Sector Indicator (DQ7) indicate whether SecSi Sector locked when shipped from factory. This permanently factory cannot changed, which prevents cloning factory locked part. This ensures security once product shipped field. offers device with SecSi Sector either factor locked custom locka factory-locked version always protected when shipped from factory, SecSi (Secured Silicon) Sector Indicator permanently "1." customer-lockable version shipped with SecSi Sector unprotected, allowing customers utilize that sector manner they choose. customer-lockable version SecSi (Secured Silicon) Sector Indicator permanently "0." Thus, SecSi Sector Indicator prevents customer-lockable devices from being used replace devices that factory locked. system accesses SecSi Sector Secure Sector through command sequence (see "Enter SecSiSector/Exit SecSi Sector Command Sequence"). After system written Enter SecSi Sector command sequence, read SecSi Sector using addresses normally occupied boot sectors. This mode operation continues until system issues Exit SecSi Sector command sequence, until power removed from device. Note that function unlock bypass modes available when SecSi Sector enabled. power-up, following hardware reset, device reverts sending commands first bytes Sector Factory Locked: SecSi Sector Programmed Protected Factory factory locked device, SecSi Sector protected when device shipped from factory. SecSi Sector cannot modified way. device preprogrammed with both random number secure ESNs. Table address location details.
Table SecSi Sector Programming
Device Data Random number 8-byte secure 16-byte secure 16-byte secure Word Mode 000000h- 000007h 000008h- 00000Fh 000000h- 000007h 1FF000h- 1FF007Fh Byte Mode 000000h- 00000Fh 000010h- 000020h 000000h- 00000Fh 3FE000h- 3FE0FFh
Am29DL640G
Am29DL320GB (Bottom boot) Am29DL320GT (Top boot)
device available preprogrammed with following: Random number secure ESNs only Customer code through ExpressFlash service Random number, secure ESNs, customer code through ExpressFlash service. Customers have their code programmed through ExpressFlash service. programs customer's code, with without random ESN. devices then shipped from AMD's factory with SecSi Sector permanently locked. Contact representative details using AMD's ExpressFlash service. Customer Lockable: SecSi Sector Programmed Protected Factory security feature required, SecSi Sector treated additional Flash memory space. SecSi Sector read number times, programmed locked only once. Note that accelerated programming (ACC) unlock bypass functions available when programming SecSi Sector. SecSi Sector area protected using following procedures: Write three-cycle Enter SecSi Sector Region command sequence, then follow in-system sector protect algorithm shown Figure except that RESET# either VID. This allows in-system protection SecSi Sector Region without raising device high voltage. Note that this method only applicable SecSi Sector. verify protect/unprotect status SecSi Sector, follow algorithm shown Figure Once SecSi Sector locked verified, system must write Exit SecSi Sector Region command sequence return reading writing remainder array. SecSi Sector lock must used with caution since, once locked, there procedure available unlocking SecSi Sector area none bits SecSi Sector memory space modified way.
Am50DL9608G
2003
Logical Inhibit Write cycles inhibited holding VIL, CE#f VIH. initiate write cycle, CE#f must logical zero while logical one. Power-Up Write Inhibit CE#f during power device does accept commands rising edge WE#. internal state machine automatically reset read mode power-up.
START RESET# Wait Write address data 00h, SecSi Sector unprotected. data 01h, SecSi Sector protected.
Remove from RESET#
Write SecSi Sector address with Read from SecSi Sector address with
COMMON FLASH MEMORY INTERFACE (CFI)
Common Flash Interface (CFI) specification outlines device host system software interrogation handshake, which allows specific vendor-specified software algorithms used entire families devices. Software support then device-independent, JEDEC ID-independent, forward- backward-compatible specified flash device families. Flash vendors standardize their existing interfaces long-term compatibility. This device enters Query mode when system writes Query command, 98h, address word mode address byte mode), time device ready read array data. system read information addresses given Tables 14-17. terminate reading data, system must write reset command.The Query mode accessible when device executing Embedded Program embedded Erase algorithm. system also write query command when device autoselect mode. device enters query mode, system read data addresses given Tables 14-17. system must write reset command return device reading array data. further information, please refer Specification Publication 100, available World Wide http://www.amd.com/flash/cfi. Alternatively, contact representative copies these documents.
Write reset command SecSi Sector Protect Verify complete
Figure
SecSi Sector Protect Verify
Hardware Data Protection
command sequence requirement unlock cycles programming erasing provides data protection against inadvertent writes (refer Table command definitions). addition, following hardware data protection measures prevent accidental erasure programming, which might otherwise caused spurious system level signals during power-up power-down transitions, from system noise. Write Inhibit When less than LKO, device does accept write cycles. This protects data during power-up power-down. command register internal program/erase circuits disabled, device resets read mode. Subsequent writes ignored until greater than VLKO. system must provide proper signals control pins prevent unintentional writes when greater than VLKO. Write Pulse "Glitch" Protection Noise pulses less than (typical) OE#, CE#f initiate write cycle.
2003
Am50DL9608G
Table
Addresses (Word Mode) Addresses (Byte Mode)
Am29DL640G Query Identification String
Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string "QRY"
Primary Command Address Primary Extended Table Alternate Command (00h none exists) Address Alternate Extended Table (00h none exists)
Table
Addresses (Word Mode) Addresses (Byte Mode)
Am29DL640G System Interface String
Description Min. (write/erase) D7-D4: volt, D3-D0: millivolt Max. (write/erase) D7-D4: volt, D3-D0: millivolt Min. voltage (00h present) Max. voltage (00h present) Typical timeout single byte/word write Typical timeout Min. size buffer write (00h supported) Typical timeout individual block erase Typical timeout full chip erase (00h supported) Max. timeout byte/word write times typical Max. timeout buffer write times typical Max. timeout individual block erase times typical Max. timeout full chip erase times typical (00h supported)
Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h
Am50DL9608G
2003
Table
Addresses (Word Mode) Addresses (Byte Mode)
Am29DL640G Device Geometry Definition
Data Description Device Size byte Flash Device Interface description (refer publication 100) Max. number byte multi-byte write (00h supported) Number Erase Block Regions within device Erase Block Region Information (refer specification publication 100)
0017h 0002h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 007Dh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h
Erase Block Region Information (refer specification publication 100)
Erase Block Region Information (refer specification publication 100)
Erase Block Region Information (refer specification publication 100)
2003
Am50DL9608G
Table
Addresses (Word Mode) Addresses (Byte Mode)
Am29DL640G Primary Vendor-Specific Extended Query
Description Query-unique ASCII string "PRI" Major version number, ASCII (reflects modifications silicon) Minor version number, ASCII (reflects modifications table) Address Sensitive Unlock (Bits 1-0) Required, Required Silicon Revision Number (Bits 7-2)
Data 0050h 0052h 0049h 0031h 0033h 0004h
0002h 0001h 0001h
Erase Suspend Supported, Read Only, Read Write Sector Protect Supported, Number sectors group Sector Temporary Unprotect Supported, Supported Sector Protect/Unprotect scheme =29F040 mode, 29F016 mode, 29F400, 29LV800 mode Simultaneous Operation Supported, Number Sectors (excluding Bank Burst Mode Type Supported, Supported Page Mode Type Supported, Word Page, Word Page (Acceleration) Supply Minimum Supported, D7-D4: Volt, D3-D0: (Acceleration) Supply Maximum Supported, D7-D4: Volt, D3-D0: Top/Bottom Boot Sector Flag
0004h
0077h 0000h 0000h 0085h
0095h
0001h
Uniform device, Kbyte Sectors, Bottom Boot with Write Protect, Bottom Boot Device, Boot Device, Both Bottom Program Suspend supported, Supported Bank Organization Data zero, Number Banks Bank Region Information Number Sectors Bank Bank Region Information Number Sectors Bank Bank Region Information Number Sectors Bank
0001h
0004h
0017h
0030h
0030h
Am50DL9608G
2003
Addresses (Word Mode) Addresses (Byte Mode)
Data 0017h Bank Region Information
Description
Number Sectors Bank
Table
Addresses (Word Mode) Addresses (Byte Mode)
Am29DL320G Query Identification String
Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string "QRY"
Primary Command Address Primary Extended Table Alternate Command (00h none exists) Address Alternate Extended Table (00h none exists)
Table
Addresses (Word Mode) Addresses (Byte Mode)
Am29DL320G System Interface String
Description Min. (write/erase) D7-D4: volt, D3-D0: millivolt Max. (write/erase) D7-D4: volt, D3-D0: millivolt Min. voltage (00h present) Max. voltage (00h present) Typical timeout single byte/word write Typical timeout Min. size buffer write (00h supported) Typical timeout individual block erase Typical timeout full chip erase (00h supported) Max. timeout byte/word write times typical Max. timeout buffer write times typical Max. timeout individual block erase times typical Max. timeout full chip erase times typical (00h supported)
Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h
2003
Am50DL9608G
Table
Addresses (Word Mode) Addresses (Byte Mode)
Am29DL320G Device Geometry Definition
Data Description Device Size byte Flash Device Interface description (refer publication 100) Max. number bytes multi-byte write (00h supported) Number Erase Block Regions within device Erase Block Region Information (refer specification publication 100)
0016h 0002h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
Erase Block Region Information
Erase Block Region Information
Erase Block Region Information
Am50DL9608G
2003
Table
Addresses (Word Mode) Addresses (Byte Mode)
Am29DL320G Primary Vendor-Specific Extended Query
Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Silicon Revision Number 0.23 0.17 Erase Suspend Supported, Read Only, Read Write Sector Protect Supported, Number sectors group Sector Temporary Unprotect Supported, Supported Sector Protect/Unprotect scheme 29LV800 mode Simultaneous Operation Number Sectors (excluding Bank Burst Mode Type Supported, Supported Page Mode Type Supported, Word Page, Word Page (Acceleration) Supply Minimum Supported, D7-D4: Volt, D3-D0: (Acceleration) Supply Maximum Supported, D7-D4: Volt, D3-D0: Top/Bottom Boot Sector Flag Bottom Boot Device, Boot Device
Data 0050h 0052h 0049h 0031h 0033h 0001h 0002h 0001h 0001h 0004h 0038h 0000h 0000h 0085h
0095h
000Xh
2003
Am50DL9608G
FLASH COMMAND DEFINITIONS
Writing specific address data commands sequences into command register initiates device operations. Table defines valid register command sequences. Writing incorrect address data values writing them improper sequence place device unknown state. reset command then required return device reading array data. addresses latched falling edge CE#f, whichever happens later. data latched rising edge CE#f, whichever happens first. Refer Flash Characteristics section timing diagrams. reset command written between sequence cycles program command sequence before programming begins. This resets bank which system writing read mode. program command sequence written bank that Erase Suspend mode, writing reset suspend-read mode. Once programming begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles autoselect command sequence. Once autoselect mode, reset command must written return read mode. bank entered autoselect mode while Erase Suspend mode, writing reset command returns that bank erase-suspend-read mode. goes high during program erase operation, writing reset command returns banks read mode erase-suspend-read mode that bank Erase Suspend).
Reading Array Data
device automatically reading array data after device power-up. commands required retrieve data. Each bank ready read array data after completing Embedded Program Embedded Erase algorithm. After device accepts Erase Suspend command, corresponding bank enters eras e-sus pend-read mode, after which system read data from non-erase-suspended sector within same bank. system read array data using standard read timing, except that reads address within erase-suspended sectors, device outputs status data. After completing programming operation Erase Suspend mode, system once again read array data with same exception. Erase Suspend/Erase Resume Commands section more information. system must issue reset command return bank read erase-suspend-read) mode goes high during active program erase operation, bank autoselect mode. next section, Reset Command, more information. also Requirements Reading Array Data section more information. Read-Only Operations table provides read parameters, Figure shows timing diagram.
Autoselect Command Sequence
autoselect command sequence allows host system access manufacturer device codes, determine whether sector protected. autoselect command sequence written address within bank that either read erase-suspend-read mode. autoselect command written while device actively programming erasing other bank. autoselect command sequence initiated first writing unlock cycles. This followed third write cycle that contains bank address autoselect command. bank then enters autoselect mode. system read number autoselect codes without reinitiating command sequence. Table shows address data requirements. determine sector protection information, system must write appropriate bank address (BA) sector address (SADD). Table shows address range bank number associated with each sector. system must write reset command return read mode erase-suspend-read mode bank previously Erase Suspend).
Reset Command
Writing reset command resets banks read erase-suspend-read mode. Address bits don't cares this command. reset command written between sequence cycles erase command sequence before erasing begins. This resets bank which system writing read mode. Once erasure begins, however, device ignores reset commands until operation complete.
Enter SecSiSector/Exit SecSi Sector Command Sequence
SecSi Sector region provides secured data area containing random, sixteen-byte electronic serial number (ESN). system access SecSi Sector region issuing three-cycle Enter SecSi
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Sector command sequence. device continues access SecSi Sector region until system issues four-cycle Exit SecSi Sector command sequence. Exit SecSi Sector command sequence returns device normal operation. SecSi Sector accessible when device executing Embedded Program embedded Erase algorithm. Table shows address data requirements both command sequences. Note that function unlock bypass modes available when SecSi sector enabled. also "SecSi(Secured Silicon) Sector SectorFlash Memory Region" further information. status bits indicate operation successful. However, succeeding read will show that data still "0." Only erase operations convert "1." Unlock Bypass Command Sequence unlock bypass feature allows system program bytes words bank faster than using standard program command sequence. unlock bypass command sequence initiated first writing unlock cycles. This followed third write cycle containing unlock bypass command, 20h. That bank then enters unlock bypass mode. two-cycle unlock bypass program command sequence that required program this mode. first cycle this sequence contains unlock bypass program command, A0h; second cycle contains program address data. Additional data programmed same manner. This mode dispenses with initial unlock cycles required standard program command sequence, resulting faster total programming time. Table shows requirements command sequence. During unlock bypass mode, only Unlock Bypass Program Unlock Bypass Reset commands valid. exit unlock bypass mode, system must issue two-cycle unlock bypass reset command sequence (See Table 12). device offers accelerated program operations through WP#/ACC pin. When system asserts WP#/ACC pin, device automatically enters Unlock Bypass mode. system then write two-cycle Unlock Bypass program command sequence. device uses higher voltage WP#/ACC accelerate operation. Note that WP#/ACC must operation other than accelerated programming, device damage result. addition, WP#/ACC must left floating unconnected; inconsistent behavior device result. Figure illustrates algorithm program operation. Refer Erase Program Operations table Characteristics section parameters, Figure timing diagrams.
Program Command Sequence
Programming four-bus-cycle operation. program command sequence initiated writing unlock write cycles, followed program set-up command. program address data written next, which turn initiate Embedded Program algorithm. system required provide further controls timings. device automatically provides internally generated program pulses verifies programmed cell margin. Table shows address data requirements byte program command sequence. Note that SecSi Sector, autoselect, functions unavailable when program operation progress. When Embedded Program algorithm complete, that bank then returns read mode addresses longer latched. system determine status program operation using DQ7, DQ6, RY/BY#. Refer Flash Write Operation Status section information these status bits. commands written device during Embedded Program Algorithm ignored. Note that hardware reset immediately terminates program operation. program command sequence should reinitiated once that bank returned read mode, ensure data integrity. Programming allowed sequence across sector boundaries. cannot programmed from back "1." Attempting cause that bank cause
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Am50DL9608G
commands written during chip erase operation ignored. However, note that hardware reset immediately terminates erase operation. that occurs, chip erase command sequence should reinitiated once that bank returned reading array data, ensure data integrity. Figure illustrates algorithm erase operation. Refer Erase Program Operations tables Characteristics section parameters, Figure section timing diagrams.
START
Write Program Command Sequence
Embedded Program algorithm progress
Data Poll from System
Sector Erase Command Sequence
Sector erase cycle operation. sector erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock cycles written, then followed address sector erased, sector erase command. Table shows address data requirements sector erase comm autoselect, functions unavailable when erase operation progress. device does require system preprogram prior erase. Embedded Erase algorithm automatically programs verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. After command sequence written, sector erase time-out occurs. During time-out period, additional sector addresses sector erase commands written. Loading sector erase buffer done sequence, number sectors from sector sectors. time between these additional cycles must less than otherwise erasure begin. sector erase address command following exceeded time-out accepted. recommended that processor interrupts disabled during this time ensure commands accepted. interrupts re-enabled after last Sector Erase command written. command other than time-out period resets that bank read mode. system must rewrite command sequence additional addresses commands. system monitor determine sector erase timer timed (See section DQ3: Sector Erase Timer.). time-out begins from rising edge final pulse command sequence. When Embedded Erase algorithm complete, bank returns reading array data addresses longer latched. Note that while Embedded Erase operation progress, system read
Verify Data?
Increment Address
Last Address?
Programming Completed
Note: Table program command sequence.
Figure
Program Operation
Chip Erase Command Sequence
Chip erase cycle operation. chip erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed chip erase command, which turn invokes Embedded Erase algorithm. device does require system preprogram prior erase. Embedded Erase algorithm automatically preprograms verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. Table shows address data requirements chip erase command sequence. Note that SecSi Sector, autoselect, functions unavailable when erase operation progress. When Embedded Erase algorithm complete, that bank returns read mode addresses longer latched. system determine status erase operation using DQ7, DQ6, DQ2, RY/BY#. Refer Flash Write Operation Status section information these status bits.
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data from non-erasing bank. system determine status erase operation reading DQ7, DQ6, DQ2, RY/BY# erasing bank. Refer Flash Write Operation Status section information these status bits. Once sector erase operation begun, only Erase Suspend command valid. other commands ignored. However, note that hardware reset immediately terminates erase operation. that occurs, sector erase command sequence should reinitiated once that bank returned reading array data, ensure data integrity. Figure illustrates algorithm erase operation. Refer Erase Program Operations tables Characteristics section parameters, Figure section timing diagrams.
Erase Suspend/Erase Resume Commands
Erase Suspend command, B0h, allows system interrupt sector erase operation then read data from, program data sector selected erasure. bank address required when writing this command. This command valid only during sector erase operation, including time-out period during sector erase command sequence. Erase Suspend command ignored written during chip erase operation Embedded Program algorithm. When Erase Suspend command written during sector erase operation, device requires maximum suspend erase operation. However, when Erase Suspend command written during sector erase time-out, device immediately terminates time-out period suspends erase operation. Addresses "don't-cares" when writing Erase suspend command. After erase operation been suspended, bank enters erase-suspend-read mode. system read data from program data sector selected erasure. (The device "erase suspends" sectors selected erasure.) Reading address within erase-suspended sectors produces status information DQ7-DQ0. system DQ7, together, determine sector actively erasing erase-suspended. Refer Flash Write Operation Status section information these status bits. After erase-suspended program operation complete, bank returns erase-suspend-read mode. system determine status program operation using status bits, just standard Byte Program operation. Refer Flash Write Operation Status section more information. erase-suspend-read mode, system also issue autoselect command sequence. device allows reading autoselect codes even addresses within erasing sectors, since codes stored memory array. When device exits autoselect mode, device reverts Erase Suspend mode, ready another valid operation. Refer Sector/Sector Block Protection Unprotection Autoselect Command Sequence sections details. resume sector erase operation, system must write Erase Resume command (address bits don't care). bank address erase-suspended bank required when writing this command. Further writes Resume command ignored. Another Erase Suspend command written after chip resumed erasing.
START
Write Erase Command Sequence (Notes
Data Poll Erasing Bank from System
Embedded Erase algorithm progress
Data FFh?
Erasure Completed
Notes: Table erase command sequence. section information sector erase timer.
Figure
Erase Operation
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Am50DL9608G
Table
Command Sequence (Note Read (Note Reset (Note Autoselect (Note Manufacturer Device (Note SecSi Sector Factory Protect (Note Sector/Sector Block Protect Verify (Note Word Word Word Word Word Word Word Word Cycles
Am29DL640G Am29DL320G Command Definitions
First Addr Data Second Addr Data Cycles (Notes 2-5) Third Fourth Addr Data Addr Data Fifth Addr Data Sixth Addr Data
(BA)555 (BA)555 (BA)555 (BA)555
(BA)X00 (BA)X01
(BA)X0E 02/0A (BA)X0F 00/01
(BA)X03 80/00 (SADD) 00/01
Enter SecSi Sector Region Exit SecSi Sector Region Program Unlock Bypass
Unlock Bypass Program (Note Unlock Bypass Reset (Note Chip Erase Word Sector Erase Word Erase Suspend (Note Erase Resume (Note Query (Note Word
SADD
Legend: Don't care Address memory location read. Data read from location during read operation. Address memory location programmed. Addresses latch falling edge CE#f pulse, whichever happens later.
Data programmed location Data latches rising edge CE#f pulse, whichever happens first. SADD Address sector verified autoselect mode) erased. Address bits A21-A12 uniquely select sector. Refer Table information sector addresses. Address bank that being switched autoselect mode, bypass mode, being erased. Address bits A21-A19 select bank. Refer Table information sector addresses.
Notes: Tables description operations. values hexadecimal. Except read cycle fourth cycle autoselect command sequence, cycles write cycles. Data bits DQ15-DQ8 don't care command sequences, except Unless otherwise noted, address bits A21-A12 don't cares unlock command cycles, unless SADD required. unlock command cycles required when bank reading array data. Reset command required return read mode erase-suspend-read mode previously Erase Suspend) when bank autoselect mode, goes high (while bank providing status information). fourth cycle autoselect command sequence read cycle. system must provide bank address obtain manufacturer device SecSi Sector factory protect information. Data bits DQ15-DQ8 don't care. Autoselect Command Sequence section more information. device must read across fourth, fifth, sixth cycles. address x0E, data Am29DL640G Am29DL320G. address x0F, data
Am29DL640G Am29DL320G (top boot) Am29DL320G (bottom boot). Am29DL640G, data factory locked factory locked. Am29DL320G, they respectively. data unprotected sector/sector block protected sector/sector block. Unlock Bypass command required prior Unlock Bypass Program command. Unlock Bypass Reset command required return read mode when bank unlock bypass mode. system read program non-erasing sectors, enter autoselect mode, when Erase Suspend mode. Erase Suspend command valid only during sector erase operation, requires bank address. Erase Resume command valid only during Erase Suspend mode, requires bank address. Command valid when device ready read array data when device autoselect mode.
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FLASH WRITE OPERATION STATUS
device provides several bits determine status program erase operation: DQ2, DQ3, DQ5, DQ6, DQ7. Table following subsections describe function these bits. each offer method determining whether program erase operation complete progress. device also provides hardware-based output signal, RY/BY#, determine whether Embedded Program Erase operation progress been completed. pleted program erase operation valid data, data outputs DQ15-DQ0 still invalid. Valid data DQ15-DQ0 DQ7-DQ0 byte mode) will appear successive read cycles. Table shows outputs Data# Polling DQ7. Figure shows Data# Polling algorithm. Figure Flash Characteristics section shows Data# Polling timing diagram.
DQ7: Data# Polling
Data# Polling bit, DQ7, indicates host system whether Embedded Program Erase algorithm progress completed, whether bank Erase Suspend. Data# Polling valid after rising edge final pulse command sequence. During Embedded Program algorithm, device outputs complement datum programmed DQ7. This status also applies programming during Erase Suspend. When Embedded Program algorithm complete, device outputs datum programmed DQ7. system must provide program address read valid status information DQ7. program address falls within protected sector, Data# Polling active approximately then that bank returns read mode. During Embedded Erase algorithm, Data# Polling produces DQ7. When Embedded Erase algorithm complete, bank enters Erase Suspend mode, Data# Polling produces DQ7. system must provide address within sectors selected erasure read valid status information DQ7. After erase command sequence written, sectors selected erasing protected, Data# Polling active approximately then bank returns read mode. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. However, system reads address within protected sector, status valid. When system detects changed from complement true data, read valid data DQ15-DQ0 DQ7-DQ0 byte mode) following read cycles. Just prior completion Embedded Program Erase operation, change asynchronously with DQ15-DQ8 (DQ7-DQ0 byte mode) while Output Enable (OE#) asserted low. That device change from providing status information valid data DQ7. Depending when system samples output, read status valid data. Even device comSTART
Read DQ7-DQ0 Addr
Data?
Read DQ7-DQ0 Addr
Data?
FAIL PASS
Notes: Valid address programming. During sector erase operation, valid address sector address within sector being erased. During chip erase, valid address non-protected sector address. should rechecked even because change simultaneously with DQ5.
Figure
Data# Polling Algorithm
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Am50DL9608G
RY/BY#: Ready/Busy#
RY/BY# dedicated, open-drain output which indicates whether Embedded Algorithm progress complete. RY/BY# status valid after rising edge final pulse command sequence. Since RY/BY# open-drain output, several RY/BY# pins tied together parallel with pull-up resistor VCC. output (Busy), device actively erasing programming. (This includes programming Erase Suspend mode.) output high (Ready), device read mode, standby mode, banks erase-suspend-read mode. Table shows outputs RY/BY#.
also toggles during erase-suspend-program mode, stops toggling once Embedded Program algorithm complete. Table shows outputs Toggle DQ6. Figure shows toggle algorithm. Figure "Flash Characteristics" section shows toggle timing diagrams. Figure shows differences between graphical form. also subsection DQ2: Toggle
START
DQ6: Toggle
Toggle indicates whether Embedded Program Erase algorithm progress complete, whether device entered Erase Suspend mode. Toggle read address, valid after rising edge final pulse command sequence (prior program erase operation), during sector erase time-out. During Embedded Program Erase algorithm operation, successive read cycles address cause toggle. system either CE#f control read cycles. When operation complete, stops toggling. After erase command sequence written, sectors selected erasing protected, toggles approximately then returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. system together determine whether sector actively erasing erase-suspended. When device actively erasing (that Embedded Erase algorithm progress), toggles. When device enters Erase Suspend mode, stops toggling. However, system must also determine which sectors erasing erase-suspended. Alternatively, system (see subsection DQ7: Data# Polling). program address falls within protected sector, toggles approximately after program command sequence written, then returns reading array data.
Read Byte (DQ7-DQ0) Address Read Byte (DQ7-DQ0) Address
Toggle Toggle?
Read Byte Twice (DQ7-DQ0) Address
Toggle Toggle?
Program/Erase Operation Complete, Write Reset Command Program/Erase Operation Complete
Note: system should recheck toggle even because toggle stop toggling changes "1." subsections more information.
Figure
Toggle Algorithm
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DQ2: Toggle
"Toggle DQ2, when used with DQ6, indicates whether particular sector actively erasing (that Embedded Erase algorithm progress), whether that sector erase-suspended. Toggle valid after rising edge final pulse command sequence. toggles when system reads addresses within those sectors that have been selected erasure. (The system either CE#f control read cycles.) cannot distinguish whether sector actively erasing erase-suspended. DQ6, comparison, indicates whether device actively erasing, Erase Suspend, cannot distinguish which sectors selected erasure. Thus, both status bits required sector mode information. Refer Table compare outputs DQ6. Figure shows toggle algorithm flowchart form, section "DQ2: Toggle explains algorithm. also DQ6: Toggle subsection. Figure shows toggle timing diagram. Figure shows differences between graphical form.
gone high. system continue monitor toggle through successive read cycles, determining status described previous paragraph. Alternatively, choose perform other system tasks. this case, system must start beginning algorithm when returns determine status operation (top Figure
DQ5: Exceeded Timing Limits
indicates whether program erase time exceeded specified internal pulse count limit. Under these conditions produces "1," indicating that program erase cycle successfully completed. device output system tries program location that previously programmed "0." Only erase operation change back "1." Under this condition, device halts operation, when timing limit been exceeded, produces "1." Under both these conditions, system must write reset command return read mode erase-suspend-read mode bank previously erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing sector erase command sequence, system read determine whether erasure begun. (The sector erase timer does apply chip erase command.) additional sectors selected erasure, entire time-out also applies after each additional sector erase command. When time-out period complete, switches from "1." time between additional sector erase commands from system assumed less than system need monitor DQ3. also Sector Erase Command Sequence section. After sector erase command written, system should read status (Data# Polling) (Toggle ensure that device accepted command sequence, then read DQ3. "1," Embedded Erase algorithm begun; further commands (except Erase Suspend) ignored until erase operation complete. "0," device will accept additional sector erase commands. ensure command been accepted, system software should check status prior following each subsequent sector erase command. high second status check, last command might have been accepted. Table shows status relative other status bits.
Reading Toggle Bits DQ6/DQ2
Refer Figure following discussion. Whenever system initially begins reading toggle status, must read DQ15-DQ0 DQ7-DQ0 byte mode) least twice determine whether toggle toggling. Typically, system would note store value toggle after first read. After second read, system would compare value toggle with first. toggle toggling, device completed program erase operation. system read array data DQ15-DQ0 DQ7-DQ0 byte mode) following read cycle. However, after initial read cycles, system determines that toggle still toggling, system also should note whether value high (see section DQ5). system should then determine again whether toggle toggling, since toggle have stopped toggling just went high. toggle longer toggling, device successfully completed program erase operation. still toggling, device completed operation successfully, system must write reset command return reading array data. remaining scenario that system initially determines that toggle toggling
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Table
Status Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program
Write Operation Status
(Note DQ7# Data DQ7# Toggle Toggle toggle Data Toggle (Note Data Data (Note toggle Toggle Toggle Data RY/BY#
Standard Mode Erase Suspend Mode
Notes: switches when Embedded Program Embedded Erase operation exceeded maximum timing limits. Refer section more information. require valid address when reading status information. Refer appropriate subsection further details. When reading write operation status bits, system must always provide bank address where Embedded Algorithm progress. device outputs array data system addresses non-busy bank.
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages -55°C +125°C Ambient Temperature with Power Applied -40°C +85°C Voltage with Respect Ground (Note .-0.5 +4.0 RESET# (Note .-0.5 +12.5 WP#/ACC .-0.5 +10.5 other pins (Note -0.5 +0.5 Output Short Circuit Current (Note
Notes: Minimum voltage input pins -0.5 During voltage transitions, input pins overshoot -2.0 periods Maximum voltage input pins +0.5 Figure During voltage transitions, input pins overshoot +2.0 periods Figure Minimum input voltage pins RESET#, WP#/ACC -0.5 During volta tran sitions, WP#/ACC, RESET# overshoot -2.0 periods Figure Maximum input voltage RESET# +12.5 which overshoot +14.0 periods Maximum input voltage WP#/ACC +9.5 which overshoot +12.0 periods more than output shorted ground time. Duration short circuit should greater than second. Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this data sheet implied. Exposure device absolute maximum rating conditions extended periods affect device reliability. +0.8 -0.5 -2.0
Figure Maximum Negative Overshoot Waveform
+2.0 +0.5
Figure Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial Devices Ambient Temperature (TA) -40°C +85°C VCCf/VCCs Supply Voltages VCCf/VCCs standard voltage range
Operating ranges define those limits between which functionality device guaranteed.
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FLASH CHARACTERISTICS CMOS Compatible
Parameter Symbol ILIT ILIA ICC1f ICC2f ICC3f ICC4f ICC5f ICC6f ICC7f Parameter Description Input Load Current RESET# Input Load Current Output Leakage Current Reset Leakage Current Input Leakage Current Flash Active Read Current (Notes Test Conditions VCC, max; RESET# 12.5 VOUT VCC, max; RESET# 12.5 max, WP#/ACC VACC CE#f VIL, VIH, Word Mode ±1.0 ±1.0 Unit
Flash Active Write Current (Notes CE#f VIL, VIH, Flash Standby Current (Note Flash Reset Current (Note Flash Current Automatic Sleep Mode (Notes Flash Active Read-While-Program Current (Notes Flash Active Read-While-Erase Current (Notes Flash Active Program-While-Erase-Suspended Current (Notes Input Voltage Input High Voltage Voltage WP#/ACC Program Acceleration Sector Protection/Unprotection Voltage Sector Protection, Autoselect Temporary Sector Unprotect Output Voltage VCCf VCCs -2.0 VCCf VCCs -100 Flash Lock-Out Voltage (Note 0.85 VCC-0.4 VCCf max, CE#f, RESET#, WP#/ACC VCCf VCCf max, RESET# WP#/ACC VCCf VCCf max, CE#f VIL, CE#f VIL,
ICC8f
CE#f VIL, OE#f -0.2
VOH1 VOH2 VLKO
11.5
12.5 0.45
Output High Voltage
Notes: current listed typically less than mA/MHz, with VIH. Maximum specifications tested with VCCmax. active while Embedded Erase Embedded Program progress.
Automatic sleep mode enables power mode when addresses remain stable tACC Typical sleep mode current 100% tested.
Flash stack together
double current limit from
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FLASH CHARACTERISTICS Zero-Power Flash
Supply Current
1000 1500 2000 Time 2500 3000 3500 4000
Note: Addresses switching
Figure
ICC1 Current Time (Showing Active Automatic Sleep Currents)
Supply Current
Note:
Frequency Figure Typical ICC1 Frequency
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Am50DL9608G
PSEUDO SRAM OPERATING CHARACTERISTICS
Parameter Symbol Parameter Description Input Leakage Current Output Leakage Current Test Conditions CE1#s VIH, CE2s VIL, VIO= Cycle time 100% duty, CE1#s Cycle time Min., 100% duty, CE1#s VIL, CE2s VIH, -0.2 (Note -1.0 CE1#s VIH, VIL, Other inputs CE1#s=VIH, CE2= VIL: Other inputs VIL: 85°C, CE1#s=VIH, CE2= VIL: Other inputs VIL: 85°C, -1.0 -1.0 Unit
ICC1s
Average Operating Current
ICC2s
Average Operating Current
Input Voltage Input High Voltage Output Voltage Output High Voltage Standby Current (TTL)
VCC+0.2 (Note
ISB1
Standby Current (CMOS)
ISB2
Standby Current (CMOS)
Notes: -40° 85°C, otherwise specified.
Overshoot: VCC+1.0V pulse width Undershoot: -1.0V pulse width Overshoot undershoot sampled, 100% tested. Stable power supply required before device operation.
Figure
Standby Current CMOS
CMOS (µA)
Note:
70°, reference only 100% tested
Sample Size
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TEST CONDITIONS
Table
Test Condition Output Load Output Load Capacitance, (including capacitance) Input Rise Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
Test Specifications
Speed Options gate 0.0-3.0 Unit
Device Under Test
Note: Diodes IN3064 equivalent
Figure
Test Setup
SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from Changing from Don't Care, Change Permitted Does Apply Changing, State Unknown Center Line High Impedance State (High OUTPUTS
KS000010-PAL
Input
Measurement Level
Output
Figure
Input Waveforms Measurement Levels
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Am50DL9608G
FLASH CHARACTERISTICS Pseudo SRAM CE#s Timing
Parameter Test Setup JEDEC tCCR Description CE#s Recover Time Speeds Unit
CE#f
tCCR CE1#s
tCCR
tCCR CE2s
tCCR
Figure Timing Diagram Alternating Between Pseudo SRAM Flash
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FLASH CHARACTERISTICS Read-Only Operations
Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Std. tACC Description Read Cycle Time (Note Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output High (Notes Output Enable Output High (Notes Output Hold Time From Addresses, CE#f OE#, Whichever Occurs First Read tOEH Output Enable Hold Time (Note Toggle Data# Polling CE#f, Test Setup Speed Options Unit
Notes: 100% tested. Figure Table test specifications Measurements performed placing termination data with bias VCC/2. time from high data driven VCC/2 taken
Addresses CE#f tOEH HIGH Outputs RESET# RY/BY# Output Valid HIGH Addresses Stable tACC
Figure
Read Operation Timings
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Am50DL9608G
FLASH CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC tReady tReady tRPD Description RESET# (During Embedded Algorithms) Read Mode (See Note) RESET# (NOT During Embedded Algorithms) Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Standby Mode RY/BY# Recovery Time Speed Options Unit
Note: 100% tested.
RY/BY#
CE#f, RESET# tReady
Reset Timings during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# CE#f,
RESET#
Figure
Reset Timings
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FLASH CHARACTERISTICS Erase Program Operations
Parameter JEDEC tAVAV tAVWL tASO tWLAX Description Write Cycle Time (Note Address Setup Time Address Setup Time during toggle polling Am29DL640G Address Hold Time Am29DL320G Address Hold Time From CE#f high during toggle polling Am29DL640G tDVWH tWHDX tOEPH tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tWHDL tGHWL tWPH tSR/W tWHWH1 tWHWH1 tWHWH2 tWHWH1 tWHWH1 tWHWH2 tVCS tBUSY Notes: 100% tested. "Flash Erase Programming Performance" section more information. Data Setup Time Am29DL320G Data Hold Time Output Enable High during toggle polling Read Recovery Time Before Write (OE# High Low) Setup Time (CE#f WE#) CE#f Setup Time Hold Time (CE#f WE#) CE#f Hold Time Write Pulse Width Write Pulse Width High Latency Between Read Write Operations Programming Operation (Note Accelerated Programming Operation, Word Byte (Note Sector Erase Operation (Note Setup Time (Note Write Recovery Time from RY/BY# Program/Erase Valid RY/BY# Delay Speed Options Unit
tAHT
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FLASH CHARACTERISTICS
Program Command Sequence (last cycles) Addresses 555h CE#f tGHWL Data tBUSY RY/BY# Status DOUT tWPH tWHWH1 Read Status Data (last cycles)
VCCf tVCS
Notes: program address, program data, DOUT true data program address. Illustration shows device word mode.
Figure
Program Operation Timings
WP#/ACC
tVHH tVHH
Figure
Accelerated Program Timing Diagram
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FLASH CHARACTERISTICS
Erase Command Sequence (last cycles) Addresses 2AAh SADD
555h chip erase
Read Status Data
CE#f tGHWL Data
Chip Erase Progress Complete
tWPH
tWHWH2
tBUSY RY/BY# tVCS VCCf
Notes: SADD sector address (for Sector Erase), Valid Address reading status data (see "Flash Write Operation Status". These waveforms word mode.
Figure
Chip/Sector Erase Operation Timings
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Am50DL9608G
FLASH CHARACTERISTICS
Addresses
Valid
Valid
Valid
Valid
tACC
CE#f
tCPH
tOEH tWPH Data
Valid
tGHWL
Valid Valid Valid
tSR/W
Controlled Write Cycle Read Cycle CE#f Controlled Write Cycles
Figure
Back-to-back Read/Write Cycle Timings
Addresses tACC CE#f tOEH
High
Complement
Complement
True
Valid Data
High
DQ6-DQ0 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: Valid address. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
Figure
Data# Polling Timings (During Embedded Algorithms)
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FLASH CHARACTERISTICS
tAHT Addresses tAHT tASO CE#f tOEH tOEPH DQ6/DQ2 Valid Data
Valid Status
tCEPH
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: Valid address; required DQ6. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
Figure
Toggle Timings (During Embedded Algorithms)
Enter Embedded Erasing
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
Note: toggles only when read address within erase-suspended sector. system CE#f toggle DQ6.
Figure
2003
Am50DL9608G
FLASH CHARACTERISTICS Temporary Sector Unprotect
Parameter JEDEC tVIDR tVHH tRSP tRRB Description Rise Fall Time (See Note) Rise Fall Time (See Note) RESET# Setup Time Temporary Sector Unprotect RESET# Hold Time from RY/BY# High Temporary Sector Unprotect Speed Options Unit
Note: 100% tested.
RESET# VSS, VIL, tVIDR Program Erase Command Sequence CE#f tVIDR
VSS, VIL,
tRSP RY/BY# tRRB
Figure
Temporary Sector Unprotect Timing Diagram
Am50DL9608G
2003
FLASH CHARACTERISTICS
RESET#
SADD,
Valid* Sector/Sector Block Protect Unprotect
Valid* Verify
Sector/Sector Block Protect: Sector/Sector Block Unprotect:
Valid*
Data
Status
CE#f
sector protect, sector unprotect, SADD Sector Address.
Figure Sector/Sector Block Protect Unprotect Timing Diagram
2003
Am50DL9608G
FLASH CHARACTERISTICS Alternate CE#f Controlled Erase Program Operations
Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH1 tWHWH2 tGHEL tCPH tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High Low) Setup Time Hold Time CE#f Pulse Width CE#f Pulse Width High Programming Operation (Note Accelerated Programming Operation, Word Byte (Note Sector Erase Operation (Note Speed Options Unit
Notes: 100% tested. "Flash Erase Programming Performance" section more information.
Am50DL9608G
2003
FLASH CHARACTERISTICS
program erase program SADD sector erase chip erase
Data# Polling
Addresses tGHEL CE#f tCPH Data
program erase program sector erase chip erase
tWHWH1
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: Figure indicates last cycles program erase operation. program address, SADD sector address, program data. DQ7# complement data written device. DOUT data written device. Waveforms word mode.
Figure
Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings
2003
Am50DL9608G
PSEUDO SRAM CHARACTERISTICS Power Time
When powering SRAM, maintain VCCs minimum with CE#1s VIH.
Read Cycle
Parameter Symbol tCO1, tCO2 tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ Speed Description Read Cycle Time Address Access Time Chip Enable Output Output Enable Access Time LB#s, UB#s Access Time Chip Enable (CE1#s CE2s High) Low-Z Output UB#, Enable Low-Z Output Output Enable Low-Z Output Chip Disable High-Z Output UB#s, LB#s Disable High-Z Output Output Disable High-Z Output Output Data Hold from Address Change Unit
Address Data Previous Data Valid Data Valid
Notes: CE1#s VIL, CE2s VIH, UB#s and/or LB#s access device with cycle timing shorter than continuous periods
Figure
Pseudo SRAM Read Cycle-Address Controlled
Am50DL9608G
2003
PSEUDO SRAM CHARACTERISTICS Read Cycle
Address tCO1
CE#1s
CE2s
tCO2 tOLZ tBLZ Data Valid
tOHZ
Data
High-Z
Notes: VIH. tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, (Max.) less than (Min.) both given device from device device interconnection. access device with cycle timing shorter than continuous periods
Figure
Pseudo SRAM Read Cycle
2003
Am50DL9608G
PSEUDO SRAM CHARACTERISTICS Write Cycle
Parameter Symbol tWHZ Speed Description Write Cycle Time Chip Enable Write Address Setup Time Address Valid Write UB#s, LB#s Write Write Pulse Time Write Recovery Time Write Output High-Z Data Write Time Overlap Data Hold from Write Time Write Output Low-Z Unit
Address (See Note CE2s (See Note (See Note (See Note High-Z tWHZ Data Data Undefined
Data Valid
CE1#s
High-Z
Data
Notes: controlled. measured from CE1#s going write. measured from write address change. applied case write ends CE1#s going high. measured from address valid beginning write. write occurs during overlap (tWP) CE#1 WE#. write begins when CE1#s goes goes when asserting UB#s LB#s single byte operation simultaneously asserting UB#s LB#s double byte operation. write ends earliest transition when CE1#s goes high goes high. measured from beginning write write.
Figure
Pseudo SRAM Write Cycle-WE# Control
Am50DL9608G
2003
PSEUDO SRAM CHARACTERISTICS
Address (See Note (See Note CE1#s CE2s (See Note Data (See Note
UB#s, LB#s
Data Valid
Data
High-Z
High-Z
Notes: CE1#s controlled. measured from CE1#s going write. measured from write address change. applied case write ends CE1#s going high. measured from address valid beginning write. write occurs during overlap (tWP) CE1#s WE#. write begins when CE1#s goes goes when asserting UB#s LB#s single byte operation simultaneously asserting UB#s LB#s double byte operation. write ends earliest transition when CE1#s goes high goes high. measured from beginning write write.
Figure
Pseudo SRAM Write Cycle-CE1#s Control
2003
Am50DL9608G
PSEUDO SRAM CHARACTERISTICS
Address (See Note CE2s UB#s, LB#s (See Note (See Note (See Note Data (See Note
CE1#s
Data Valid
Data
High-Z
High-Z
Notes: UB#s LB#s controlled. measured from CE1#s going write. measured from write address change. applied case write ends CE1#s going high. measured from address valid beginning write. write occurs during overlap (tWP) CE#1s WE#. write begins when CE1#s goes goes when asserting UB#s LB#s single byte operation simultaneously asserting UB#s LB#s double byte operation. write ends earliest transition when CE1#s goes high goes high. measured from beginning write write.
Figure Pseudo SRAM Write Cycle- UB#s LB#s Control
Am50DL9608G
2003
FLASH ERASE PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Am29DL640G Chip Erase Time Am29DL320G Accelerated Word Program Time Word Program Time Chip Program Time (Note Am29DL640G Am29DL320G Excludes system level overhead (Note (Note (Note Unit Comments Excludes programming prior erasure (Note
Notes: Typical program erase times assume following conditions: 25°C, VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. Under worst case conditions 90°C, 1,000,000 cycles. typical chip programming time considerably less than maximum chip programming time listed, since most bytes program faster than maximum program times listed. pre-programming step Embedded Erase algorithm, bytes programmed before erasure. System-level overhead time required execute two- four-bus-cycle sequence program command. Table further information command definitions. device minimum erase program cycle endurance 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Input voltage with respect pins except pins (including OE#, RESET#) Input voltage with respect pins Current -1.0 -1.0 -100 12.5 +100
Note: Includes pins except VCC. Test conditions: time.
PACKAGE CAPACITANCE
Parameter Symbol COUT CIN2 CIN3 Parameter Description Input Capacitance Output Capacitance Control Capacitance WP#/ACC Capacitance Test Setup VOUT Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
FLASH DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time 125°C Years Test Conditions 150°C Unit Years
2003
Am50DL9608G
PHYSICAL DIMENSIONS FTA073-73-Ball Fine-Pitch Grid Array 11.6
0.15 (2X)
INDEX MARK CORNER
VIEW
0.15 (2X)
CORNER
BOTTOM VIEW
0.20
0.08
SIDE VIEW
0.15 0.08
NOTES: PACKAGE JEDEC 11.60 8.00 PACKAGE MIN. NOM. MAX. -0.25 1.00 -11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 0.30 0.35 0.80 0.80 0.40 A2,A3,A4,A5,A6,A7,A8,A9 B2,B3,B4,B7,B8,B9,C2,C9,C10 D1,D10,E1,E10,F5,F6,G5,G6 H1,H10,J1,J10,K1,K2,K9,K10 L2,L3,L4,L7,L8,L9 M2,M3,M4,M5,M6,M7,M8,M9 0.40 1.40 -1.11 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE DIRECTION MATRIX SIZE DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALL NOTE DIMENSIONING TOLERANCING METHODS ASME Y14.5M-1994. DIMENSIONS MILLIMETERS. BALL POSITION DESIGNATION JESD 95-1, SPP-010. REPRESENTS SOLDER BALL GRID PITCH. SYMBOL "MD" BALL MATRIX SIZE DIRECTION. SYMBOL "ME" BALL MATRIX SIZE DIRECTION. NUMBER POPULTED SOLDER BALL POSITIONS MATRIX SIZE DIMENSION MEASURED MAXIMUM BALL DIAMETER PLANE PARALLEL DATUM MEASURED WITH RESPECT DATUMS DEFINE POSITION CENTER SOLDER BALL OUTER ROW. WHEN THERE NUMBER SOLDER BALLS OUTER 0.000. WHEN THERE EVEN NUMBER SOLDER BALLS OUTER ROW, INDICATES THEORETICAL CENTER DEPOPULATED BALLS.
SYMBOL
SD/SE
CORNER IDENTIFIED CHAMFER, LASER MARK, METALLIZED MARK INDENTION OTHER MEANS.
3159\38.14b
Am50DL9608G
2003
REVISION SUMMARY Revision (October 2002)
Initial release. Added "Note that SecSi Sector, autoselect, functions unavailable when [program/erase] operation progress." Common Flash Memory Interface (CFI) Changed wording last sentence third paragraph from, ".the autoselect mode." ".reading array data." Changed website address. Command Definitions Changed wording last sentence first paragraph from, ".resets device reading array data." ."may place device unknown state. reset command then required return device reading array data." Table Am29DL640G Command Definitions Product Selector Guide Removed speed options. Added speed option. Removed from Access. Special Package Handling Instructions Modified wording. Ordering Information Modified order numbers package markings reflect speed option. Pseudo SRAM Operating Characteristics Changed typical maximum Average Operating Current (ICC1s ICC2s). Changed maximum Standby Current (CMOS) Customer Lockable: SecSi Sector Programmed Protected factory. Added second bullet, SecSi sector-protect verify text figure SecSi Sector Flash Memory Region, Enter SecSi Sector/Exit SecSi Sector Command Sequence Added notes, "Note that function unlock bypass modes available when SecSi sector enabled." Byte/Word Program Command Sequence, Sector Erase Command Sequence, Chip Erase Command Sequence Changed first address unlock bypass reset command sequence from XXX. CMOS Compatible Added parameter table. Deleted IACC parameter from table. Changed maximums ICC3f, ICC4f, ICC5f from Added Note Pseudo SRAM Operating Characteristics Changed test conditions maximum added ISB2 parameter symbol. Figure Standby Current CMOS Added figure.
Revision (October 2002)
Flash Characteristics Added CMOS compatible table.
Revision (November 2002)
Distinctive Characteristics Added Pseudo SRAM access time. Changed power dissipation standby from maximum Changed wording from million write cycles million erase cycles.
Revision (January 2003)
Pseudo SRAM Characteristics Write Cycle table: Changed Physical Dimensions Deleted specification from table.
Revision (May 2003)
pSRAM Data Retention, Figure CE#1 Controlled Data Retention Mode, Figure CE2s Controlled Data Retention Mode Removed table figures from data sheet.
2003
Am50DL9608G
Pseudo SRAM Operating Characteristics Changed value Average operating current Standby current (CMOS)
Trademarks Copyright 2003 Advanced Micro Devices, Inc. rights reserved. AMD, logo, combinations thereof registered trademarks Advanced Micro Devices, Inc. ExpressFlash trademark Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
Am50DL9608G
2003
Sales Offices Representatives
North America
ALABAMA ARIZONA CALIFORNIA, Irvine Sunnyvale COLORADO CONNECTICUT FLORIDA, Clearwater Miami (Lakes) GEORGIA ILLINOIS, Chicago MASSACHUSETTS MICHIGAN MINNESOTA JERSEY, Chatham YORK NORTH CAROLINA OREGON PENNSYLVANIA SOUTH DAKOTA TEXAS, Austin Dallas Houston VIRGINIA
Representatives U.S. Canada
ARIZONA, Tempe Centaur CALIFORNIA, Calabasas Centaur Irvine Centaur Diego Centaur. Santa Clara Fourfront. CANADA, Burnaby, B.C. Davetek Marketing. Calgary, Alberta Davetek Marketing. Kanata, Ontario J-Squared Tech. Mississauga, Ontario J-Squared Tech. Laurent, Quebec J-Squared Tech. COLORADO, Golden Compass Marketing FLORIDA, Melbourne Marathon Technical Sales Lauderdale Marathon Technical Sales Orlando Marathon Technical Sales Petersburg Marathon Technical Sales GEORGIA, Duluth Quantum Marketing ILLINOIS, Skokie Industrial Reps, Inc. INDIANA, Kokomo IOWA, Cedar Rapids Lorenz Sales KANSAS, Lenexa Lorenz Sales MASSACHUSETTS, Burlington Synergy Associates MICHIGAN, Brighton MINNESOTA, Paul Cahill, Schmitz Cahill, Inc. MISSOURI, Louis Lorenz Sales JERSEY, Laurel Associates YORK, Buffalo Nycom, Inc. East Syracuse Nycom, Inc. Pittsford Nycom, Inc. Rockville Centre Associates NORTH CAROLINA, Raleigh Quantum Marketing OHIO, Middleburg Dolfuss Root Powell Dolfuss Root Vandalia Dolfuss Root Westerville Dolfuss Root OREGON, Lake Oswego Squared, Inc. UTAH, Murray Front Range Marketing VIRGINIA, Glen Burnie Coherent Solution, Inc. WASHINGTON, Kirkland Squared, Inc. WISCONSIN, Pewaukee Industrial Representatives
International
AUSTRALIA, North Ryde BELGIUM, Antwerpen BRAZIL, Paulo CHINA, Beijing Shanghai Shenzhen FINLAND, Helsinki FRANCE, Paris GERMANY, Homburg Munich HONG KONG, Causeway ITALY, Milan INDIA, Delhi JAPAN, Osaka Tokyo KOREA, Seoul RUSSIA, Moscow .TEL(7)-095-795-06-22 SWEDEN, Stockholm TAIWAN,Taipei UNITED KINGDOM, Frimley Haydock
Advanced Micro Devices reserves right make changes product without notice order improve design performance characteristics.The performance characteristics listed this document guaranteed specific tests, guard banding, design other practices common industry. specific testing details, contact your local sales representative.The company assumes responsibility circuits described herein. Advanced Micro Devices, Inc. rights reserved. AMD, Arrow logo combination thereof, trademarks Advanced Micro Devices, Inc. Other product names informational purposes only trademarks their respective companies.
Representatives Latin America
ARGENTINA, Capital Federal Argentina/WW Rep. .54-11)4373-0655 CHILE, Santiago LatinRep/WWRep. .(+562)264-0993 COLUMBIA, Bogota Dimser. MEXICO, Guadalajara LatinRep/WW Rep. Mexico City LatinRep/WW Rep. Monterrey LatinRep/WW Rep. PUERTO RICO, Boqueron Infitronics.
Place, P.O. 3453, Sunnyvale, 94088-3453 408-732-2400 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com
©2003 Advanced Micro Devices, Inc. 01/03 Printed

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