-XO\ IROORZLQJ GRFXPHQW VSHFLILHV 6SDQVLRQ PHPRU\ SURGXFWV WKDW RIIHUH

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

-XO\ IROORZLQJ GRFXPHQW VSHFLILHV 6SDQVLRQ PHPRU\ SURGXFWV WKDW RIIHUH

Datasheet Thumbnail

Top Searches for this datasheet

Am29DL400B
-XO\ IROORZLQJ GRFXPHQW VSHFLILHV 6SDQVLRQ PHPRU\ SURGXFWV WKDW RIIHUHG ERWK $GYDQFHG 0LFUR 'HYLFHV )XMLWVX $OWKRXJK GRFXPHQW PDUNHG ZLWK QDPH FRPSDQ\ WKDW RULJ LQDOO\ GHYHORSHG VSHFLILFDWLRQ WKHVH SURGXFWV ZLOO RIIHUHG FXVWRPHUV ERWK )XMLWVX
7KHUH FKDQJH WKLV GDWDVKHHW UHVXOW RIIHULQJ GHYLFH 6SDQVLRQ SURGXFW FKDQJHV WKDW KDYH EHHQ PDGH UHVXOW QRUPDO GDWDVKHHW LPSURYHPHQW QRWHG GRFXPHQW UHYLVLRQ VXPPDU\ ZKHUH VXSSRUWHG )XWXUH URXWLQH UHYLVLRQV ZLOO RFFXU ZKHQ DSSURSULDWH FKDQJHV ZLOO QRWHG UHYLVLRQ VXPPDU\
Continuity Ordering Part Numbers
)XMLWVX FRQWLQXH VXSSRUW H[LVWLQJ SDUW QXPEHUV EHJLQQLQJ ZLWK RUGHU WKHVH SURGXFWV SOHDVH RQO\ 2UGHULQJ 3DUW 1XPEHUV OLVWHG WKLV GRFXPHQW
More Information
3OHDVH FRQWDFW \RXU ORFDO )XMLWVX VDOHV RIILFH DGGLWLRQDO LQIRUPDWLRQ DERXW 6SDQVLRQ PHPRU\ VROXWLRQV
Srvv
6rqr
Am29DL400B
Megabit (512 8-Bit/256 16-Bit) CMOS Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
Simultaneous Read/Write operations Host system program erase bank, then immediately simultaneously read from other bank Zero latency between read write operations Read-while-erase Read-while-program Single power supply operation volt read write operations battery-powered applications Manufactured 0.32 process technology High performance Access times fast current consumption (typical values MHz) active read current active read-while-program read-whileerase current active program-while-erase-suspended current standby mode automatic sleep mode Standard chip enable access time applies transition from automatic sleep mode active mode Flexible sector architecture Kword, Kword, four Kword, Kword sectors word mode Kbyte, Kbyte, four Kbyte, Kbyte sectors byte mode combination sectors erased Supports full chip erase Unlock Bypass Program Command Reduces overall programming time when issuing multiple program command sequences Sector protection Hardware method locking sector prevent program erase operation within that sector Sectors locked in-system programming equipment Temporary Sector Unprotect feature allows code changes previously locked sectors bottom boot block configurations available Embedded Algorithms Embedded Erase algorithm automatically pre-programs erases sectors entire chip Embedded Program algorithm automatically programs verifies data specified address Minimum million program/erase cycles guaranteed sector 20-year data retention 125° Reliable operation life system Package options 44-pin 48-pin TSOP Compatible with JEDEC standards Pinout software compatible with single-power-supply flash standard Superior inadvertent write protection Data# Polling Toggle Bits Provides software method detecting program erase cycle completion Ready/Busy# output (RY/BY#) Hardware method detecting program erase cycle completion Erase Suspend/Erase Resume Suspends resumes erasing sectors allow reading programming other sectors need suspend sector other bank Hardware reset (RESET#) Hardware method resetting device reading array data
Publication# 21606 Rev: Amendment/+2 Issue Date: November 2000
This Data Sheet states AMD's current technical specifications regarding Products described herein. This Data Sheet revised subsequent versions modifications changes technical specifications.
GENERAL DESCRIPTION
Am29DL400B Mbit, volt-only flash memory device, organized 262,144 words 524,288 bytes. device offered 44-pin 48-pin TSOP packages. word-wide (x16) data appears DQ0-DQ15; byte-wide (x8) data appears DQ0-DQ7. This device requires only single volt supply perform read, program, erase operations. standard EPROM programmer also used program erase device. standard device offers access times allowing high-speed microprocessors operate without wait states. Standard control pins- chip enable (CE#), write enable (WE#), output enable (OE#)-control read write operations, avoid contention issues. device requires only single volt power supply both read write functions. Internally generated regulated voltages provided program erase operations. Device erasure occurs executing erase command sequence. This initiates Embedded Erase algorithm-an internal algorithm that automatically preprograms array already programmed) before executing erase operation. During erase, device automatically times erase pulse widths verifies proper cell margin. host system detect whether program erase operation complete observing RY/BY# pin, reading (Data# Polling) (toggle) status bits. After program erase cycle been completed, device automatically returns reading array data. sector erase architecture allows memory sectors erased reprogrammed without affecting data contents other sectors. device fully erased when shipped from factory. Hardware data protection measures include detector that automatically inhibits write operations during power transitions. hardware sector protection feature disables both program erase operations combination sectors memo programming equipment. Erase Suspend feature enables user erase hold period time read data from, program data sector within that bank that selected erasure. True background erase thus achieved. There need suspend erase operation read data other bank. hardware RESET# terminates operation progress resets internal state machine reading array data. RESET# tied system reset circuitry. system reset would thus also reset device reading array data, enabling system microprocessor read boot-up firmware from Flash memory. device offers power-saving features. When addresses have been stable specified amount time, device enters automatic sleep mode. system also place device into standby mode. Power consumption greatly reduced both these modes. AMD's Flash technology combines years Flash memory manufacturing experience produce leve effectiveness. device electrically erases bits within sector simultaneously Fowler-Nordheim tunneling. bytes programmed byte word time using electron injection.
Simultaneous Read/Write Operations with Zero Latency
Simultaneous Read/Write architecture provides simultaneous operation dividing memory space into banks. Bank contains boot/parameter sectors, Bank consists larger, code sectors uniform size. device improve overall system performance allowing host system program erase bank, then immediately simultaneously read from other bank, with zero latency. This releases system from waiting completion program erase operations.
Am29DL400B Features
device offers complete compatibility with JEDEC single-power-supply Flash command standard. Commands written command register using standard microprocessor write timings. Register contents serve input internal state machine that controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from other Flash EPROM devices. Device programming occurs executing program command sequence. This initiates Embedded Program algorithm-an internal algorithm that automatically times program pulse widths verifies proper cell margin. Unlock Bypass mode facilitates faster programming times requiring only write cycles program data instead four.
Am29DL400B
TABLE CONTENTS
Product Selector Guide Block Diagram Connection Diagrams Description. Logic Symbol Ordering Information Device Operations
Table Am29DL400B Device Operations
Reading Toggle Bits DQ6/DQ2
Figure Toggle Algorithm.
DQ5: Exceeded Timing Limits DQ3: Sector Erase Timer
Table Write Operation Status
Absolute Maximum Ratings
Figure Maximum Negative Overshoot Waveform Figure Maximum Positive Overshoot Waveform.
Word/Byte Configuration Requirements Reading Array Data Writing Commands/Command Sequences Simultaneous Read/Write Operations with Zero Latency Standby Mode Automatic Sleep Mode RESET#: Hardware Reset Output Disable Mode
Table Am29DL400BT Boot Sector Architecture Table Am29DL400BB Bottom Boot Sector Architecture
Operating Ranges Characteristics
Figure ICC1 Current Time (Showing Active Automatic Sleep Currents) Figure Typical ICC1 Frequency
Test Conditions
Figure Test Setup. Table Test Specifications
Switching Waveforms
Figure Input Waveforms Measurement Levels
Autoselect Mode
Table Am29DL400B Autoselect Codes (High Voltage Method)
Characteristics
Figure Read Operation Timings Figure Reset Timings Figure BYTE# Timings Read Operations. Figure BYTE# Timings Write Operations. Figure Program Operation Timings. Figure Chip/Sector Erase Operation Timings Figure Back-to-Back Read/Write Cycle Timings Figure Data# Polling Timings (During Embedded Algorithms). Figure Toggle Timings (During Embedded Algorithms). Figure DQ6. Figure Temporary Sector Unprotect Timing Diagram Figure Sector Protect/Unprotect Timing Diagram Figure Alternate Controlled Erase/Program Operation Timings.
Sector Protection/Unprotection Temporary Sector Unprotect
Figure Temporary Sector Unprotect Operation. Figure In-System Sector Protect/Unprotect Algorithms
Hardware Data Protection Write Inhibit Write Pulse "Glitch" Protection Logical Inhibit Power-Up Write Inhibit Command Definitions Reading Array Data Reset Command Autoselect Command Sequence Byte/Word Program Command Sequence Unlock Bypass Command Sequence
Figure Program Operation
Chip Erase Command Sequence Sector Erase Command Sequence Erase Suspend/Erase Resume Commands
Figure Erase Operation.
Command Definitions
Table Am29DL400B Command Definitions
Write Operation Status DQ7: Data# Polling
Figure Data# Polling Algorithm
RY/BY#: Ready/Busy# DQ6: Toggle DQ2: Toggle
Erase Programming Performance Latchup Characteristics TSOP Capacitance Data Retention. Physical Dimensions 048-48-Pin Standard TSOP TSR048-48-Pin Reverse TSOP 044-44-Pin Small Outline Revision Summary Revision (January 1998) Revision (March 1998) Revision (April 1998) Revision (June 1999) Revision (March 1999) Revision (December 1999) Revision (May 2000)
Am29DL400B
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options (Full Voltage Range: Access Time (ns) Access (ns) Access (ns) Am29DL400B -120
Note: Characteristics" full specifications.
BLOCK DIAGRAM
BYTE#
Y-Decoder
A0-A17
Upper Bank Address
Upper Bank
Latches Control Logic
RY/BY#
A0-A17 RESET# BYTE# DQ0-DQ15 A0-A17 STATE CONTROL COMMAND REGISTER Status
X-Decoder
DQ0-DQ15
A0-A17
DQ0-DQ15 Control DQ0-DQ15
X-Decoder
Lower Bank
A0-A17
Lower Bank Address
BYTE#
Am29DL400B
Latches Control Logic
Y-Decoder
CONNECTION DIAGRAMS
RESET# RY/BY# BYTE# DQ15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10
Standard TSOP
BYTE# DQ15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10
Reverse TSOP
RESET# RY/BY#
Am29DL400B
CONNECTION DIAGRAMS
RY/BY# DQ10 DQ11 RESET# BYTE# DQ15/A-1 DQ14 DQ13 DQ12
Am29DL400B
DESCRIPTION
A0-A17 Addresses DQ0-DQ14 Data Inputs/Outputs DQ15/A-1 DQ15 (Data Input/Output, word mode), (LSB Address Input, byte mode) BYTE# RESET# RY/BY# Chip Enable Output Enable Write Enable Selects 8-bit 16-bit mode Hardware Reset Pin, Active Ready/Busy Output volt-only single power supply (see Product Selector Guide speed options voltage supply tolerances) Device Ground Connected Internally
LOGIC SYMBOL
A0-A17 DQ0-DQ15 (A-1) RESET# BYTE# RY/BY#
Am29DL400B
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination following:
Am29DL400B
TEMPERATURE RANGE Commercial (0°C +70°C) Industrial (-40°C +85°C) Extended (-55°C +125°C) PACKAGE TYPE 48-Pin Thin Small Outline Package (TSOP) Standard Pinout 048) 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) 44-Pin Small Outline Package 044) SPEED OPTION Product Selector Guide Valid Combinations BOOT CODE SECTOR ARCHITECTURE sector Bottom sector DEVICE NUMBER/DESCRIPTION Am29DL400B
Megabit (512 8-Bit/256 16-Bit) CMOS Flash Memory
Volt-only Read, Program, Erase
Valid Combinations Valid Combinations AM29DL400BT-70 AM29DL400BB-70 AM29DL400BT-80 AM29DL400BB-80 AM29DL400BT-90 AM29DL400BB-90 AM29DL400BT-120 AM29DL400BB-120 Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am29DL400B
DEVICE OPERATIONS
This section describes requirements device operations, which initiated through internal command register. command register itself does occupy addressable memory location. register latch used store commands, along with address data information needed execute command. contents register serve inputs internal state machine. state machine outputs dictate function device. Table lists device operations, inputs control levels they require, resulting output. following subsections describe each these operations further detail.
Table
Am29DL400B Device Operations
DQ8-DQ15 Addresses (Note Sector Address, Sector Address, DQ0- DOUT High-Z High-Z High-Z BYTE# DOUT High-Z High-Z High-Z BYTE# DQ8-DQ14 High-Z, DQ15 High-Z High-Z High-Z
Operation Read Write Standby Output Disable Reset Sector Protect (Note
RESET#
Sector Unprotect (Note Temporary Sector Unprotect
High-Z
Legend: Logic VIL, Logic High VIH, 12.0 Don't Care, Address Data DOUT Data Notes: Addresses A17:A0 word mode (BYTE# VIH), A17:A-1 byte mode (BYTE# VIL). sector protect sector unprotect functions also implemented programming equipment. "Sector Protection/Unprotection" section.
Word/Byte Configuration
BYTE# controls whether device data pins operate byte word configuration. BYTE# logic `1', device word configuration, DQ0-15 active controlled BYTE# logic `0', device byte configuration, only data pins DQ0-DQ7 active controlled OE#. data pins DQ8-DQ14 tri-stated, DQ15 used input (A-1) address function.
internal state machine reading array data upon device power-up, after hardware reset. This ensures that spurious alteration memory content occurs during power transition. command necessary this mode obtain array data. Standard microprocessor read cycles that assert valid addresses device address inputs produce valid data device data outputs. Each bank remains enabled read access until command register contents altered. "Reading Array Data" more information. Refer Read-Only Operations table timing specifications Figure timing diagram. ICC1 Characteristics table represents active current specification reading array data.
Requirements Reading Array Data
read array data from outputs, system must drive pins VIL. power control selects device. output control gates array data output pins. should remain VIH. BYTE# determines whether device outputs array data words bytes.
Writing Commands/Command Sequences
write command command sequence (which includes programming data device erasing
Am29DL400B
sectors memory), system must drive VIL, VIH. program operations, BYTE# determines whether device accepts program data bytes words. Refer "Word/Byte Configuration" more information. device features Unlock Bypass mode facilitate faster programming. Once bank enters Unlock Bypass mode, only write cycles required program word byte, instead four. "Byte/Word Program Command Sequence" section details programming data device using sequences. erase operation erase sector, multiple sectors, entire device. Tables indicate address space that each sector occupies. device address space divided into banks: Bank contains boot/parameter sectors, Bank contains larger, code sectors uniform size. "bank address" address bits required uniquely select bank. Similarly, "sector address" address bits required uniquely select sector. system writes autoselect command sequence, device enters autoselect mode. system then read autoselect codes from internal register (which separate from memory array) DQ7-DQ0. Standard read cycle timings apply this mode. Refer Autoselect Mode Autoselect Command Sequence sections more information. ICC2 Characteristics table represents active current specification write mode. Characteristics section contains timing specification tables timing diagrams write operations.
(Note that this more restricted voltage range than VIH.) RESET# held VIH, within device will standby mode, standby current will greater. device requires standard access time (tCE) read access when device either these standby modes, before ready read data. device also enters standby mode when RESET# driven low. Refer next section, "RESET#: Hardware Reset Pin". device deselected during erasure programming, device draws active current until operation completed. ICC3 Characteristics table represents standby current specification.
Automatic Sleep Mode
automatic sleep mode minimizes Flash device energy consumption. device automatically enables this mode when addresses remain stable tACC automatic sleep mode independent CE#, WE#, control signals. Standard address access timings provide data when addresses changed. While sleep mode, output data latched always available system. Characteristics table represents automatic sleep mode current specification.
RESET#: Hardware Reset
RESET# provides hardware method resetting device reading array data. When RESET# driven least period tRP, device immediately terminates operation progress, tristates output pins, ignores read/ write commands duration RESET# pulse. device also resets internal state machine reading array data. operation that interrupted should reinitiated once device ready accept another command sequence, ensure data integrity. Current reduced duration RESET# pulse. When RESET# held VSS±0.3 device draws CMOS standby current (ICC4). RESET# held within VSS±0.3 standby current will greater. RESET# tied system reset circuitry. system reset would thus also reset Flash memory, enabling system read boot-up firmware from Flash memory. RESET# asserted during program erase operation, RY/BY# remains (busy) until internal reset operation complete, which requires time tREADY (during Embedded Algorithms). system thus monitor RY/BY# determine whether reset operation complete. RESET# asserted when program erase operation executing (RY/BY# "1"), reset operation completed
Simultaneous Read/Write Operations with Zero Latency
This device capable reading data from bank memory while programming erasing other bank memory. erase operation also suspended read from program another location within same bank (except sector being erased). Figure shows read write cycles initiated simultaneous operation with zero latency. ICC6 ICC7 Characteristics table represent current specifications read-while-program read-while-erase, respectively.
Standby Mode
When system reading writing device, place device standby mode. this mode, current consumption greatly reduced, outputs placed high impedance state, independent input. device enters CMOS standby mode when RESET# pins both held
Am29DL400B
within time tREADY (not during Embedded Algorithms). system read data after RESET# returns VIH. Refer Characteristics tables RESET# parameters Figure timing diagram.
Output Disable Mode
When input VIH, output from device disabled. output pins placed high impedance state.
Table Am29DL400BT Boot Sector Architecture
Sector Address Bank Address Bank Sector Bank Bank SA10 SA11 SA12 SA13 16/8 7C000h-7FFFFh 3E000h-3FFFFh 32/16 74000h-7BFFFh 3A000h-3DFFFh 70000h-71FFFh 72000h-73FFFh 38000h-38FFFh 39000h-39FFFh 6C000h-6DFFFh 6E000h-6FFFFh 36000h-36FFFh 37000h-37FFFh 32/16 64000h-6BFFFh 32000h-35FFFh 64/32 64/32 64/32 16/8 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-63FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-31FFFh Sector Size (Kbytes/ Kwords) 64/32 64/32 64/32
(x8) Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh
(x16) Address Range 00000h-07FFFh 08000h-0FFFFh 10000h-17FFFh
Note: address range A17:A-1 byte mode (BYTE# VIL). address range A17:A0 word mode (BYTE# VIH).
Am29DL400B
Table
Am29DL400BB Bottom Boot Sector Architecture
Sector Address Bank Address Bank Sector SA13 SA12 SA11 Bank SA10 Bank 16/8 00000h-03FFFh 00000h-01FFFh 32/16 04000h-0BFFFh 02000h-05FFFh 0E000h-0FFFFh 0C000h-0DFFFh 07000h-07FFFh 06000h-06FFFh 12000h-13FFFh 10000h-11FFFh 09000h-09FFFh 08000h-08FFFh 32/16 14000h-1BFFFh 0A000h-0DFFFh 64/32 64/32 64/32 16/8 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 1C000h-1FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 0E000h-0FFFFh
Sector Size (Kbytes/Kwords) 64/32 64/32 64/32
(x8) Address Range 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh
(x16) Address Range 38000h-3FFFFh 30000h-37FFFh 28000h-2FFFFh
Note: address range A17:A-1 byte mode (BYTE# VIL). address range A17:A0 word mode (BYTE# VIH).
Autoselect Mode
autoselect mode provides manufacturer device identification, sector protection verification, through identifier codes output DQ7-DQ0. This mode primarily intended programming equipment automatically match device programmed with corresponding programming algorithm. However, autoselect codes also accessed in-system through command register. When using programming equipment, autoselect mode requires (11.5 12.5 address Address pins must shown
Table addition, when verifying sector protection, sector address must appear appropriate highest order address bits (see Tables Table shows remaining address bits that don't care. When necessary bits have been required, programming equipment then read corresponding identifier code DQ7-DQ0. access autoselect codes in-system, host system issue autoselect command command register, shown Table This method does require VID. Refer Autoselect Command Sequence section more information.
Am29DL400B
Table
Am29DL400B Autoselect Codes (High Voltage Method)
(protected) (unprotected) DQ15
Description
Mode
Manufacturer Device Am29DL400B (Top Boot Block) Device Am29DL400B (Bottom Boot Block) Word Byte Word Byte
Sector Protection Verification
Note: Logic VIL, Logic High VIH, Bank Address, Sector Address, Don't care.
Sector Protection/Unprotection
hardware sector protection feature disables both program erase operations sector. hardware sector unprotection feature re-enables both program erase operations previously protected sectors. Sector protection/unprotection implemented methods. primary method requires RESET# only, implemented either in-system programming equipment. Figure shows algorithms Figure shows timing diagram. This method uses standard microprocessor cycle timing. sector unprotect, unprotected sectors must first protected prior first sector unprotect write cycle. alternate method intended only programming equipment requires address OE#. This method compatible with programmer routines written earlier volt-only flash devices. Publication number 22145 contains further details; contact representative request copy. device shipped with sectors unprotected. offers option programming protecting sectors factory prior shipping device through AMD's ExpressFlashService. Contact representative details. possible determine whether sector protected unprotected. Autoselect Mode section details.
SET# (11.5 12.5 During this mode, formerly protected sectors programmed erased selecting sector addresses. Once removed from RESET# pin, previously protected sectors protected again. Figure shows algorithm, Figure shows timing diagrams, this feature.
START
RESET# (Note Perform Erase Program Operations
RESET#
Temporary Sector Unprotect Completed (Note
Notes: protected sectors unprotected. previously protected sectors protected once again.
Temporary Sector Unprotect
This feature allows temporary unprotection previously protected sectors change data in-system. Sector Unprotect mode activated setting
Figure
Temporary Sector Unprotect Operation
Am29DL400B
START PLSCNT RESET# Wait Protect sectors: indicated portion sector protect algorithm must performed unprotected sectors prior issuing first sector unprotect address
START PLSCNT RESET# Wait
Temporary Sector Unprotect Mode
First Write Cycle 60h? sector address Sector Protect: Write sector address with Wait Verify Sector Protect: Write sector address with Read from sector address with
First Write Cycle 60h? sectors protected? first sector address Sector Unprotect: Write sector address with
Temporary Sector Unprotect Mode
Increment PLSCNT
Reset PLSCNT
Wait Verify Sector Unprotect: Write sector address with
PLSCNT Data 01h?
Increment PLSCNT
Read from sector address with next sector address
Device failed
Protect another sector? Remove from RESET#
PLSCNT 1000?
Data 00h?
Device failed Write reset command
Last sector verified?
Sector Protect Algorithm
Sector Protect complete
Sector Unprotect Algorithm
Remove from RESET#
Write reset command Sector Unprotect complete
Figure
In-System Sector Protect/Unprotect Algorithms
Am29DL400B
Hardware Data Protection
command sequence requirement unlock cycles programming erasing provides data protection against inadvertent writes (refer Table command definitions). addition, following hardware data protection measures prevent accidental erasure programming, which might otherwise caused spurious system level signals during power-up power-down transitions, from system noise. Write Inhibit When less than VLKO, device does accept write cycles. This protects data during power-up power-down. command register internal program/erase circuits disabled, device resets reading array data. Subsequent writes ignored until greater than VLKO. system must provide proper signals control pins
prevent unintentional writes when greater than VLKO. Write Pulse "Glitch" Protection Noise pulses less than (typical) OE#, initiate write cycle. Logical Inhibit Write cycles inhibited holding VIL, VIH. initiate write cycle, must logical zero while logical one. Power-Up Write Inhibit during power device does accept commands rising edge WE#. internal state machine automatically reset reading array data power-up.
COMMAND DEFINITIONS
Writing specific address data commands sequences into command register initiates device operations. Table defines valid register command sequences. Writing incorrect address data values writing them improper sequence resets device reading array data. addresses latched falling edge CE#, whichever happens later. data latched rising edge CE#, whichever happens first. Refer appropriate timing diagrams Characteristics section.
Reset Command
Writing reset command resets banks read erase-suspend-read mode. Address bits don't cares this command. reset command written between sequence cycles erase command sequence before erasing begins. This resets bank which system writing reading array data. Once erasure begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles program command sequence before programming begins. This resets bank which system writing reading array data. program command sequence written bank that Erase Suspend mode, writing reset command returns that bank erase-suspend-read mode. Once programming begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles autoselect command sequence. Once autoselect mode, reset command must written return reading array data. bank entered autoselect mode while Erase Suspend mode, writing reset command returns that bank erase-suspend-read mode. goes high during program erase operation, writing reset command returns banks reading array data erase-suspend-read mode that bank Erase Suspend).
Reading Array Data
device automatically reading array data after device power-up. commands required retrieve data. Each bank ready read array data after completing Embedded Program Embedded Erase algorithm. After device accepts Erase Suspend command, corresponding bank enters erase-suspendread mode, after which system read data from non-erase-suspended sector within same bank. After completing programming operation Erase Suspend mode, system once again read array data with same exception. Erase Suspend/Erase Resume Commands section more information. system must issue reset command return bank read erase-suspend-read) mode goes high during active program erase operation, bank autoselect mode. next section, Reset Command, more information. also Requirements Reading Array Data Device Operations section more information. "Read-Only Operations" table provides read parameters, Figure shows timing diagram.
Autoselect Command Sequence
autoselect command sequence allows host system access manufacturer devices codes,
Am29DL400B
determine whether sector protected. Table shows address data requirements. This method alternative that shown Table which intended PROM programmers requires address autoselect command sequence written address within bank that either read erase-suspend-read mode. autoselect command written while device actively programming erasing other bank. autoselect command sequence initiated first writing unlock cycles. This followed third write cycle that contains bank address autoselect command. addressed bank then enters autoselect mode. system read address within same bank number times without initiating another autoselect command sequence: read cycle address (BA)XX00h (where bank address) returns manufacturer code. read cycle address (BA)XX01h word mode (BA)XX02h byte mode) returns device code. read cycle address containing sector address (SA) within same bank, address A7-A0 word mode address A6-A-1 byte mode) returns sector protected, unprotected. Refer Tables valid sector addresses. system continue read array data from other bank while bank autoselect mode. exit autoselect mode, system must write reset command return both banks reading array data. bank enters autoselect mode while erase suspended, reset command returns that bank erase-suspend-read mode. subsequent Erase Resume command retur bank erase operation.
When Embedded Program algorithm complete, that bank then returns reading array data addresses longer latched. system determine status program operation using DQ7, DQ6, RY/BY#. Note that while Embedded Program operation progress, system read data from non-programming bank. Refer Write Operation Status section information these status bits. commands written device during Embedded Program Algorithm ignored. Note that hardware reset immediately terminates program operation. program command sequence should reinitiated once that bank returned reading array data, ensure data integrity. Programming allowed sequence across sector boundaries. cannot programmed from back "1." Attempting cause that bank cause status bits indicate operation successful. However, succeeding read will show that data still "0." Only erase operations convert "1." Unlock Bypass Command Sequence unlock bypass feature allows system program bytes words bank faster than using standard program command sequence. unlock bypass command sequence initiated first writing unlock cycles. This followed third write cycle containing unlock bypass command, 20h. That bank then enters unlock bypass mode. two-cycle unlock bypass program command sequence that required program this mode. first cycle this sequence contains unlock bypass program command, A0h; second cycle contains program address data. Additional data programmed same manner. This mode dispenses with initial unlock cycles required standard program command sequence, resulting faster total programming time. Table shows requirements command sequence. During unlock bypass mode, only Unlock Bypass Program Unlock Bypass Reset commands valid. exit unlock bypass mode, system must issue two-cycle unlock bypass reset command sequence. first cycle must contain bank address data 90h. second cycle need only contain data 00h. bank then returns reading array data. Figure illustrates algorithm program operation. Refer Erase Program Operations table Characteristics section parameters, Figure timing diagrams.
Byte/Word Program Command Sequence
system program device word byte, depending state BYTE# pin. Programming four-bus-cycle operation. program command sequence initiated writing unlock write cycles, followed program set-up command. program address data written next, which turn initiate Embedded Program algorithm. system required provide further controls timings. device automatically generates program pulses verifies programmed cell margin. Table shows address data requirements byte program command sequence.
Am29DL400B
START
occurs, chip erase command sequence should reinitiated once that bank returned reading array data, ensure data integrity. Figure illustrates algorithm erase operation. Refer Erase Program Operations tables Characteristics section parameters, Figure section timing diagrams.
Write Program Command Sequence
Sector Erase Command Sequence
Data Poll from System
Embedded Program algorithm progress
Verify Data?
Sector erase cycle operation. sector erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock cycles written, then followed address sector erased, sector erase command. Table shows address data requirements sector erase command sequence. device does require system preprogram prior erase. Embedded Erase algorithm automatically programs verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. After command sequence written, sector erase time-out occurs. During time-out period, additional sector addresses sector erase commands written. Loading sector erase buffer done sequence, number sectors from sector sectors. time between these additional cycles must less than otherwise last address command accepted, erasure begin. recommended that processor interrupts disabled during this time ensure commands accepted. interrupts re-enabled after last Sector Erase command written. command other than Sector Erase Erase Suspend during time-out period resets that bank reading array data. system must rewrite command sequence additional addresses commands. system monitor erasing bank) determine sector erase timer timed (See section DQ3: Sector Erase Timer.). time-out begins from rising edge final pulse command sequence. When Embedded Erase algorithm complete, bank returns reading array data addresses longer latched. Note that while Embedded Erase operation progress, system read data from non-erasing bank. system determine status erase operation reading DQ7, DQ6, DQ2, RY/BY# erasing bank. Refer Write Operation Status section information these status bits. Once sector erase operation begun, only Erase Suspend command valid. other commands ignored. However, note that hardware reset
Increment Address
Last Address?
Programming Completed
Note: Table program command sequence.
Figure
Program Operation
Chip Erase Command Sequence
Chip erase cycle operation. chip erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed chip erase command, which turn invokes Embedded Erase algorithm. device does require system preprogram prior erase. Embedded Erase algorithm automatically preprograms verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. Table shows address data requirements chip erase command sequence. When Embedded Erase algorithm complete, that bank returns reading array data addresses longer latched. system determine status erase operation using DQ7, DQ6, DQ2, RY/BY#. Refer Write Operation Status section information these status bits. commands written during chip erase operation ignored. However, note that hardware reset immediately terminates erase operation. that
Am29DL400B
mediately terminates erase operation. that occurs, sector erase command sequence should reinitiated once that bank returned reading array data, ensure data integrity. Figure illustrates algorithm erase operation. Refer Erase Program Operations tables Characteristics section parameters, Figure section timing diagrams.
erase-suspend-read mode, system also issue autoselect command sequence. Refer Autoselect Mode Autoselect Command Sequence sections details. resume sector erase operation, system must write Erase Resume command. bank address erase-suspended bank required when writing this command. Further writes Resume command ignored. Another Erase Suspend command written after chip resumed erasing.
Erase Suspend/Erase Resume Commands
Erase Suspend command, B0h, allows system interrupt sector erase operation then read data from, program data sector selected erasure. bank address required when writing this command. This command valid only during sector erase operation, including time-out period during sector erase command sequence. Erase Suspend command ignored written during chip erase operation Embedded Program algorithm. When Erase Suspend command written during sector erase operation, device requires maximum suspend erase operation. However, when Erase Suspend command written during sector erase time-out, device immediately terminates time-out period suspends erase operation. After erase operation been suspended, bank enters erase-suspend-read mode. system read data from program data sector selected erasure. (The device "erase suspends" sectors selected erasure.) Reading address within erase-suspended sectors produces status information DQ7-DQ0. system DQ7, together, determine sector actively erasing erase-suspended. Refer Write Operation Status section information these status bits. After erase-suspended program operation complete, bank returns erase-suspend-read mode. system determine status program operation using status bits, just standard Byte Program operation. Refer Write Operation Status section more information.
START
Write Erase Command Sequence (Notes
Data Poll Erasing Bank from System
Embedded Erase algorithm progress
Data FFh?
Erasure Completed
Notes: Table erase command sequence. section information sector erase timer.
Figure
Erase Operation
Am29DL400B
Command Definitions
Table
Command Sequence (Note Read (Note Reset (Note Manufacturer Word Byte Word Byte Word Byte Word Byte Program Unlock Bypass Word Byte Word Byte
Data programmed location Data latches rising edge pulse, whichever happens first. Address sector verified autoselect mode) erased. Address bits A17-A12 uniquely select sector. Address bank that being switched autoselect mode, bypass mode, being erased. Address bits A17-A16 select bank. data unprotected sector protected sector. Autoselect Command Sequence section more information. Unlock Bypass command required prior Unlock Bypass Program command. Unlock Bypass Reset command required return reading array data when bank unlock bypass mode. system read program non-erasing sectors, enter autoselect mode, when Erase Suspend mode. Erase Suspend command valid only during sector erase operation, requires bank address. Erase Resume command valid only during Erase Suspend mode, requires bank address.
Am29DL400B Command Definitions
Cycles (Notes 2-5) Second Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data
Cycles
First
Addr Data Addr Data
(BA)555 (BA)AAA (BA)555 (BA)AAA (BA)555 (BA)AAA (BA)555
(BA)X00 (BA)X01 (BA)X02 (BA)X01 (BA)X02 (SA)
220C 220F XX00 XX01
Autoselect (Note
Device Boot Block Device Bottom Boot Block Sector Protect Verify (Note
(BA)AAA
(SA)
Unlock Bypass Program (Note Unlock Bypass Reset (Note Chip Erase Sector Erase Erase Suspend (Note Erase Resume (Note
Legend: Don't care
Word Byte Word Byte
Address memory location read. Data read from location during read operation. Address memory location programmed. Addresses latch falling edge pulse, whichever happens later.
Notes: Table description operations. values hexadecimal. Except when reading array autoselect data, cycles write operations. Data bits DQ15-DQ8 don't cares unlock command cycles word mode. Address bits A17-A11 don't cares unlock command cycles, unless bank address (BA) required. unlock command cycles required when bank read mode. Reset command required return reading array data erase-suspend-read mode previously Erase Suspend) when bank autoselect mode, goes high (while bank providing status information). fourth cycle autoselect command sequence read cycle. system must provide bank address obtain manufacturer device information.
Am29DL400B
WRITE OPERATION STATUS
device provides several bits determine status write operation bank where program erase operation progress: DQ2, DQ3, DQ5, DQ6, DQ7, RY/BY#. Table following subsections describe function these bits. DQ7, RY/BY#, each offer method determining whether program erase operation complete progress. These three bits discussed first. invalid. Valid data DQ0-DQ7 will appear successive read cycles. Table shows outputs Data# Polling DQ7. Figure shows Data# Polling algorithm. Figure Characteristics section shows Data# Polling timing diagram.
DQ7: Data# Polling
Data# Polling bit, DQ7, indicates host system whether Embedded Program Erase algorithm progress completed, whether bank Erase Suspend. Data# Polling valid after rising edge final pulse command sequence. During Embedded Program algorithm, device outputs complement datum programmed DQ7. This status also applies programming during Erase Suspend. When Embedded Program algorithm complete, device outputs datum programmed DQ7. system must provide program address read valid status information DQ7. program address falls within protected sector, Data# Polling active approximately then that bank returns reading array data. During Embedded Erase algorithm, Data# Polling produces DQ7. When Embedded Erase algorithm complete, bank enters Erase Suspend mode, Data# Polling produces DQ7. system must provide address within sectors selected erasure read valid status information DQ7. After erase command sequence written, sectors selected erasing protected, Data# Polling active approximately then bank returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. However, system reads address within protected sector, status valid. Just prior completion Embedded Program Erase operation, change asynchronously with DQ0-DQ6 while Output Enable (OE#) asserted low. That device change from providing status information valid data DQ7. Depending when system samples output, read status valid data. Even device completed program erase operation valid data, data outputs DQ0-DQ6 still
START
Read DQ7-DQ0 Addr
Data?
Read DQ7-DQ0 Addr
Data?
FAIL PASS
Notes: Valid address programming. During sector erase operation, valid address sector address within sector being erased. During chip erase, valid address non-protected sector address. should rechecked even because change simultaneously with DQ5.
Figure
Data# Polling Algorithm
Am29DL400B
RY/BY#: Ready/Busy#
RY/BY# dedicated, open-drain output that indicates whether Embedded Algorithm progress complete. RY/BY# status valid after rising edge final pulse command sequence. Since RY/BY# open-drain output, several RY/BY# pins tied together parallel with pull-up resistor VCC. output (Busy), device actively erasing programming. (This includes programming Erase Suspend mode.) output high (Ready), device ready read array data, standby mode, banks erase-suspend-read mode. Table shows outputs RY/BY#.
Table shows outputs Toggle DQ6. Figure shows toggle algorithm. Figure Characteristics" section shows toggle timing diagrams. Figure shows differences between graphical form. also subsection DQ2: Toggle
DQ2: Toggle
"Toggle DQ2, when used with DQ6, indicates whether particular sector actively erasing (that Embedded Erase algorithm progress), whether that sector erase-suspended. Toggle valid after rising edge final pulse command sequence. toggles when system reads addresses within those sectors that have been selected erasure. (The system either control read cycles.) cannot distinguish whether sector actively erasing erase-suspended. DQ6, comparison, indicates whether device actively erasing, Erase Suspend, cannot distinguish which sectors selected erasure. Thus, both status bits required sector mode information. Refer Table compare outputs DQ6. Figure shows toggle algorithm flowchart form, section "DQ2: Toggle explains algorithm. also DQ6: Toggle subsection. Figure shows toggle timing diagram. Figure shows differences between graphical form.
DQ6: Toggle
Toggle indicates whether Embedded Program Erase algorithm progress complete, whether device entered Erase Suspend mode. Toggle read address within programming erasing bank, valid after rising edge final pulse command sequence (prior program erase operation), during sector erase time-out. During Embedded Program Erase algorithm operation, successive read cycles address within programming erasing bank cause toggle. system either control read cycles. When operation complete, stops toggling. After erase command sequence written, sectors selected erasing protected, toggles approximately then returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. system together determine whether sector actively erasing erasesuspended. When bank actively erasing (that Embedded Erase algorithm progress), toggles. When that bank enters Erase Suspend mode, stops toggling. However, system must also determine which sectors erasing erase-suspended. Alternatively, system (see subsection DQ7: Data# Polling). program address falls within protected sector, toggles approximately after program command sequence written, then returns reading array data. also toggles during erase-suspend-program mode, stops toggling once Embedded Program algorithm complete.
Reading Toggle Bits DQ6/DQ2
Refer Figure following discussion. Whenever system initially begins reading toggle status, must read DQ7-DQ0 least twice determine whether toggle toggling. Typically, system would note store value toggle after first read. After second read, system would compare value toggle with first. toggle toggling, device completed program erase operation. system read array data DQ7-DQ0 following read cycle. However, after initial read cycles, system determines that toggle still toggling, system also should note whether value high (see section DQ5). system should then determine again whether toggle toggling, since toggle have stopped toggling just went high. toggle longer toggling, device successfully completed program erase operation. still toggling, device completed operation successfully, system must write reset command return reading array data.
Am29DL400B
remaining scenario that system initially determines that toggle toggling gone high. system continue monitor toggle through successive read cycles, determining status described previous paragraph. Alternatively, choose perform other system tasks. this case, system must start beginning algorithm when returns determine status operation (top Figure
DQ5: Exceeded Timing Limits
indicates whether program erase time exceeded specified internal pulse count limit. Under these conditions produces "1," indicating that program erase cycle successfully completed. device output system tries program location that previously programmed "0." Only erase operation change back "1." Under this condition, device halts operation, when timing limit been exceeded, produces "1". Under both these conditions, system must write reset command return reading array data erase-suspend-read mode bank previously erase-suspend-program mode).
START
Read DQ7-DQ0
DQ3: Sector Erase Timer
Read DQ7-DQ0
Toggle Toggle?
After writing sector erase command sequence, system read determine whether erasure begun. (The sector erase timer does apply chip erase command.) additional sectors selected erasure, entire time-out also applies after each additional sector erase command. When time-out period complete, switches from "1". system guarantee time between additional sector erase commands less than need monitor DQ3. also Sector Erase Command Sequence section. After sector erase command written, system should read status (Data# Polling) (Toggle ensure that device accepted command sequence, then read DQ3. "1", Embedded Erase algorithm begun; further commands (except Erase Suspend) ignored until erase operation complete. "0", device will accept additional sector erase commands. ensure command been accepted, system software should check status prior following each subsequent sector erase command. high second status check, last command might have been accepted. Table shows status relative other status bits.
Read DQ7-DQ0 Twice
Toggle Toggle?
Program/Erase Operation Complete, Write Reset Command Program/Erase Operation Complete
Note: system should recheck toggle even because toggle stop toggling changes "1." subsections more information.
Figure
Toggle Algorithm
Am29DL400B
Table
Status Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Erase-SuspendRead Erase Suspended Sector Non-Erase Suspended Sector
Write Operation Status
(Note DQ7# Data DQ7# Toggle Toggle toggle Data Toggle (Note Data Data (Note toggle Toggle Toggle Data RY/BY#
Erase-Suspend-Program
Notes: switches when Embedded Program Embedded Erase operation exceeded maximum timing limits. Refer section more information. require valid address when reading status information. Refer appropriate subsection further details. When reading write operation status bits, system must always provide bank address where Embedded Algorithm progress. device outputs array data system addresses non-busy bank.
Am29DL400B
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages -65°C +150°C Ambient Temperature with Power Applied. -65°C +125°C Voltage with Respect Ground (Note -0.5 +4.0 OE#, RESET# (Note -0.5 +12.5 other pins (Note -0.5 VCC+0.5 Output Short Circuit Current (Note
Notes: Minimum voltage input pins -0.5 During voltage transitions, input pins undershoot -2.0 periods Maximum voltage input pins +0.5 Figure During voltage transitions, input pins overshoot +2.0 periods Figure Minimum input voltage pins OE#, RESET# -0.5 During voltage transitions, OE#, RESET# undershoot -2.0 periods Maximum input voltage +12.5 which overshoot 14.0 periods more than output shorted ground time. Duration short circuit should greater than second. Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this data sheet implied. Exposure device absolute maximum rating conditions extended periods affect device reliability.
+0.8 -0.5 -2.0
Figure Maximum Negative Overshoot Waveform
+2.0 +0.5
Figure Maximum Positive Overshoot Waveform
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) +70°C Industrial Devices Ambient Temperature (TA) -40°C +85°C Extended Devices Ambient Temperature (TA) -55°C +125°C Supply Voltages devices
Operating ranges define those limits between which functionality device guaranteed.
Am29DL400B
CHARACTERISTICS CMOS Compatible
Parameter Symbol ILIT Parameter Description Input Load Current Input Load Current Output Leakage Current Test Conditions VCC, max; 12.5 VOUT VCC, VIL, VIH, Byte Mode VIL, VIH, Word Mode Byte Word Byte Word -0.5 -2.0 -100 Lock-Out Voltage (Note 0.85 VCC-0.4 11.5 ±1.0 ±1.0 12.5 0.45 Unit
ICC1
Active Read Current (Notes
ICC2 ICC3 ICC4 ICC5 ICC6
Active Write Current (Notes Standby Current (Note Reset Current (Note Automatic Sleep Mode (Notes
VIL, VIH, VIL; CE#, RESET# RESET#
Active Read-WhileCE# VIL, Program Current (Notes Active Read-While-Erase Current (Notes Active Program-WhileErase-Suspended Current (Notes Input Voltage Input High Voltage Voltage Autoselect Temporary Sector Unprotect Output Voltage Output High Voltage VIL, VIL,
ICC7
ICC8 VOH1 VOH2 VLKO
Notes: current listed typically less than mA/MHz, with VIH. Maximum specifications tested with VCCmax. active while Embedded Erase Embedded Program progress. Automatic sleep mode enables power mode when addresses remain stable tACC Typical sleep mode current 100% tested.
Am29DL400B
CHARACTERISTICS Zero-Power Flash
Supply Current
1000 1500 2000 Time
Note: Addresses switching
2500
3000
3500
4000
Figure
ICC1 Current Time (Showing Active Automatic Sleep Currents)
Supply Current
Frequency
Note:
Figure
Typical ICC1 Frequency
Am29DL400B
TEST CONDITIONS
Table
Test Condition Device Under Test Input Rise Fall Times Input Pulse Levels Input timing measurement reference levels 0.0-3.0 Output Load Output Load Capacitance, (including capacitance) -70, others Unit
Test Specifications
gate
Note: Diodes IN3064 equivalent
Figure
Test Setup
Output timing measurement reference levels
Switching Waveforms
WAVEFORM INPUTS Steady Changing from Changing from Don't Care, Change Permitted Does Apply Changing, State Unknown Center Line High Impedance State (High OUTPUTS
Input
Measurement Level
Output
Figure
Input Waveforms Measurement Levels
Am29DL400B
CHARACTERISTICS Read-Only Operations
Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tACC Description Read Cycle Time (Note Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output High (Note Output Enable Output High (Note Output Hold Time From Addresses, OE#, Whichever Occurs First Read tOEH Output Enable Hold Time (Note Toggle Data# Polling CE#, Test Setup Speed Options -120 Unit
Notes: 100% tested. Figure Table test specifications.
Addresses tOEH HIGH Outputs RESET# RY/BY# Output Valid HIGH Addresses Stable tACC
Figure
Read Operation Timings
Am29DL400B
CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC tReady tReady tRPD Description RESET# (During Embedded Algorithms) Read Mode (See Note) RESET# (NOT During Embedded Algorithms) Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Standby Mode RY/BY# Recovery Time Speed Options Unit
Note: 100% tested.
RY/BY#
CE#, RESET# tReady
Reset Timings during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# CE#,
RESET#
Figure
Reset Timings
Am29DL400B
CHARACTERISTICS Word/Byte Configuration (BYTE#)
Parameter JEDEC tELFL/tELFH tFLQZ tFHQV Description BYTE# Switching High BYTE# Switching Output HIGH BYTE# Switching High Output Active Speed Options -120 Unit
BYTE# tELFL DQ0-DQ14
BYTE# Switching from word byte mode
Data Output (DQ0-DQ14)
Data Output (DQ0-DQ7) Address Input
DQ15/A-1
DQ15 Output tFLQZ tELFH
BYTE# BYTE# Switching from byte word mode
DQ0-DQ14
Data Output (DQ0-DQ7) Address Input tFHQV
Data Output (DQ0-DQ14) DQ15 Output
DQ15/A-1
Figure
BYTE# Timings Read Operations
falling edge last signal
BYTE#
tSET (tAS)
tHOLD (tAH)
Note: Refer Erase/Program Operations table specifications.
Figure
BYTE# Timings Write Operations
Am29DL400B
CHARACTERISTICS Erase Program Operations
Parameter JEDEC tAVAV tAVWL tASO tWLAX tAHT tDVWH tWHDX tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tWPH tSR/W tWHWH1 tWHWH2 tWHWH1 tWHWH2 tVCS tBUSY Description Write Cycle Time (Note Address Setup Time Address Setup Time during toggle polling Address Hold Time Address Hold Time From high during toggle polling Data Setup Time Data Hold Time Output Enable High during toggle polling Read Recovery Time Before Write (OE# High Low) Setup Time Hold Time Write Pulse Width Write Pulse Width High Zero Latency Between Read Write Operations Byte Programming Operation (Note Word Sector Erase Operation (Note Setup Time (Note Write Recovery Time from RY/BY# Program/Erase Valid RY/BY# Delay Speed Options -120 Unit
Notes: 100% tested. "Erase Programming Performance" section more information.
Am29DL400B
CHARACTERISTICS
Program Command Sequence (last cycles) Addresses 555h Data tBUSY RY/BY# Status DOUT tWPH tWHWH1 Read Status Data (last cycles)
tVCS
Notes: program address, program data, DOUT true data program address. Illustration shows device word mode.
Figure
Program Operation Timings
Addresses 2AAh
555h chip erase
tWPH
tWHWH2
Data
Chip Erase Progress Complete
tBUSY RY/BY# tVCS
Notes: sector address (for Sector Erase), Valid Address reading status data (see "Write Operation Status" Illustration shows device word mode.
Figure
Chip/Sector Erase Operation Timings
Am29DL400B
CHARACTERISTICS
Addresses
Valid
Valid
Valid
Valid
tACC tOEH tWPH Data
Valid
tCPH
tGHWL
Valid Valid Valid
tSR/W
Controlled Write Cycle Read Cycle Controlled Write Cycles
Figure
Back-to-Back Read/Write Cycle Timings
Addresses tACC tOEH
High
Complement
Complement
True
Valid Data
High
DQ0-DQ6 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: Valid address. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
Figure
Data# Polling Timings (During Embedded Algorithms)
Am29DL400B
CHARACTERISTICS
tAHT Addresses tAHT tASO tOEH tOEPH DQ6/DQ2 Valid Data
Valid Status
tCEPH
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: Valid address; required DQ6. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle
Figure
Toggle Timings (During Embedded Algorithms)
Enter Embedded Erasing
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
Note: toggles only when read address within erase-suspended sector. system toggle DQ6.
Figure
Am29DL400B
CHARACTERISTICS Temporary Sector Unprotect
Parameter JEDEC tVIDR tRSP tRRB Description Rise Fall Time (See Note) RESET# Setup Time Temporary Sector Unprotect RESET# Hold Time from RY/BY# High Temporary Sector Unprotect Speed Options Unit
Note: 100% tested.
RESET# tVIDR Program Erase Command Sequence tVIDR
tRSP RY/BY# tRRB
Figure
Temporary Sector Unprotect Timing Diagram
Am29DL400B
CHARACTERISTICS
RESET#
Valid* Sector Protect/Unprotect
Valid* Verify
Sector Protect: Sector Unprotect:
Valid*
Data
Status
sector protect, sector unprotect,
Figure
Sector Protect/Unprotect Timing Diagram
Am29DL400B
CHARACTERISTICS Alternate Controlled Erase/Program Operations
Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 tGHEL tCPH tWHWH1 tWHWH2 Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High Low) Setup Time Hold Time Pulse Width Pulse Width High Byte Programming Operation (Note Word Sector Erase Operation (Note Speed Options -120 Unit
Notes: 100% tested. "Erase Programming Performance" section more information.
Am29DL400B
CHARACTERISTICS
program erase program sector erase chip erase
Data# Polling
Addresses tGHEL tCPH Data
program erase program sector erase chip erase
tWHWH1
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: Figure indicates last cycles program erase operation. program address, sector address, program data, DQ7# complement data written device, DOUT data written device. Waveforms word mode.
Figure
Alternate Controlled Erase/Program Operation Timings
Am29DL400B
ERASE PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Program Time Word Program Time Chip Program Time (Note Byte Mode Word Mode (Note 13.5 (Note Unit Excludes system level overhead (Note Comments Excludes programming prior erasure (Note
Notes: Typical program erase times assume following conditions: 25°C, VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. Under worst case conditions 90°C, 1,000,000 cycles. typical chip programming time considerably less than maximum chip programming time listed, since most bytes program faster than maximum program times listed. pre-programming step Embedded Erase algorithm, bytes programmed before erasure. System-level overhead time required execute two- four-bus-cycle sequence program command. Table further information command definitions. device guaranteed minimum erase program cycle endurance 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Input voltage with respect pins except pins (including OE#, RESET#) Input voltage with respect pins Current -1.0 -1.0 -100 12.5 +100
Includes pins except VCC. Test conditions: time.
TSOP CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time 125°C Years Test Conditions 150°C Unit Years
Am29DL400B
PHYSICAL DIMENSIONS* 048-48-Pin Standard TSOP
10/99
reference only. ANSI standard Basic Space Centering
Am29DL400B
PHYSICAL DIMENSIONS (continued) TSR048-48-Pin Reverse TSOP
10/99
reference only. ANSI standard Basic Space Centering.
Am29DL400B
PHYSICAL DIMENSIONS (continued) 044-44-Pin Small Outline
10/99
Am29DL400B
REVISION SUMMARY Revision (January 1998)
Initial release. Alternate Controlled Erase/Program Operations Corrected note references tWHWH1, tWHWH2 Erase Programming Performance Note changed worst case endurance million cycles.
Revision (March 1998)
Expanded data sheet from Advance Information Preliminary version.
Revision (April 1998)
Global Changed -70R speed option -70. Figure In-system Sector Protect/Unprotect Algorithm Added "PSLSCNT=1" sector protect algorithm. Reset Command Deleted last paragraph; applies only hardware reset. DQ6: Toggle First second para., clarified that toggle read address within programming erasing bank," "any address." Fourth para., clarified "device" "bank" Operating Ranges Deleted reference regulated voltage range Characteristics Added Note reference ICC6 ICC7. Erase Program Operations Corrected note references tWHWH1, tWHWH2, tVCS Temporary Sector Unprotect Added note reference tVIDR. Figure Sector Protect/Unprotect Timing Diagram Updated figure correct address waveform-valid address required first cycle.
Revision (June 1999)
Distinctive Characterisitics Added Year data retention 125° bullet. Ordering Information Corrected TSOP description 48-pin.
Revision (March 1999)
Characteristics, Read-only Operations table Corrected tRC, tACC, speed option
Revision (December 1999)
Characteristics-Figure Program Operations Timing Figure Chip/Sector Erase Operations Deleted tGHWL changed waveform start high. Physical Dimensions Replaced figures with more detailed illustrations.
Revision (May 2000)
Ordering Information
Optional processing: Deleted burn-in option
Characteristics-Read-Only Operations Changed speeds.
Revision (November 2000)
Added table contents.
Trademarks
Copyright 2000 Advanced Micro Devices, Inc. rights reserved. AMD, logo, combinations thereof registered trademarks Advanced Micro Devices, Inc. ExpressFlash trademark Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
Am29DL400B

-XO\ IROORZLQJ GRFXPHQW VSHFLILHV 6SDQVLRQ PHPRU\ SURGXFWV WKDW RIIHUH

Top Searches for this datasheet

Other recent searches