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Publication Number 26493 Revision
Amendment Issue Date 2002
ADVANCE INFORMATION
Am29DS32xG
Megabit 8-Bit/2 16-Bit) CMOS Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES Simultaneous Read/Write operations Data continuously read from bank while executing erase/program functions other bank Zero latency between read write operations Multiple bank architectures Three devices available with different bank sizes (refer Table 256-byte SecSi (Secured Silicon) Sector Factory locked identifiable: bytes available secure, random factory Electronic Serial Number; verifiable factory locked through autoselect function. ExpressFlash option allows entire sector available factory-secured data Customer lockable: time programmable. Once locked, data cannot changed. Zero Power Operation Sophisticated power management circuits reduce power consumed during inactive periods nearly zero Package options 48-ball FBGA 48-pin TSOP bottom boot block Manufactured 0.17 process technology Compatible with JEDEC standards Pinout software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS High performance Access time fast Program time: µs/word typical utilizing Accelerate function Ultra power consumption (typical values) active read current active read current standby automatic sleep mode Minimum million write cycles guaranteed sector year data retention 125°C Reliable operation life system SOFTWARE FEATURES Data Management Software (DMS) AMD-supplied software manages data programming, enabling EEPROM emulation Eases historical sector erase flash limitations Supports Common Flash Memory Interface (CFI) Erase Suspend/Erase Resume Suspends erase operations allow programming same bank Data# Polling Toggle Bits Provides software method detecting status program erase cycles Unlock Bypass Program command Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES combination sectors erased Ready/Busy# output (RY/BY#) Hardware method detecting program erase cycle completion Hardware reset (RESET#) Hardware method resetting internal state machine read mode WP#/ACC input Write protect (WP#) function allows protection outermost boot sectors, regardless sector protect status Acceleration (ACC) function accelerates program timing Sector protection Hardware method locking sector, either in-system using programming equipment, prevent program erase operation within that sector Temporary Sector Unprotect allows changing data protected sectors in-system
This document contains information product under development Advanced Micro Devices. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice.
Publication# 26493 Rev: Issue Date: 2002
Refer AMD's Website (www.amd.com) latest information.
GENERAL DESCRIPTION
Am29DS32xG family consists megabit, volt-only flas memory ices, ganiz 2,097,152 words bits each 4,194,304 bytes bits each. Word mode data appears DQ15-DQ0; byte mode data appears DQ7-DQ0. device designed programmed in-system with standard volt supply, also programmed standard EPROM programmers. devices available with access time speed option standard voltage range also available. Contact representative more information.) devices offered 48-pin TSOP 48-ball FBGA packages. Standard control pins-chip enable (CE#), write enable (WE#), output enable (OE#)-control normal read write operations, avoid contention issues. devices requires only single volt power supply both read write functions. Internally generated regulated voltages provided program erase operations. (Electronic Serial Number), customer code (programmed through AMD's ExpressFlash service), both. (Data Management Software) allows systems easily take advantage advanced architecture simultaneous read/write product line allowing removal EEPROM devices. will also allow system software simplified, will perform functions necessary modify data file structures, opposed single-byte modifications. write update particular piece data phone number configuration data, example), user only needs state which piece data updated, where updated data located system. This user-written software must keep track data location, status, logical physical translation data onto Flash memory device memory devices), more. Using DMS, user-written software does need interface with Flash memory directly. Instead, user's software accesses Flash memory calling only functions. provides this software simplify system design software integration efforts. device offers complete compatibility with JEDEC single-power-supply Flash command standard. Commands written command register using standard microprocessor write timings. Reading data device similar reading from other Flash EPROM devices. host system detect whether program erase operation complete using device status bits: RY/BY# pin, (Data# Polling) DQ6/DQ2 (toggle bits). After program erase cycle been completed, device automatically returns read mode. sector erase architecture allows memory sectors erased reprogrammed without affecting data contents other sectors. device fully erased when shipped from factory. Hardware data protection measures include detector that automatically inhibits write operations during power transitions. hardware sector protection feature disables both program erase operations combination sectors memory. This achieved in-system programming equipment. device offers power-saving features. When addresses have been stable specified amount time, device enters automatic sleep mode. system also place device into standby mode. Power consumption greatly reduced both modes.
Simultaneous Read/Write Operations with Zero Latency
Simultaneous Read/Write architecture provides simultaneous operation dividing memory space into banks. device improve overall system performance allowing host system program erase bank, then immediately simultaneously read from other bank, with zero latency. This releases system from waiting completion program erase operations. Am29DS32xG device family uses multiple bank architectures provide flexibility different applications. Three devices available with following bank sizes:
Device DS322 DS323 DS324 Bank Bank
Am29DS32xG Features
SecSi(Secured Silicon) Sector extra sector capable being permanently locked customers. SecSi Indicator (DQ7) permanently part factory locked, customer lockable. This way, customer lockable parts never used replace factory locked part. Current version device bytes, which differs from previous versions this device. Factory locked parts provide several options. SecSi Sector store secure, random byte
Am29DS32xG
2002
TABLE CONTENTS
Product Selector Guide Block Diagram Connection Diagrams Special Handling Instructions FBGA Package Description Logic Symbol Ordering Information Device Operations
Table Device Operations
Unlock Bypass Command Sequence
Figure Program Operation
Chip Erase Command Sequence Sector Erase Command Sequence Erase Suspend/Erase Resume Commands
Figure Erase Operation Table Command Definitions
Write Operation Status DQ7: Data# Polling
Figure Data# Polling Algorithm
Word/Byte Configuration Requirements Reading Array Data Writing Commands/Command Sequences Accelerated Program Operation Autoselect Functions Simultaneous Read/Write Operations with Zero Latency Standby Mode Automatic Sleep Mode RESET#: Hardware Reset Output Disable Mode
Table Device Bank Divisions Table Boot Sector Addresses Table Boot SecSiSector Addresses Table Bottom Boot Sector Addresses Table Bottom Boot SecSiSector Addresses
RY/BY#: Ready/Busy# DQ6: Toggle
Figure Toggle Algorithm
DQ2: Toggle Reading Toggle Bits DQ6/DQ2 DQ5: Exceeded Timing Limits DQ3: Sector Erase Timer
Table Write Operation Status
Absolute Maximum Ratings
Figure Maximum Negative Overshoot Waveform Figure Maximum Positive Overshoot Waveform
Characteristics
Figure ICC1 Current Time (Showing Active Automatic Sleep Currents). Figure Typical ICC1 Frequency.
Autoselect Mode
Table Autoselect Codes, (High Voltage Method)
Test Conditions
Figure Test Setup Figure Input Waveforms Measurement Levels
Sector/Sector Block Protection Unprotection
Table Boot Sector/Sector Block Addresses Protection/Unprotection Table Bottom Boot Sector/Sector Block Addresses Protection/Unprotection
Characteristics
Figure Read Operation Timings. Figure Reset Timings.
Word/Byte Configuration (BYTE#)
Figure BYTE# Timings Read Operations Figure BYTE# Timings Write Operations
Write Protect (WP#) Temporary Sector Unprotect
Figure Temporary Sector Unprotect Operation. Figure In-System Sector Protection/ Sector Unprotection Algorithms
Erase Program Operations
Figure Program Operation Timings Figure Accelerated Program Timing Diagram Figure Chip/Sector Erase Operation Timings Figure Back-to-back Read/Write Cycle Timings Figure Data# Polling Timings (During Embedded Algorithms) Figure Toggle Timings (During Embedded Algorithms) Figure
SecSi(Secured Silicon) Sector Flash Memory Region Factory Locked: SecSi Sector Programmed Protected Factory Customer Lockable: SecSi Sector Programmed Protected Factory Hardware Data Protection Write Inhibit Write Pulse "Glitch" Protection Logical Inhibit Power-Up Write Inhibit
Temporary Sector Unprotect
Figure Temporary Sector Unprotect Timing Diagram Figure Sector/Sector Block Protect Unprotect Timing Diagram
Alternate Controlled Erase Program Operations
Figure Alternate Controlled Write (Erase/Program) Operation Timings
Common Flash Memory Interface (CFI)
Table Query Identification String Table System Interface String. Table Device Geometry Definition Table Primary Vendor-Specific Extended Query
Command Definitions Reading Array Data Reset Command Autoselect Command Sequence Enter SecSiSector/Exit SecSi Sector Command Sequence Byte/Word Program Command Sequence
Erase Programming Performance Latchup Characteristics TSOP Capacitance Data Retention. Physical Dimensions FBD048-Fine-Pitch Ball Grid Array, 048-Thin Small Outline Package Revision Summary Revision (May 2002)
2002
Am29DS32xG
PRODUCT SELECTOR GUIDE
Part Number Speed Rating Standard Voltage Range: 1.8-2.2 Am29DS32xG
Access Time (ns) Access (ns) Access (ns)
BLOCK DIAGRAM
BYTE#
Y-Decoder
A20-A0
Upper Bank Address
Upper Bank
Latches Control Logic
RY/BY#
A20-A0 RESET# BYTE# WP#/ACC DQ15-DQ0 A20-A0 STATE CONTROL COMMAND REGISTER
X-Decoder
Status DQ15-DQ0 Control DQ15-DQ0
X-Decoder
Lower Bank
A20-A0
Lower Bank Address
BYTE#
Am29DS32xG
Latches Control Logic
Y-Decoder
DQ15-DQ0
A20-A0
2002
CONNECTION DIAGRAMS
RESET# WP#/ACC RY/BY# BYTE# DQ15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10
48-Pin Standard TSOP
48-Ball FBGA View, Balls Facing Down
RESET#
BYTE# DQ15/A-1 DQ14 DQ12 DQ10 DQ13 DQ11
RY/BY# WP#/ACC
Special Handling Instructions FBGA Package
Special handling required Flash Memory products FBGA packages.
Flash memory devices FBGA packages damaged exposed ultrasonic cleaning methods. package and/or data integrity compromised package body exposed temperatures above 150°C prolonged periods time.
2002
Am29DS32xG
DESCRIPTION
A20-A0 Addresses DQ14-DQ0 Data Inputs/Outputs DQ15/A-1 DQ15 (Data Input/Output, word mode), (LSB Address Input, byte mode) Chip Enable Output Enable Write Enable Hardware Write Protect/ Acceleration Hardware Reset Pin, Active Selects 8-bit 16-bit mode Ready/Busy Output volt-only single power supply (see Product Selector Guide speed options voltage supply tolerances) Device Ground Connected Internally
LOGIC SYMBOL
A20-A0 DQ15-DQ0 (A-1) WP#/ACC RESET# BYTE# RY/BY#
WP#/ACC RESET# BYTE# RY/BY#
Am29DS32xG
2002
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination following: Am29DS32xG
OPTIONAL PROCESSING Blank Standard Processing 16-byte devices (Contact representative more information) TEMPERATURE RANGE Industrial (-40°C +85°C) Extended (-55°C +125°C) PACKAGE TYPE 48-Pin Thin Small Outline Package (TSOP) Standard Pinout 048) 48-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 pitch, package (FBD048) SPEED OPTION Product Selector Guide Valid Combinations BOOT CODE SECTOR ARCHITECTURE sector Bottom sector DEVICE NUMBER/DESCRIPTION Am29DS32xG Megabit 8-Bit/2 16-Bit) CMOS Flash Memory Volt-only Read, Program, Erase
Valid Combinations TSOP Packages AM29DS322GT70, AM29DS322GB70 AM29DS323GT70, AM29DS323GB70 AM29DS324GT70, AM29DS324GB70 AM29DS322GT90, AM29DS322GB90 AM29DS323GT90, AM29DS323GB90 AM29DS324GT90R, AM29DS324GB90R AM29DS322GT120, AM29DS322GB120 AM29DS323GT120, AM29DS323GB120 AM29DS324GT120, AM29DS324GB120 Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Valid Combinations FBGA Packages Order Number AM29DS322GT70, AM29DS322GB70 AM29DS323GT70, AM29DS323GB70 AM29DS324GT70, AM29DS324GB70 AM29DS322GT90, AM29DS322GB90 AM29DS323GT90, AM29DS323GB90 AM29DS324GT90, AM29DS324GB90 AM29DS322GT120, AM29DS322GB120 AM29DS323GT120, AM29DS323GB120 AM29DS324GT120, AM29DS324GB120 WMI, WMIN Package Marking S322GT70U S322GB70U S323GT70U S323GB70U S324GT70U S324GB70U S322GT90U S322GB90U S323GT90U S323GB90U S324GT90U S324GB90U S322GT12U S322GB12U S323GT12U S323GB12U S324GT12U S324GB12U
2002
Am29DS32xG
DEVICE OPERATIONS
This section describes requirements device operations, which initiated through internal command register. command register itself does occupy addressable memory location. register latch used store commands, along with address data information needed execute command. contents Table register serve inputs internal state machine. state machine outputs dictate function device. Table lists device operations, inputs control levels they require, resulting output. following subsections describe each these operations further detail.
Device Operations
DQ15-DQ8
Operation Read Write Standby Output Disable Reset Sector Protect (Note Sector Unprotect (Note Temporary Sector Unprotect
RESET#
WP#/ACC (Note (Note (Note
Addresses (Note
BYTE# DOUT High-Z High-Z High-Z
BYTE# DQ14-DQ8 High-Z, DQ15 High-Z High-Z High-Z High-Z
DQ7- DOUT High-Z High-Z High-Z
Legend: Logic VIL, Logic High VIH, 9.0-11.0 Don't Care, Sector Address, Address Data DOUT Data Notes: Addresses A20:A0 word mode (BYTE# VIH), A20:A-1 byte mode (BYTE# VIL). sector protect sector unprotect functions also implemented programming equipment. "Sector/Sector Block Protection Unprotection" section. WP#/ACC VIL, outermost boot sectors remain protected. WP#/ACC VIH, outermost boot sector protection depends whether they were last protected unprotected using method described "Sector/Sector Block Protection Unprotection". WP#/ACC VHH, sectors will unprotected.
Word/Byte Configuration
BYTE# controls whether device data pins operate byte word configuration. BYTE# logic `1', device word configuration, DQ15-DQ0 active controlled OE#. BYTE# logic `0', device byte configuration, only data pins DQ7-DQ0 active controlled OE#. data pins DQ14-DQ8 tri-stated, DQ15 used input (A-1) address function.
Requirements Reading Array Data
read array data from outputs, system must drive pins VIL. power control selects device. output control gates array data output pins. should remain BYTE# determines whether device outputs array data words bytes. internal state machine reading array data upon device power-up, after hardware reset. This ensures that spurious alteration memory content occurs during power transition. command necessary this mode obtain array data. Standard microprocessor read cycles that assert valid
Am29DS32xG
2002
operation. Note that WP#/ACC must operations other than accelerated programming, device damage result. addition, WP#/ACC must left floating unconnected; inconsistent behavior device result. Autoselect Functions system writes autoselect command sequence, device enters autoselect mode. system then read autoselect codes from internal register (which separate from memory array) DQ7-DQ0. Standard read cycle timings apply this mode. Refer Autoselect Mode Autoselect Command Sequence sections more information.
addresses device address inputs produce valid data device data outputs. Each bank remains enabled read access until command register contents altered. "Requirements Reading Array Data" more information. Refer Read-Only Operations table timing specifications Figure timing diagram. ICC1 Characteristics table represents active current specification reading array data.
Writing Commands/Command Sequences
write command command sequence (which includes programming data device erasing sectors memory), system must drive VIL, VIH. program operations, BYTE# determines whether device accepts program data bytes words. Refer "Word/Byte Configuration" more information. device features Unlock Bypass mode facilitate faster programming. Once bank enters Unlock Bypass mode, only write cycles required program word byte, instead four. "Word/Byte Configuration" section details programming data device using both standard Unlock Bypass command sequences. erase operation erase sector, multiple sectors, entire device. Tables indicate address space that each sector occupies. device address space divided into banks: Bank contains boot/parameter sectors, Bank contains larger, code sectors uniform size. "bank address" address bits required uniquely select bank. Similarly, "sector address" address bits required uniquely select sector. ICC2 Characteristics table represents active current specification write mode. Characteristics section contains timing specification tables timing diagrams write operations. Accelerated Program Operation device offers accelerated program operations through function. This functions provided WP#/ACC pin. This function primarily intended allow faster manufacturing throughput factory. system asserts this pin, device automatically enters aforementioned Unlock Bypass mode, temporarily unprotects protected sectors, uses higher voltage reduce time required program operations. system would two-cycle program command sequence required Unlock Bypass mode. Removing from WP#/ACC returns device norMay 2002
Simultaneous Read/Write Operations with Zero Latency
This device capable reading data from bank memory while programming erasing other bank memory. erase operation also suspended read from program another location within same bank (except sector being erased). Figure shows read write cycles initiated simultaneous operation with zero latency. ICC6 ICC7 Characteristics table represent current specifications read-while-program read-while-erase, respectively.
Standby Mode
When system reading writing device, place device standby mode. this mode, current consumption greatly reduced, outputs placed high impedance state, independent input. device enters CMOS standby mode when RESET# pins both held (Note that this more restricted voltage range than VIH.) RESET# held VIH, within device will standby mode, standby current will greater. device requires standard access time read access when device either these standby modes, before ready read data. device deselected during erasure programming, device draws active current until operation completed. Characteristics table represents standby current specification.
Automatic Sleep Mode
automatic sleep mode minimizes Flash device energy consumption. device automatically enables this mode when addresses remain stable tACC automatic sleep mode independent CE#, WE#, control signals. Standard
Am29DS32xG
RESET# tied system reset circuitry. system reset would thus also reset Flash memory, enabling system read boot-up firmware from Flash memory. RESET# asserted during program erase operation, RY/BY# remains (busy) until internal reset operation complete, which requires time READY (during Embedded Algorithms). system thus monitor RY/BY# determine whether reset operation complete. RESET# asserted when program erase operation executing (RY/BY# "1"), reset operation completed within time tREADY (not during Embedded Algorithms). system read data after RESET# returns VIH. Characteristics table represents reset current. Also refer Characteristics tables RESET# timing parameters Figure timing diagram.
dress access timings provide data when addresses changed. While sleep mode, output data latched always available system. Characteristics table represents automatic sleep mode current specification.
RESET#: Hardware Reset
RESET# provides hardware method resetting device reading array data. When RESET# driven least period tRP, device immediately terminates operation progress, tristates output pins, ignores read/write commands duration RESET# pulse. device also resets internal state machine reading array data. operation that interrupted should reinitiated once device ready accept another command sequence, ensure data integrity. Current reduced duration RESET# pulse. When RESET# held VSS±0.3 device draws CMOS standby current (ICC4). RESET# held within VSS±0.3 standby current will greater.
Output Disable Mode
When input VIH, output from device disabled. output pins placed high impedance state.
Table Device Bank Divisions
Device Part Number Am29DS322G Am29DS323G Am29DS324G Bank Megabits Mbit Mbit Mbit Sector Sizes Eight Kbyte/4 Kword, seven Kbyte/32 Kword Eight Kbyte/4 Kword, fifteen Kbyte/32 Kword Eight Kbyte/4 Kword, thrity-one Kbyte/32 Kword Megabits Mbit Mbit Mbit Bank Sector Sizes Fifty-six Kbyte/32 Kword Forty-eight Kbyte/32 Kword Thirty-two Kbyte/32 Kword
Am29DS32xG
2002
Table Boot Sector Addresses
Am29DS324GT Am29DS323GT Am29DS322GT
Sector
Sector Address A20-A12
Sector Size (Kbytes/Kwords)
(x8) Address Range
(x16) Address Range
SA10 SA11 SA12 SA13 SA14 Bank SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 Bank Bank SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
Bank
000000xxx 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh
000000h-07FFFh 008000h-0FFFFh 010000h-17FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh
SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47
2002
Am29DS32xG
Table Boot Sector Addresses (Continued)
Am29DS324GT Am29DS323GT Am29DS322GT
Sector
Sector Address A20-A12
Sector Size (Kbytes/Kwords)
(x8) Address Range
(x16) Address Range
SA48 SA49 SA50 Bank SA51 SA52 SA53 SA54 SA55 SA56 SA57 Bank Bank SA58 SA59 SA60 SA61 Bank SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
110000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3F1FFFh 3F2000h-3F3FFFh 3F4000h-3F5FFFh 3F6000h-3F7FFFh 3F8000h-3F9FFFh 3FA000h-3FBFFFh 3FC000h-3FDFFFh 3FE000h-3FFFFFh
180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F8FFFh 1F9000h-1F9FFFh 1FA000h-1FAFFFh 1FB000h-1FBFFFh 1FC000h-1FCFFFh 1FD000h-1FDFFFh 1FE000h-1FEFFFh 1FF000h-1FFFFFh
Note: address range A20:A-1 byte mode (BYTE#=VIL) A20:A0 word mode (BYTE#=VIH). bank address bits A20-A18 Am29DS322, Am29DS323, Am29DS324.
Table
Device Am29DS32xGT
Boot SecSiSector Addresses
Sector Size (Bytes/Words) 256/128 (x8) Address Range 3FE000h-3FE0FFh (x16) Address Range 1FF000h-1FF07Fh
Sector Address A20-A12 111111xxx
Am29DS32xG
2002
Table
Am29DS324GB Am29DS323GB Am29DS322GB
Bottom Boot Sector Addresses
Sector
Sector Address A20-A12
Sector Size (Kbytes/Kwords)
(x8) Address Range
(x16) Address Range
Bank Bank SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 Bank SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 Bank SA30 SA31 SA32 SA33 Bank SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41
Bank
000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh
000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh
SA42 SA43 SA44 SA45 SA46 SA47
2002
Am29DS32xG
Table
Am29DS324GB Am29DS323GB Am29DS322GB
Bottom Boot Sector Addresses (Continued)
Sector
Sector Address A20-A12
Sector Size (Kbytes/Kwords)
(x8) Address Range
(x16) Address Range
SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 Bank Bank Bank SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 111000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111xxx
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh
148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh
Note: address range A20:A-1 byte mode (BYTE#=VIL) A20:A0 word mode (BYTE#=VIH). bank address bits A20-A18 Am29DS322, Am29DS323, Am29DS324.
Table
Device Am29DS32xGB
Bottom Boot SecSiSector Addresses
Sector Size (Bytes/Words) 256/128 (x8) Address Range 000000h-0000FFh (x16) Address Range 00000h-00007Fh
Sector Address A20-A12 000000xxx
Am29DS32xG
2002
tion, when verifying sector protection, sector address must appear appropriate highest order address bits (see Tables 3-6). Table shows remaining address bits that don't care. When necessary bits have been required, programming equipment then read corresponding identifier code DQ7-DQ0. access autoselect codes in-system, host system issue autoselect command command register, shown Table This method does require Refer Autoselect Command Sequence section more information.
Autoselect Mode
autoselect mode provides manufacturer device identification, sector protection verification, through identifier codes output DQ7-DQ0. This mode primarily intended programming equipment automatically match device programmed with corresponding programming algorithm. However, autoselect codes also accessed in-system through command register. When using programming equipment, autoselect mode requires address Address pins must shown Table addi-
Table
Autoselect Codes, (High Voltage Method)
DQ15 BYTE# BYTE# (T), B7hh (T), (T), (protected), (unprotected) (factory locked), (not factory locked)
Description Manufacturer Device Am29DS322G Device Am29DS323G Device Am29DS324G Sector Protection Verification SecSi Indicator (DQ7)
Legend: Boot Block, Bottom Boot Block, Logic VIL, Logic High VIH, Bank Address, Sector Address, Don't care.
2002
Am29DS32xG
Table Bottom Boot Sector/Sector Block Addresses Protection/Unprotection
Sector SA70 SA69-SA67 SA66-SA63 SA62-SA59 SA58-SA55 SA54-SA51 SA50-SA47 SA46-SA43 A20-A12 111111XXX 111110XXX, 111101XXX, 111100XXX 1110XXXXX 1101XXXXX 1100XXXXX 1011XXXXX 1010XXXXX 1001XXXXX 1000XXXXX 0111XXXXX 0110XXXXX 0101XXXXX 0100XXXXX 0011XXXXX 0010XXXXX 0001XXXXX 000011XXX, 000010XXX, 000001XXX 000000111 000000110 000000101 000000100 000000011 000000010 000000001 000000000 Sector/Sector Block Size Kbytes (3x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (3x64) Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes
Sector/Sector Block Protection Unprotection
(Note: following discussion, term "sector" applies both sectors sector blocks. sector block consists more adjacent sectors that protected unprotected same time (see Tables hardware sector protection feature disables both program erase operations sector. hardware sector unprotection feature re-enables both program erase operations previously protected sectors. Sector protection/unprotection implemented methods. Table Boot Sector/Sector Block Addresses Protection/Unprotection
Sector SA1-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 A20-A12 000000XXX 000001XXX, 000010XXX 000011XXX 0001XXXXX 0010XXXXX 0011XXXXX 0100XXXXX 0101XXXXX 0110XXXXX 0111XXXXX 1000XXXXX 1001XXXXX 1010XXXXX 1011XXXXX 1100XXXXX 1101XXXXX 1110XXXXX 111100XXX, 111101XXX, 111110XXX 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111 Sector/ Sector Block Size Kbytes (3x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (4x64) Kbytes (3x64) Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes
SA42-SA39 SA38-SA35 SA34-SA31 SA30-SA27 SA26-SA23 SA22-SA19 SA18-SA15 SA14-SA11 SA10-SA8
primary method requires RESET# only, implemented either in-system programming equipment. Figure shows algorithms Figure shows timing diagram. This method uses standard microprocessor cycle timing. sector unprotect, unprotected sectors must first protected prior first sector unprotect write cycle. sector unprotect algorithm unprotects sectors parallel. previously protected sectors must individually re-protected. change data protected sectors efficiently, temporary sector unprotect function available. "Temporary Sector Unprotect".
Am29DS32xG
2002
alternate method intended only programming equipment requires address OE#. This method compatible with programmer routines written earlier volt-only flash devices. Publication number 22244 contains further details; contact representative request copy. device shipped with sectors unprotected. offers option programming protecting sectors factory prior shipping device through AMD's ExpressFlashService. Contact representative details. possible determine whether sector protected unprotected. Autoselect Mode section details.
Temporary Sector Unprotect
(Note: following discussion, term "sector" applies both sectors sector blocks. sector block consists more adjacent sectors that protected unprotected same time (see Tables This feature allows temporary unprotection previously protected sectors change data in-system. Sector Unprotect mode activated setting RESET# VID. During this mode, formerly protected sectors programmed erased selecting sector addresses. Once removed from RESET# pin, previously protected sectors protected again. Figure shows algorithm, Figure shows timing diagrams, this feature.
Write Protect (WP#)
Write Protect function provides hardware method protecting certain boot sectors without using VID. This function provided WP#/ACC pin. system asserts WP#/ACC pin, device disables program erase functions "outermost" Kbyte boot sectors independently whether those sectors were protected unprotected using method described "Sector/Sector Block Protection Unprotection". outermost Kbyte boot sectors sectors containing lowest addresses bottom-boot-configured device, sectors containing highest addresses top-boot-configured device. system asserts WP#/ACC pin, device reverts whether outermost Byte boot sectors were last protected unprotected. That sector protection unprotection these sectors depends whether they were last protected unprotected using method described "Sector/Sector Block Protection Unprotection". Note that WP#/ACC must left floating unconnected; inconsistent behavior device result.
START
RESET# (Note Perform Erase Program Operations
RESET#
Temporary Sector Unprotect Completed (Note
Notes: protected sectors unprotected WP#/ACC VIL, outermost boot sectors will remain protected). previously protected sectors protected once again.
Figure Temporary Sector Unprotect Operation
2002
Am29DS32xG
START PLSCNT RESET# Wait Protect sectors: indicated portion sector protect algorithm must performed unprotected sectors prior issuing first sector unprotect address
START PLSCNT RESET# Wait
Temporary Sector Unprotect Mode
First Write Cycle 60h? sector address Sector Protect: Write sector address with Wait Verify Sector Protect: Write sector address with Read from sector address with
First Write Cycle 60h? sectors protected? first sector address Sector Unprotect: Write address with
Temporary Sector Unprotect Mode
Increment PLSCNT
Reset PLSCNT
Wait Verify Sector Unprotect: Write sector address with
PLSCNT Data 01h?
Increment PLSCNT
Read from sector address with next sector address
Device failed
Protect another sector? Remove from RESET#
PLSCNT 1000?
Data 00h?
Device failed Write reset command
Last sector verified?
Sector Protect Algorithm
Sector Protect complete
Sector Unprotect Algorithm
Remove from RESET#
Write reset command Sector Unprotect complete
Figure In-System Sector Protection/ Sector Unprotection Algorithms
Am29DS32xG
2002
Customers have their code programmed through ExpressFlash service. programs customer's code, with without random ESN. devices then shipped from AMD's factory with SecSi Sector permanently locked. Contact representative details using AMD's ExpressFlash service. Customer Lockable: SecSi Sector Programmed Protected Factory security feature required, SecSi Sector treated additional 256-byte Flash memory space, expanding size available Flash array. Additionally, note difference location compared previous Am29DL32x boot factory locked devices. SecSi Sector one-time programmable, erased, locked only once. Note that accelerated programming (ACC) unlock bypass functions available when programming SecSi Sector. SecSi Sector area protected using following procedures: Write three-cycle Enter SecSi Sector Region command sequence, then follow in-system sector protect algorithm shown Figure except that RESET# either VID. This allows in-system protection SecSi Sector without raising device high voltage. Note that this method only applicable SecSi Sector Write three-cycle Enter SecSi Sector Region command sequence, then alternate method sector protection described "Sector/Sector Block Protection Unprotection" section. SecSi Sector one-time programmable. Once SecSi Sector locked verified, system must write Exit SecSi Sector Region command sequence return reading writing remainder array. SecSi Sector protection must used with caution since, once protected, there procedure available unprotecting SecSi Sector area none bits SecSi Sector memory space modified way.
SecSi(Secured Silicon) Sector Flash Memory Region
SecSi (Secured Silicon) Sector feature provides 256-byte Flash memory region that enables permanent part identification through Electronic Serial Number (ESN). SecSi Sector uses SecSi Sector Indicator (DQ7) indicate whether SecSi Sector locked when shipped from factory. This permanently factory cannot changed, which prevents cloning factory locked part. This ensures security once product shipped field. offers device with SecSi Sector either lock customer lock able. tory-locked version always protected when shipped from factory, SecSi (Secured Silicon) Sector Indicator permanently "1." customer-lockable version shipped with SecSi Sector unprotected, allowing customers utilize that sector manner they choose. customer-lockable version SecSi (Secured Silicon) Sector Indicator permanently "0." Thus, SecSi Sector Indicator prevents customer-lockable devices from being used replace devices that factory locked. system accesses SecSi Sector through command sequence (see "Enter SecSiSector/Exit SecSi Sector Command Sequence"). After system written Enter SecSi Sector command sequence, read SecSi Sector using addresses normally occupied boot sectors. This mode operation continues until system issues Exit SecSi Sector command sequence, until power removed from device. power-up, following hardware reset, device reverts sending commands boot sectors. Factory Locked: SecSi Sector Programmed Protected Factory factory locked device, SecSi Sector protected when device shipped from factory. SecSi Sector cannot modified way. device available preprogrammed with following: random, secure only Customer code through ExpressFlash service Both random, secure customer code through ExpressFlash service. devices that have ESN, Bottom Boot device will have 16-byte addresses 000000h-000007h word mode 000000h-00000Fh byte mode). Boot device will addresses 1FF000h-1FF007Fh word mode addresses 3FE000h-3FE0FFh byte mode). 2002
Hardware Data Protection
command sequence requirement unlock cycles programming erasing provides data protection against inadvertent writes (refer Table command definitions). addition, following hardware data protection measures prevent accidental erasure programming, which might otherwise caused spurious system level signals during power-up power-down transitions, from system noise.
Am29DS32xG
Write Inhibit
When less than VLKO, device does accept write cycles. This protects data during power-up power-down. command register internal program/erase circuits disabled, device resets read mode. Subsequent writes ignored until greater than VLKO. system must provide proper signals control pins prevent unintentional writes when greater than VLKO. Write Pulse "Glitch" Protection Noise pulses less than (typical) OE#, initiate write cycle. Logical Inhibit Write cycles inhibited holding VIL, VIH. initiate write cycle, must logical zero while logical one. Power-Up Write Inhibit during power device does accept commands rising edge WE#. internal state machine automatically reset read mode power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
Common Flash Interface (CFI) specification outlines device host system software interrogation handshake, which allows specific vendor-specified software algorithms used entire families devices. Software support then device-independent, JEDEC ID-independent, forward- backward-compatible specified flash device families. Flash vendors standardize their existing interfaces long-term compatibility. This device enters Query mode when system writes Query command, 98h, address word mode address byte mode), time device ready read array data. system read information addresses given Tables 10-13. terminate reading data, system must write reset command. Query mode accessible when device executing Embedded Program Embedded Erase algorithm. system also write query command when device autoselect mode. device enters query mode, system read data addresses given Tables 10-13. system must write reset command return device autoselect mode. further information, please refer Specification Publication 100, available World Wide DownloadableAssets/cfi100.pdf. Alternatively, contact representative copies these documents.
Table Query Identification String
Addresses (Word Mode) Addresses (Byte Mode) Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string "QRY"
Primary Command Address Primary Extended Table Alternate Command (00h none exists) Address Alternate Extended Table (00h none exists)
Am29DS32xG
2002
Table System Interface String
Addresses (Word Mode) Addresses (Byte Mode) Data 0018h 0022h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h Description Min. (write/erase) D7-D4: volt, D3-D0: millivolt Max. (write/erase) D7-D4: volt, D3-D0: millivolt Min. voltage (00h present) Max. voltage (00h present) Typical timeout single byte/word write Typical timeout Min. size buffer write (00h supported) Typical timeout individual block erase Typical timeout full chip erase (00h supported) Max. timeout byte/word write times typical Max. timeout buffer write times typical Max. timeout individual block erase times typical Max. timeout full chip erase times typical (00h supported)
Table
Addresses (Word Mode) Addresses (Byte Mode) Data 0016h 0002h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
Device Geometry Definition
Description Device Size byte Flash Device Interface description (refer publication 100) Max. number bytes multi-byte write (00h supported) Number Erase Block Regions within device Erase Block Region Information (refer specification publication 100)
Erase Block Region Information
Erase Block Region Information
Erase Block Region Information
2002
Am29DS32xG
Table Primary Vendor-Specific Extended Query
Addresses (Word Mode) Addresses (Byte Mode) Data 0050h 0052h 0049h 0031h 0033h 0004h Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) Required, Required Silicon Revision Number (Bits 7-2) 0002h 0001h 0001h 0004h 00XXh (See Note) 0000h 0000h 0085h Erase Suspend Supported, Read Only, Read Write Sector Protect Supported, Number sectors group Sector Temporary Unprotect Supported, Supported Sector Protect/Unprotect scheme 29LV800 mode Simultaneous Operation Supported, Number Sectors Bank (Uniform Bank) Burst Mode Type Supported, Supported Page Mode Type Supported, Word Page, Word Page (Acceleration) Supply Minimum Supported, D7-D4: Volt, D3-D0: (Acceleration) Supply Maximum Supported, D7-D4: Volt, D3-D0: Top/Bottom Boot Sector Flag Bottom Boot Device, Boot Device
0095h
000Xh
Note: number sectors Bank device dependent. Am29DS322 38h, Am29DS323 30h, Am29DS324
COMMAND DEFINITIONS
Writing specific address data commands sequences into command register initiates device operations. Table defines valid register command sequences. Writing incorrect address data values writing them improper sequence resets device reading array data. addresses latched falling edge CE#, whichever happens later. data latched rising edge CE#, whichever happens first. Refer Characteristics section timing diagrams.
Reading Array Data
device automatically reading array data after device power-up. commands required retrieve data. Each bank ready read array data after completing Embedded Program Embedded Erase algorithm. After device accepts Erase Suspend command, corresponding bank enters erase-suspend-read mode, after which system read data from non-erase-suspended sector within same bank. After completing programming operation Erase Suspend mode, system once
Am29DS32xG
2002
bank that either read erase-suspend-read mode. autoselect command written while device actively programming erasing other bank. autoselect command sequence initiated first writing unlock cycles. This followed third write cycle that contains bank address autoselect command. bank then enters autoselect mode. system read address within same bank number times without initiating another autoselect command sequence: read cycle address (BA)XX00h (where bank address) returns manufacturer code. read cycle address (BA)XX01h word mode (BA)XX02h byte mode) returns device code. read cycle address containing sector address (SA) within same bank, address A7-A0 word mode address A6-A-1 byte mode) returns sector protected, unprotected. (Refer Tables valid sector addresses). system must write reset command return read mode erase-suspend-read mode bank previously Erase Suspend).
again read array data with same exception. Erase Suspend/Erase Resume Commands section more information. system must issue reset command return bank read erase-suspend-read) mode goes high during active program erase operation, bank autoselect mode. next section, Reset Command, more information. also Requirements Reading Array Data Device Operations section more information. Read-Only Operations table provides read parameters, Figure shows timing diagram.
Reset Command
Writing reset command resets banks read erase-suspend-read mode. Address bits don't cares this command. reset command written between sequence cycles erase command sequence before erasing begins. This resets bank which system writing read mode. Once erasure begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles program command sequence before programming begins. This resets bank which system writing read mode. program command sequence written bank that Erase Suspend mode, writing reset mand turns pend-read mode. Once programming begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles autoselect command sequence. Once autoselect mode, reset command must written return read mode. bank entered autoselect mode while Erase Suspend mode, writing reset command returns that bank erase-suspend-read mode. goes high during program erase operation, writing reset command returns banks read mode erase-suspend-read mode that bank Erase Suspend).
Enter SecSiSector/Exit SecSi Sector Command Sequence
SecSi Sector region provides secured data area containing random, sixteen-byte electronic serial number (ESN). system access SecSi Sector region issuing three-cycle Enter SecSi Sector command sequence. device continues access SecSi Sector region until system issues four-cycle Exit SecSi Sector command sequence. Exit SecSi Sector command sequence returns device normal operation. SecSi Sector accessible when device executing Embedded Program Embedded Erase algorithm. Table shows address data requirements both command sequences. also "SecSi(Secured Silicon) Sector Flash Memory Region" further information.
Byte/Word Program Command Sequence
system program device word byte, depending state BYTE# pin. Programming four-bus-cycle operation. program command sequence initiated writing unlock write cycles, followed program set-up command. program address data written next, which turn initiate Embedded Program algorithm. system required provide further controls timings. device automatically provides internally generated program pulses verifies pro-
Autoselect Command Sequence
autoselect command sequence allows host system access manufacturer device codes, determine whether sector protected. Table shows address data requirements. This method alternative that shown Table which intended PROM programmers requires address autoselect command sequence written address within
2002
Am29DS32xG
sequence. device uses higher voltage WP#/ACC accelerate operation. Note that WP#/ACC must operation other than accelerated programming, device damage result. addition, WP#/ACC must left floating unconnected; inconsistent behavior device result. Figure illustrates algorithm program operation. Refer Erase Program Operations table Characteristics section parameters, Figure timing diagrams.
grammed cell margin. Table shows address data requirements byte program command sequence. When Embedded Program algorithm complete, that bank then returns read mode addresses longer latched. system determine status program operation using DQ7, DQ6, RY/BY#. Refer Write Operation Status section information these status bits. commands written device during Embedded Program Algorithm ignored. Note that hardware reset immediately terminates program operation. program command sequence should reinitiated once that bank returned read mode, ensure data integrity. Programming allowed sequence across sector boundaries. cannot programmed from back "1." Attempting cause that bank cause status bits indicate operation successful. However, succeeding read will show that data still "0." Only erase operations convert "1." Unlock Bypass Command Sequence unlock bypass feature allows system program bytes words bank faster than using standard program command sequence. unlock bypass command sequence initiated first writing unlock cycles. This followed third write cycle containing unlock bypass command, 20h. That bank then enters unlock bypass mode. two-cycle unlock bypass program command sequence that required program this mode. first cycle this sequence contains unlock bypass program command, A0h; second cycle contains program address data. Additional data programmed same manner. This mode dispenses with initial unlock cycles required standard program command sequence, resulting faster total programming time. Table shows requirements command sequence. During unlock bypass mode, only Unlock Bypass Program Unlock Bypass Reset commands valid. exit unlock bypass mode, system must issue two-cycle unlock bypass reset command sequence. first cycle must contain bank address data 90h. second cycle need only contain data 00h. bank then returns read mode. device offers accelerated program operations through WP#/ACC pin. When system asserts WP#/ACC pin, device automatically enters Unlock Bypass mode. system then write two-cycle Unlock Bypass program command
START
Write Program Command Sequence
Embedded Program algorithm progress
Data Poll from System
Verify Data?
Increment Address
Last Address?
Programming Completed
Note: Table program command sequence.
Figure
Program Operation
Chip Erase Command Sequence
Chip erase cycle operation. chip erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed chip erase command, which turn invokes Embedded Erase algorithm. device does require system preprogram prior erase. Embedded Erase algorithm automatically preprograms verifies entire 2002
Am29DS32xG
command sequence additional addresses commands. system monitor determine sector erase timer timed (See section DQ3: Sector Erase Timer.). time-out begins from rising edge final pulse command sequence. When Embedded Erase algorithm complete, bank returns reading array data addresses longer latched. Note that while Embedded Erase operation progress, system read data from non-erasing bank. system determine status erase operation reading DQ7, DQ6, DQ2, RY/BY# erasing bank. Refer Write Operation Status section information these status bits. Once sector erase operation begun, only Erase Suspend command valid. other commands ignored. However, note that hardware reset immediately terminates erase operation. that occurs, sector erase command sequence should reinitiated once that bank returned reading array data, ensure data integrity. Figure illustrates algorithm erase operation. Refer Erase Program Operations tables Characteristics section parameters, Figure section timing diagrams.
memory zero data pattern prior electrical erase. system required provide controls timings during these operations. Table shows address data requirements chip erase command sequence. When Embedded Erase algorithm complete, that bank returns read mode addresses longer latched. system determine status erase operation using DQ7, DQ6, DQ2, RY/BY#. Refer Write Operation Status section information these status bits. commands written during chip erase operation ignored. However, note that hardware reset immediately terminates erase operation. that occurs, chip erase command sequence should reinitiated once that bank returned reading array data, ensure data integrity. Figure illustrates algorithm erase operation. Refer Erase Program Operations tables Characteristics section parameters, Figure section timing diagrams.
Sector Erase Command Sequence
Sector erase cycle operation. sector erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock cycles written, then followed address sector erased, sector erase command. Table shows address data requirements sector erase command sequence. device does require system preprogram prior erase. Embedded Erase algorithm automatically programs verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. After command sequence written, sector erase time-out occurs. During time-out period, additional sector addresses sector erase commands (for sectors within same bank) written. Loading sector erase buffer done sequence, number sectors from sector sectors. time between these additional cycles must less than otherwise erasure begin. sector erase address command following exceeded time-out accepted. recommended that processor interrupts disabled during this time ensure commands accepted. interrupts re-enabled after last Sector Erase command written. command other than Sector Erase Erase Suspend during time-out period resets that bank read mode. system must rewrite
Erase Suspend/Erase Resume Commands
Erase Suspend command, B0h, allows system interrupt sector erase operation then read data from, program data sector selected erasure. bank address required when writing this command. This command valid only during sector erase operation, including time-out period during sector erase command sequence. Erase Suspend command ignored written during chip erase operation Embedded Program algorithm. When Erase Suspend command written during sector erase operation, device requires maximum suspend erase operation. However, when Erase Suspend command written during sector erase time-out, device immediately terminates time-out period suspends erase operation. After erase operation been suspended, bank enters erase-suspend-read mode. system read data from program data sector selected erasure. (The device "erase suspends" sectors selected erasure.) Reading address within erase-suspended sectors produces status information DQ7-DQ0. system DQ7, together, determine
2002
Am29DS32xG
sector actively erasing erase-suspended. Refer Write Operation Status section information these status bits. After erase-suspended program operation complete, bank returns erase-suspend-read mode. system determine status program operation using status bits, just standard Byte Program operation. Refer Write Operation Status section more information. erase-suspend-read mode, system also issue autoselect command sequence. Refer Autoselect Mode Autoselect Command Sequence sections details. resume sector erase operation, system must write Erase Resume command. bank address erase-suspended bank required when writing this command. Further writes Resume command ignored. Another Erase Suspend command written after chip resumed erasing.
START
Write Erase Command Sequence (Notes
Data Poll Erasing Bank from System
Embedded Erase algorithm progress
Data FFh?
Erasure Completed
Notes: Table erase command sequence. section information sector erase timer.
Figure Erase Operation
Am29DS32xG
2002
Table Command Definitions
Command Sequence (Note Read (Note Reset (Note Manufacturer Autoselect (Note Device SecSi Sector Factory Protect (Note Sector/Sector Block Protect Verify (Note Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Cycles Cycles (Notes 2-5) First Addr Data (BA)555 (BA)AAA (BA)555 (BA)AAA (BA)555 (BA)AAA (BA)555 (BA)AAA (BA)X00 (BA)X01 (BA)X02 (BA)X03 (BA)X06 (SA)X02 (SA)X04 00/01 (see Table 81/01 Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data
Enter SecSi Sector Region Exit SecSi Sector Region Program Unlock Bypass
Unlock Bypass Program (Note Unlock Bypass Reset (Note Chip Erase Sector Erase Erase Suspend (Note Erase Resume (Note Query (Note Word Byte Word Byte Word Byte
Legend: Don't care Address memory location read. Data read from location during read operation. Address memory location programmed. Addresses latch falling edge pulse, whichever happens later. Notes: Table description operations. values hexadecimal. Except read cycle fourth cycle autoselect command sequence, cycles write cycles. Data bits DQ15-DQ8 don't care command sequences, except Unless otherwise noted, address bits A20-A11 don't cares. unlock command cycles required when bank reading array data. Reset command required return read mode erase-suspend-read mode previously Erase Suspend) when bank autoselect mode, goes high (while bank providing status information). fourth cycle autoselect command sequence read cycle. system must provide bank address obtain manufacturer device SecSi Sector factory protect information. Data bits DQ15-DQ8 don't care. Autoselect Command Sequence section more information.
Data programmed location Data latches rising edge pulse, whichever happens first. Address sector verified autoselect mode) erased. Address bits A20-A12 uniquely select sector. Address bank that being switched autoselect mode, bypass mode, being erased.
data factory locked factory locked.
data unprotected sector/sector block protected sector/sector block. Unlock Bypass command required prior Unlock Bypass Program command. Unlock Bypass Reset command required return read mode when bank unlock bypass mode. system read program non-erasing sectors, enter autoselect mode, when Erase Suspend mode. Erase Suspend command valid only during sector erase operation, requires bank address. Erase Resume command valid only during Erase Suspend mode, requires bank address.
Command valid when device ready read array data when device autoselect mode.
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Am29DS32xG
WRITE OPERATION STATUS
device provides several bits determine status program erase operation: DQ2, DQ3, DQ5, DQ6, DQ7. Table following subsections describe function these bits. each offer method determining whether program erase operation complete progress. device also provides hardware-based output signal, RY/BY#, determine whether Embedded Program Erase operation progress been completed. invalid. Valid data DQ7-DQ0 will appear successive read cycles. Table shows outputs Data# Polling DQ7. Figure shows Data# Polling algorithm. Figure Characteristics section shows Data# Polling timing diagram.
DQ7: Data# Polling
Data# Polling bit, DQ7, indicates host system whether Embedded Program Erase algorithm progress completed, whether bank Erase Suspend. Data# Polling valid after rising edge final pulse command sequence. During Embedded Program algorithm, device outputs complement datum programmed DQ7. This status also applies programming during Erase Suspend. When Embedded Program algorithm complete, device outputs datum programmed DQ7. system must provide program address read valid status information DQ7. program address falls within protected sector, Data# Polling active approximately then that bank returns read mode. During Embedded Erase algorithm, Data# Polling produces DQ7. When Embedded Erase algorithm complete, bank enters Erase Suspend mode, Data# Polling produces DQ7. system must provide address within sectors selected erasure read valid status information DQ7. After erase command sequence written, sectors selected erasing protected, Data# Polling active approximately then bank returns read mode. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. However, system reads address within protected sector, status valid. Just prior completion Embedded Program Erase operation, change asynchronously with DQ0-DQ6 while Output Enable (OE#) asserted low. That device change from providing status information valid data DQ7. Depending when system samples output, read status valid data. Even device completed program erase operation valid data, data outputs DQ0-DQ6 still
START
Read DQ7-DQ0 Addr
Data?
Read DQ7-DQ0 Addr
Data?
FAIL PASS
Notes: Valid address programming. During sector erase operation, valid address sector address within sector being erased. During chip erase, valid address non-protected sector address. should rechecked even because change simultaneously with DQ5.
Figure Data# Polling Algorithm
Am29DS32xG
2002
Table shows outputs Toggle DQ6. Figure shows toggle algorithm. Figure Characteristics" section shows toggle timing diagrams. Figure shows differences between graphical form. also subsection DQ2: Toggle
RY/BY#: Ready/Busy#
RY/BY# dedicated, open-drain output which indicates whether Embedded Algorithm progress complete. RY/BY# status valid after rising edge final pulse command sequence. Since RY/BY# open-drain output, several RY/BY# pins tied together parallel with pull-up resistor VCC. output (Busy), device actively erasing programming. (This includes programming Erase Suspend mode.) output high (Ready), device read mode, standby mode, banks erase-suspend-read mode. Table shows outputs RY/BY#.
START
Read DQ7-DQ0
DQ6: Toggle
Toggle indicates whether Embedded Program Erase algorithm progress complete, whether device entered Erase Suspend mode. Toggle read address, valid after rising edge final pulse command sequence (prior program erase operation), during sector erase time-out. During Embedded Program Erase algorithm operation, successive read cycles address cause toggle. system either control read cycles. When operation complete, stops toggling. After erase command sequence written, sectors selected erasing protected, toggles approximately then returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. system together determine whether sector actively erasing erase-suspended. When device actively erasing (that Embedded Erase algorithm progress), toggles. When device enters Erase Suspend mode, stops toggling. However, system must also determine which sectors erasing erase-suspended. Alternatively, system (see subsection DQ7: Data# Polling). program address falls within protected sector, toggles approximately after program command sequence written, then returns reading array data. also toggles during erase-suspend-program mode, stops toggling once Embedded Program algorithm complete.
Read DQ7-DQ0
Toggle Toggle?
Read DQ7-DQ0 Twice
Toggle Toggle?
Program/Erase Operation Complete, Write Reset Command Program/Erase Operation Complete
Note: system should recheck toggle even because toggle stop toggling changes "1." subsections more information.
Figure Toggle Algorithm
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Am29DS32xG
toggle through successive read cycles, determining status described previous paragraph. Alternatively, choose perform other system tasks. this case, system must start beginning algorithm when returns determine status operation (top Figure
DQ2: Toggle
"Toggle DQ2, when used with DQ6, indicates whether particular sector actively erasing (that Embedded Erase algorithm progress), whether that sector erase-suspended. Toggle valid after rising edge final pulse command sequence. toggles when system reads addresses within those sectors that have been selected erasure. (The system either control read cycles.) cannot distinguish whether sector actively erasing erase-suspended. DQ6, comparison, indicates whether device actively erasing, Erase Suspend, cannot distinguish which sectors selected erasure. Thus, both status bits required sector mode information. Refer Table compare outputs DQ6. Figure shows toggle algorithm flowchart form, section "DQ2: Toggle explains algorithm. also DQ6: Toggle subsection. Figure shows toggle timing diagram. Figure shows differences between graphical form.
DQ5: Exceeded Timing Limits
indicates whether program erase time exceeded specified internal pulse count limit. Under these conditions produces "1," indicating that program erase cycle successfully completed. device output system tries program location that previously programmed "0." Only erase operation change back "1." Under this condition, device halts operation, when timing limit been exceeded, produces "1." Under both these conditions, system must write reset command return read mode erase-suspend-read mode bank previously erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing sector erase command sequence, system read determine whether erasure begun. (The sector erase timer does apply chip erase command.) additional sectors selected erasure, entire time-out also applies after each additional sector erase command. When time-out period complete, switches from "1." time between additional sector erase commands from system assumed less than system need monitor DQ3. also Sector Erase Command Sequence section. After sector erase command written, system should read status (Data# Polling) (Toggle ensure that device accepted command sequence, then read DQ3. "1," Embedded Erase algorithm begun; further commands (except Erase Suspend) ignored until erase operation complete. "0," device will accept additional sector erase commands. ensure command been accepted, system software should check status prior following each subsequent sector erase command. high second status check, last command might have been accepted. Table shows status relative other status bits.
Reading Toggle Bits DQ6/DQ2
Refer Figure following discussion. Whenever system initially begins reading toggle status, must read DQ7-DQ0 least twice determine whether toggle toggling. Typically, system would note store value toggle after first read. After second read, system would compare value toggle with first. toggle toggling, device completed program erase operation. system read array data DQ7-DQ0 following read cycle. However, after initial read cycles, system determines that toggle still toggling, system also should note whether value high (see section DQ5). system should then determine again whether toggle toggling, since toggle have stopped toggling just went high. toggle longer toggling, device successfully completed program erase operation. still toggling, device completed operation successfully, system must write reset command return reading array data. remaining scenario that system initially determines that toggle toggling gone high. system continue monitor
Am29DS32xG
2002
Table Write Operation Status
Status Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program (Note DQ7# Data DQ7# Toggle Toggle toggle Data Toggle (Note Data Data (Note toggle Toggle Toggle Data RY/BY#
Standard Mode Erase Suspend Mode
Notes: switches when Embedded Program Embedded Erase operation exceeded maximum timing limits. Refer section more information. require valid address when reading status information. Refer appropriate subsection further details. When reading write operation status bits, system must always provide bank address where Embedded Algorithm progress. device outputs array data system addresses non-busy bank.
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Am29DS32xG
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages -65°C +150°C Ambient Temperature with Power Applied -65°C +125°C Voltage with Respect Ground (Note .-0.5 +4.0 OE#, RESET# (Note -0.5 +11.0 WP#/ACC .-0.5 +10.5 other pins (Note -0.5 +0.5 Output Short Circuit Current (Note
Notes: Minimum voltage input pins -0.5 During voltage transitions, input pins overshoot -2.0 periods Maximum voltage input pins +0.5 Figure During voltage transitions, input pins overshoot +2.0 periods Figure Minimum input voltage pins OE#, RESET#, WP#/ACC -0.5 During voltage transitions, OE#, WP#/ACC, RESET# overshoot -2.0 periods Figure Maximum input voltage +12.5 which overshoot +14.0 periods Maximum input voltage WP#/ACC +9.5 which overshoot +12.0 periods more than output shorted ground time. Duration short circuit should greater than second. Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this data sheet implied. Exposure device absolute maximum rating conditions extended periods affect device reliability. +0.8 -0.5 -2.0
Figure Maximum Negative Overshoot Waveform
+2.0 +0.5
Figure Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial Devices Ambient Temperature (TA) -40°C +85°C Extended Devices Ambient Temperature (TA) -55°C +125°C Supply Voltages standard voltage range
Operating ranges define those limits between which functionality device guaranteed.
Am29DS32xG
2002
CHARACTERISTICS CMOS Compatible
Parameter Symbol ILIT Parameter Description Input Load Current Input Load Current Output Leakage Current Test Conditions VCC, max; 12.5 VOUT VCC, VIL, VIH, Byte Mode VIL, VIH, Word Mode Byte Word Byte Word -0.5 -2.0 -100 0.7x VCC-0.1 ±3.0 ±3.0 Unit
ICC1
Active Read Current (Notes
ICC2 ICC3 ICC4 ICC5 ICC6
Active Write Current (Notes VIL, VIH, Standby Current (Note Reset Current (Note Automatic Sleep Mode (Notes Active Read-While-Program Current (Notes Active Read-While-Erase Current (Notes Active Program-While-Erase-Suspended Current (Notes Accelerated Program Current, Word Byte Input Voltage Input High Voltage Voltage WP#/ACC Sector Protect/Unprotect Program Acceleration Voltage Autoselect Temporary Sector Unprotect Output Voltage Output High Voltage Lock-Out Voltage (Note CE#, RESET# RESET# VIL,
ICC7
VIL,
ICC8
VIL,
IACC
VIL,
VOH1 VOH2 VLKO
11.0 0.25
Notes: current listed typically less than mA/MHz, with VIH. Maximum specifications tested with VCCmax. active while Embedded Erase Embedded Program progress. Automatic sleep mode enables power mode when addresses remain stable tACC Typical sleep mode current 100% tested.
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Am29DS32xG
CHARACTERISTICS Zero-Power Flash
Supply Current
1000 1500 2000 Time 2500 3000 3500 4000
Note: Addresses switching
Figure
ICC1 Current Time (Showing Active Automatic Sleep Currents)
Supply Current
Note:
Frequency Figure Typical ICC1 Frequency
Am29DS32xG
2002
TEST CONDITIONS
Table Test Specifications
Test Condition Output Load Device Under Test Output Load Capacitance, (including capacitance) Input Rise Fall Times Input Pulse Levels Input timing measurement reference levels Note: Diodes IN3064 equivalent Output timing measurement reference levels 0.0-2.0 gate Unit
Figure
Test Setup
SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from Changing from Don't Care, Change Permitted Does Apply Changing, State Unknown Center Line High Impedance State (High OUTPUTS
Input
Measurement Level
Output
Figure Input Waveforms Measurement Levels
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Am29DS32xG
CHARACTERISTICS Read-Only Operations
Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Std. tACC Description Read Cycle Time (Note Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output High (Note Output Enable Output High (Note Output Hold Time From Addresses, OE#, Whichever Occurs First Read Output Enable Hold Time Toggle (Note Data# Polling CE#, Test Setup Speed Options Unit
tOEH
Notes: 100% tested. Figure Table test specifications.
Addresses tOEH HIGH Outputs RESET# RY/BY# Output Valid HIGH Addresses Stable tACC
Figure
Read Operation Timings
Am29DS32xG
2002
CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC tReady tReady tRPD Description RESET# (During Embedded Algorithms) Read Mode (See Note) RESET# (NOT During Embedded Algorithms) Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Standby Mode RY/BY# Recovery Time Speed Options Unit
Note: 100% tested.
RY/BY#
CE#, RESET# tReady
Reset Timings during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# CE#,
RESET#
Figure Reset Timings
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Am29DS32xG
CHARACTERISTICS Word/Byte Configuration (BYTE#)
Parameter JEDEC tELFL/tELFH tFLQZ tFHQV Description BYTE# Switching High BYTE# Switching Output HIGH BYTE# Switching High Output Active Speed Options Unit
BYTE# tELFL BYTE# Switching from word byte mode DQ14-DQ0
Data Output (DQ14-DQ0)
Data Output (DQ7-DQ0) Address Input
DQ15/A-1
DQ15 Output tFLQZ tELFH
BYTE# BYTE# Switching from byte word mode
DQ14-DQ0
Data Output (DQ7-DQ0) Address Input tFHQV
Data Output (DQ14-DQ0) DQ15 Output
DQ15/A-1
Figure
BYTE# Timings Read Operations
falling edge last signal
BYTE#
tSET (tAS)
tHOLD (tAH)
Note: Refer Erase/Program Operations table specifications.
Figure BYTE# Timings Write Operations
Am29DS32xG
2002
CHARACTERISTICS Erase Program Operations
Parameter JEDEC tAVAV tAVWL tASO tWLAX tAHT tDVWH tWHDX tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tWPH tSR/W tWHWH1 tWHWH1 Description Write Cycle Time (Note Address Setup Time Address Setup Time during toggle polling Address Hold Time Address Hold Time From high during toggle polling Data Setup Time Data Hold Time Output Enable High during toggle polling Read Recovery Time Before Write (OE# High Low) Setup Time Hold Time Write Pulse Width Write Pulse Width High Latency Between Read Write Operations Byte Programming Operation (Note Word Accelerated Programming Operation, Word Byte (Note Sector Erase Operation (Note Setup Time (Note Write Recovery Time from RY/BY# Program/Erase Valid RY/BY# Delay Speed Options Unit
tWHWH1 tWHWH2
tWHWH1 tWHWH2 tVCS tBUSY
Notes: 100% tested. "Erase Programming Performance" section more information.
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Am29DS32xG
CHARACTERISTICS
Program Command Sequence (last cycles) Addresses 555h Data tBUSY RY/BY# Status DOUT tWPH tWHWH1 Read Status Data (last cycles)
tVCS
Notes: program address, program data, DOUT true data program address. Illustration shows device word mode.
Figure
Program Operation Timings
WP#/ACC
tVHH tVHH
Figure
Accelerated Program Timing Diagram
Am29DS32xG
2002
CHARACTERISTICS
Erase Command Sequence (last cycles) Addresses 2AAh
555h chip erase
Read Status Data
tWPH
tWHWH2
Data
Chip Erase Progress Complete
tBUSY RY/BY# tVCS
Notes: sector address (for Sector Erase), Valid Address reading status data (see "Write Operation Status". These waveforms word mode.
Figure
Chip/Sector Erase Operation Timings
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Am29DS32xG
CHARACTERISTICS
Addresses
Valid
Valid
Valid
Valid
tACC tOEH tWPH Data
Valid
tCPH
tGHWL
Valid Valid Valid
tSR/W
Controlled Write Cycle Read Cycle Controlled Write Cycles
Figure Back-to-back Read/Write Cycle Timings
Addresses tACC tOEH
High
Complement
Complement
True
Valid Data
High
DQ0-DQ6 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: Valid address. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
Figure
Data# Polling Timings (During Embedded Algorithms)
Am29DS32xG
2002
CHARACTERISTICS
tAHT Addresses tAHT tASO tOEH tOEPH DQ6/DQ2 Valid Data
Valid Status
tCEPH
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: Valid address; required DQ6. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle
Figure
Toggle Timings (During Embedded Algorithms)
Enter Embedded Erasing
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
Note: toggles only when read address within erase-suspended sector. system toggle DQ6.
Figure
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Am29DS32xG
CHARACTERISTICS Temporary Sector Unprotect
Parameter JEDEC tVIDR tVHH tRSP tRRB Description Rise Fall Time (See Note) Rise Fall Time (See Note) RESET# Setup Time Temporary Sector Unprotect RESET# Hold Time from RY/BY# High Temporary Sector Unprotect Speed Options Unit
Note: 100% tested.
RESET# VSS, VIL, tVIDR Program Erase Command Sequence tVIDR
VSS, VIL,
tRSP RY/BY# tRRB
Figure Temporary Sector Unprotect Timing Diagram
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2002
CHARACTERISTICS
RESET#
Valid* Sector/Sector Block Protect Unprotect
Valid* Verify
Sector/Sector Block Protect: Sector/Sector Block Unprotect:
Valid*
Data
Status
sector protect, sector unprotect,
Figure Sector/Sector Block Protect Unprotect Timing Diagram
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Am29DS32xG
CHARACTERISTICS Alternate Controlled Erase Program Operations
Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH1 tWHWH2 tGHEL tCPH tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High Low) Setup Time Hold Time Pulse Width Pulse Width High Programming Operation (Note Accelerated Programming Operation, Word Byte (Note Sector Erase Operation (Note Byte Word Speed Options Unit
Notes: 100% tested. "Erase Programming Performance" section more information.
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2002
CHARACTERISTICS
program erase program sector erase chip erase
Data# Polling
Addresses tGHEL tCPH Data
program erase program sector erase chip erase
tWHWH1
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: Figure indicates last cycles program erase operation. program address, sector address, program data. DQ7# complement data written device. DOUT data written device. Waveforms word mode.
Figure Alternate Controlled Write (Erase/Program) Operation Timings
2002
Am29DS32xG
ERASE PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte/Word Program Time Word Program Time Chip Program Time (Note Byte Mode Word Mode (Note (Note Unit Excludes system level overhead (Note Comments Excludes programming prior erasure (Note
Notes: Typical program erase times assume following conditions: 25°C, VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. Under worst case conditions 90°C, (3.0 regulated devices), 1,000,000 cycles. typical chip programming time considerably less than maximum chip programming time listed, since most bytes program faster than maximum program times listed. pre-programming step Embedded Erase algorithm, bytes programmed before erasure. System-level overhead time required execute two- four-bus-cycle sequence program command. Table further information command definitions. device minimum erase program cycle endurance 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Input voltage with respect pins except pins (including OE#, RESET#) Input voltage with respect pins Current -1.0 -0.5 -100 11.0 +100
Note: Includes pins except VCC. Test conditions: time.
TSOP CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Unit
Notes: Sampled, 100% tested. Test conditions 25°C, MHz.
DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time 125°C Years Test Conditions 150°C Unit Years
Am29DS32xG
2002
PHYSICAL DIMENSIONS FBD048-Fine-Pitch Ball Grid Array,
7/2000
6.00 12.00 PACKAGE
1.20 0.20 0.94 0.84 12.00 6.00 5.60 4.00 0.25 0.30 0.35 0.80 0.40
2002
Am29DS32xG
PHYSICAL DIMENSIONS 048-Thin Small Outline Package
10/99
Am29DS32xG
2002
REVISION SUMMARY Revision (May 2002)
Global Initial release.
Trademarks Copyright 2002 Advanced Micro Devices, Inc. rights reserved. AMD, logo, combinations thereof registered trademarks Advanced Micro Devices, Inc. ExpressFlash trademark Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
2002
Am29DS32xG
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