AMD-K6-III-P Processor Data Sheet Publication 22655 Rev: Iss
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AMD-K6-III-P
Processor Data Sheet
Publication 22655 Rev: Issue Date: September 1999
Amendment/0
1999 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, logo, 3DNow!, combinations thereof, TriLevel Cache, Super7 trademarks, AMD-K6 RISC86 registered trademarks Advanced Micro Devices, Inc. trademark Intel Corporation. Microsoft, Windows, Windows registered trademarks Microsoft Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
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Contents
Revision History About This Data Sheet .xiii Mobile AMD-K6®-III-P Processor
Super7Platform Initiative Super7 Platform Enhancements:
Internal Architecture
Introduction Mobile AMD-K6®-III-P Processor Microarchitecture Overview Enhanced RISC86® Microarchitecture Cache, Instruction Prefetch, Predecode Bits Cache Prefetching. Predecode Bits Instruction Fetch Decode Instruction Fetch Instruction Decode Centralized Scheduler Execution Units Register Pipelines Branch-Prediction Logic Branch History Table. Branch Target Cache Return Address Stack Branch Execution Unit
Logic Symbol Diagram Signal Descriptions Mobile AMD-K6-III-P Processor Operation
Process Technology Clock Control Halt State Stop Grant State Stop Grant Inquire State Stop Clock State
Contents
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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System Management Mode (SMM) Overview. Operating Mode Default Register Values State-Save Area Revision Identifier Base Address Halt Restart Slot Trap Dword. Trap Restart Slot Exceptions, Interrupts, Debug
Signal Switching Characteristics
Switching Characteristics Clock Switching Characteristics 100-MHz Operation Clock Switching Characteristics 66-MHz Operation Valid Delay, Float, Setup, Hold Timings Output Delay Timings 100-MHz Operation Input Setup Hold Timings 100-MHz Operation Output Delay Timings 66-MHz Operation Input Setup Hold Timings 66-MHz Operation RESET Test Signal Timing
Electrical Data
Operating Ranges Absolute Ratings Characteristics Power Dissipation Power Grounding Power Connections Decoupling Recommendations Connection Requirements
Thermal Design
Package Thermal Specifications Heat Dissipation Path Measuring Case Temperature
Package Specifications
321-Pin Staggered CPGA Package Specification
Contents
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Description Diagrams
10.1 Designations Functional Grouping
Ordering Information
Index.
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Contents
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List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Mobile AMD-K6®-III-P Processor Block Diagram Cache Sector Organization Instruction Buffer Mobile AMD-K6-III-P Processor Decode Logic Mobile AMD-K6-III-P Processor Scheduler Register Functional Units Clock Control State Transitions Memory Waveform
Figure Diagrams Figure Output Valid Delay Timing Figure Maximum Float Delay Timing Figure Input Setup Hold Timing Figure Reset Configuration Timing Figure Waveform Figure TRST# Timing. Figure Test Signal Timing Diagram Figure Suggested Component Placement Figure Thermal Model Figure Power Consumption versus Thermal Resistance Figure Processor's Heat Dissipation Path Figure Measuring Case Temperature. Figure 321-Pin Staggered CPGA Package Specification Figure Mobile AMD-K6-III-P Processor Bottom-Side View Figure Mobile AMD-K6-III-P Processor Top-Side View
List Figures
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List Figures
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List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Execution Latency Throughput Execution Units Input Types Output Float Conditions Input/Output Float Conditions Test Pins Cycle Definition Special Cycles Initial State Registers State-Save Area Revision Identifier Trap Dword Configuration Trap Restart Slot Switching Characteristics 100-MHz Operation Switching Characteristics 66-MHz Operation Output Delay Timings 100-MHz Operation Input Setup Hold Timings 100-MHz Operation Output Delay Timings 66-MHz Operation Input Setup Hold Timings 66-MHz Operation RESET Configuration Signals 100-MHz Operation RESET Configuration Signals 66-MHz Operation Waveform TRST# Timing Test Signal Timing Operating Ranges. Absolute Ratings Characteristics Power Dissipation. Package Thermal Specifications. 321-Pin Staggered CPGA Package Specification Valid Ordering Part Number Combinations
List Tables
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List Tables
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Revision History
Date 1999 July 1999 Sept 1999 Initial published release. Added VCC2 decoupling capacitors Figure "Suggested Component Placement," page Added specifications OPNs MHz, MHz, frequencies Chapter "Electrical Data", Chapter "Thermal Design", Chapter "Ordering Information". Description
Revision History
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Revision History
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About This Data Sheet
Mobile AMD-K6®-III-P Processor Data Sheet supplement AMD-K6®-III Processor Data Sheet, order# 21918. When combined, data sheets provide complete specification Mobile AMD-K6-III-P processor.
About This Data Sheet
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About This Data Sheet
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Mobile AMD-K6®-III-P Processor
Advanced 6-Issue RISC86® Superscalar Microarchitecture parallel specialized execution units Multiple sophisticated x86-to-RISC86 instruction decoders Advanced two-level branch prediction Speculative execution Out-of-order execution Register renaming data forwarding Issues RISC86 instructions clock TriLevel CacheDesign Large On-Chip Split 64-Kbyte Level-One (L1) Cache 32-Kbyte instruction cache with additional predecode cache 32-Kbyte writeback dual-ported data cache On-die 256-Kbyte full processor speed, backside Level-Two (L2) Cache Support external Level-Three (L3) Cache 100-MHz frontside MESI protocol support High-Performance IEEE 754-Compatible 854-Compatible Floating-Point Unit Superscalar MMXunit supports industry-standard instructions 3DNow!Technology high-performance multimedia graphics capabilities Compatible with Super7100-MHz frontside Socket 66-MHz notebook design Socket 7-Compatible Ceramic Grid Array (CPGA) Package Industry-Standard System Management Mode (SMM) IEEE 1149.1 Boundary Scan Binary Software Compatibility Voltage 0.25-Micron Process Technology 21.3 Million Transistors
Mobile AMD-K6 ®-III-P processor AMD's third generation mobile AMD-K6 processor delivering highest performance notebook systems. Mobile AMD-K6-III-P processor based advanced Mobile AMD-K6-2 core adds AMD's unique TriLevel Cachedesign enhanced system performance. TriLevel Cache design provides large 64-Kbyte cache, 256-Kbyte cache operating full processor speed backside bus, Mbyte available cache memory external 100-MHz frontside bus. This combination largest Chapter Mobile AMD-K6®-III-P Processor
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fastest cache memory subsystem gives Mobile AMD-K6-III-P processor performance edge over competing mobile solutions. Mobile AMD-K6-III-P processor also incorporates superscalar unit, support 100-MHz frontside bus, AMD's innovative 3DNow! technology high-performance multimedia graphics operation. Mobile AMD-K6-III-P processor includes several features mobile market. processor implemented using AMD-developed, state-of-the-art power 0.25-micron process technology. This process technology features split-plane design that allows processor core operate lower voltage while portion operates industry-standard level. 0.25-micron process technology with split-plane voltage design enables Mobile AMD-K6-III-P processor deliver excellent portable performance solutions while utilizing lower processor core voltage, which results lower power consumption longer battery life. addition, Mobile AMD-K6-III-P processor includes complete industry-standard System Management Mode (SMM), which critical system resource power management. Mobile AMD-K6-III-P processor also features industry-standard Stop-Clock (STPCLK#) control circuitry Halt instruction, both required implementing ACPI power management specification. Mobile AMD-K6-III-P processor offered industry-standard Socket 7-compatible, 321-pin Ceramic Grid Array (CPGA) package. Mobile AMD-K6-III-P processor's RISC86 microarchitecture decoupled decode/execution superscalar design that implements state-of-the-art design techniques achieve leading-edge performance. Advanced design techniques implemented Mobile AMD-K6-III-P processor include multiple instruction decode, single-clock internal RISC operations, execution units that support superscalar operation, out-of-order execution, data forwarding, speculative execution, register renaming. addition, processor supports industry's most advanced branch prediction logic implementing 8192-entry branch history table, industry's only branch target cache, return address stack, which combine deliver better than prediction rate. These design techniques enable Mobile AMD-K6-III-P processor issue, execute, retire multiple instructions clock, resulting excellent scaleable performance. AMD's 3DNow! technology instruction extension that includes instructions improve graphics operations other single precision floatingpoint compute intensive operations. already shipped millions AMD-K6 family processors with 3DNow! technology desktop PCs, revolutionizing experience with four times peak floating-point performance previous generation solutions. bringing this advanced capability notebook computing, working conjunction with advanced mobile graphic controllers reach levels realism mobile computing. With support from Microsoft® software developer community, generation visually compelling applications coming market that support 3DNow! technology. Mobile AMD-K6®-III-P Processor Chapter
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Mobile AMD-K6-III-P processor remains compatible with existing Socket notebook solutions, however maximum system performance, processor works optimally newer Super7 designs that incorporate advanced features such support 100-MHz frontside graphics. Mobile AMD-K6-III-P processor undergone extensive testing compatible with Windows® Windows other leading operating systems. Mobile AMD-K6-III-P processor also compatible with more than 60,000 software applications, including latest 3DNow! technology technology software. world's second-largest supplier processors Windows environment, shipped more than million Microsoft Windows compatible processors last five years. Mobile AMD-K6-III-P processor next generation long line Microsoft Windows compatible processors from AMD. With combination state-of-the-art features, leading-edge performance, high-performance multimedia engine, compatibility, low-cost infrastructure, Mobile AMD-K6-III-P processor superior choice notebook computers.
Super7Platform Initiative
industry partners investing future Socket with Super7 platform initiative. goal initiative maintain competitive vitality Socket infrastructure through series planned enhancements, including development industry-standard 100-MHz processor protocol. addition 100-MHz processor protocol, Super7 initiative includes introduction chipsets that support specification, support backside cache frontside cache. Super7Platform Enhancements: 100-MHz processor bus-The Mobile AMD-K6-III-P processor supports 100-MHz, Mbyte/second frontside provide high-speed interface Super7 platform-based chipsets. 100-MHz interface frontside cache main system memory speeds access frontside cache main memory percent over 66-MHz Socket interface-resulting significant increase overall system performance. Accelerated graphics port support-AGP improves performance mid-range that have small amounts video memory graphics card. industry-standard specification enables 133-MHz graphics interface will scale even higher levels performance. Support backside frontside cache-The Super7 platform `headroom' support higher-performance AMD-K6 processors, with clock speeds scaling beyond.
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Internal Architecture
Introduction
Mobile AMD-K6-III-P processor implements advanced design techniques known RISC86 microarchitecture. RISC86 microarchitecture decoupled decode/execution design approach that yields superior sixth-generation performance x86-based software. This chapter describes techniques used functional elements RISC86 microarchitecture.
Mobile AMD-K6®-III-P Processor Microarchitecture Overview
When discussing processor design, important understand implementation. term architecture refers instruction features processor that visible software rchi termines software processor run. architecture Mobile AMD-K6-III-P processor industry-standard instruction set. term microarchitecture refers design techniques used processor reach target cost, performance, functionality goals. Mobile AMD-K6 family processors based sophisticated RISC core known Enhanced microarchitecture advanced, second-order decoupled industry-leading performance x86-based software. term design implementation refers actual logic circuit designs from which processor created according microarchitecture specifications.
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Enhanced RISC86® Microarchitecture
anced RISC86 croarchi tecture characteristics AMD-K6 family. innovative RISC86 microarchitecture approach implements instruction internally translating instructions into RISC86 operations. These RISC86 operations were specially designed include direct support instruction while observing RISC performance principles fixed length encoding, regularized instruction fields, large register set. Enhanced RISC86 microarchitecture used Mobile AMD-K6-III-P processor enables higher processor core performance promotes straightforward extensions, such those added current Mobile AMD-K6-III-P processor those planned future. Instead directly executing complex instructions, which have lengths bytes, Mobile AMD-K6-III-P processor executes simpler easier fixed-length RISC86 operations, while maintaining instruction coding efficiencies found programs. Mobile AMD-K6-III-P processor contains parallel decoders, centralized RISC86 operation scheduler, execution units that support superscalar operation multiple decode, execution, retirement-of instructions. These elements packed into aggressive highly efficient six-stage pipeline. Mobile AMD-K6®-III-P Processor Block Diagram. shown Figure page high-performance, out-of-order execution engine Mobile AMD-K6-III-P processor mated split, level-one, 64-Kbyte, writeback cache with Kbytes instruction cache Kbytes data cache. Backing level-one cache large, unified, level-two, 256-Kbyte, writeback cache. level-one instruction cache feeds decoders and, turn, decoders feed scheduler. issues retires RISC86 operations contained scheduler. system interface industry-standard 64-bit Super7 Socket demultiplexed bus. Mobile AMD-K6-III-P processor combines latest processor microarchitecture provide highest performance today's personal computers. Mobile performance binary software compatibility.
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KByte Level-One Instruction Cache Predecode Logic Entry ITLB KByte Predecode Cache Byte Fetch Level-One Cache Controller Super7Bus Interface Branch Logic Dual Instruction Decoders
RISC86 (8192-Entry BHT) (16-Entry BTC) (16-Entry RAS)
Out-of-Order Execution Engine RISC86® Operation Issue
Four RISC86 Decode Scheduler Buffer
RISC86)
Instruction Control Unit
Branch Resolution Unit
Level-Two Cache
(256 KByte)
Load Unit
Store Unit
Register Unit (Integer/ Multimedia/3DNow!TM)
Register Unit (Integer/ Multimedia/3DNow!)
Floating- Point Unit
Store Queue
Level-One Dual-Port Data Cache
KByte)
Entry DTLB
Figure Mobile AMD-K6®-III-P Processor Block Diagram Decoders. Decoding instructions begins when on-chip level-one instruction cache filled. Predecode logic determines length instruction byte-by-byte basis. This predecode information stored, along with instructions, level-one instruction cache, used later decoders. decoders translate on-the-fly, with additional latency, instructions clock into RISC86 operations. Note: this chapter, "clock" refers processor clock. instructions into three types decodes-short, long, vector. decoders process either short, long, vector decode time. three types decodes have following characteristics: Short decodes-x86 instructions less than equal seven bytes length Long decodes-x86 instructions less than equal bytes length Vector decodes-complex instructions
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Short long decodes processed completely within decoders. Vector decodes started decoders then completed fetched sequences from on-chip ROM. After decoding, RISC86 operations delivered scheduler dispatching executions units. Scheduler/Instruction Control Unit. centraliz scheduler buffer managed Instruction Control Unit (ICU). buffers manages RISC86 operations time. This equals from instructions. This buffer size (24) perfectly matched processor's six-stage RISC86 pipeline four RISC86-operations decode rate. scheduler accepts many four RISC86 operations time from decoders retires four RISC86 operations clock cycle. capable simultaneously issuing RISC86 operations time execution units. This consists following types operations: Memory load operation Memory store operation Complex integer, 3DNow! register operation Simple integer, 3DNow! register operation Floating-point register operation Branch condition evaluation Registers. When managing RISC86 operations, uses physical registers contained within RISC86 microarchitecture. physical registers located general register file grouped committed architectural registers plus rename registers. architectural registers consist scratch registers registers that correspond general-purpose registers- EAX, EBX, ECX, EDX, EBP, ESP, ESI, EDI. There analogous registers specifically 3DNow! architectural registers plus MMX/3DNow! rename registers. architectural registers consist scratch register registers that correspond registers (mm0-mm7). more detailed information, 3DNow!Technology Manual, order# 21928. Branch Logic. Mobile AMD-K6-III-P processor designed with highly sophisticated dynamic branch logic consisting following:
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Branch history/Prediction table Branch target cache Return address stack
Mobile AMD-K6-III-P processor implements two-level branch prediction scheme based 8192-entry branch history table. branch history table stores prediction information that used predicting conditional branches. Because branch history table does store predicted target addresses, special address ALUs calculate target addresses on-the-fly during instruction decode. branch target cache augments predicted branch performance avoiding clock cache-fetch penalty. This specialized target cache does this supplying first bytes target instructions decoders when branches predicted. return address stack unique device specifically designed optimizing AMD-K6-III-P processor uses dynamic branch logic minimize delays branch instructions that common software. 3DNow!Technology. taken lead role improving multimedia capabilities processor family with introduction 3DNow! technology, which uses packed, single-precision, floating-point data format Single Instruction Multiple Data (SIMD) operations based technology model.
Cache, Instruction Prefetch, Predecode Bits
writeback level-one cache Mobile AMD-K6-III-P processor organized separate 32-Kbyte instruction cache 32-Kbyte data cache with two-way associativity. level-two cache Kbytes, organized unified, fourway set-associative cache. cache line size bytes, lines fetched from external memory using efficient pipelined burst transaction. level-one instruction cache filled from level-two cache from external memory, each instruction byte analyzed instruction boundaries using predecoding logic. Predecoding annotates information bits byte) each instruction byte that later enables simultaneously.
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Cache
processor cache design takes advantage sectored organization (see Figure Each sector consists bytes configured 32-byte cache lines. cache lines sector share common have separate pairs MESI (Modified, Exclusive, Shared, Invalid) bits that track state each cache line. forms cache misses associated cache fills take place-a tag-miss cache fill tag-hit cache fill. case tag-miss cache fill, level-one cache miss mismatch, which case required cache line filled either from level-two cache from external memory, level-one cache line within sector that required marked invalid. case tag-hit cache fill, address matches tag, requested cache line marked invalid. required level-one cache line filled from level-two cache from external memory, level-one cache line within sector that required remains same cache state. Mobile AMD-K6-III-P processor conditionally performs cache prefetching which results filling required cache line first, prefetch second cache line making other half sector. From perspective external bus, cache-line fills typically appear 32-byte burst read cycles occurring back-to-back allowed, pipelined cycles. 3DNow! technology includes instruction called PREFETCH that allows cache line prefetched into level-one data cache level-two cache. more detailed information, 3DNow!Technology Manual, order# 21928. Decoding instructions particularly difficult because instructions variable-length from bytes long. Predecode logic supplies five predecode bits that associated with each instruction byte. predecode bits indicate number bytes start next instruction. predecode bits stored extended instruction cache alongside each instruction byte shown Figure predecode bits passed with instruction bytes decoders where they assist with parallel instruction decoding.
Cache Line Byte Predecode Bits Byte Predecode Bits Byte Predecode Bits MESI Bits Cache Line Byte Predecode Bits Byte Predecode Bits Byte Predecode Bits MESI Bits
Prefetching
Predecode Bits
Address
Figure Cache Sector Organization Internal Architecture Chapter
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Instruction Fetch Decode
processor fetch bytes clock levelone instruction cache branch target cache. fetched information placed into 16-byte instruction buffer that feeds directly into decoders (see Figure Fetching occur along single execution stream with seven outstanding branches taken. instruction fetch logic capable retrieving contiguous bytes information within 32-byte boundary. There additional penalty when bytes instructions across cache line boundary. instruction bytes loaded into instruction buffer they consumed decoders. Although instructions consumed with byte memory-aligned word (two bytes) organization. Therefore, instructions loaded replaced with word granularity. When control transfer occurs-such instruction- entire instruction buffer flushed reloaded with instruction bytes.
Bytes 32-Kbyte Level-One Instruction Cache Bytes Branch-Target Cache Bytes
Instruction Fetch
Branch Target Address Adders Return Address Stack Bytes Fetch Unit Instruction Bytes plus Sets Predecode Bits
Instruction Buffer
Figure Instruction Buffer Chapter Internal Architecture
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Instruction Decode
Mobile AMD-K6-III-P processor decode logic designed decode multiple instructions clock (see Figure decode logic accepts instruction bytes their predecode bits from instruction buffer, locates actual instruction boundaries, generates RISC86 operations from these instructions. RISC86 operations fixed-length internal instructions. Most RISC86 operations execute single clock. RISC86 operations combined perform every function instruction set. Some instructions decoded into zero RISC86 operations instance RISC86 operation register-to-register add. More complex instructions decoded into several RISC86 operations.
Instruction Buffer
Short Decoder Short Decoder
Long Decoder On-Chip
Vector Decoder
RISC86® Sequencer
Vector Address
RISC86 Operations
Figure Mobile AMD-K6®-III-P Processor Decode Logic
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Mobile AMD-K6-III-P processor uses combination decoders convert instructions into RISC86 operations. hardware consists three sets decoders-two parallel short decoders, long decoder, vector decoder. parallel short decoders translate most commonly-used instructions moves, shifts, branches, ALU, FPU) extensions instruction (including 3DNow! instructions) into zero, one, RISC86 operations each. short decoders only operate instructions that seven bytes long. addition, they designed commonly-used instructions that greater than seven bytes more than bytes long, semi-commonly-used instructions that seven bytes long handled long decoder. long decoder only performs decode clock generates four RISC86 operations. other translations (complex instructions, serializing conditions, interrupts exceptions, etc.) handled combination vector decoder RISC86 operation sequences fetched from on-chip ROM. complex operations, vector decoder logic provides first RISC86 operations vector (initial address) sequence further RISC86 operations. same types RISC86 operations fetched from those that generated hardware decoders. Note: Although three sets decoders simultaneously copy instruction buffer contents, only three types decoders used during decode clock. decoders on-chip RISC86 always generate group four RISC86 operations. decodes that cannot fill entire group with four RISC86 operations, RISC86 operations placed empty locations grouping. example, long-decoded instruction that converts only three RISC86 operations padded with single RISC86 operation then passed scheduler. groups RISC86 operations placed scheduler time. common, uncommon, floating-point instructions (also known instructions) hardware decoded short decodes. This decode generates RISC86 floating-point operation and, optionally, associated Chapter Internal Architecture
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floating-point load store operation. Floating-point instruction decode only allowed first short decoder, non-ESC instructions decoded simultaneously second short decoder along with instruction decode first short decoder. 3DNow! instructions, with exception EMMS, FEMMS, PREFETCH instructions, hardware decoded short decodes. instruction decode generates RISC86 operation and, optionally, associated load store operation. 3DNow! instruction decode generates RISC86 3DNow! operation and, optionally, associated load store operation. 3DNow! instructions decoded either both short decoders.
Centralized Scheduler
scheduler heart Mobile AMD-K6-III-P processor (see Figure page 15). contains logic necessary manage out-of-order execution, data forwarding, register renaming, simultaneous issue retirement multiple RISC86 operations, speculative execution. scheduler's buffer hold RISC86 operations. This equates maximum instructions. scheduler issue RISC86 operations from locations buffer. When possible, scheduler simultaneously issue RISC86 operation available execution unit (store, load, branch, register integer/multimedia, register integer/multimedia, floating-point). total, scheduler issue retire four RISC86 operations clock. main advantage scheduler operation buffer ability examine instruction window equal instructions time. This advantage fact that scheduler operates RISC86 operations parallel allows Mobile AMD-K6-III-P processor perform dynamic on-the-fly instruction code scheduling optimized execution. Although scheduler issue RISC86 operations out-of-order execution, always retires instructions order.
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From Decode Logic RISC86 RISC86 RISC86 RISC86
Centralized RISC86® Operation Scheduler
RISC86 Issue Buses
RISC86 Operation Buffer
Figure Mobile AMD-K6®-III-P Processor Scheduler
Execution Units
Mobile AMD-K6-III-P processor contains parallel execution units-store, load, integer ALU, integer ALU, (X), (Y), MMX/3DNow! multiplier, 3DNow! ALU, floating-point, branch condition. Each unit independent capable handling RISC86 operations. Table page details execution units, functions performed within these units, operation latency, operation throughput. store load execution units two-stage pipelined designs. store unit performs data writes register calculation LEA/PUSH. Data memory register writes from stores available after clock. Store operations held store queue prior execution. From there, they execute order. load unit performs data memory reads. Data available from load unit after clocks.
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executio unit operat operations, multiplies, divides (signed unsigned), shifts, rotates. Integer execution unit operate basic word doubleword operations ADD, AND, CMP, SUB, XOR, zero-extend sign-extend operands. Table Execution Latency Throughput Execution Units
Function LEA/PUSH, Address (Pipelined) Memory Store (Pipelined) Memory Loads (Pipelined) Integer Integer Integer Multiply Integer Shift Multimedia (processes Shifts, Packs, Unpack instructions) Multiply Integer Branch 3DNow! Basic (16-bit 32-bit operands) Resolves Branch Conditions FADD, FSUB, FMUL 3DNow! 3DNow! Multiply 3DNow! Convert Latency Throughput
Functional Unit Store Load
Register Pipelines
onal that 3DNow! instructions share pipeline control with Integer Integer units. register functional units attached issue register execution pipeline issue register execution pipeline both. Each register pipeline dedicated resources that consist integer execution unit execution unit, therefore allowing superscalar operation integer instructions. addition, both issue buses connected 3DNow! ALU, MMX/3DNow! multiplier shifter, which allows appropriate RISC86 operation issued through either bus. Figure page shows details register pipelines.
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Scheduler Buffer RISC86® Operations) Issue Register Execution Pipeline Issue Register Execution Pipeline
Integer
MMXALU
MMX/ 3DNow!Multiplier
Shifter
3DNow!
Integer
Figure Register Functional Units branch condition unit separate from branch prediction logic that resolves conditional branches such LOOP after branch condition been evaluated.
Branch-Prediction Logic
Sophisticated branch logic that minimize hide impact changes program flow designed into Mobile AMD-K6-III-P processor. Branches code into categories -unconditional branches, which always change program flow (that branches always taken) conditional branches, which divert program flow (that branches taken not-taken). When conditional branch taken, processor simply continues decoding executing next instructions memory. Typical applications have unconditional branches another conditional branches. Mobile AMD-K6-III-P processor branch logic been designed
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handle this type program behavior negative effects instruction execution, such stalls delayed instruction fetching draining processor pipeline. branch logic contains 8192-entry branch history table, 16-entry 16-byte branch target cache, 16-entry return address stack, branch execution unit. Branch History Table Mobile AMD-K6-III-P processor handles unconditional branches without penalty redirecting instruction fetching target address unconditional branch. However, conditional branches require dynamic AMD-K6-III-P processor. two-level adaptive history algorithm implemented 8192-entry branch history table. This table stores executed branch information, predicts individual branches, predicts behavior groups branches. accommodate large branch history table, Mobile AMD-K6-III-P processor does store predicted target addresses. Instead, branch target addresses calculated on-the-fly using ALUs during decode stage. adders calculate possible target addresses before instructions fully decoded processor chooses which addresses valid. avoid clock cache-fetch penalty when branch predicted taken, built-in branch target cache supplies first bytes instructions directly instruction buffer (assuming target address hits this cache). (See Figure page 11.) branch target cache organized entries bytes. total, branch prediction logic achieves branch prediction rates greater than 95%. return address stack special device designed optimize CALL pairs. Software typically compiled with subroutines that frequently called from various places program. This usually done save space. Entry into subroutine occurs with execution CALL instruction. that time, processor pushes address next instruction memory following CALL instruction onto stack (allocated space memory). When processor encounters instruction (within subroutine), branch logic pops address from stack begins fetching from that location. avoid latency
Branch Target Cache
Return Address Stack
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main memory accesses during CALL operations, return address stack caches pushed addresses. Branch Execution Unit branch execution unit enables efficient speculative execution. This unit gives processor ability execute instructions beyond conditional branches before knowing whether branch prediction correct. Mobile AMD-K6-III-P processor does permanently update registers memory locations until speculatively executed conditional branch instructions resolved. When prediction incorrect, processor backs point mispredicted branch instruction restores registers. Mobile AMD-K6-III-P processor support seven outstanding branches.
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Logic Symbol Diagram
Clock Voltage Detection
BF[2:0]
VCC2DET VCC2H/L#
Arbitration
AHOLD BOFF# BREQ HLDA HOLD
BRDY# BRDYC# D[63:0] DP[7:0] PCHK#
Data Data Parity
Address Address Parity
A20M# A[31:3] ADS# ADSC# APCHK# BE[7:0]#
EADS# HIT# HITM#
Inquire Cycles
Cycle Definition Control
D/C# EWBE# LOCK# M/IO# SCYC W/R#
Mobile AMD-K6®-III-P
Processor
FERR# IGNNE#
Floating-Point Error Handling
Cache Control
CACHE# KEN# WB/WT#
FLUSH# INIT INTR RESET SMI# SMIACT# STPCLK#
External Interrupts, SMM, Reset Initialization
TRST#
JTAG Test
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Logic Symbol Diagram
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Logic Symbol Diagram
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Signal Name A20M#
Signal Descriptions
Location AK-08
Attribute Input Address Mask
Name Summary A20M# used simulate behavior 8086 when running Real mode. assertion A20M# causes processor force physical address prior accessing cache driving memory cycle. clearing address maps addresses that wrap above Mbyte addresses below Mbyte.
A[31:3]
"Pin A31-A5: Bidirectional Designations A4-A3: Output Functional Grouping" page AJ-05 Output
Address A[31:3] contains physical address current cycle. processor drives addresses A[31:3] during memory cycles, cycle definition information during special cycles. processor samples addresses A[31:5] during inquire cycles. Address Strobe assertion ADS# indicates beginning cycle. address cycle definition signals corresponding this cycle driven valid same clock edge ADS#.
ADS#
ADSC#
AM-02
Output
Address Strobe Copy ADSC# identical function timing ADS#. event ADS# becomes heavily loaded large fanout system, ADSC# used split load across outputs, which improves timing.
AHOLD
V-04
Input
Address Hold AHOLD asserted system initiate more inquire cycles. allow system drive address during inquire cycle, processor floats A[31:3] clock edge which AHOLD sampled asserted. data other control status signals remain under control processor floated.
AK-02
Bidirectional
Address Parity contains even parity cache line addresses driven sampled A[31:5]. term even parity means that total number bits A[31:5] even. used generation checking address parity because these bits required address cache line.)
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Signal Name APCHK#
Location AE-05
Attribute Output Address Parity Check
Name Summary processor detects address parity error during inquire cycle, APCHK# asserted clock.
BE[7:0]#
"Pin Output Designations Functional Grouping" page
Byte Enables BE[7:0]# used processor indicate valid data bytes during write cycle requested data bytes during read cycle. eight byte enables correspond eight bytes data follows:
BE7#: D[63:56] BE6#: D[55:48] BE5#: D[47:40] BE4#: D[39:32]
BE3#: D[31:24] BE2#: D[23:16] BE1#: D[15:8] BE0#: D[7:0]
byte enables also used distinguish between special cycles defined Table page BF[2:0] "Pin Inputs, Designations Internal Pullups Functional Grouping" page Frequency BF[2:0] determine internal operating frequency processor. frequency input signal multiplied internally ratio determined state these signals shown below: State BF[2:0] Inputs 100b 101b 111b 010b 000b 001b 011b 110b Processor-Clock Bus-Clock Ratio 2.5x 3.0x 3.5x 4.0x 4.5x 5.0x 5.5x 6.0x
BF[2:0] have weak internal pullups default ratio left unconnected.
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Signal Name BOFF#
Location Z-04
Attribute Input Backoff
Name Summary BOFF# sampled asserted, processor unconditionally aborts cycles progress transitions hold state floating following signals: A[31:3], ADS#, ADSC#, BE[7:0]#, CACHE#, D[63:0], D/C#, DP[7:0], LOCK#, M/IO#, PCD, PWT, SCYC, W/R#. These signals remain floated until BOFF# sampled negated. This allows alternate master system control bus.
BRDY#
X-04
Input, Internal Pullup
Burst Ready BRDY# asserted processor system logic indicate either that data being driven with valid data during read cycle that data been latched during write cycle. BRDY# also used indicate completion special cycles. Burst Ready Copy BRDYC# identical function BRDY#. event BRDY# becomes heavily loaded large fanout system, BRDYC# used reduce this loading, which improves timing. Request BREQ asserted processor request order complete internally pending cycle. system logic BREQ arbitrate among participants.
BRDYC#
Y-03
Input, Internal Pullup
BREQ
AJ-01
Output
CACHE#
U-03
Output
Cacheable Access reads, CACHE# asserted indicate cacheability current cycle. write cycles, CACHE# asserted indicate current cycle modified cache-line writeback.
AK-18
Input
Clock signal clock processor reference signal timings under normal operation.
D/C#
AK-04
Output
Data/Code processor drives D/C# during memory cycle indicate whether addressing data executable code. D/C# also used define other cycles, including interrupt acknowledge special cycles.
D[63:0]
"Pin Bidirectional Designations Functional Grouping" page
Data D[63:0] represent processor's 64-bit data bus. Each eight bytes data that comprise this qualified corresponding byte enable.
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Signal Name DP[7:0]
Location
Attribute Data Parity
Name Summary DP[7:0] even parity bits each valid byte data-as defined BE[7:0]#-driven sampled D[63:0] data bus. processor detects parity valid byte data during read cycle, PCHK# asserted. eight data parity bits correspond eight bytes data follows:
"Pin Bidirectional Designations Functional Grouping" page
DP7: D[63:56] DP6: D[55:48] DP5: D[47:40] DP4: D[39:32]
DP3: D[31:24] DP2: D[23:16] DP1: D[15:8] DP0: D[7:0]
systems that support data parity, DP[7:0] should connected VCC3 through pullup resistors. EADS# AM-04 Input External Address Strobe System logic asserts EADS# during cache inquire cycle indicate that address contains valid address. EWBE# W-03 Input External Write Buffer Empty system logic negate EWBE# processor indicate that external write buffers full that additional data cannot stored this time. This causes processor delay following activities until EWBE# sampled asserted:
commitment write cycles cache lines modified state exclusive state processor's cache decode execution instruction that follows currently-executing serializing instruction assertion negation SMIACT# entering Halt state Stop Grant state
FERR#
Q-05
Output
Floating-Point Error assertion FERR# indicates occurrence unmasked floating-point exception resulting from execution floating-point instruction.
Signal Descriptions
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Signal Name FLUSH#
Location AN-07
Attribute Input Cache Flush
Name Summary response sampling FLUSH# asserted, processor writes back cache lines data cache cache that modified state, invalidates lines caches, then executes flush acknowledge special cycle. addition, FLUSH# sampled when RESET negated determine processor enters Tri-State Test mode.
HIT#
AK-06
Output
Inquire Cycle processor asserts HIT# during inquire cycle indicate that cache line valid within processor's and/or caches (also known cache hit).
HITM#
AL-05
Output
Inquire Cycle Modified Line processor asserts HITM# during inquire cycle indicate that cache line exists processor's data cache cache modified state. processor performs writeback cycle result this cache hit.
HLDA
AJ-03
Output
Hold Acknowledge When HOLD sampled asserted, processor completes current cycles, floats processor bus, asserts HLDA acknowledgment that these events have been completed. following signals floated when HLDA asserted: A[31:3], ADS#, ADSC#, BE[7:0]#, CACHE#, D[63:0], D/C#, DP[7:0], LOCK#, M/IO#, PCD, PWT, SCYC, W/R#.
HOLD
AB-04
Input
Hold Request system logic assert HOLD gain control processor's bus. When HOLD sampled asserted, processor completes current cycles, floats processor bus, asserts HLDA acknowledgment that these events have been completed.
IGNNE#
AA-35
Input
Ignore Numeric Exception IGNNE# used external logic control effect unmasked floating-point exception. Under certain circumstances, IGNNE# sampled asserted, processor ignores floating-point exception.
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Signal Name INIT
Location AA-33
Attribute Input Initialization
Name Summary assertion INIT causes processor flush pipelines, initialize most internal state, branch address FFFF_FFF0h-the same instruction execution starting point used after RESET. Unlike RESET, processor preserves contents caches, floating-point state, state, model-specific registers, bits register, other specific internal resources.
INTR
AD-34
Input
Maskable Interrupt INTR system's maskable interrupt input processor. When processor samples recognizes INTR asserted, processor executes pair interrupt acknowledge cycles then jumps interrupt service routine specified interrupt number that returned during interrupt acknowledge sequence.
U-05
Input
Invalidation Request During inquire cycle, state determines whether addressed cache line that found processor's and/or caches transitions invalid state shared state.
KEN#
W-05
Input
Cache Enable KEN# sampled asserted, indicates that address presented processor cacheable. Otherwise, single-transfer cycle executed processor does cache data. KEN# ignored during writebacks.
LOCK#
AH-04
Output
Lock processor asserts LOCK# during sequence cycles ensure that cycles completed without allowing other masters intervene.
M/IO#
T-04
Output
Memory processor drives M/IO# during cycle indicate whether addressing memory space. M/IO# used define other cycles, including interrupt acknowledge special cycles.
Y-05
Input
Next Address System logic asserts indicate processor that ready accept another address pipelined into previous cycle.
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Signal Name
Location AC-33
Attribute Input
Name Summary Non-Maskable Interrupt When sampled asserted, processor jumps interrupt service routine defined interrupt number 02h. Unlike INTR signal, software cannot mask effect sampled asserted processor.
AG-05
Output
Page Cache Disable processor drives indicate operating system's specification cacheability page being addressed. System logic control external caching.
PCHK#
AF-04
Output
Parity Check processor asserts PCHK# during read cycles detects even parity error more valid bytes D[63:0] during read cycle.
AL-03
Output
Page Writethrough processor drives indicate operating system's specification writeback state writethrough state page being addressed. PWT, together with WB/WT#, specifies data cache-line state during cacheable read misses write hits shared cache lines.
RESET
AK-20
Input
Reset When processor samples RESET asserted, immediately flushes initializes internal resources internal state including pipelines caches, floating-point state, state, registers, then processor jumps address FFFF_FFF0h start instruction execution. FLUSH# sampled during falling transition RESET invoke Tri-State Test mode.
RSVD
"Pin Designations Functional Grouping" page
Reserved Reserved signals special class pins that treated following ways:
no-connect (NC) pins, which case these pins left unconnected pins connected system logic defined industry-standard Super7 Socket interface combination Socket pins
SCYC
AL-17
Output
Split Cycle processor asserts SCYC during misaligned, locked transfers D[63:0] data bus.
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Signal Name SMI#
Location AB-34
Attribute Input, Internal Pullup
Name Summary System Management Interrupt assertion SMI# causes processor enter System Management Mode (SMM). Upon recognizing SMI#, processor performs following actions, order shown: Flushes instruction pipelines. Completes pending in-progress cycles. Acknowledges interrupt asserting SMIACT# after sampling EWBE# asserted EWBE# masked off, then SMIACT# affected EWBE#). Saves internal processor state memory. Disables interrupts. Jumps entry point service routine.
SMIACT#
AG-03
Output
System Management Interrupt Active processor acknowledges assertion SMI# with assertion SMIACT# indicate that processor entered System Management Mode (SMM).
STPCLK#
V-34
Input, Internal Pullup
Stop Clock assertion STPCLK# causes processor enter Stop Grant state, during which processor's internal clock stopped. From Stop Grant state, processor subsequently transition Stop Clock state, which clock stopped. Upon recognizing STPCLK#, processor performs following actions, order shown: Flushes instruction pipelines. Completes pending in-progress cycles. Acknowledges STPCLK# assertion executing Stop Grant special cycle (see Table page 34). Stops internal clock after BRDY# Stop Grant special cycle sampled asserted after EWBE# sampled asserted EWBE# masked off, then entry into Stop Grant state affected EWBE#). Enters Stop Clock state system logic stops clock (optional).
M-34
Input, Internal Pullup
Test Clock clock boundary-scan testing using Test Access Port (TAP).
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Signal Name
Location N-35
Attribute Input, Internal Pullup Test Data Input
Name Summary serial test data instruction input boundary-scan testing using Test Access Port (TAP). Test Data Output serial test data instruction output boundary-scan testing using Test Access Port (TAP).
N-33
Output
P-34
Input, Internal Pullup
Test Mode Select specifies test function sequence state changes boundary-scan testing using Test Access Port (TAP). Test Reset assertion TRST# initializes Test Access Port (TAP) resetting state machine Test-Logic-Reset state. VCC2 Detect VCC2DET tied (logic level indicate system logic that must supply specified dual-voltage requirements VCC2 VCC3 pins.
TRST#
Q-33
Input, Internal Pullup
VCC2DET
AL-01
Output
VCC2H/L#
AN-05
Output
VCC2 High/Low VCC2H/L# tied (logic level indicate system logic that must supply specified processor core voltage VCC2 pins.
W/R#
AM-06
Output
Write/Read processor drives W/R# indicate whether performing write read cycle bus. addition, W/R# used define other cycles, including interrupt acknowledge special cycles.
WB/WT#
AA-05
Input
Writeback Writethrough WB/WT#, together with PWT, specifies data cache-line state during cacheable read misses write hits shared cache lines.
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Table Input Types
Name A20M# AHOLD BF[2:0] BOFF# BRDY# BRDYC# EADS# EWBE# FLUSH# HOLD
Notes:
Type Asynchronous Synchronous Synchronous Synchronous Synchronous Synchronous Clock Synchronous Synchronous Asynchronous Synchronous
Note Note Note INIT INTR
Name IGNNE#
Type Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous
Note Note Note Note
KEN# RESET SMI# Note STPCLK# WB/WT#
Note Note Note Note
These level-sensitive signals asserted synchronously asynchronously. sampled specific clock edge, setup hold times must met. asserted asynchronously, they must asserted minimum pulse width clocks. These edge-sensitive signals asserted synchronously asynchronously. sampled specific clock edge, setup hold times must met. asserted asynchronously, they must have been negated least clocks prior assertion must remain asserted least clocks. FLUSH# also sampled during falling transition RESET asserted synchronously asynchronously. sampled specific clock edge, setup hold times must clock edge before clock edge which RESET sampled negated. asserted asynchronously, FLUSH# must meet minimum setup hold time clocks relative negation RESET. BF[2:0] sampled during falling transition RESET. They must meet minimum setup time minimum hold time clocks relative negation RESET. During initial power-on reset processor, RESET must remain asserted minimum after reach specification before negated. During warm reset, while within their specification, RESET must remain asserted minimum clocks prior negation.
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Table Output Float Conditions
Name A[4:3] ADS# ADSC# APCHK# BE[7:0]# BREQ CACHE# D/C# FERR# HIT# HITM#
Notes:
Floated (Note HLDA, AHOLD, BOFF# HLDA, BOFF# HLDA, BOFF# Always Driven HLDA, BOFF# Always Driven HLDA, BOFF# HLDA, BOFF# Always Driven Always Driven Always Driven
Note Note Note Note Note Note Note
Name HLDA LOCK# M/IO# PCHK# SCYC SMIACT# VCC2DET VCC2H/L# W/R#
Floated (Note Always Driven HLDA, BOFF# HLDA, BOFF# HLDA, BOFF# Always Driven HLDA, BOFF# HLDA, BOFF# Always Driven Always Driven Always Driven HLDA, BOFF#
Note Note Note Note Note Note
Note
outputs except VCC2DET, VCC2H/L#, float during Tri-State Test mode. Floated clock edge that BOFF# sampled asserted clock edge that HLDA asserted. Floated clock edge that AHOLD sampled asserted.
Table Input/Output Float Conditions
Name A[31:5] D[63:0] DP[7:0]
Notes:
Floated (Note HLDA, AHOLD, BOFF# HLDA, AHOLD, BOFF# HLDA, BOFF# HLDA, BOFF#
Note Note Note Note Note
outputs except VCC2DET float during Tri-State Test mode. Floated clock edge that BOFF# sampled asserted clock edge that HLDA asserted. Floated clock edge that AHOLD sampled asserted.
Table Test Pins
Name TRST# Type Clock Input Output Input Input Sampled rising edge Driven falling edge Sampled rising edge Asynchronous (Independent TCK) Note
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Table Cycle Definition
Cycle Initiated M/IO# Code Read, Instruction Cache Line Fill Code Read, Noncacheable Code Read, Noncacheable Encoding Special Cycle Interrupt Acknowledge Read Write Memory Read, Data Cache Line Fill Memory Read, Noncacheable Memory Read, Noncacheable Memory Write, Data Cache Writeback Memory Write, Noncacheable
Note:
Generated D/C# W/R# CACHE#
Generated System Logic KEN#
means "don't care"
Table Special Cycles
CACHE# M/IO# W/R# Special Cycle Stop Grant Flush Acknowledge (FLUSH# sampled asserted) Writeback (WBINVD instruction) Halt Flush (INVD, WBINVD instruction) Shutdown
Note:
means "don't care"
Signal Descriptions
Chapter
KEN#
BE7#
BE6#
BE5#
BE4#
BE3#
BE2#
BE1#
BE0#
D/C#
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Mobile AMD-K6®-III-P Processor Operation
Process Technology
Mobile AMD-K6-III-P processor implemented using advanced CMOS process technology that utilizes split core voltage supply, which allows core processor operate voltage while portion operates industry-standard volts. This technology enables high performance while reducing power consumption operating core voltage limiting power requirements acceptable levels today's mobile PCs.
Clock Control
Mobile AMD-K6-III-P processor supports five modes clock control. processor transition between these dissipation, provide balance between performance power. (See "Power Dissipation" page maximum power dissipation Mobile AMD-K6-III-P within normal reduced-power states.) five clock-control states supported follows:
Normal State: processor running Real Mode, Virtual-8086 Mode, Protected Mode, System Management Mode (SMM). this state, clocks running- including external clock internal processor clock-and full features functions processor available. Halt State: This low-power state entered following successful execution instruction. During this state, internal processor clock stopped. Stop Grant State: This low-power state entered following recognition assertion STPCLK# signal. During this state, internal processor clock stopped. Stop Grant Inquire State: This state entered from Halt state Stop Grant state result system-initiated inquire cycle. Stop Clock State: This low-power state entered from Stop Grant state when signal stopped. Mobile AMD-K6®-III-P Processor Operation
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following sections describe each four low-power states. Figure page illustrates clock control state transitions. Halt State Enter Halt State. During execution instruction, Mobile AMD-K6-III-P processor executes Halt special cycle. After BRDY# sampled asserted during this cycle, then EWBE# also sampled asserted masked off), processor enters Halt state which processor disables most internal clock distribution. order support following operations, internal phase-lock loop (PLL) continues run, some internal resources still clocked Halt state:
Inquire Cycles: processor continues sample AHOLD, BOFF#, HOLD order support inquire cycles that initiated system logic. processor transitions Stop Grant Inquire state during inquire cycle. After returning Halt state following inquire cycle, processor does execute another Halt special cycle. Flush Cycles: processor continues sample FLUSH#. FLUSH# sampled asserted, processor performs flush operation same manner performed Normal state. Upon completing flush operation, processor executes Halt special cycle which indicates processor Halt state. Time Stamp Counter (TSC): continues count Halt state. Signal Sampling: processor continues sample INIT, INTR, NMI, RESET, SMI#.
After entering Halt state, signals driven processor retain their state they existed following completion Halt special cycle. Exit Halt State. Mobile AMD-K6-III-P processor remains Halt state until samples INIT, INTR interrupts enabled), NMI, RESET, SMI# asserted. these signals sampled asserted, processor returns Normal state performs corresponding operation. normal requirements recognition these input signals apply within Halt state.
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Stop Grant State
Enter Stop Grant State. STPCLK#, Mobile AMD-K6-III-P processor flushes instruction pipelines, completes pending in-progress cycles, acknowledges STPCLK# assertion executing Stop Grant special cycle. After BRDY# sampled asserted during this cycle, after EWBE# also sampled asserted masked off), processor enters Stop Grant state. Stop Grant state like Halt state ssor disables inter clock distribution Stop Grant state. order support following operations, internal still runs, some internal resources still clocked Stop Grant state:
Inquire cycles: processor transitions Stop Grant Inquire state during inquire cycle. After returning Stop Grant state following inquire cycle, processor does execute another Stop Grant special cycle. Time Stamp Counter (TSC): continues count Stop Grant state. Signal Sampling: processor continues sample INIT, INTR, NMI, RESET, SMI#.
FLUSH# recognized Stop Grant state (unlike while Halt state). Upon entering Stop Grant state, signals driven processor retain their state they existed following completion Stop Grant special cycle. Exit Stop Grant State. Mobile AMD-K6-III-P processor remains Stop Grant state until samples STPCLK# negated RESET asserted. STPCLK# sampled negated, processor returns Normal state less than clock (CLK) periods. After transition Normal state, processor resumes execution instruction boundary which STPCLK# initially recognized. STPCLK# recognized negated Stop Grant state subsequently sampled asserted prior returning Normal state, minimum instruction executed prior re-entering Stop Grant state. INIT, INTR interrupts enabled), FLUSH#, NMI, SMI# sampled asserted Stop Grant state, processor latches edge-sensitive signals (INIT, FLUSH#, Chapter Mobile AMD-K6®-III-P Processor Operation
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NMI, SMI#), otherwise does exit Stop Grant state service interrupt. When processor returns Normal state sampling STPCLK# negated, pending interrupts recognized after returning Normal state. ensure their recognition, normal requirements these input signals apply within Stop Grant state. RESET sampled asserted Stop Grant state, processor immediately returns Normal state reset process begins. Stop Grant Inquire State Enter Stop Grant Inquire State. Stop Grant Inquire state entered from Stop Grant state Halt state when EADS# sampled asserted during inquire cycle initiated system logic. Mobile AMD-K6-III-P processor responds inquire cycle same manner Normal state driving HIT# HITM#. inquire cycle hits modified cache line, processor performs writeback cycle. Exit Stop Grant Inquire State. Follow completion writeback, processor returns state from which entered Stop Grant Inquire state. Stop Clock State Enter Stop Clock State. signal stopped while Mobile AMD-K6-III-P processor Stop Grant state, processor enters Stop Clock state. Because internal clocks running Stop Clock state, Stop Clock state represents minimum-power state clock control states. signal must held while stopped. Stop Clock state cannot entered from Halt state. INTR only input signal that allowed change states while processor Stop Clock state. However, INTR sampled until processor returns Stop Grant state. other input signals must remain unchanged Stop Clock state. Exit Stop Clock State. Mobile AMD-K6-III-P processor returns Stop Grant state from Stop Clock state after signal started internal stabilized. stabilization achieved after signal been running within specification minimum
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frequency when exiting Stop Clock state different than frequency when entering Stop Clock state. state BF[2:0] signals when exiting Stop Clock state ignored because BF[2:0] signals only sampled during falling transition RESET.
Instruction RESET, SMI#, INIT, INTR Asserted
Normal Mode
Real Virtual-8086 Protected
STPCLK# Asserted STPCLK# Negated, RESET Asserted
Halt State
EADS# Asserted
Writeback Completed
Stop Grant Inquire State
EADS# Asserted
Stop Grant State
Writeback Completed
Started
Stopped
Stop Clock State
Figure Clock Control State Transitions
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Overview
System Management Mode (SMM)
alternate operating mode entered system management interrupt (SMI) handled interrupt service routine. designed system control activities transparent conventional operating systems like Windows. primarily targeted Basic Input Output System (BIOS) specialized low-level device drivers. code data stored memory area, which isolated from main memory. processor enters system logic's assertion SMI# interrupt processor's acknowledgment assertion SMIACT#. this point processor saves state into memory state-save area jumps service routine. processor returns from when executes (resume) instruction from within service routine. Subsequently, processor restores state from save area, negates SMIACT#, resumes execution with instruction following point where entered SMM. following sections summarize state-save area, entry into exit from SMM, exceptions interrupts SMM, memory allocation addressing SMM, SMI# SMIACT# signals.
Operating Mode Default Register Values
software environment within following characteristics:
Addressing operation Real mode 4-Gbyte segment limits Default 16-bit operand, address, stack sizes, although instruction prefixes override these defaults Control transfers that override default operand size truncate bits jumps calls cannot transfer control segment with base address requiring more than bits, Real mode segment-base addressing A20M# masked Interrupt vectors Real-mode interrupt vector table flag EFLAGS cleared (INTR recognized) Mobile AMD-K6®-III-P Processor Operation Chapter
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flag EFLAGS cleared INIT interrupts disabled Debug register cleared (debug traps disabled)
Figure shows default memory area. -Kbyt 0003_FFFFh, which Kbytes (0003_8000h 0003_FFFFh) must populated with RAM. default code-segment (CS) base address area-called base address-is 0003_0000h. bytes (0003_FE00h 0003_FFFFh) contain fill-down state-save area. default entry point service routine 0003_8000h.
Fill Down
State-Save Area
0003_FFFFh
0003_FE00h
32-Kbyte Minimum
Service Routine Service Routine Entry Point 0003_8000h
Base Address (CS)
0003_0000h
Figure Memory
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Table shows initial state registers when entering SMM. Table Initial State Registers
Registers General Purpose Registers EFLAGs GDTR, LDTR, IDTR, TSSR, unmodified 0000_0002h cleared (bits 31). other bits unmodified. 0000_0400h unmodified 0000_8000h 0003_0000h 0000_0000h Initial State
State-Save Area
When processor acknowledges SMI# interrupt asserting SMIACT#, saves state 512-byte state-save area shown Table save begins memory area (SMM base address FFFFh) fills down base address FE00h. Table shows offsets state-save area relative base address. service routine alter read/write values state-save area. Table State-Save Area
Address Offset FFFCh FFF8h FFF4h FFF0h FFECh FFE8h FFE4h FFE0h FFDCh FFD8h
Notes:
Contents Saved EFLAGS
data dump that address Only contains information SMI# asserted during valid cycle.
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Table State-Save Area (continued)
Address Offset FFD4h FFD0h FFCCh FFC8h FFC4h FFC0h FFBCh FFB8h FFB4h FFB0h FFACh FFA8h FFA4h FFA0h FF9Ch FF98h FF94h FF90h FF8Ch FF88h FF84h FF80h FF7Ch FF78h FF74h FF70h FF6Ch FF68h FF64h FF60h FF5Ch
Notes:
Contents Saved LDTR Base Trap Dword Trap EIP* Base Limit Base Limit Attr Base Limit High Attr Base Limit Attr
data dump that address Only contains information SMI# asserted during valid cycle.
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Table State-Save Area (continued)
Address Offset FF58h FF54h FF50h FF4Ch FF48h FF44h FF40h FF3Ch FF38h FF34h FF30h FF2Ch FF28h FF24h FF20h FF1Ch FF18h FF14h FF10h FF0Ch FF08h FF04h FF02h FF00h FEFCh FEF8h FEF7h-FE00h
Notes:
Contents Saved Base Limit Attr Base Limit Attr Base Limit Attr Base Limit Attr Base Limit restart ESI* restart ECX* restart EDI* HALT Restart Slot Trap Restart Slot RevID BASE
data dump that address Only contains information SMI# asserted during valid cycle.
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Revision Identifier
revision identifier offset FEFCh state-save area specifies version extensions that available processor. revision identifier fields follows:
Bits 31-18-Reserved 17-SMM base address relocation enabled) 16-I/O trap restart enabled) Bits 15-0- revision level Mobile AMD-K6-III-P processor 0002h
Table shows format Revision Identifier. Table Revision Identifier
31-18 Reserved Base Relocation Trap Extension 15-0 Revision Level 0002h
Base Address
During RESET, processor sets base address code-segment (CS) memory area-the base address-to default, 0003_0000h. base address offset FEF8h state-save area changed service routine address that aligned 32-Kbyte boundary. (Locations aligned 32-Kbyte boundary cause processor enter Shutdown state when executing instruction.) some operating environments desirable relocate 64-Kbyte memory area high memory area order provide more memory legacy software. During system initialization, base 64-Kbyte memory area relocated BIOS. relocate base address, system enters handler default address. This handler changes base address location state-save area, copies handler location, exits SMM. next time entered, processor saves state base address. This address used every entry until base address state-save area changed hardware reset occurs.
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Halt Restart Slot
During entry into SMM, halt restart slot offset FF02h state-save area indicates entered from Halt state. Before returning from SMM, halt restart slot (offset FF02h) written service routine specify whether return from takes processor back Halt state next instruction after instruction. Upon entry into SMM, halt restart slot defined follows:
Bits 15-1-Reserved 0-Point entry SMM: entered from Halt state entered from Halt state
After entry into handler before returning from SMM, halt restart slot written using following definition:
Bits 15-1-Reserved 0-Point return when exiting from SMM: return Halt state return next instruction after instruction
return from takes processor back Halt state, instruction re-executed, Halt special cycle driven after return. Trap Dword assertion SMI# recognized during execution instruction, trap dword offset FFA4h state-save area contains information about instruction. fields trap dword configured follows:
Bits 31-16-I/O port address Bits 15-4-Reserved 3-REP (repeat) string operation string, string) 2-I/O string operation string, string) 1-Valid instruction valid, invalid) 0-Input output instruction INx, OUTx)
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Table shows format trap dword. Table Trap Dword Configuration
31-16 Port Address 15-4 Reserved String Operation String Operation Valid Instruction Input Output
trap dword related trap restart slot (see "I/O Trap Restart Slot" page 47). trap dword processor, means that SMI# asserted during execution instruction. handler tests there valid instruction trapped. instruction valid, handler required ensure trap restart slot properly. trap restart slot informs whether should re-execute instruction after execute instruction following trapped instruction. Note: SMI# sampled asserted during cycle minimum three clock edges before BRDY# sampled asserted, associated instruction guaranteed trapped handler. Trap Restart Slot trap restart slot offset FF00h state-save area specifies whether trapped instruction should re-executed return from SMM. This slot state-save area called instruction restart function. Re-executing trapped instruction useful, example, write occurs disk that powered down. system logic monitoring such access assert SMI#. Then service routine would query system logic, detect failed write, take action power-up device, enable trap restart slot feature, return from SMM. fields trap restart slot defined follows:
Bits 31-16-Reserved Bits 15-0-I/O instruction restart return from SMM: 0000h execute next instruction after trapped instruction 00FFh re-execute trapped instruction
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Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Table shows format trap restart slot. Table Trap Restart Slot
31-16 Reserved
15-0 Instruction restart return from SMM: 0000h execute next instruction after trapped 00FFh re-execute trapped instruction
processor initializes trap restart slot 0000h upon entry into SMM. entered trapped instruction, processor indicates validity instruction setting clearing trap dword offset FFA4h state-save area. service routine should test trap dword determine valid instruction being executed when entering before writing trap restart slot. instruction valid, service routine safely rewrite trap restart slot with value 00FFh, which causes processor re-execute trapped instruction instruction executed. instruction invalid, writing trap restart slot undefined results. second SMI# asserted valid instruction trapped first handler, services second SMI# prior re-executing trapped instruction. second entry into never trap dword set, second service routine must rewrite trap restart slot. During simultaneous SMI# instruction trap debug breakpoint trap, Mobile AMD-K6-III-P processor first responds SMI# postpones recognizing debug exception until after returning from instruction. debug registers DR3-DR0 used while SMM, they must saved restored handler. processor automatically saves restores DR7-DR6. trap restart slot state-save area contains value 00FFh when instruction executed, debug trap does occur until after instruction re-executed.
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Exceptions, Interrupts, Debug
During SMI# trap, exception/interrupt priority Mobile AMD-K6-III-P processor changes from normal priority. normal priority places debug traps priority higher than sampling FLUSH# SMI# signals. However, during SMI# trap, sampling FLUSH# SMI# signals takes precedence over debug traps. processor recognizes assertion within immediately after completion IRET instruction. Once recognized within SMM, recognition remains enabled until exited, which point masking restored state before entering SMM.
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Mobile AMD-K6®-III-P Processor Operation
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Mobile AMD-K6®-III-P Processor Operation
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Signal Switching Characteristics
characteristics presented Table through Table Valid delay, float, setup, hold timing specifications listed. These specifications provided system designer determine timings necessary processor interface with system logic met. Table Table contain switching characteristics input. Table through Table contain timings normal operation signals. Table Table contain timings RESET configuration signals. Table Table contain timings test operation signals. signal timings provided are:
Measured between CLK, TCK, RESET corresponding signal V-this applies input output signals that switching from High, from High Based input signals applied slew rate V/ns between (rising) (falling) Valid within operating ranges given "Operating Ranges" page Based load capacitance (CL)
Switching Characteristics
Table Table contain switching characteristics input Mobile AMD-K6-III-P processor 100-MHz 66-MHz operation, respectively, measured voltage levels indicated Figure page Period Stability specifies variance (jitter) allowed between successive periods input measured This parameter must considered elements clock skew between Mobile AMD-K6-III-P system logic.
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Signal Switching Characteristics
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Clock Switching Characteristics 100-MHz Operation
Preliminary Data 33.3 10.0 0.15 0.15 Note
Table Switching Characteristics 100-MHz Operation
Symbol Parameter Description Frequency
Note:
Figure
Comments Normal Mode Normal Mode
Period High Time Time Fall Time Rise Time Period Stability
Jitter frequency power spectrum peaking must occur frequencies greater than (Frequency CLK)/3 less than kHz.
Clock Switching Characteristics 66-MHz Operation
Table Switching Characteristics 66-MHz Operation
Symbol Parameter Description Frequency
Note:
Preliminary Data 33.3 15.0 0.15 0.15 66.6 30.0
Figure
Comments Normal Mode
Period High Time Time Fall Time Rise Time Period Stability
Normal Mode
Note
Jitter frequency power spectrum peaking must occur frequencies greater than (Frequency CLK)/3 less than KHz.
Signal Switching Characteristics
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Figure Waveform
Valid Delay, Float, Setup, Hold Timings
Valid delay float timings given output signals during functional operation given relative rising edge CLK. During boundary-scan testing, valid delay float timings output signals with respect falling edge TCK. maximum valid delay timings provided allow system designer determine setup times system logic met. Likewise, minimum valid delay timings used analyze hold times system logic. setup hold requirements Mobile AMD-K6-III-P processor input signals must system logic assure proper operation processor. setup hold timings during functional boundary-scan test mode given relative rising edge TCK, respectively.
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Output Delay Timings 100-MHz Operation
Preliminary Data
Table Output Delay Timings 100-MHz Operation
Symbol Parameter Description A[31:3] Valid Delay A[31:3] Float Delay ADS# Valid Delay ADS# Float Delay ADSC# Valid Delay ADSC# Float Delay Valid Delay Float Delay APCHK# Valid Delay BE[7:0]# Valid Delay BE[7:0]# Float Delay BREQ Valid Delay CACHE# Valid Delay CACHE# Float Delay D/C# Valid Delay D/C# Float Delay D[63:0] Write Data Valid Delay D[63:0] Write Data Float Delay DP[7:0] Write Data Valid Delay DP[7:0] Write Data Float Delay FERR# Valid Delay HIT# Valid Delay HITM# Valid Delay HLDA Valid Delay LOCK# Valid Delay LOCK# Float Delay M/IO# Valid Delay M/IO# Float Delay Figure Comments
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Table Output Delay Timings 100-MHz Operation (continued)
Symbol Parameter Description Valid Delay Float Delay PCHK# Valid Delay Valid Delay Float Delay SCYC Valid Delay SCYC Float Delay SMIACT# Valid Delay W/R# Valid Delay W/R# Float Delay Preliminary Data Figure Comments
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Input Setup Hold Timings 100-MHz Operation
Preliminary Data
Table Input Setup Hold Timings 100-MHz Operation
Symbol
Notes:
Parameter Description A[31:5] Setup Time A[31:5] Hold Time A20M# Setup Time A20M# Hold Time AHOLD Setup Time AHOLD Hold Time Setup Time Hold Time BOFF# Setup Time BOFF# Hold Time BRDY# Setup Time BRDY# Hold Time BRDYC# Setup Time BRDYC# Hold Time D[63:0] Read Data Setup Time D[63:0] Read Data Hold Time DP[7:0] Read Data Setup Time DP[7:0] Read Data Hold Time EADS# Setup Time EADS# Hold Time EWBE# Setup Time EWBE# Hold Time FLUSH# Setup Time FLUSH# Hold Time
Figure
Comments
Note Note
Note Note
These level-sensitive signals asserted synchronously asynchronously. sampled specific clock edge, setup hold times must met. asserted asynchronously, they must asserted minimum pulse width clocks. These edge-sensitive signals asserted synchronously asynchronously. sampled specific clock edge, setup hold times must met. asserted asynchronously, they must have been negated least clocks prior assertion must remain asserted least clocks.
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Table Input Setup Hold Timings 100-MHz Operation (continued)
Symbol
Notes:
Parameter Description HOLD Setup Time HOLD Hold Time IGNNE# Setup Time IGNNE# Hold Time INIT Setup Time INIT Hold Time INTR Setup Time INTR Hold Time Setup Time Hold Time KEN# Setup Time KEN# Hold Time Setup Time Hold Time Setup Time Hold Time SMI# Setup Time SMI# Hold Time STPCLK# Setup Time STPCLK# Hold Time WB/WT# Setup Time WB/WT# Hold Time
Preliminary Data
Figure
Comments
Note Note Note Note Note Note
Note Note Note Note Note Note
These level-sensitive signals asserted synchronously asynchronously. sampled specific clock edge, setup hold times must met. asserted asynchronously, they must asserted minimum pulse width clocks. These edge-sensitive signals asserted synchronously asynchronously. sampled specific clock edge, setup hold times must met. asserted asynchronously, they must have been negated least clocks prior assertion must remain asserted least clocks.
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Signal Switching Characteristics
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Output Delay Timings 66-MHz Operation
Preliminary Data 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
Table Output Delay Timings 66-MHz Operation
Symbol Parameter Description A[31:3] Valid Delay A[31:3] Float Delay ADS# Valid Delay ADS# Float Delay ADSC# Valid Delay ADSC# Float Delay Valid Delay Float Delay APCHK# Valid Delay BE[7:0}# Valid Delay BE[7:0}# Float Delay BREQ Valid Delay CACHE# Valid Delay CACHE# Float Delay D/C# Valid Delay D/C# Float Delay D[63:0] Write Data Valid Delay D[63:0] Write Data Float Delay DP[7:0] Write Data Valid Delay DP[7:0] Write Data Float Delay FERR# Valid Delay HIT# Valid Delay HITM# Valid Delay HLDA Valid Delay LOCK# Valid Delay LOCK# Float Delay M/IO# Valid Delay M/IO# Float Delay Figure Comments
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Table Output Delay Timings 66-MHz Operation (continued)
Symbol Parameter Description Valid Delay Float Delay PCHK# Valid Delay Valid Delay Float Delay SCYC Valid Delay SCYC Float Delay SMIACT# Valid Delay W/R# Valid Delay W/R# Float Delay Preliminary Data 10.0 10.0 10.0 10.0 Figure Comments
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Signal Switching Characteristics
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Input Setup Hold Timings 66-MHz Operation
Preliminary Data
Table Input Setup Hold Timings 66-MHz Operation
Symbol
Notes:
Parameter Description A[31:5] Setup Time A[31:5] Hold Time A20M# Setup Time A20M# Hold Time AHOLD Setup Time AHOLD Hold Time Setup Time Hold Time BOFF# Setup Time BOFF# Hold Time BRDY# Setup Time BRDY# Hold Time BRDYC# Setup Time BRDYC# Hold Time D[63:0] Read Data Setup Time D[63:0] Read Data Hold Time DP[7:0] Read Data Setup Time DP[7:0] Read Data Hold Time EADS# Setup Time EADS# Hold Time EWBE# Setup Time EWBE# Hold Time FLUSH# Setup Time FLUSH# Hold Time
Figure
Comments
Note Note
Note Note
These level-sensitive signals asserted synchronously asynchronously. sampled specific clock edge, setup hold times must met. asserted asynchronously, they must asserted minimum pulse width clocks. These edge-sensitive signals asserted synchronously asynchronously. sampled specific clock edge, setup hold times must met. asserted asynchronously, they must have been negated least clocks prior assertion must remain asserted least clocks.
Signal Switching Characteristics
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Table Input Setup Hold Timings 66-MHz Operation (continued)
Symbol
Notes:
Parameter Description HOLD Setup Time HOLD Hold Time IGNNE# Setup Time IGNNE# Hold Time INIT Setup Time INIT Hold Time INTR Setup Time INTR Hold Time Setup Time Hold Time KEN# Setup Time KEN# Hold Time Setup Time Hold Time Setup Time Hold Time SMI# Setup Time SMI# Hold Time STPCLK# Setup Time STPCLK# Hold Time WB/WT# Setup Time WB/WT# Hold Time
Preliminary Data
Figure
Comments
Note Note Note Note Note Note
Note Note Note Note Note Note
These level-sensitive signals asserted synchronously asynchronously. sampled specific clock edge, setup hold times must met. asserted asynchronously, they must asserted minimum pulse width clocks. These edge-sensitive signals asserted synchronously asynchronously. sampled specific clock edge, setup hold times must met. asserted asynchronously, they must have been negated least clocks prior assertion must remain asserted least clocks.
Chapter
Signal Switching Characteristics
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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RESET Test Signal Timing
Preliminary Data clocks clocks
Table RESET Configuration Signals 100-MHz Operation
Symbol t100 t101 t102
Notes:
Parameter Description RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable BF[2:0] Setup Time BF[2:0] Hold Time Intentionally left blank Intentionally left blank Intentionally left blank FLUSH# Setup Time FLUSH# Hold Time FLUSH# Setup Time FLUSH# Hold Time
Figure
Comments
Note Note
clocks clocks
Note Note Note Note
sampled specific clock edge, setup hold times must clock edge before clock edge which RESET sampled negated. asserted asynchronously, these signals must meet minimum setup hold time clocks relative negation RESET. BF[2:0] must meet minimum setup time minimum hold time clocks relative negation RESET.
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Table RESET Configuration Signals 66-MHz Operation
Symbol t100 t101 t102
Notes:
Parameter Description RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable BF[2:0] Setup Time BF[2:0] Hold Time Intentionally left blank Intentionally left blank Intentionally left blank FLUSH# Setup Time FLUSH# Hold Time FLUSH# Setup Time FLUSH# Hold Time
Preliminary Data clocks clocks
Figure
Comments
Note Note
clocks clocks
Note Note Note Note
sampled specific clock edge, setup hold times must clock edge before clock edge which RESET sampled negated. asserted asynchronously, these signals must meet minimum setup hold time clocks relative negation RESET. BF[2:0] must meet minimum setup time minimum hold time clocks relative negation RESET.
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Signal Switching Characteristics
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Table Waveform TRST# Timing
Symbol Parameter Description Frequency t103 t104 t105 t106 t107 t108
Notes:
Preliminary Data 40.0 14.0 14.0 30.0
Figure
Comments
Period High Time Time Fall Time Rise Time TRST# Pulse Width
Note Note Asynchronous
Rise/Fall times increased each that below maximum frequency MHz. Rise/Fall times measured between
Table Test Signal Timing
Symbol t109 t110 t111 t112 t113 t114 t115 t116 t117 t118
Notes:
Parameter Description Setup Time Hold Time Setup Time Hold Time Valid Delay Float Delay Outputs (Non-Test) Valid Delay Outputs (Non-Test) Float Delay Inputs (Non-Test) Setup Time Inputs (Non-Test) Hold Time
Preliminary Data 13.0 16.0 13.0 16.0
Figure
Notes Note Note Note Note Note Note Note Note Note Note
Parameter measured from falling edge. Parameter measured from rising edge.
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WAVEFORM
INPUTS
Must steady
OUTPUTS
Steady
change from High
Changing from High
change from High
Changing from High
Don't care, change permitted
Changing, State Unknown
(Does apply)
Center line high impedance state
Figure Diagrams
Output Signal Valid
Valid
Figure Output Valid Delay Timing
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Signal Switching Characteristics
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Output Signal
Valid
Figure Maximum Float Delay Timing
Input Signal
Figure Input Setup Hold Timing
Signal Switching Characteristics
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RESET
t92,
t100
FLUSH# (Synchronous)
FLUSH# (Asynchronous)
t101 t102
BF[2:0] (Asynchronous)
Figure Reset Configuration Timing
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Signal Switching Characteristics
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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t104
t107 t103 t106 t105
Figure Waveform
t108
Figure TRST# Timing
t103 t109, TDI, t113 Output Signals Input Signals t117 t118 t115 t116 t114 t110,
Figure Test Signal Timing Diagram
Signal Switching Characteristics
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Electrical Data
Operating Ranges
Mobile AMD-K6-III-P processor designed provide functional operation voltage temperature parameters within limits defined Table Table Operating Ranges
Parameter VCC2 VCC2 VCC3 TCASE
Note:
Minimum 3.135
Typical
Maximum 80°C
Comments Note Note Note
VCC2 VCC3 referenced from VSS. VCC2 specification components. VCC2 specification components.
Chapter
Electrical Data
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Absolute Ratings
Mobile AMD-K6-III-P processor designed operated beyond operating ranges listed Table Exposure conditions outside these operating ranges extended periods time affect long-term reliability. Permanent damage occur absolute ratings listed Table exceeded. Table Absolute Ratings
Parameter VCC2 VCC2 VCC3 VPIN TCASE (under bias) TSTORAGE
Note:
Minimum -0.5 -0.5 -0.5 -0.5 -65°C -65°C
Maximum Vcc3 +110°C +150°C
Comments Note Note Note
VCC2 specification components. VCC2 specification components. VPIN (the voltage pin) must greater than above voltage being applied VCC3. addition, VPIN voltage must never exceed
Electrical Data
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Characteristics
characteristics Mobile AMD-K6-III-P processor shown Table
Table Characteristics
Symbol ICC2 Parameter Description Input Voltage Input High Voltage Output Voltage Output High Voltage Power Supply Current 8.50 Preliminary Data -0.3 +0.8 VCC3 +0.3V Note 4.0-mA load 3.0-mA load MHz, Note 2,8,10 MHz, Note 2,11 MHz, Note 2,10 MHz, Note 3,10 ICC2 Power Supply Current 8.50 0.60 0.60 ICC3 Power Supply Current 0.61 0.62 0.64 0.66
Notes:
Comments
MHz, Note MHz, Note MHz, Note 4,10 MHz, Note MHz, Note MHz, Note 4,8,10 MHz, Note 4,11 MHz, Note 4,10 Note Note
Input Leakage Current Output Leakage Current
VCC3 refers voltage being applied VCC3 during functional operation. VCC2 maximum power supply current must taken into account when designing power supply. VCC2 maximum power supply current must taken into account when designing power supply. VCC3 maximum power supply current must taken into account when designing power supply. Refers inputs without internal pullup resistor VCC3. Refers inputs with internal pullup Refers inputs with internal pulldown This specification applies components using frequency MHz. This specification applies components using frequency MHz. This specification applies components using frequency MHz. This specification applies components using frequency 96.2 MHz.
Chapter
Electrical Data
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Table Characteristics (continued)
Symbol COUT COUT CCLK CTIN CTOUT CTCK
Notes:
Parameter Description Input Leakage Current Bias with Pullup Input Leakage Current Bias with Pulldown Input Capacitance Output Capacitance Capacitance Capacitance Test Input Capacitance (TDI, TMS, TRST#) Test Output Capacitance (TDO) Capacitance
Preliminary Data -400
Comments Note Note
VCC3 refers voltage being applied VCC3 during functional operation. VCC2 maximum power supply current must taken into account when designing power supply. VCC2 maximum power supply current must taken into account when designing power supply. VCC3 maximum power supply current must taken into account when designing power supply. Refers inputs without internal pullup resistor VCC3. Refers inputs with internal pullup Refers inputs with internal pulldown This specification applies components using frequency MHz. This specification applies components using frequency MHz. This specification applies components using frequency MHz. This specification applies components using frequency 96.2 MHz.
Electrical Data
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Power Dissipation
Table contains typical maximum power dissipation Mobile AMD-K6-III-P processor during normal reduced power states.
Table Power Dissipation
Clock Control State Design Power Application Power Stop Grant/Halt (Maximum) Stop Clock (Maximum)
Notes:
MHz7 MHz5 MHz6 MHz5,7 MHz8 MHz7 Comments 16.00 12.60 2.56 2.25 Note Note Note Note
Design Power represents maximum sustained power dissipated while executing software instruction sequences under normal system operation with VCC2 (for 2.0V components) VCC2 (for 2.2V components) VCC3 Thermal solutions must thermal feedback limit processor's peak power. Specified through characterization. Application Power represents average power dissipated while executing software instruction sequences under normal system operation with VCC2 (for 2.0V components) VCC2 (for 2.2V components) VCC3 signal internal still running most internal clocking stopped. signal, internal PLL, internal clocking stopped. This specification applies components using frequency MHz. This specification applies components using frequency MHz. This specification applies components using frequency MHz. This specification applies components using frequency 96.2 MHz.
Chapter
Electrical Data
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Power Grounding
Mobile AMD-K6-III-P processor dual voltage device. separate supply voltages required: provides core voltage Mobile AMD-K6-III-P processor VCC3 provides voltage. "Electrical Data" page value range VCC2 VCC3. There pins Mobile AMD-K6-III-P processor. (See "Pin Description Diagrams" page power ground designations.) large number power ground pins provided ensure that processor package maintain clean stable power distribution network. proper operation functionality, VCC2, VCC3, pins must connected appropriate planes circuit board. power planes have been arranged pattern simplify routing minimize crosstalk circuit board. isolation region between voltage planes must least 0.254mm they same layer circuit board. (See Figure page 75.) order maintain low-impedance current sink reference, ground plane must never split. Although Mobile AMD-K6-III-P processor separate supply voltages, there special power sequencing requirements. best procedure minimize time between which VCC2 VCC3 either both both off.
Power Connections
Electrical Data
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0.254mm (min.) isolation region
VCC3 (I/O) Plane
VCC2 (Core) Plane
Figure Suggested Component Placement Decoupling Recommendations addition isolation region mentioned "Power Connections" page adequate decoupling capacitance required between system power planes ground plane minimize ringing provide low-impedance path return currents. Suggested decoupling capacitor placement shown Figure Surface mounted capacitors should used close possible processor minimize resistance inductance recommendations regarding value, quantity, location capacitors illustrated Figure Mobile AMD-K6® Processor Power Supply Application Note, order# 22495.
Chapter
Electrical Data
CC10
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Connection Requirements
proper operation, following requirements signal connections must met:
drive address data signals into large capacitive loads high frequencies. necessary, buffer chips drive large capacitive loads. Leave (no-connect) pins unconnected. Unused inputs should always connected appropriate signal level. Active inputs that being used should connected VCC3 through 20k-ohm pullup resistor. Active High inputs that being used should connected through pulldown resistor. Reserved signals treated following ways: no-connect (NC) pins, which case these pins left unconnected pins connected system logic defined industry-standard Super7 Socket interface combination Socket pins Keep trace lengths minimum.
Electrical Data
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Thermal Design
Package Thermal Specifications
Mobile AMD-K6-III-P processor operating specifications call case temperature (TC) range 80°C. ambient temperature (TA) specified long case temperature violated. case temperature must measured center package. Table specifications.
Table Package Thermal Specifications
Maximum Design Power Case Temperature 80°C Components
16.00
Figure page shows thermal model processor sive temperature calculated from following equation: PMAX PMAX Where:
PMAX Maximum Power Consumption Case-to-Ambient Thermal Resistance Interface Material Thermal Resistance Sink-to-Ambient Thermal Resistance
Chapter
Thermal Design
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Temperature (Ambient)
Thermal Resistance (°C/W) Heat Exchange Device
Sink Case
Figure Thermal Model Figure illustrates case-to-ambient temperature (TCA) relation power consumption (X-axis) thermal resistance (Y-axis). power consumption case mperat known, herma resist ance requirement calculated given ambient temperature (TA) value.
=CAC
Thermal Resistance (°C/W)
Power Consumption (Watts)
Figure Power Consumption versus Thermal Resistance thermal resistance heatsink determined heat dissipation surface area, material shape heatsink, airflow volume across heatsink. general, larger surface area lower thermal resistance. Thermal Design Chapter
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required thermal resistance heatsink calculated using following example: 80°C 55°C PMAX 16.00W Then:
25°C 1.56 16.00W
Thermal grease recommended interface material because provides lowest thermal resistance (approx. 0.20°C/W). required thermal resistance (SA) heat sink this example calculated follows: 1.56 0.20 1.36(°C/W) Heat Dissipation Path Figure illustrates heat dissipation path processor. lower thermal resistance between processor junction case, most heat generated processor transferred from surface case. small amount heat generated from bottom side processor where processor socket blocks convection safely ignored.
Ambient Temperature
Thin Case temperature
Figure Processor's Heat Dissipation Path
Chapter
Thermal Design
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Measuring Case Temperature
processor case temperature measured ensure that specification. This temperature should measured center package where most heat dissipated. Figure shows correct location measuring case temperature. heatsink installed while measuring, thermocouple must installed into heatsink small hole drilled through heatsink base (for example, 1/16 inch). thermocouple then attached base heatsink small hole filled using thermal epoxy, allowing thermocouple touch processor case.
Thermally Conductive Epoxy
Thermocouple
Figure Measuring Case Temperature more information thermal design considerations, AMD-K6 Thermal Solution Design Application Note, order# 21085.
Thermal Design
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Package Specifications
321-Pin Staggered CPGA Package Specification
Millimeters 49.28 45.59 31.01 44.90 2.91 1.30 3.05 0.43 2.29 1.14 1.52 1.52 49.78 45.85 32.89 45.10 3.63 1.52 3.30 0.51 2.79 1.40 2.29 2.54 0.13 1.940 1.795 1.221 1.768 0.115 0.051 0.120 0.017 0.090 0.045 0.060 0.060 Inches 1.960 1.805 1.295 1.776 0.143 0.060 0.130 0.020 0.110 0.055 0.090 0.100 0.005 Flatness
Table 321-Pin Staggered CPGA Package Specification
Symbol Notes
Figure 321-Pin Staggered CPGA Package Specification Chapter Package Specifications
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Package Specifications
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Description Diagrams
Figure Mobile AMD-K6®-III-P Processor Bottom-Side View Chapter Description Diagrams
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
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Figure Mobile AMD-K6®-III-P Processor Top-Side View
Description Diagrams
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10.1
Address Name
Designations Functional Grouping
Data Name
Control Name
A20M# ADS# ADSC# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BRDY# BRDYC# BREQ CACHE# D/C# EADS# EWBE# FERR# FLUSH# HIT# HITM# HLDA HOLD IGNNE# INIT INTR KEN# LOCK# M/IO# PCHK# RESET SCYC SMI# SMIACT# STPCLK#
VCC2DET VCC2H/L#
Test Name
TRST#
A-37 E-17 E-25 R-34 S-33 S-35 W-33 AJ-15 AJ-23 AL-19 AN-35
Vcc2
A-07 A-09 A-11 A-13 A-15 A-17 B-02 E-15 G-01 J-01 L-01 N-01 Q-01 S-01 U-01 W-01 Y-01 AA-01 AC-01 AE-01 AG-01 AJ-11 AN-09 AN-11 AN-13 AN-15 AN-17 AN-19
Vcc3
A-19 A-21 A-23 A-25 A-27 A-29 E-21 E-27 E-37 G-37 J-37 L-33 L-37 N-37 Q-37 S-37 T-34 U-33 U-37 W-37 Y-37 AA-37 AC-37 AE-37 AG-37 AJ-19 AJ-29 AN-21 AN-23 AN-25 AN-27 AN-29
A-03 B-06 B-08 B-10 B-12 B-14 B-16 B-18 B-20 B-22 B-24 B-26 B-28 E-11 E-13 E-19 E-23 E-29 E-31 H-02 H-36 K-02 K-36 M-02 M-36 P-02 P-36 R-02 R-36 T-02 T-36 U-35 V-02 V-36 X-02 X-36 Z-02 Z-36 AB-02 AB-36 AD-02 AD-36 AF-02 AF-36 AH-02 AJ-07 AJ-09 AJ-13 AJ-17 AJ-21 AJ-25 AJ-27 AJ-31 AJ-37 AL-37 AM-08 AM-10 AM-12 AM-14 AM-16 AM-18 AM-20 AM-22 AM-24 AM-26 AM-28 AM-30 AN-37
AL-35 AM-34 AK-32 AN-33 AL-33 AM-32 AK-30 AN-31 AL-31 AL-29 AK-28 AL-27 AK-26 AL-25 AK-24 AL-23 AK-22 AL-21 AF-34 AH-36 AE-33 AG-35 AJ-35 AH-34 AG-33 AK-36 AK-34 AM-36 AJ-33
K-34 G-35 J-35 G-33 F-36 F-34 E-35 E-33 D-34 C-37 C-35 B-36 D-32 B-34 C-33 A-35 B-32 C-31 A-33 D-28 B-30 C-29 A-31 D-26 C-27 C-23 D-24 C-21 D-22 C-19 D-20 C-17 C-15 D-16 C-13 D-14 C-11 D-12 C-09 D-10 D-08 A-05 E-09 B-04 D-06 C-05 E-07 C-03 D-04 E-05 D-02 F-04 E-03 G-05 E-01 G-03 H-04 J-03 J-05 K-04 L-05 L-03 M-04 N-03
W/R# WB/WT#
AK-08 AJ-05 AM-02 V-04 AE-05 AL-09 AK-10 AL-11 AK-12 AL-13 AK-14 AL-15 AK-16 Y-33 X-34 W-35 Z-04 X-04 Y-03 AJ-01 U-03 AK-18 AK-04 AM-04 W-03 Q-05 AN-07 AK-06 AL-05 AJ-03 AB-04 AA-35 AA-33 AD-34 U-05 W-05 AH-04 T-04 Y-05 AC-33 AG-05 AF-04 AL-03 AK-20 AL-17 AB-34 AG-03 V-34 AL-01 AN-05 AM-06 AA-05
M-34 N-35 N-33 P-34 Q-33
Parity
AK-02 D-36 D-30 C-25 D-18 C-07 F-06 F-02 N-05
C-01 H-34 Y-35 Z-34 AC-35 AL-07 AN-01 AN-03
RSVD
J-33 L-35 P-04 Q-03 Q-35 R-04 S-03 S-05 AA-03 AC-03 AC-05 AD-04 AE-03 AE-35
AH-32
Chapter
Description Diagrams
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
22655C/0-September 1999
Description Diagrams
Chapter
22655C/0-September 1999
Mobile AMD-K6®-III-P Processor Data Sheet
Ordering Information
Standard Products
standard mobile products available several operating ranges. ordering part number (OPN) formed combination elements below.
AMD-K6-III /450 Case Temperature 0°C-80°C Operating Voltage V-2.1 (Core) 3.135 V-3.6 (I/O) V-2.3 (Core) 3.135 V-3.6 (I/O) Package Type 321-pin CPGA Performance Rating /450 /433 /400 /380 /366 /350 Family/Core AMD-K6-III
Table Valid Ordering Part Number Combinations
AMD-K6-III/450ACK AMD-K6-III/433ACK AMD-K6-III/400ACK AMD-K6-III/380AFK
Note:
Package Type 321-pin CPGA 321-pin CPGA 321-pin CPGA 321-pin CPGA
Operating Voltage 1.9V-2.1V (Core) 3.135V-3.6V (I/O) 1.9V-2.1V (Core) 3.135V-3.6V (I/O) 1.9V-2.1V (Core) 3.135V-3.6V (I/O) 2.1V-2.3V (Core) 3.135V-3.6V (I/O)
Case Temperature 0°C-80°C 0°C-80°C 0°C-80°C 0°C-80°C
This table lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly-released combinations.
Chapter
Ordering Information
Preliminary Information Mobile AMD-K6®-III-P Processor Data Sheet
22655C/0-September 1999
Table Valid Ordering Part Number Combinations (continued)
AMD-K6-III/366AFK AMD-K6-III/350AFK
Note:
Package Type 321-pin CPGA 321-pin CPGA
Operating Voltage 2.1V-2.3V (Core) 3.135V-3.6V (I/O) 2.1V-2.3V (Core) 3.135V-3.6V (I/O)
Case Temperature 0°C-80°C 0°C-80°C
This table lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly-released combinations.
Ordering Information
Chapter
22655C/0-September 1999
Mobile AMD-K6®-III-P Processor Data Sheet
Index
Numerics
100-MHz input setup hold timings. 321-Pin Staggered CPGA package specification 3DNow!. 13-17 execution unit 16-17 register operation technology 66-MHz clock switching characteristics input setup hold timings. output delay timings. stop grant inquire Control unit, scheduler/instruction Cycles inquire. .23-24, 26-27, 35-38 interrupt acknowledge pipelined. special 36-37, writeback 38-39
Data 23-26, Decode, Instruction Decoders Dual Voltage
Accelerated Graphic Port (AGP) Address stack, return Address Architecture internal 5-19
Electrical Specifications absolute ratings operating ranges Exception debug. floating-point Exceptions, Interrupts, Debug Execution units. Execution Unit 3DNow! 16-17 branch floating-point load multimedia 16-17 register 16-17 register 16-17 store. Execution Units 6-8,
Bits, Predecode Block Diagram Boundary-Scan 30-31 Branch execution unit history table. logic prediction prediction logic .1-2, 17-18 target cache 100-MHz address cycle de
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