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Processor Model Data Sheet Publication 23802 Rev: Issue Date: Jun


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Duron
Processor Model Data Sheet
Publication 23802 Rev: Issue Date: June 2001
2000, 2001 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, logo, Athlon, Duron, HyperTransport 3DNow! combinations thereof trademarks Advanced Micro Devices, Inc. trademark Intel Corporation. Digital Alpha trademarks Digital Equipment Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
23802I-June 2001
DuronProcessor Model Data Sheet
Contents
Revision History. Overview
DuronProcessor Model Microarchitecture Summary Overview Signaling Technology Push-Pull (PP) Drivers Duron System Signals
Interface Signals
Logic Symbol Diagram Power Management
Power Management States Working State Halt State Stop Grant States. Probe State. Connect Disconnect Protocol Connect Protocol Connect State Diagram Clock Control
Thermal Design CPUID Support Electrical Data
7.10 7.11 7.12 7.13 Conventions Interface Signal Groupings Voltage Identification (VID[4:0]) Frequency Identification (FID[3:0]) VCCA Characteristics Decoupling Operating Ranges Absolute Ratings VCC_CORE Voltage Current SYSCLK SYSCLK# Characteristics Duron System Characteristics General Characteristics APIC Pins Characteristics
Contents
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Signal Power-Up Requirements
Power-Up Requirements Signal Sequence Timing Description Clock Multiplier Selection (FID[3:0]). Serial Initialization Packet (SIP) Protocol Processor Warm Reset Requirements Duron Processor Model Northbridge Reset Pins Introduction Loading Pinout Diagram Socket Tabs Heatsink Clips Diagram Name Abbreviations List Detailed Descriptions A20M# Duron System Pins. Analog APIC Pins, PICCLK, PICD[1:0]# CLKFWDRST CLKIN, RSTCLK (SYSCLK) Pins CONNECT COREFB COREFB# Pins CPU_PRESENCE# DBRDY DBREQ# Pins. FERR FID[3:0] Pins FLUSH# IGNNE# INIT# INTR JTAG Pins K7CLKOUT K7CLKOUT# Pins Pins Pins Orientation Pins Bypass Test Pins PWROK SADDIN[1:0]# SADDOUT[1:0]# Pins Scan Pins SCHECK[7:0]# SMI#
Mechanical Data
Descriptions
10.1 10.2 10.3
Contents
23802I-June 2001
DuronProcessor Model Data Sheet
STPCLK# SYSCLK SYSCLK#. SYSVREFMODE Pin. VCCA VID[4:0] Pins VREFSYS VCC_Z, VSS_Z Pins
Ordering Information
Standard Duron Processor Model Products
Appendix Conventions, Abbreviations, References
Signals Bits Data Terminology Abbreviations Acronyms.
Contents
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Contents
23802I-June 2001
DuronProcessor Model Data Sheet
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Typical DuronProcessor Model System Block Diagram Logic Symbol Diagram Duron Processor Model Power Management States Example Duron System Disconnect Sequence Exiting Stop Grant State/Bus Reconnect Sequence Northbridge Connect State Diagram Processor Connect State Diagram SYSCLK SYSCLK# Differential Clock Signals SYSCLK Waveform
Figure Signal Relationship Requirements During Power-Up Sequence Figure Package, Top, Side, Bottom Views Figure Socket with Outline Socket Heatsink Figure Socket Heatsink Side View Figure Duron Processor Model Diagram-Topside View Figure Duron Processor Model Diagram-Bottomside View Figure Example Duron Processor Model
List Figures
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
viii
List Figures
23802I-June 2001
DuronProcessor Model Data Sheet
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Thermal Design Power. Interface Signal Groupings VID[4:0] Characteristics FID[3:0] Characteristics VCCA Characteristics Operating Ranges. Absolute Ratings VCC_CORE Voltage Current. SYSCLK SYSCLK# Characteristics SYSCLK SYSCLK# Characteristics DuronSystem Characteristics Duron System Characteristics General Characteristics. APIC Pins Characteristics CPGA Mechanical Loading Name Abbreviations Cross-Reference Location FID[3:0] Clock Multiplier Encodings VID[4:0] Code Voltage Definition Abbreviations Acronyms.
List Tables
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
List Tables
23802I-June 2001
DuronProcessor Model Data Sheet
Revision History
Date Description This revision includes added information about DuronProcessor Model following changes:
June 2001
Chapter included APIC information "Halt State" page "Stop Grant States" page Chapter updated Table "Thermal Design Power," page Chapter updated Table "VCC_CORE Voltage Current," page Chapter revised description "FERR Pin" page Table page
This revision includes added information about DuronProcessor Model changes since January 2001 follows:
April 2001
Chapter revised Figure "AMD DuronProcessor Model Power Management States" page Chapter updated Table "Thermal Design Power," page Chapter revised Table "VID[4:0] Characteristics," page Table "FID[3:0] Characteristics," page Table "AMD DuronSystem Characteristics," page Table "APIC Pins Characteristics," page updated Table "VCC_CORE Voltage Current," page Chapter revised description "Serial Initialization Packet (SIP) Protocol" page Chapter added Table "CPGA Mechanical Loading," page Chapter revised description "VID[4:0] Pins" page revised Table "Pin Name Abbreviations," page revised description "AMD Pin" page added description "APIC Pins, PICCLK, PICD[1:0]#" page
Added information about DuronProcessor Model follows: Table "Thermal Design Power," page Table "Operating Ranges," page Table "VCC_CORE Voltage Current," page Table "SYSCLK SYSCLK# Characteristics," page Added Chapter "CPUID Support" page
January 2001
Revised Figure "OPN Example DuronProcessor Model page October 2000 Revised VID[4:0] information Table page "VID[4:0] Pins" page
Revision History
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Date
Description Added information about DuronProcessor Model follows: Table "Thermal Design Power," page Table "Operating Ranges," page Table "VCC_CORE Voltage Current," page Added Athlon trademark list Updated "Motherboard Design Guide, order# 90009" with document name "Socket Motherboard Design Guide, order# 24363" throughout book Added SAI#[0] location AJ29 Figure "AMD DuronProcessor Model Diagram-Topside View" page Added (AH6) Table "Cross-Reference Location," page descriptions Section 10.3 page Revised connect (NC) pins grid array (PGA) follows: Figure "AMD DuronProcessor Model Diagram-Topside View" page Table "Pin Name Abbreviations," page Table "Cross-Reference Location," page Revised "K7CLKOUT K7CLKOUT# Pins" description page Updated ordering information page Table "Thermal Design Power," page Table "Operating Ranges," page Table "VCC_CORE Voltage Current," page Added Table "Thermal Design Power," page Revised VCC_CORE Table "Operating Ranges," page Revised reorganized characteristics SYSCLK SYSCLK#. Table "SYSCLK SYSCLK# Characteristics," page Table "SYSCLK SYSCLK# Characteristics," page Added Table "Miscellaneous Pins Characteristics" page Revised mechanical drawings Chapter pages Made corrections updates Chapter "Pin Descriptions", particular Table "Socket Cross-Reference Location," page Revised from digits (i.e. from 0550=0550 MHz) Chapter "Ordering Information" page
October 2000
Added information about DuronProcessor Model processor follows: September 2000
August 2000
June 2000
Initial public release
Revision History
23802I-June 2001
DuronProcessor Model Data Sheet
Overview
DuronProcessor Model enables optimized solution value-conscious business home users providing capability flexibility meet their computing needs both today tomorrow.
DuronProcessor Model latest offering from designed value segment market. innovative design developed accommodate more advanced applications, meeting requirements today's most demanding value-conscious buyers without compromising their budget. Delivered package, Duron Processor Model workhorse processor value desktop systems, live multimedia performance applications running system platforms. Duron Processor Model provides value-conscious customers with access advanced technology that allows their system investment last years come. Duron Processor Model designed solid platform surfing Internet, digital entertainment, personal creativity. addition, engineered enable superior business productivity delivering optimized combination computing performance value. seventh-generation microarchitecture with integrated cache, which supports growing processor system bandwidth requirements emerging software, graphics, I/O, memory technologies. Duron Processor Model high-speed execution core includes multiple instruction decoders, dual-ported 128-Kbyte split level-one (L1) cache, 64-Kbyte on-chip cache, three independent integer -way floating-point engine. floating-point engine capable delivering superior performance numerically complex applications.
Chapter
Overview
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Duron Processor Model microarchitecture high-perfo rmance cache archit ure, 0-MHz, 1.6-Gigabyte second system bus. Duron system combines latest technological advances, such point-to-point topology, source-synchronous packet-based transfers, low-voltage signaling, provide most powerful, scalable available processor. Duron Processor Model binary-compatible with existing software backwards compatible with applications optimized MMXand 3DNow! instructions. Using data format single-instruction multiple-data (SIMD) operations based instruction model, Duron Processor Model produce many four, 32-bit, single-precision floating-point results clock cycle. enhanced 3DNow! technology implemented multimedia instructions software-directed data movement instructions deliver superior performance Celeron multimedia number-intensive applications.
DuronProcessor Model Microarchitecture Summary
following features summarize Duron Processor Model microarchitecture:
industry's first nine-issue, superpipelined, superscalar processor microarchitecture designed high clock frequencies Multiple instruction decoders Three out-of-order, superscalar, fully pipelined floating-point execution units, which execute (floating-point), 3DNow! instructions Three out-of-order, superscalar, pipelined integer units Three out-of-order, superscalar, pipelined address calculation units 72-entry instruction control unit Advanced dynamic branch prediction Enhanced 3DNow! technology with instructions enable improved integer math calculations speech video encoding improved data movement internet plug-ins other streaming applications Overview Chapter
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DuronProcessor Model Data Sheet
200-MHz Duron system (scalable beyond MHz) enabling leading-edge system bandwidth data movement-intensive applications High-performance cache architecture featuring integrated 128-Kbyte cache 16-way, on-chip 64-Kbyte cache
Duron Processor Model delivers superior system performance cost-effective, industry-standard form factor. Duron Processor Model compatible with motherboards based AMD's Socket Figure shows typical Duron Processor Model system block diagram.
DuronProcessor Model System Controller (Northbridge) Memory DRAM
Peripheral Controller (Southbridge) System Management
SCSI
Dual EIDE BIOS
Figure Typical DuronProcessor Model System Block Diagram
Chapter
Overview
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Overview
Chapter
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DuronProcessor Model Data Sheet
Interface Signals
Overview
Duron system architecture designed deliver superior data movement bandwidth value platforms. system architecture consists three high-speed channels unidirectional processor request channel, unidirectional probe channel, 72-bit bidirectional data protection), source-synchronous clocking, packet-based protocol. addition, system supports several control, clock, legacy signals. interface signals impedance controlled push-pull low-voltage swing signaling technology contained within Socket socket. more information, "AMD DuronSystem Signals" page Chapter "Pin Descriptions" page Athlonand DuronSystem Specification, order# 21902.
Signaling Technology
Duron system uses low-voltage, swing signaling technology, which been enhanced provide larger noise margins, reduced ringing, variable voltage levels. signals push-pull impedance compensated. signal inputs differential receivers, which require reference voltage (VREF). reference signal used receivers determine signal asserted deasserted source. Termination resistors needed because driver impedance matched motherboard high impedance reflection used receiver bring signal past input threshold. more information about pins signals, Chapter "Pin Descriptions" page
Chapter
Interface Signals
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Push-Pull (PP) Drivers
Socket DuronProcessor Model supports Push-Pull (PP) drivers. system logic configures Duron Processor Model with configuration parameter called SysPushPull (1=PP). impedance drivers match impedance motherboard external resistors connected pins. "ZN, VCC_Z, VSS_Z Pins" page more information.
DuronSystem Signals
Duron system clock-forwarded, point-to-point interface with following three point-to-point channels:
13-bit unidirectional output address/command channel 13-bit unidirectional input address/command channel 72-bit bidirectional data channel
more information, Chapter "Electrical Data" page Athlonand DuronSystem Specification, order# 21902.
Interface Signals
Chapter
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DuronProcessor Model Data Sheet
Logic Symbol Diagram
Clock
SYSCLK SDATA[63:0]# SDATAINCLK[3:0]# SDATAOUTCLK[3:0]# SCHECK[7:0]# SDATAINVAL# SDATAOUTVAL# SFILLVAL#
SYSCLK# VID[4:0] COREFB COREFB# PWROK
Data
Voltage Control Frequency Control
FID[3:0]
Probe/SysCMD Request
SADDIN[14:2]# SADDINCLK# SADDOUT[14:2]# SADDOUTCLK# PROCRDY CLKFWDRST CONNECT STPCLK# RESET#
DuronProcessor Model
FERR IGNNE# INIT# INTR A20M# SMI#
Legacy
Power Management Initialization
PICCLK PICD[1:0]#
APIC
Figure Logic Symbol Diagram
Chapter
Logic Symbol Diagram
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Logic Symbol Diagram
Chapter
23802I-June 2001
DuronProcessor Model Data Sheet
Power Management
Power Management States
DuronProcessor Model supports low-power Halt Stop Grant states. These states used Advanced Configuration Power Interface (ACPI) enabled operating systems processor power management. Figure shows power management states Duron Processor Model figure includes ACPI "Cx" naming convention these states.
Halt
Execute SMI#, INTR, NMI, INIT#, RESET#
Working
(Read PLVL2 register throttling)
STPCLK# deasserted
STPCLK# asserted
DuronSystem connected during states: System connected during followingfollowing states: Probe state During transitions from Halt state Stop Grant state Stop Grant state Halt state Working State
Figure DuronProcessor Model Power Management States
Chapter
Incoming Probe
Probe State1
Probe Serviced
Incoming Probe Probe Serviced
Stop Grant Cache Snoopable
C3/S1 Stop Grant Cache Snoopable Sleep
Legend: Hardware transitions Software transitions
Power Management
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
following paragraphs descr each powe management states. Note: power management states, system must disable system clock (SYSCLK/SYSCLK#) processor. Working State Halt State Working state refers state which processor executing instructions. When Duron Processor Model executes instruction, processor issues Halt special cycle system bus. phase-lock loop (PLL) continues run, enabling processor monitor activity provide quick resume from Halt state. processor enters lower power state system logic (Northbridge) disconnects Duron system response Halt special cycle. Halt state exited when processor detects assertion INIT#, RESET#, SMI#, interrupt INTR pins, local APIC interrupt message. Stop Grant States Duron Processor Model enters Stop Grant state upon recognition assertion STPCLK# input. There mechanisms asserting STPCLK#-hardware software. Southbridge force STPCLK# assertion throttling protect processor from exceeding maximum case temperature. This task accomplished asserting THERM# input Southbridge. Throttling asserts STPCLK# percentage predefined throttling period: STPCLK# repetitively asserted deasserted until THERM# deasserted. Software force processor into Stop Grant state accessing ACPI-defined registers typically located Southbridge. Software places processor reading PLVL_2 register Southbridge. probes allowed, shown Figure page ACPI Thermal Zone defined processor, initiate throttling with STPCLK# using ACPI defined P_CNT register Southbridge. processor enters Northbridge during Stop Grant throttling.
Power Management
Chapter
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DuronProcessor Model Data Sheet
Stop Grant state also entered system sleep state based write SLP_TYP field ACPI-defined power management control register. During sleep state, system software ensures master probe activity occurs. After recognizing assertion STPCLK#, Duron Processor Model completes pending in-progress cycles acknowledges STPCLK# assertion issuing Stop Grant special cycle Duron system bus. After Northbridge disconnects Duron system response Stop Grant special cycle, processor enters low-power state dictated CLK_Ctl register. During Stop Grant states, processor latches INIT#, INTR, NMI, SMI#, local APIC interrupt message they asserted. Stop Grant state exited upon deassertion STPCLK# assertion RESET#. When STPCLK# deasserted, processor initiates connection Duron system disconnected. After processor enters Working state, pending interrupts recognized serviced processor resumes execution instruction boundary where STPCLK# initially recognized. RESET# sampled asserted during Stop Grant state, processor returns Working state reset process begins. Probe State Probe state entered when Northbridge initiates Duron system connect required probe processor. processor been disconnected from system bus, Northbridge must initiate system connection prior probing processor snoop processor's caches example. When Probe state, processor responds probe cycle same manner when Working state. When probe been serviced, processor returns same state when entered Probe state (Halt Stop Grant state). Once Halt Stop Grant state, low-power disconnection from system bus.
Chapter
Power Management
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Connect Disconnect Protocol
Significant power savings Duron Processor Model only occurs processor disconnected from system Northbridge while Halt Stop Grant state. Northbridge optionally initiate disconnect upon receipt Halt Stop Grant special cycle. option disconnecting controlled enable Northbridge. Northbridge requires processor service probe after system been disconnected, must first initiate system connect.
Connect Protocol
addition legacy STPCLK# signal Halt Stop Grant special cycles, Duron system connect protocol includes CONNECT, PROCRDY, CLKFWDRST signals Connect special cycle. Duron system disconnects initiated Northbridge response receipt Halt Stop Grant special cycle. Reconnect initiated processor response interrupt Halt, STPCLK# deassertion, Northbridge service probe. Northbridge contains BIOS programmable registers enable system disconnect response Halt Stop Grant special cycles. When Northbridge receives Halt Stop Grant special cycle from processor and, there outstanding probes data movements, Northbridge deasserts CONNECT minimum eight SYSCLK periods after last command sent processor. processor detects deassertion CONNECT rising edge SYSCLK, deasserts PROCRDY Northbridge. return, Northbridge asserts CLKFWDRST anticipation reestablishing connection some later point. Note: Northbridge must disconnect processor from Duron system before issuing Stop Grant special cycle bus, passing Stop Grant special cycle Southbridge systems that connect Southbridge with HyperTransporttechnology. This note applies current chipset implementation: alternate chipset implementations that require this state possible.
Power Management
Chapter
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DuronProcessor Model Data Sheet
Note: response Halt special cycles, Northbridge passes Halt special cycle Southbridge immediately. processor receive interrupt after sends Halt special cycle, STPCLK# deassertion after sends Stop Grant special cycle Northbridge before disconnect actually occurs. this case, processor sends Connect special cycle Northbridge, rather than continuing with disconnect sequence. response Connect special cycle, Northbridge cancels disconnect request. system required assert CONNECT signal before returning C-bit connect special cycle (assuming CONNECT been deasserted). more information, Athlonand DuronSystem Specification, order# 21902 definition C-bit Connect special cycle. Figure shows sequence events from Northbridge perspective, which leads disconnecting processor from Duron system placing processor Stop Grant state.
STPCLK# System CONNECT PROCRDY CLKFWDRST Stop Grant Stop Grant
Figure Example DuronSystem Disconnect Sequence following sequence events describes processor placed Stop Grant state when disconnect enabled within Northbridge: Southbridge asserts STPCLK# place processor Stop Grant state.
Chapter
Power Management
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
When processor recognizes STPCLK# asserted, processor enters Stop Grant State, then issues Stop Grant special cycle Duron system bus. When Stop Grant special cycle received Northbridge probe traffic pending, Northbridge deasserts CONNECT, initiating disconnect processor. processor responds Northbridge deasserting PROCRDY, acknowledging disconnect request. Northbridge asserts CLKFWDRST complete disconnect sequence. After processor disconnected from bus, Northbridge passes Stop Grant special cycle Southbridge. Figure shows signal sequence events that take processor Stop Grant state, reconnect processor Duron system bus, processor into Working state.
STPCLK# PROCRDY CONNECT CLKFWDRST
Figure Exiting Stop Grant State/Bus Reconnect Sequence following sequence events removes processor from Stop Grant state reconnects Duron system bus: Southbridge deasserts STPCLK# response resume event. When processor recognizes STPCLK# deassertion, asserts PROCRDY, notifying Northbridge reconnect bus. Northbridge asserts CONNECT.
Power Management
Chapter
23802I-June 2001
DuronProcessor Model Data Sheet
Northbridge finally deasserts CLKFWDRST, which synchronizes forwarded clocks between processor Northbridge.
Chapter
Power Management
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Connect State Diagram
Figure Figure describe Northbridge processor connect state diagrams, respectively.
Disconnect Pending Connect
Disconnect Requested
Disconnect 7/D,C
Reconnect Pending
Probe Pending
Probe Pending
Condition disconnect requested probes still pending disconnect requested probes pending CONNECT special cycle from processor probes pending PROCRDY deasserted probe needs service PROCRDY asserted SYSCLK periods after CLKFWDRST deasserted. Although reconnected system interface, Northbridge must issue non-NOP SysDC commands minimum four SYSCLK periods after deasserting CLKFWDRST.
Action Deassert CONNECT SYSCLK periods after last SysDC sent
Assert CLKFWDRST Assert CONNECT Deassert CLKFWDRST
Figure Northbridge Connect State Diagram Power Management Chapter
23802I-June 2001
DuronProcessor Model Data Sheet
Connect Connect Pending Connect Pending Disconnect
Disconnect Pending
Condition CONNECT deasserted Northbridge (for previously sent Halt Stop Grant special cycle). Processor receives wake-up event must cancel disconnect request.
Action CLKFWDRST asserted Northbridge. Issue CONNECT special cycle.* Return internal clocks full speed assert PROCRDY
Connect special cycle only issued after
Deassert PROCRDY slow down internal clocks. Processor wake-up event CONNECT asserted Northbridge. CLKFWDRST deasserted Northbridge. Forward clocks start SYSCLK periods after CLKFWDRST deasserted.
processor wake-up event (interrupt STPCLK# deassertion) occurs. Duron system connected Northbridge probe processor Connect special cycle issued that time only issued after subsequent processor wake-up event).
Figure Processor Connect State Diagram
Chapter
Power Management
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Clock Control
processor implements Clock Control (CLK_Ctl) (address C001_001Bh) that determines internal clock divisor when Duron system disconnected. Refer Athlonand DuronProcessors BIOS, Software, Debug Developers Guide, order# 21656, more details CLK_Ctl register.
Power Management
Chapter
23802I-June 2001
DuronProcessor Model Data Sheet
Thermal Design
information about thermal design, including layout airflow considerations, Thermal, Mechanical, Chassis Cooling Design Guide, order# 23794 cooling guidelines www.amd.com. Table shows thermal design power. thermal design power represents maximum sustained power dissipated while executing publicly available software instruction sequences under normal system operation nominal VCC_CORE. Thermal solutions must monitor processor temperature prevent processor from exceeding maximum temperature. characterization 90°C. Table Thermal Design Power
Maximum Thermal Power 27.4 29.4 31.4 33.4 35.4 37.4 39.5 41.5 Typical Thermal Power 24.5 26.4 28.2 30.0 31.8 33.6 35.4 37.2 Temperature
Frequency Nominal (MHz) Voltage
Chapter
Thermal Design
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Thermal Design
Chapter
23802I-June 2001
DuronProcessor Model Data Sheet
CPUID Support
DuronProcessor Model version feature recognition performed through CPUID instruction, that provides complete information about processor-vendor, type, name, etc., capabilities. Software make this information accurately tune system maximum performance benefit users. information CPUID instruction, Processor Recognition Application Note order# 20734.
Chapter
CPUID Support
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
CPUID Support
Chapter
23802I-June 2001
DuronProcessor Model Data Sheet
Electrical Data
Conventions
conventions used this chapter follows:
Current specified being sourced processor negative. Current specified being sunk processor positive.
Interface Signal Groupings
electrical data this chapter presented separately each signal group. Table defines each group signals contained each group.
Table
Interface Signal Groupings
Signals VID[4:0], VCC_CORE, VCCA, COREFB, COREFB# Notes "Voltage Identification (VID[4:0])" page "VID[4:0] Pins" page "VCCA Characteristics" page "Frequency Identification (FID[3:0])" page "FID[3:0] Pins" page "SYSCLK SYSCLK# Characteristics" page "AMD DuronSystem Characteristics" page "General Characteristics" page "General Characteristics" page "APIC Pins Characteristics" page "APIC Pins, PICCLK, PICD[1:0]#" page
Signal Group Power
Frequency System Clocks
FID[3:0] SYSCLK, SYSCLK# (Tied CLKIN/CLKIN# RSTCLK/RSTCLK#), PLLBYPASSCLK#, PLLBYPASSCLK
SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, SADDOUTCLK#, SFILLVAL#, SDATAINVAL#, DuronSDATAOUTVAL#, SDATA[63:0]#, SDATAINCLK[3:0]#, System SDATAOUTCLK[3:0]#, SCHECK[7:0]#, CLKFWDRST, PROCRDY, CONNECT Southbridge JTAG APIC RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#, STPCLK#, FLUSH# TMS, TCK, TRST#, TDI, PICD[1:0]#, PICCLK
Chapter
Electrical Data
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Table
Interface Signal Groupings (continued)
Signals PLLTEST#, PLLMON1, PLLMON2, SCANCLK1, SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG Notes "General Characteristics" page "General Characteristics" page
Signal Group Test
Miscellaneous DBREQ#, DBRDY, PWROK, PLLBYPASS#
Voltage Identification (VID[4:0])
Table shows VID[4:0] characteristics. more information, "VID[4:0] Pins" page
Table
Parameter
Note:
VID[4:0] Characteristics
Description Output Current Output High Voltage 2.625
pins must pulled above this voltage external pullup resistor.
Frequency Identification (FID[3:0])
Table shows FID[3:0] characteristics. more information, "VID[4:0] Pins" page
Table
Note:
FID[3:0] Characteristics
Description Output Current Output High Voltage 2.625
Parameter
pins must pulled above this voltage external pullup resistor.
Electrical Data
Chapter
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DuronProcessor Model Data Sheet
VCCA Characteristics
Table shows characteristics VCCA. more information, "VCCA Pin" page
Table
Symbol IVCCA VVCCA
Notes:
VCCA Characteristics
Parameter VCCA Current VCCA Voltage 2.25 Nominal 2.75 Units mA/GHz Notes
Measured Minimum maximum voltages absolute. transients below minimum above maximum voltages permitted.
Decoupling
AthlonProcessor-Based Motherboard Design Guide, order# 24363, contact your local office information about decoupling required motherboard with DuronProcessor Model
Operating Ranges
Duron Processor Model designed provide functional operation voltage temperature parameters within limits defined Table
Table
VCC_CORE
Operating Ranges
Description Processor core supply Temperature processor 600-950 Processor core supply Sleep state Nominal Notes
Parameter VCC_CORESLEEP TDIE
Notes:
normal operating conditions (nominal VCC_CORE Sleep Voltage used sleep state.
Chapter
Electrical Data
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Absolute Ratings
Duron Processor Model should subjected conditions exceeding absolute ratings listed Table such conditions adversely affect long-term reliability result functional damage.
Table
VCC_CORE VCCA VPIN TSTORAGE
Absolute Ratings
Description DuronProcessor Model core supply Duron Processor Model Supply Voltage signal Storage temperature processor -0.5 -0.5 -0.5 VCC_CORE VCCA VCC_CORE
Parameter
Electrical Data
Chapter
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DuronProcessor Model Data Sheet
VCC_CORE Voltage Current
Table shows power current processor during normal reduced power states.
Table
VCC_CORE Voltage Current
Nominal Voltage Maximum Voltage Stop Grant (Maximum)1 Maximum (Power Supply Current)2 17.1 18.4 19.6 20.9 22.1 23.4 24.7 25.9 Temperature
Frequency (MHz)
Notes:
Measured 1.3V Sleep state operating conditions. BIOS must program CLK_Ctrl fff0_d22fh DuronProcessor Model Measured Nominal voltage
Chapter
Electrical Data
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
7.10
SYSCLK SYSCLK# Characteristics
Table shows characteristics SYSCLK SYSCLK# differential clocks. SYSCLK signal represents CLKIN RSTCLK tied together while SYSCLK# signal represents CLKIN# RSTCLK# tied together. Figure shows this condition.
Table
Symbol
SYSCLK SYSCLK# Characteristics
Description VCC_CORE/2 Units
VThreshold-DC Crossing before transition detected (DC) VThreshold-AC Crossing before transition detected (AC) ILEAK_P ILEAK_N VCROSS CPIN Leakage current through P-channel pullup VCC_CORE Leakage current through N-channel pulldown (Ground) Differential signal crossover Capacitance
VCROSS
VThreshold-DC 400mV
VThreshold-AC 450mV
Figure SYSCLK SYSCLK# Differential Clock Signals
Electrical Data
Chapter
23802I-June 2001
DuronProcessor Model Data Sheet
Table shows SYSCLK/SYSCLK# differential clock characteristics Duron Processor Model Figure shows sample waveform.
Table SYSCLK SYSCLK# Characteristics
Symbol Parameter Description Clock Frequency Duty Cycle
Notes:
Units
Notes
Period High Time Time Fall Time Rise Time Period Stability
Circuitry driving SYSCLK SYSCLK# inputs must exhibit suitably closed-loop jitter bandwidth allow track jitter. attenuation point, measured into 10-pF 20-pF load must less than kHz. Circuitry driving SYSCLK SYSCLK# inputs purposely alter SYSCLK SYSCLK# period (spread spectrum clock generators). cases SYSCLK SYSCLK# period violate minimum specification above. SYSCLK SYSCLK# inputs vary from 100% specified period specified period maximum rate kHz.
VCROSS
VThreshold-AC
Figure SYSCLK Waveform
Chapter
Electrical Data
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
7.11
DuronSystem Characteristics
Table shows characteristics System used Duron Processor Model
Table DuronSystem Characteristics
Symbol VREF Parameter Input Reference Voltage VREF Nominal VREF Nominal VREF -500 IOUT -200 IOUT (Ground) VCC_CORE Nominal 0.85*VCC_CORE -500 Condition Units Notes (0.5*VCC_CORE) (0.5*VCC_CORE) -100 +100 VCC_CORE VREF VCC_CORE+500
IVREF_LEAK_P VREF Tristate Leakage Pullup IVREF_LEAK_N VREF Tristate Leakage Pulldown ILEAK_P ILEAK_N
Notes:
Input High Voltage Input Voltage Output High Voltage Output Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Input Capacitance
VREF nominally VCC_CORE with actual values that specific motherboard design implementation. VREF must created with sufficiently accurate source sufficiently quiet response adhere specification listed above. Specified 90°C VCC_CORE following processor inputs have twice listed capacitance because they connect input pads- SYSCLK, SYSCLK#. SYSCLK connects CLKIN/RSTCLK. SYSCLK# connects CLKIN#/RSTCLK#. more information, Table page
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characteristics Duron system shown Table parameters grouped based source destination signals involved. Table DuronSystem Characteristics
Group Signals Symbol TRISE TFALL TSKEWSAMEEDGE Forward Clocks TSKEWDIFFEDGE
Parameter Output Rise Slew Rate Output Fall Slew Rate Output skew with respect same clock edge Output skew with respect different clock edge Input Data Setup Time Input Data Hold Time Capacitance input Clocks Capacitance output Clocks RSTCLK Output Valid Setup RSTCLK Hold from RSTCLK
Units V/ns V/ns
Notes
COUT
1000 2000
Sync
Notes:
Rise fall time ranges guidelines over which been characterized. TSKEW-SAMEEDGE maximum skew within clock forwarded group between signals between signal forward clock, measured package, with respect same clock edge. TSKEW-DIFFEDGE maximum skew within clock forwarded group between signals between signal forward clock, measured package, with respect different clock edges. Input times with respect appropriate Clock Forward Group input clock. synchronous signals include PROCRDY, CONNECT, CLKFWDRST. RSTCLK rising edge output valid PROCRDY. Test Loadis 25pF. setup CONNECT/CLKFWDRST rising edge RSTCLK. hold CONNECT/CLKFWDRST from rising edge RSTCLK.
Chapter
Electrical Data
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
7.12
General Characteristics
Table shows Duron Processor Model miscellaneous pins.
Table General Characteristics
Symbol ILEAK_P ILEAK_N TDELAY TBIT TRPT
Notes:
Parameter Description Input High Voltage Input Voltage Output High Voltage Output Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Output High Current Output Current Sync Input Setup Time Sync Input Hold Time Output Delay with respect RSTCLK Input Time Acquire Input Time Reacquire
Condition
(VCC_CORE/2) 200mV -300 VCC_CORE -300
VCC_CORE VCC_CORE
Units
Notes
(Ground) VCC_CORE Nominal
20.0 40.0
9-13
Characterized across supply voltage range. Values specified nominal VCC_CORE. Scale parameters between VCC_CORE VCC_CORE Max. measured min, respectively. Synchronous inputs/outputs specified with respect RSTCLK RSTCK# pins. These aggregate numbers. Edge rates indicate range over which inputs were characterized. asynchronous operation, signal must persist this time guarantee capture. This value assumes RSTCLK frequency TBIT 2*fRST. approximate value standard case normal mode operation. This value dependent RSTCLK frequency, divisors, LowPower mode, core frequency. Reassertions signal within this time guaranteed seen core. This value assumes that skew between RSTCLK K7CLKOUT much less than phase. This value assumes RSTCLK K7CLKOUT running same frequency, though processor capable other configurations.
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Table General Characteristics (continued)
Symbol TRISE TFALL CPIN
Notes:
Parameter Description Signal Rise Time Signal Fall Time Capacitance
Condition
Units V/ns V/ns
Notes
Characterized across supply voltage range. Values specified nominal VCC_CORE. Scale parameters between VCC_CORE VCC_CORE Max. measured min, respectively. Synchronous inputs/outputs specified with respect RSTCLK RSTCK# pins. These aggregate numbers. Edge rates indicate range over which inputs were characterized. asynchronous operation, signal must persist this time guarantee capture. This value assumes RSTCLK frequency TBIT 2*fRST. approximate value standard case normal mode operation. This value dependent RSTCLK frequency, divisors, LowPower mode, core frequency. Reassertions signal within this time guaranteed seen core. This value assumes that skew between RSTCLK K7CLKOUT much less than phase. This value assumes RSTCLK K7CLKOUT running same frequency, though processor capable other configurations.
Chapter
Electrical Data
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
7.13
APIC Pins Characteristics
Table shows Duron Processor Model characteristics APIC pins.
Table APIC Pins Characteristics
Symbol ILEAK_P ILEAK_N TRISE TFALL CPIN
Notes:
Parameter Description Input High Voltage Input Voltage Output High Voltage Output Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Output Current Signal Rise Time Signal Fall Time Capacitance
Condition
-300
2.625 2.625
Units
Notes
-300 (Ground)
V/ns V/ns
Characterized across supply voltage range Values specified nominal (1.5 Scale parameters with 2.625 maximum Edge rates indicate range over which inputs were characterized
Electrical Data
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DuronProcessor Model Data Sheet
Signal Power-Up Requirements
This chapter describes DuronProcessor Model power-up requirements during system power-up warm resets.
Power-Up Requirements
Figure shows relationship between signals system during power-up sequence. This figure details requirements processor.
Signal Sequence Timing Description
3.3V Supply VCCA (2.5V) (for PLL) VCC_CORE (Processor Core) RESET# NB_RESET#
PWROK
System Clock
Figure Signal Relationship Requirements During Power-Up Sequence Notes:1) Figure represents several signals generically using names necessarily consistent with lists schematics. Requirements Figure described following section.
Chapter
Signal Power-Up Requirements
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Power-Up Timing Requirements. signal timing requirements follows: RESET# must asserted before PWROK asserted. Duron Processor Model does correct clock multiplier PWROK asserted prior RESET# assertion. recommended that RESET# asserted least 10ns prior assertion PWROK. practice, Southbridges assert RESET# milliseconds before PWROK deasserted. motherboard voltage planes must specification before PWROK asserted. within
PWROK output voltage regulation circuit motherboard. PWROK indicates that VCC_CORE other voltage planes system within specification. motherboard required delay PWROK assertion minimum milliseconds from 3.3V supply being within specification. This delay ensures that system clock (SYSCLK/SYSCLK#) operating within specification when PWROK asserted. processor core voltage, VCC_CORE, must within specification dictated VID[4:0] pins driven processor before PWROK asserted. Before PWROK assertion, processor clocked ring oscillator. processor powered VCCA. processor does lock VCCA high enough processor logic switch some period before PWROK asserted. VCCA must within spec least microseconds before PWROK asserted. practice VCCA, VCC_CORE, other voltage planes must within specification several milliseconds before PWROK asserted. After PWROK asserted, processor locks operational frequency.
Signal Power-Up Requirements
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system clock (SYSCLK/SYSCLK#) must running within specification before PWROK asserted. When PWROK asserted, processor switches from driving internal processor clock grid from ring oscillator driving from PLL. reference system clock should valid this time. system clocks guaranteed running after 3.3V been within specification milliseconds. PWROK assertion deassertion RESET#. duration RESET# assertion during cold boots intended satisfy time takes lock with less than 1-ns phase error. processor begins after PWROK asserted internal clock grid switched from ring oscillator PLL. lock time take from hundreds nanoseconds tens microseconds. recommended that minimum time between PWROK assertion deassertion RESET# least 1.0ms. Southbridges enforce delay milliseconds between PWRGD (Southbridge version PWROK) assertion NB_RESET# deassertion. PWROK must monotonic. processor should switch between ring oscillator after initial assertion PWROK. NB_RESET# must asserted (causing CONNECT also assert) before RESET# deasserted. practice Southbridges enforce this requirement. NB_RESET# does assert until after RESET# deasserted, processor misinterprets CONNECT assertion (due NB_RESET# being asserted) beginning transfer (See "Serial Initialization Packet (SIP) Protocol" page 38). There must sufficient overlap resets ensure that CONNECT sampled asserted processor before RESET# deasserted. Clock Multiplier Selection (FID[3:0]) When RESET# de-asserted, Northbridge samples FID[3:0] Frequency from processor chipset specific manner. more information, "FID[3:0] Clock Multiplier Encodings" page
Chapter
Signal Power-Up Requirements
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
orthbridge uses this informat other information sampled deassertion RESET# determine correct Serial Initialization Packet (SIP) send processor configuration Duron system clock multiplier (processor frequency) indicated FID[3:0] code. sent processor using protocol. This protocol uses PROCRDY, CONNECT, CLKFWDRST signals, which synchronous SYSCLK. Serial Initialization Packet (SIP) Protocol Refer Athlonand DuronSystem Specification, order# 21902 details protocol. Packet (SIP) Protocol
Processor Warm Reset Requirements
RESET cannot asserted processor without also being asserted Northbridge. RESET# Northbridge same RESET#. minimum assertion RESET# millisecond. Southbridges enforce minimum assertion RESET# (processor, Northbridge, PCI) milliseconds.
DuronProcessor Model Northbridge Reset Pins
Signal Power-Up Requirements
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23802I-June 2001
DuronProcessor Model Data Sheet
Mechanical Data
Introduction
DuronProces Mode connects motherboard through socket named Socket more information, Athlon Processor Socket Application Note, order# 90020.
Loading
processor CPGA package exposed package. This done facilitate heat transfer from approved heat sink. critical that mechanical loading heat sink does exceed limits shown Table heat sink design should avoid loads corners edges die. CPGA package compliant pads that serve bring surfaces planar contact. Table CPGA Mechanical Loading
Location Surface Edge
Notes:
Dynamic (MAX)
Static (MAX)
Units
Note
Tool-assisted zero insertion force sockets should designed such that load placed ceramic substrate package. Load specified coplanar contact surface. Load defined surface more than degree angle inclination surface.
Chapter
Mechanical Data
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Pinout Diagram
location designations Socket connector shown Figure page Voided (plugged) locations should have base that accepts contact, plate Socket should have openings. exceptions plugs outside corners, which should permanently closed accommodate contact. permissible, necessary manufacturing reasons, place contact base plug sites (except plugs outside corners). Socket sites, with plugs total. more information, Chapter "Pin Descriptions" page addition, Figure page shows Socket package side view view.
Mechanical Data
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23802I-June 2001
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Figure Package, Top, Side, Bottom Views Chapter Mechanical Data
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Socket Tabs Heatsink Clips
Figure shows socket required Socket These features required support 300g heatsink. Figure page shows socket side view.
Note: Measurements
Figure Socket with Outline Socket Heatsink
Mechanical Data
Chapter
23802I-June 2001
DuronProcessor Model Data Sheet
Figure Socket Heatsink Side View
Chapter
Mechanical Data
Preliminary Information DuronProcessor Model Data Sheet
23802I-June 2001
Mechanical Data
Chapter
23802I-June 2001
DuronProcessor Model Data Sheet
10.1
Descriptions
Diagram Name Abbreviations
Figure page shows staggered Grid Array (PGA) DuronProcessor Model Because some names long grid, they abbreviated. Figure page shows bottomside view array. Table page lists pins alphabetical order name, along with abbreviation where necessary.
Chapter
Descriptions
DuronProcessor Model Data Sheet
SAO#12 SAO#7 SAO#11 SAO#10 SAO#0 VID[0] PICCLK SCNCK1 FID[0] FID[2] DBRDY STPC# A20M# FERR IGNNE# INTR
SAO#5 SAO#8 SAO#4 SAO#13 VID[2] PICD#1 SCNSN SCNCK2 VREF_S SVRFM CPR# SMI#
SAO#3 SAO#2 SAO#6
SD#55 SD#54 SD#52
SD#61 SDOC#3 SD#50
SD#53 SCK#6 SD#49
SD#63 SD#51 SDIC#3
SD#62 SD#60 SD#48
SCK#7 SD#59 SD#58
SD#57 SD#56 SD#36
SD#39 SD#37 SD#46
SD#35 SD#47 SCK#4
SD#34 SD#38 SDIC#2
SD#44 SD#45 SD#33
SCK#5 SD#43 SD#32
SDOC#2 SD#42 SCK#3 SD#20 SD#19 SD#26 SD#25 SD#24 SD#7 SD#5 SDIC#0 SCK#1 SD#8 SD#10 SAI#5 SAI#2 SAIC# SAI#8 SDINV#
SD#40 SD#41 SD#31 SD#23 SDIC#1 SCK#2 SD#27 SD#17 SD#15 SD#4 SD#2 SD#3 SD#0 SD#14 SDOC#0 SAI#11 SAI#6 SAI#4 SAI#13
SD#30
SAO#9
SDOC#1
SAOC#
SD#22
SAO#14
SD#21
SAO#1
VID[4] VID[3]
SD#29
VID[1]
SD#28
PICD#0
SD#18
VCC_Z VSS_Z
SD#16
SCNINV
TRST#
FID[1]
DuronProcessor Model Topside View
SD#6
Descriptions Chapter
SCK#0
SD#1
FID[3]
SD#12
DBREQ#
SD#13
COREFB
PLTST#
SD#11
PWROK
SD#9
COREFB# PLMN2
ANLOG PLBYC# PLMN1
CLKFR RCLK# K7CO RCLK K7CO#
VCCA CNNCT PRCRDY
PLBYP#
SAI#0 SFILLV# SAI#1 SDOV# SAI#12 SAI#14
RESET#
SAI#7
CLKIN# PLBYC
INIT#
SAI#3
23802I-June 2001
FLUSH#
SAI#10
CLKIN
SAI#9
Figure DuronProcessor Model Diagram-Topside View
DuronProcessor Model Data Sheet
SAO#7 SAO#12 SAO#5 SAO#3 SD#55 SD#61 SD#53 SD#63 SD#62 SCK#7 SD#57 SD#39 SD#35 SD#34 SD#44 SCK#5 SDOC#2 SD#40 SD#30
SAO#11 SAOC# SAO#4 SAO#6 SD#52 SD#50 SD#49 SDIC#3 SD#48 SD#58 SD#36 SD#46 SCK#4 SDIC#2 SD#33 SD#32 SCK#3 SD#31 SD#22
SAO#10 SAO#14 SAO#13
SAO#0 SAO#1 VID[4]
VID[0] VID[1] VID[2] VID[3]
PICCLK PICD#0 PICD#1
SCNSN
SCNCK1 SCNINV SCNCK2
TRST#
FID[0] FID[1] VREF_S
FID[2] FID[3]
DBRDY DBREQ# SVRFM
STPC# PLTST# VCC_Z
A20M# PWROK VSS_Z
FERR RESET#
IGNNE# INIT# CPR#
INTR FLUSH# PLMN2 PLBYC# CLKIN# RCLK# K7CO CNNCT SAI#1 SDOV# SAI#8 SAI#4 SAI#10
SAO#9
SAO#8
SMI#
SAO#2
SD#54
COREFB# COREFB
SDOC#3
SCK#6
ANLOG
PLMN1
SD#51
PLBYC
Descriptions Chapter
SD#60
CLKIN
SD#59
SD#56
DuronProcessor Model Bottomside View
CLKFR VCCA PLBYP#
RCLK
K7CO#
SD#37
PRCRDY
SD#20 SD#23 SD#21
SD#47
SD#38
SD#19 SDIC#1 SD#29
SAI#0 SFILLV# SAI#2 SAIC# SAI#11 SAI#6 SAI#7 SAI#3
SD#45
SAI#12
SD#26 SCK#2 SD#28
SD#25 SD#27 SD#18
SD#24 SD#17 SD#16
SD#7 SD#15 SD#6
SD#5 SD#4 SCK#0
SDIC#0 SD#2 SD#1
SCK#1 SD#3 SD#12
SD#8 SD#0 SD#13
SD#10 SD#14 SD#11
SAI#5 SDOC#0 SD#9
SD#43
SAI#14
SD#42
SDINV#
23802I-June 2001
SD#41
SAI#13
SDOC#1
SAI#9
Figure DuronProcessor Model Diagram-Bottomside View
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DuronProcessor Model Data Sheet
Table Name Abbreviations
Abbreviation Full Name A20M# ANALOG CLKFWDRST CLKIN CLKIN# CONNECT COREFB COREFB# CPU_PRESENCE# DBRDY DBREQ# FERR FID[0] FID[1] FID[2] FID[3] FLUSH# IGNNE# INIT# INTR K7CLKOUT K7CLKOUT# AJ13 AJ21 AN17 AL17 AL23 AG11 AG13 AL21 AN21 AG15 AG17 AG27 AG29
Table Name Abbreviations (continued)
Abbreviation Full Name AA31 AC31 AD30 AE31 AF10 AF28
ANLOG CLKFR
CNNCT
CPR#
K7CO K7CO#
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Preliminary Information DuronProcessor Model Data Sheet
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Table Name Abbreviations (continued)
Abbreviation Full Name PICCLK PICD[0]# PICD[1]# PLLBYPASS# PLLBYPASSCLK PLLBYPASSCLK# PLLMON1 PLLMON2 PLLTEST# AF30 AF32 AG19 AG21 AG23 AG25 AG31 AH30 AJ11 AJ15 AJ17 AJ19 AJ27 AL11 AL25 AL27 AN11 AN25 AN27 AJ25 AN15 AL15 AN13 AL13
Table Name Abbreviations (continued)
Abbreviation PRCRDY Full Name PROCREADY PWROK RESET# RSTCLK RSTCLK# SADDIN[0]# SADDIN[1]# SADDIN[2]# SADDIN[3]# SADDIN[4]# SADDIN[5]# SADDIN[6]# SADDIN[7]# SADDIN[8]# SADDIN[9]# SADDIN[10]# SADDIN[11]# SADDIN[12]# SADDIN[13]# SADDIN[14]# SADDINCLK# SADDOUT[0]# SADDOUT[1]# SADDOUT[2]# SADDOUT[3]# SADDOUT[4]# SADDOUT[5]# SADDOUT[6]# SADDOUT[7]# SADDOUT[8]# SADDOUT[9]# SADDOUT[10]# SADDOUT[11]# SADDOUT[12]# SADDOUT[13]# SADDOUT[14]# SADDOUTCLK# SCANCLK1 SCANCLK2 AN23 AN19 AL19 AJ29 AL29 AG33 AJ37 AL35 AE33 AJ35 AG37 AL33 AN37 AL37 AG35 AN29 AN35 AN31 AJ33
PICD#0 PICD#1 PLBYP# PLBYC PLBYC# PLMN1 PLMN2 PLTST#
RCLK RCLK# SAI#0 SAI#1 SAI#2 SAI#3 SAI#4 SAI#5 SAI#6 SAI#7 SAI#8 SAI#9 SAI#10 SAI#11 SAI#12 SAI#13 SAI#14 SAIC# SAO#0 SAO#1 SAO#2 SAO#3 SAO#4 SAO#5 SAO#6 SAO#7 SAO#8 SAO#9 SAO#10 SAO#11 SAO#12 SAO#13 SAO#14 SAOC# SCNCK1 SCNCK2
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Table Name Abbreviations (continued)
Abbreviation SCNINV SCNSN SCK#0 SCK#1 SCK#2 SCK#3 SCK#4 SCK#5 SCK#6 SCK#7 SD#0 SD#1 SD#2 SD#3 SD#4 SD#5 SD#6 SD#7 SD#8 SD#9 SD#10 SD#11 SD#12 SD#13 SD#14 SD#15 SD#16 SD#17 SD#18 SD#19 SD#20 SD#21 SD#22 SD#23 SD#24 SD#25 SD#26 SD#27 SD#28 Full Name SCANINTEVAL SCANSHIFTEN SCHECK[0]# SCHECK[1]# SCHECK[2]# SCHECK[3]# SCHECK[4]# SCHECK[5]# SCHECK[6]# SCHECK[7]# SDATA[0]# SDATA[1]# SDATA[2]# SDATA[3]# SDATA[4]# SDATA[5]# SDATA[6]# SDATA[7]# SDATA[8]# SDATA[9]# SDATA[10]# SDATA[11]# SDATA[12]# SDATA[13]# SDATA[14]# SDATA[15]# SDATA[16]# SDATA[17]# SDATA[18]# SDATA[19]# SDATA[20]# SDATA[21]# SDATA[22]# SDATA[23]# SDATA[24]# SDATA[25]# SDATA[26]# SDATA[27]# SDATA[28]# AA35 AA33 AE37 AC33 AC37 AA37 AC35
Table Name Abbreviations (continued)
Abbreviation SD#29 SD#30 SD#31 SD#32 SD#33 SD#34 SD#35 SD#36 SD#37 SD#38 SD#39 SD#40 SD#41 SD#42 SD#43 SD#44 SD#45 SD#46 SD#47 SD#48 SD#49 SD#50 SD#51 SD#52 SD#53 SD#54 SD#55 SD#56 SD#57 SD#58 SD#59 SD#60 SD#61 SD#62 SD#63 SDIC#0 SDIC#1 SDIC#2 SDIC#3 Full Name SDATA[29]# SDATA[30]# SDATA[31]# SDATA[32]# SDATA[33]# SDATA[34]# SDATA[35]# SDATA[36]# SDATA[37]# SDATA[38]# SDATA[39]# SDATA[40]# SDATA[41]# SDATA[42]# SDATA[43]# SDATA[44]# SDATA[45]# SDATA[46]# SDATA[47]# SDATA[48]# SDATA[49]# SDATA[50]# SDATA[51]# SDATA[52]# SDATA[53]# SDATA[54]# SDATA[55]# SDATA[56]# SDATA[57]# SDATA[58]# SDATA[59]# SDATA[60]# SDATA[61]# SDATA[62]# SDATA[63]# SDATAINCLK[0]# SDATAINCLK[1]# SDATAINCLK[2]# SDATAINCLK[3]#
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Table Name Abbreviations (continued)
Abbreviation SDINV# SDOC#0 SDOC#1 SDOC#2 SDOC#3 SDOV# SFILLV# STPC# SVRFM Full Name SDATAINVALID# SDATAOUTCLK[0]# SDATAOUTCLK[1]# SDATAOUTCLK[2]# SDATAOUTCLK[3]# SDATAOUTVALID# SFILLVALID# SMI# STPCLK# SYSVREFMODE TRST# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE AN33 AE35 AL31 AJ31
Table Name Abbreviations (continued)
Abbreviation Full Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE
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Table Name Abbreviations (continued)
Abbreviation Full Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE AB30 AB32 AB34 AB36 AF14 AF18 AF22 AF26 AF34 AF36 AH10 AH14 AH18 AH22 AH26 AK10 AK14 AK18 AK22 AK26 AK30 AK34 AK36 AM10 AM14 AM18 AM22 AM26 AM22 AM26 AM30
Table Name Abbreviations (continued)
Abbreviation Full Name VCC_CORE VCCA VCC_Z VID[0] VID[1] VID[2] VID[3] VID[4] VREF_SYS AM34 AJ23
VREF_S
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Table Name Abbreviations (continued)
Abbreviation Full Name AD32 AD34
Table Name Abbreviations (continued)
Abbreviation VSS_Z Full Name AD36 AF12 AF16 AH12 AH16 AH20 AH24 AH28 AH32 AH34 AH36 AK12 AK16 AK20 AK24 AK28 AK32 AM12 AM16 AM20 AM24 AM28 AM32 AM36
Descriptions
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10.2
List
Table cross-references Socket location signal name. (Level) column shows electrical specification this pin. indicates push-pull mode driven single source. indicates open-drain mode that allows devices share pin. Note: Socket Duron Processor supports push-pull drivers. more information, "Push-Pull (PP) Drivers" page (Port) column indicates this signal input (I), output (O), bidirectional signal. (Reference) column indicates this signal should referenced VCC_CORE planes purpose signal routing with respect current return paths. Table Cross-Reference Location
VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Name SDATA[30]# Description
Table Cross-Reference Location
SADDOUT[12]# SADDOUT[5]# SADDOUT[3]# SDATA[55]# SDATA[61]# SDATA[53]# SDATA[63]# SDATA[62]# SCHECK[7]# SDATA[57]# SDATA[39]# SDATA[35]# SDATA[34]# SDATA[44]# SCHECK[5]# SDATAOUTCLK[2]# SDATA[40]# page page Name Description page
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Table Cross-Reference Location (continued) Table Cross-Reference Location
Name VCC_CORE SADDOUT[7]# SADDOUT[9]# SADDOUT[8]# SADDOUT[2]# SDATA[54]# SDATAOUTCLK[3]# SCHECK[6]# SDATA[51]# SDATA[60]# SDATA[59]# SDATA[56]# SDATA[37]# SDATA[47]# SDATA[38]# SDATA[45]# SDATA[43]# SDATA[42]# SDATA[41]# SDATAOUTCLK[1]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE page Description VCC_CORE SADDOUT[11]# SADDOUTCLK# SADDOUT[4]# SADDOUT[6]# SDATA[52]# SDATA[50]# SDATA[49]# SDATAINCLK[3]# SDATA[48]# SDATA[58]# SDATA[36]# SDATA[46]# SCHECK[4]# SDATAINCLK[2]# SDATA[33]# SDATA[32]# SCHECK[3]# SDATA[31]# SDATA[22]# VCC_CORE VCC_CORE VCC_CORE page page page Name Description
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Table Cross-Reference Location (continued) Table Cross-Reference Location
VCC_CORE VCC_CORE VCC_CORE VCC_CORE SADDOUT[10]# SADDOUT[14]# SADDOUT[13]# SDATA[20]# SDATA[23]# SDATA[21]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE page page page page page page page page page page page page page page page page page Name VCC_CORE Description VCC_CORE VCC_CORE SADDOUT[0]# SADDOUT[1]# VID[4] SDATA[19]# SDATAINCLK[1]# SDATA[29]# VCC_CORE VCC_CORE VCC_CORE VID[0] VID[1] VID[2] VID[3] SDATA[26]# SCHECK[2]# SDATA[28]# page page page page page page page page page page page page page page page page Name Description
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Table Cross-Reference Location (continued) Table Cross-Reference Location
Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE PICCLK PICD#[0] PICD#[1] SDATA[25]# SDATA[27]# SDATA[18]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE SCANSHIFTEN SDATA[24]# SDATA[17]# SDATA[16]# VCC_CORE VCC_CORE page page page page page page page page page page Description Name VCC_CORE VCC_CORE SCANCLK1 SCANINTEVAL SCANCLK2 SDATA[7]# SDATA[15]# SDATA[6]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE TRST# SDATA[5]# SDATA[4]# SCHECK[0]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE page page page page page page page page page page page Description
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Table Cross-Reference Location (continued) Table Cross-Reference Location
FID[0] FID[1] VREFSYS SDATAINCLK[0]# SDATA[2]# SDATA[1]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE FID[2] FID[3] SCHECK[1]# SDATA[3]# SDATA[12]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE page page page page page page page page page page page Name Description AA31 AA33 AA35 AA37 AB30 AB32 AB34 AB36 AC31 AC33 AC35 AC37 AD30 AD32 AD34 AD36 DBRDY DBREQ# SYSVREFMODE SDATA[8]# SDATA[0]# SDATA[13]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE STPCLK# PLLTEST# VCC_Z SDATA[10]# SDATA[14]# SDATA[11]# VCC_CORE VCC_CORE VCC_CORE page page page page page page page page page page page page Name Description
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Table Cross-Reference Location (continued) Table Cross-Reference Location
AE31 AE33 AE35 AE37 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AF30 AF32 AF34 AF36 AG11 AG13 AG15 Name A20M# PWROK VSS_Z SADDIN[5]# SDATAOUTCLK[0]# SDATA[9]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE FERR RESET# COREFB COREFB# page page page page page page page page page page page page page page page page Description AG17 AG19 AG21 AG23 AG25 AG27 AG29 AG31 AG33 AG35 AG37 AH10 AH12 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AH32 AH34 AH36 SADDIN[2]# SADDIN[11]# SADDIN[7]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE IGNNE# INIT# VCC_CORE page page page page page page page Name Description page page page page page page page page
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Table Cross-Reference Location (continued) Table Cross-Reference Location
AJ11 AJ13 AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AJ33 AJ35 AJ37 AK10 AK12 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK30 AK32 AK34 AK36 Analog CLKFWDRST VCCA PLLBYPASS# SADDIN[0]# SFILLVALID# SADDINCLK# SADDIN[6]# SADDIN[3]# CPU_PRESENCE# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE INTR FLUSH# page page page page Name Description page page page page page page page page page page AL11 AL13 AL15 AL17 AL19 AL21 AL23 AL25 AL27 AL29 AL31 AL33 AL35 AL37 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AM32 AM34 PLLMON2 PLLBYPASSCLK# CLKIN# RSTCLK# K7CLKOUT CONNECT SADDIN[1]# SDATAOUTVALID# SADDIN[8]# SADDIN[4]# SADDIN[10]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE page Name VCC_CORE page page page page page page page page page page page page Description
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Table Cross-Reference Location (continued)
AM36 AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25 AN27 AN29 AN31 AN33 AN35 AN37 SMI# PLLMON1 PLLBYPASSCLK CLKIN RSTCLK K7CLKOUT# PROCRDY SADDIN[12]# SADDIN[14]# SDATAINVALID# SADDIN[13]# SADDIN[9]# page page page page page page page page page page page Name Description
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10.3
Detailed Descriptions
information this section pertains Table page
A20M#
A20M# input from system used simulate address wrap-around 20-bit 8086. Socket processors implement location AH6. Socket designs must have plate cover that blocks this location. When cover plate blocks this location, non-AMD part (e.g., PGA370) does into socket. However, socket manufacturers allowed have contact loaded position. Therefore, motherboard socket design should account possibility that contact could loaded this position. Athlonand DuronSystem Specification, order# 21902 information about system pins PROCRDY, PWROK, RESET#, SADDIN[14:2]#, SADDINCLK#, SADDOUT[14:2]#, SADDOUTCLK#, DATA DATA SDATAINVALID#, SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#. Treat this Advanced Programmable Interrupt Controller (APIC) feature that provides flexible expandable means delivering interrupts system using processor. pins, PICD[1:0], bi-directional message-passing signals used APIC driven Southbridge dedicated APIC. pin, PICCLK, must driven with valid clock input. more information, Table "APIC Pins Characteristics," page CLKFWDRST resets clock-forward circuitry both system processor. Connect CLKIN (AN17) with RSTCLK (AN19) name SYSCLK. Connect CLKIN# (AL17) with RSTCLK# (AL19) name SYSCLK#. Length match clocks from clock generator Northbridge processor. "SYSCLK SYSCLK#" page more information.
DuronSystem Pins
Analog APIC Pins, PICCLK, PICD[1:0]#
CLKFWDRST CLKIN, RSTCLK (SYSCLK) Pins
Descriptions
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CONNECT COREFB COREFB# Pins CPU_PRESENCE#
CONNECT input from system used power management clock-forward initialization reset. COREFB COREFB# outputs system that provide processor core voltage feedback system. CPU_PRESENCE# connected processor package. pulled-up motherboard, CPU_PRESENCE# used detect presence absence processor Socket A-style socket. DBRDY (AA1) DBREQ# (AA3) routed debug connector. DBREQ# tied VCC_CORE with pullup resistor. FERR output system that asserted unmasked numerical exception independent CR0. FERR push-pull active High signal that must inverted level shifted active signal. more information about FERR FERR#, "Required Circuits" chapter AthlonProcessor-Based Motherboard Design Guide, order# 24363. "Frequency Identification (FID[3:0])" page characteristics FID[3:0]. FID[3] (Y3), FID[2] (Y1), FID[1] (W3), FID[0] (W1) 4-bit processor clock-to-SYSCLK ratio. Table page describes encodings clock multipliers FID[3:0]
DBRDY DBREQ# Pins FERR
FID[3:0] Pins
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Preliminary Information DuronProcessor Model Data Sheet
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Table FID[3:0] Clock Multiplier Encodings
FID[3]
Note:
FID[2]
FID[1]
FID[0]
Processor Clock SYSCLK Frequency Ratio 11.5 12.5* 10.5
*All ratios greater than equal 12.5x have same FID[3:0] code 0011, which causes configuration ratios 12.5x greater same.
FID[3:0] signals open drain processor outputs that Northbridge deassertion RESET# determine (serialization initialization packet) that gets sent processor. Athlonand DuronSystem Specification, order#21902 more information about protocol. processor FID[3:0] outputs open drain 2.5V tolerant. prevent damage processor, these signals pulled High above they must electrically isolated from processor. information about FID[3:0] isolation circuit, AthlonProcessor-Based Motherboard Design Guide, order# 24363.
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FLUSH#
FLUSH# must tied VCC_CORE with pullup resistor. debug connector implemented, FLUSH# routed debug connector. IGNNE# input from system that tells processor ignore numeric errors. INIT# input from system that resets integer registers without affecting floating-point registers internal caches. Execution starts 0FFFF FFF0h. INTR input from system that causes processor start interrupt acknowledge transaction that fetches 8-bit interrupt vector starts execution that location. (Q1), (Q3), (U1), TRST# (U3), (U5) JTAG interface. Connect these pins directly motherboard debug connector. Pullup TDI, TCK, TMS, TRST# VCC_CORE with pullup resistors. K7CLKOUT (AL21) K7CLKOUT# (AN21) each inches then terminated with resistor pair, ohms VCC_CORE ohms VSS. effective termination resistance voltage ohms VCC_CORE/2. These locations processor type keying forwards backwards compatibility (G7, G15, G17, G23, G25, AA7, AG7, AG9, AG15, AG17, AG27, AG29). Motherboard designers should treat pins like connect) pins. Pins" page more information. socket designer option creating mold piece that allows pins only where designated. However, sockets that populate pins must allowed, motherboard must always provide pins locations. motherboard should provide plated hole pin. hole should electrically connected anything. input from system that causes non-maskable interrupt. present locations AN1. Motherboard designers should allow socket these locations. Descriptions
IGNNE# INIT#
INTR
JTAG Pins
K7CLKOUT K7CLKOUT# Pins
Pins
Pins Orientation Pins
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23802I-June 2001
more information, AthlonProcessor-Based Motherboard Design Guide, order# 24363. Bypass Test Pins PLLTEST# (AC3), PLLBYPASS# (AJ25), PLLMON1 (AN13), PLLBYPASSCLK# (AL15) bypass test interface. This interface tied disabled motherboard. signals routed debug connector. four processor inputs (PLLTEST#, PLLBYPASS#, PLLMON1, PLLMON2) tied VCC_CORE with pullup resistors. PWROK input processor must asserted until voltage planes system within specification system clocks running within specification. Requirements" page SADDIN[1:0]# SADDOUT[1:0]# Pins SADDIN[1:0]# SADDOUT[1:0]#. SADDIN[1]# tied with pullup resistors, this supported Northbridge (future models support SADDIN[1]#). SADDOUT[1:0]# tied with pullup resistors these pins supported Northbridge. more information, AthlonSystem Specification, order# 21902. SCANSHIFTEN (Q5), SCANCLK1 (S1), SCANINTEVAL (S3), SCANCLK2 (S5) scan interface. This interface internal tied disabled with pulldown resistors ground motherboard. systems that support ECC, SCHECK[7:0]# should treated pins. SMI# input that causes processor enter system management mode. STPCLK# input that causes processor enter lower power mode issue Stop Grant special cycle. SYSCLK SYSCLK# differential input clock signals provided processor's from system-clock generator. "CLKIN, RSTCLK (SYSCLK) Pins" page more information.
PWROK
Scan Pins
SCHECK[7:0]# SMI# STPCLK# SYSCLK SYSCLK#
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DuronProcessor Model Data Sheet
SYSVREFMODE
SYSVREFMODE (AA5) ensure that external VREFSYS voltage actual voltage used input buffers that scaling occurs internally between VREFSYS voltage input threshold. This tied with pulldown resistor. VCCA processor supply. information about VCCA pin, Table "VCCA Characteristics," page AthlonProcessor-Based Motherboard Design Guide, order# 24363. VID[4:0] (Voltage Identification) outputs used dictate VCC_CORE voltage level. VID[4:0] pins strapped ground left unconnected processor's package. VID[4:0] pins pulled-up motherboard used VCC_CORE DC/DC converter. These voltage values defined inTable page
VCCA
VID[4:0] Pins
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Table VID[4:0] Code Voltage Definition
VID[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 VCC_CORE 1.850 1.825 1.800 1.775 1.750 1.725 1.700 1.675 1.650 1.625 1.600 1.575 1.550 1.525 1.500 1.475 VID[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 VCC_CORE 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100
more information, "Required Circuits" chapter AthlonProcessor-Based Motherboard Design Guide, order# 24363. VREFSYS VREFSYS (W5) drives threshold voltage system input receivers. value VREFSYS system specific. addition, minimize VCC_CORE noise rejection from information, AthlonProcessor-Based Motherboard Design Guide, order# 24363. (AC5), VCC_Z (AC7), (AE5), VSS_Z(AE7) push-pull compensation circuit pins. VCC_ tied VCC_CORE. VSS_Z tied VSS. Push-Pull mode (selected parameter SysPushPull asserted), tied VCC_CORE with resistor that resistance matching impedance transmission line. tied with resistor that resistance matching impedance transmission line.
VCC_Z, VSS_Z Pins
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Ordering Information
Standard DuronProcessor Model Products
standard products available several operating ranges. ordering part numbers (OPN) formed combination elements shown Figure These OPNs examples only.
FSB: Size Cache: 1=64Kbytes Case Temperature: Operating Voltage: 1.6V Package Type: Speed: MHz, MHz, MHz, MHz, MHz, MHz, MHz, MHz, etc. Family/Architecture: DuronProcessor Model Architecture
Note: Spaces added number shown above viewing clarity only.
Figure Example DuronProcessor Model
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Ordering Information
Preliminary Information DuronProcessor Model Data Sheet
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Ordering Information
Chapter
23802I-June 2001
DuronProcessor Model Data Sheet
Appendix
Conventions, Abbreviations, References
This section contains information about conventions abbreviations used this document.
Signals Bits
Active-Low Signals-Signal names containing pound sign, such SFILL#, indicate active-Low signals. They asserted their Low-voltage state negated their High-voltage state. When used this context, High written with initial upper case letter. Signal Ranges-In range signals, highest lowest signal numbers contained brackets separated colon (for example, D[63:0]). Reserved Bits Signals-Signals bits marked reserved must driven inactive left unconnected, indicated signal descriptions. These bits signals reserved future implementations. When software reads registers with reserved bits, reserved bits must masked. When software writes such registers, must first read register change only non-reserved bits before writing back register. Three-State-In timing diagrams, signal ranges that high impedance shown straight horizontal line half-way between high levels.
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Invalid Don't-Care-In timing diagrams, signal ranges that invalid don't-care filled with screen pattern.
Data Terminology
following list defines data terminology:
Quantities word bytes bits) doubleword four bytes bits) quadword eight bytes bits) Addressing-Memory addressed series bytes eight-byte (64-bit) boundaries which each byte separately enabled. Abbreviations-The following notation used bits bytes: Kilo 4-Kbyte page) Mega Mbits/sec) Giga Gbytes memory space) Table more abbreviations. Little-Endian Convention-The byte with address xx.xx00 least-significant byte position (little end). byte diagrams, positions numbered from right left-the little right left. Data structure diagrams memory show addresses bottom high addresses top. When data items aligned, notation 64-bit data maps directly notation 64-bit-wide memory. Because byte addresses increase from right left, strings appear reverse order when illustrated. Ranges-In text, ranges shown with dash (for example, bits 9-1). When accompanied signal name, highest lowest numbers contained brackets separated colon (for example, AD[31:0]). Values-Bits either cleared Hexadecimal Binary Numbers-Unless context makes interpretation clear, hexadecimal numbers followed binary numbers followed
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Abbreviations Acronyms
Table contains definitions abbreviations used this document. Table Abbreviations
Abbreviation Gbit Gbyte Kbyte Mbit Mbyte Meaning Ampere Farad GigaGigabit Gigabyte Henry Hexadecimal KiloKilobyte MegaMegabit Megabyte Megahertz MilliMillisecond Milliwatt MicroMicroampere Microfarad Microhenry Microsecond Microvolt nanonanoampere nanofarad nanohenry nanosecond picopicoampere
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Table
Abbreviation
Abbreviations (continued)
Meaning picofarad picohenry picosecond Second Volt Watt
Table contains definitions acronyms used this document. Table Acronyms
Abbreviation ACPI APCI APIC BIOS BIST DIMM DRAM EIDE EISA EPROM FIFO GART HSTL Meaning Advanced Configuration Power Interface Accelerated Graphics Port Peripheral Component Interconnect Application Programming Interface Advanced Programmable Interrupt Controller Basic Input/Output System Built-In Self-Test Interface Unit Double-Data Rate Dual Inline Memory Module Direct Memory Access Direct Random Access Memory Error Correcting Code Enhanced Integrated Device Electronics Extended Industry Standard Architecture Enhanced Programmable Read Only Memory DigitalAlphaBus First First Graphics Address Remapping Table High-Speed Transistor Logic Integrated Device Electronics Industry Standard Architecture
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Table
Abbreviation JEDEC JTAG LVTTL MTRR PBGA PMSM POST SDRAM SMbus SRAM SROM
Acronyms (continued)
Meaning Joint Electron Device Engineering Council Joint Test Action Group Large Area Network Least-Recently Used Voltage Transistor Transistor Logic Most Significant Memory Type Range Registers Multiplexer Non-Maskable Interrupt Open-Drain Plastic Ball Grid Array Physical Address Peripheral Component Interconnect Page Directory Entry Page Directory Table Phase Locked Loop Power Management State Machine Power-On Suspend Power-On Self-Test Random Access Memory Read Only Memory Read Acknowledge Queue System DRAM Interface Synchronous Direct Random Access Memory Serial Initialization Packet System Management Serial Presence Detect Synchronous Random Access Memory Serial Read Only Memory Translation Lookaside Buffer Memory Transistor Transistor Logic Virtual Address Space Virtual Page Address
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Table
Abbreviation
Acronyms (continued)
Meaning Video Graphics Adapter Universal Serial Zero Delay Buffer
Chapter

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