Processor Module Data Sheet Publication 21016 Rev: Issue Date: Ju

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Athlon
Processor Module Data Sheet
Publication 21016 Rev: Issue Date: June 2000
2000 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, logo, Athlon, combinations thereof, 3DNow!, AMD-751, AMD-756 trademarks Advanced Micro Devices, Inc. trademark Intel Corporation. Digital Alpha trademarks Digital Equipment Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
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AthlonProcessor Module Data Sheet
Contents
Revision History. About This Data Sheet. Overview
AthlonProcessor Microarchitecture Summary Overview Signaling Technology Athlon System Signals
Interface Signals
Logic Symbol Diagram Power Management
Power Management States Full-On Halt State Stop Grant Sleep States. Probe State. Connection Disconnection Protocol Connection Protocol Connection State Machines
Thermal Design Electrical Data
Athlon System Signal Groupings Clock Forwarding. Voltage Identification Frequency Identification Decoupling Termination Termination CLKFWD Signal Groups SYSCLK, SYSCLK# Operating Ranges Absolute Ratings Power Dissipation Characteristics Characteristics Southbridge Characteristics APIC Characteristics Signal Power-Up Requirements
6.10 6.11 6.12 6.13 6.14
Contents
Preliminary Information AthlonProcessor Module Data Sheet
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Mechanical Data
Introduction Module Dimensions Athlon Processor Card-Edge Signal Listing
Ordering Information
Standard Athlon Processor Products
Appendix Conventions, Abbreviations, References
Signals Bits Data Terminology Abbreviations Acronyms. Related Publications. Publications Website
Contents
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AthlonProcessor Module Data Sheet
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Typical AthlonProcessor System Block Diagram Logic Symbol Diagram Athlon Processor Athlon Processor Power Management States Example System Disconnection Sequence Exiting Stop Grant State/Bus Reconnection Sequence System Connection States Processor Connection States Test Circuit Athlon Processor Module Dimensions-Front View
Figure Athlon Processor Module Dimensions-Plate Side View Figure Athlon Processor Module Dimensions-Side View Figure Athlon Processor Module Dimensions-Edge View. Figure Card Edge Dimensions-Thermal Plate Side View Figure Card Edge Dimensions (Detail) Figure Example Athlon Processor Model Figure Example Athlon Processor Model
List Figures
Preliminary Information AthlonProcessor Module Data Sheet
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List Figures
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AthlonProcessor Module Data Sheet
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Pin-Type Definitions AthlonSystem Legacy Interface Signals Athlon Processor Power Management States Athlon Processor Interface Signal Groupings Source-Synchronous Clock Signal Groups Voltage Values Signal Clock Layout Termination Requirements. Operating Ranges. Absolute Ratings VCC_CORE Power Current Model Model Model Characteristics Characteristics Southbridge Characteristics APIC Characteristics. Athlon Processor Module Dimensions Notes Dimension Drawings Athlon Processor Signals Ordered Number. Athlon Processor Signals Ordered Name. Athlon Processor Signals Ordered Physical Location. Valid Ordering Part Number Combinations Model Valid Ordering Part Number Combinations Model Valid Ordering Part Number Combinations Model Abbreviations Acronyms.
List Tables
Preliminary Information AthlonProcessor Module Data Sheet
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viii
List Tables
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AthlonProcessor Module Data Sheet
Revision History
Date
Description Added information about Athlonprocessor Model following chapters: "About This Data Sheet" page Chapter "Overview" page Chapter "Electrical Data" page Chapter "Ordering Information" page Revised SADDIN SADDOUT information Chapter "Logic Symbol Diagram" page Added "Signal Power-Up Requirements" page Revised Chapter "Thermal Design" page
June 2000
2000
Non-public version Added information about 950-MHz Athlon processor following tables: Table "VCC_CORE Power Current Model Model Model page Table "Valid Ordering Part Number Combinations Model page Revised information about 900-MHz 1-GHz (1000 MHz) Athlon processor Table "Valid Ordering Part Number Combinations Model page
March 2000
Added information about 900-MHz 1-GHz (1000 MHz) Athlon processor following chapters:
February 2000
Chapter "Overview" page Chapter "Electrical Data" page following tables: Table "Operating Ranges," page Table "VCC_CORE Power Current Model Model Model page Table Characteristics," page Chapter "Ordering Information" page
Added information about 850-MHz Athlon processor following chapters: Chapter "Overview" page Chapter "Electrical Data" page following tables: Table "Operating Ranges," page Table "Typical Maximum Power Dissipation Model 2-Part One," page Table Characteristics," page Chapter "Ordering Information" page Reorganized entire book merging Part Part together integrate Model Model information.
February 2000
Revised Power Supply Current Maximum values 550-MHz through 800-MHz Model processors Table Characteristics," page Revised Power Supply Current Maximum values Model 1processors Table Characteristics Model page
Revision History
Preliminary Information AthlonProcessor Module Data Sheet
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Date
Description Added information about 800-MHz Athlon processor following chapters: Chapter "Electrical Data" page following tables: Table "Operating Ranges," page Table "Typical Maximum Power Dissipation (Model 2)," page Table Characteristics (Model 2)," page Chapter "Ordering Information" page Changed value pullup resistors from 68-ohms 47-ohms "Termination" section starting page Table "Signal Clock Layout Termination Requirements," page Figure "Test Circuit" page Revised maximum thermal power values Model processors Table "Typical Maximum Power Dissipation (Model 2)," page Divided book into Part Part Two. Part provides information about Athlonprocessor family (Model Model Part provides information specific Athlon processor Model (0.18-micron process technology). Revisions Part One: Chapter "Electrical Data" page Expanded information "Termination" section starting page including addition Table "Signal Clock Layout Termination Requirements". Revised maximum rating Table "Absolute Ratings," page Revised Stop Grant values Table "Typical Maximum Power Dissipation (Model 1)," page Added values notes Table Characteristics (Model 1)," page Chapter "Mechanical Data" page added SCHECK[2]# SCHECK[7]# signal Tables starting page
January 2000
December 1999
October 1999
Added Athlonprocessor Table "Typical Maximum Power Dissipation (Model 1)," page Table "Valid Ordering Part Number Combinations," page Revised Table Characteristics (Model 1)," page Table Characteristics," page Revised VCC_CORE minimum value from 1.4V 1.5V Table "Operating Ranges," page
August 1999 August 1999
Revised information Table "Absolute Ratings," page Revised information Table "Typical Maximum Power Dissipation (Model 1)," page Initial public release
Revision History
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AthlonProcessor Module Data Sheet
About This Data Sheet
This Athlonprocessor data sheet describes technical specifications Athlon processor family designed Slot mechanical connector. processor module include either Athlon processor Model Model Model more information about determining Model number features Athlon processor module, Processor Recognition Application Note, order# 20734 Athlon Processor Revision Guide, order# 22557. information about versions Athlon processor, AthlonProcessor Data Sheet, order#23792.
About This Data Sheet
Preliminary Information AthlonProcessor Module Data Sheet
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About This Data Sheet
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AthlonProcessor Module Data Sheet
Overview
Athlonprocessor powers next generation computing platforms, delivering ultimate performance cutting-edge applications unprecedented computing experience.
Athlonprocessor family continues deliver leading-edge processor performance high-performance desktop systems, workstations, servers. newest member Athlon processor family integrates high-performance, full-speed 256-Kbyte Level-Two (L2) cache. Achieving frequencies 1-GHz (1000 MHz), Athlon processor world's most powerful processor, delivering highest integer, floating-point multimedia performance applications running system platforms. Athlon processors provide industry-leading processing power cutting-edge software applications, including digital content creation, digital photo editing, digital video, image compression, video encoding streaming over internet, DVD, ommerc modeling, workstation-class computer-aided design (CAD), commercial desktop publishing, speech recognition. also offers scalability `peace-of-mind' reliability that managers business users require enterprise computing. Athlon processor family features industry's first seventh-generation microarchitecture, which designed support rowing processo system bandwidt requirements emerging software, graphics, I/O, memory chnologies. Athlon processor' nine -issue superpipelined microarchitecture includes multiple full instruction decoders, high-performance cache architecture, three independent integer units, three address calculation units, industry's first superscalar, fully pipelined, out-of-order, three-way floating-point unit. floating-point single-precision more than Gflops double-precision floating-point results GHz, superior performance numerically complex applications.
Chapter
Overview
Preliminary Information AthlonProcessor Module Data Sheet
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Only Athlon processor microarchitecture incorporates Enhanced 3DNow!technology industry's first 200-MHz, 1.6-Gigabyte second front-side (FSB) fastest system platforms. AMD's Enhanced 3DNow! technology includes additional instructions popular 3DNow! instruction set. consists integer multimedia instructions software-directed data movement instructions optimizing such applications digital content creation streaming video internet, well inst ruct ions digit process (DSP)/communications applications. Based high-performance AlphaEV6 interface protocol licensed from Digital Equipment Corporation, Athlon system combines latest technological advances, such point-to-point topology, source-synchronous packet-based transfers, low-voltage signaling, provide most powerful, scalable available processor. Athlon processor binary-compatible with existing software backwards compatible with applications optimized MMXand 3DNow! instructions. Using data format single-instruction multiple-data (SIMD) operations based instruction model, Athlon processor produce many four, 32-bit, single-precision floating-point results clock cycle, potentially resulting Gflops (fully scalable). Athlon processors implemented AMD's advanced 0.18-micron process technology achieve maximum performance scalability. information about versions Athlon processor, AthlonProcessor Data Sheet, order#23792.
Overview
Chapter
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AthlonProcessor Module Data Sheet
AthlonProcessor Microarchitecture Summary
following features summarize Athlon processor microarchitecture:
Nine-issue, superpipelined, superscalar processor microarchitecture designed achieve high clock frequencies Multiple full instruction decoders Three out-of-order, superscalar, fully pipelined floating-point execution units, which execute (floating-point), MMX, 3DNow!, Enhanced 3DNow! instructions Three out-of-order, superscalar, pipelined integer units three address calculation units 72-entry instruction control unit Advanced dynamic branch prediction Enhanced 3DNow! technology 200-MHz Athlon system (scalable beyond MHz) enabling leading-edge system bandwidth data movement-intensive applications High-performance cache architecture including split 128-Kbyte cache, integrated 256-Kbyte cache (external 512-Kbyte cache Model Model large dual-level, split Translation Look-aside Buffer (TLB)
committed delivering reliable, high-performance, cost-effective solutions customers applications configurations. Athlon processor continues deliver superior system performance systems from desktops servers. Figure page shows typical Athlon processor system block diagram.
Chapter
Overview
Preliminary Information AthlonProcessor Module Data Sheet
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AthlonProcessor System Controller (Northbridge) Memory DRAM
Peripheral Controller (Southbridge) System Management
SCSI
Dual EIDE BIOS
Figure Typical AthlonProcessor System Block Diagram
Overview
Chapter
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AthlonProcessor Module Data Sheet
Interface Signals
Overview
Athlonsystem architecture designed liver unprecede oveme bandw idth next-generation platforms, well high performance required enterprise-class application software. system architecture consists three high-speed channels unidirectional processor request channel, unidirectional probe channel, 72-bit bidirectional data channel, including 8-bit error code correction [ECC] protection), source-synchronous clocking, packet-based protocol. addition, system supports several control, clock, legacy signals. interface signals HSTL-like, low-voltage swing signaling technology contained within Slot mechanical connector, which mechanically compatible with industry-standard SC242 connector.
Signaling Technology
Athlon system uses variation low-voltage, JEDEC HSTL signaling technology, which been enhanced provide larger noise margins, reduced ringing, variable voltage levels. signals open-drained require termination supply that provides High signal level. HSTL+ inputs differential receivers, which require reference voltage (VREF). reference signal used receivers determine signal asserted deasserted source. Termination resistors placed both ends interface used provide High signal level control reflections interface.
Chapter
Interface Signals
Preliminary Information AthlonProcessor Module Data Sheet
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AthlonSystem Signals
Table page shows Athlon system signals legacy interface signals. Table shows pin-type definitions used Type column Table Signals with pound signs active Low. Table
Pin-Type Definitions
Definition Standard input processor Standard output from processor Bidirectional, three-state input/output Open-drain structure that allows multiple devices share wired-OR configuration Push/Pull structure driven single source
Mnemonic
Table
AthlonSystem Legacy Interface Signals
Type Level Number Pins Description A20M# input from system used simulate address wrapping around 20-bit 8086. CLKFWDRST resets clock-forward circuitry both system processor. CONNECT input from system used power management clock-forward initialization reset. COREFB+ COREFB- outputs system that provide Athlon processor core voltage feedback system. FERR output system that asserted unmasked numerical exception independent CR0. FID[3:0] signals outputs system that report multiplier used system clock (SYSCLK) producing Athlon processor core clock. IGNNE# input from system that tells processor ignore numeric errors. INIT# input from system that resets integer registers without affecting floating-point registers internal caches. Execution starts 0FFFF FFF0h.
Signal Name A20M# CLKFWDRST CONNECT COREFB+ COREFB- FERR
FID[3:0] IGNNE# INIT#
Note:
industry-standard APIC signals, PICCLK PICD[1:0]#, available Model
Interface Signals
Chapter
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Table
AthlonSystem Legacy Interface Signals (continued)
Type Level Number Pins Description INTR input from system that causes processor start interrupt acknowledge transaction that fetches 8-bit interrupt vector starts execution that location. input from system that causes non-maskable interrupt. PICCLK input clock that required operation APIC bus. PICD[1:0]# bidirectional signals that used APIC bus, must connected APIC data pins devices APIC bus. PROCRDY output system used power management source-synchronous clock initialization reset. PWROK input from system indicating that core power within specified limits. RESET# input from system that initializes resets processor invalidates cache blocks. SADDIN[14:2]# unidirectional system probe data movement command channel from system. SADDINCLK# single-ended source-synchronous clock SADDIN[14:2]# driven system. SADDOUT[14:2]# unidirectional processor request channel system. used transfer processor requests probe responses system. SADDOUTCLK# single-ended source-synchronous clock SADDOUT[14:2]# driven processor. SCHECK[7:0]# contain bits data transfers SDATA[63:0]#. SDATA[63:0]# bidirectional channel between processor system data movement. SDATAINCLK[3:0]# single-ended forwarded clock driven system transfer data SDATA[63:0]#. Each 16-bit data word skewed-aligned with this clock. SDATAINVAL# driven system pace data into processor. SDATAINVAL# used introduce arbitrary number cycles between octawords into processor.
Signal Name INTR PICCLK* PICD[1:0]#*
PROCRDY PWROK RESET# SADDIN[14:2]# SADDINCLK# SADDOUT[14:2]# SADDOUTCLK# SCHECK[7:0]# SDATA[63:0]# SDATAINCLK[3:0]#
SDATAINVAL#
Note:
industry-standard APIC signals, PICCLK PICD[1:0]#, available Model
Chapter
Interface Signals
Preliminary Information AthlonProcessor Module Data Sheet
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Table
AthlonSystem Legacy Interface Signals (continued)
Type Level Number Pins Description SDATAOUTCLK[3:0]# single-ended source-synchronous clock driven processor transfer data SDATA[63:0]#. Each 16-bit data word SDATA[63:0]# skewed-aligned with this clock. SDATAOUTVAL# driven system pace data from processor. SDATAOUTVAL# used introduce arbitrary number cycles between quadwords from processor. SFILLVAL# validates data transfer processor. system this asserted state (validating fills). processor samples SFILLVAL# first second data beat. SMI# input that causes processor enter system management mode. STPCLK# input that causes processor enter lower power mode issue Stop Grant special cycle. SYSCLK SYSCLK# differential input clock signals provided processor's from system-clock generator. VCC2SEL output system that indicates required core voltage SRAM. High=2.5V, Low=3.3V. VID[3:0] signals outputs motherboard that indicate required VCC_CORE voltage processor.
Signal Name
SDATAOUTCLK[3:0]#
SDATAOUTVAL#
SFILLVAL#
SMI# STPCLK# SYSCLK SYSCLK# VCC2SEL VID[3:0]
Note:
industry-standard APIC signals, PICCLK PICD[1:0]#, available Model
Interface Signals
Chapter
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AthlonProcessor Module Data Sheet
Logic Symbol Diagram
Clock
SYSCLK SDATA[63:0]# SDATAINCLK[3:0]# SDATAOUTCLK[3:0]# SCHECK[7:0]# SDATAINVAL# SDATAOUTVAL# SFILLVAL#
SYSCLK# VID[3:0] COREFB+ COREFB- PWROK VCC2SEL FID[3:0]
Data
Voltage Control Frequency Control
Probe/SysCMD Request
SADDIN[14:1]# SADDINCLK# SADDOUT[14:0]# SADDOUTCLK# PROCRDY CLKFWDRST CONNECT STPCLK# RESET#
AthlonProcessor
FERR IGNNE# INIT# INTR A20M# SMI# *PICCLK *PICD[1:0]#
Legacy
Power Management Initialization
APIC*
Note:
industry-standard APIC signals, PICCLK PICD[1:0]#, available Model
Figure Logic Symbol Diagram AthlonProcessor
Chapter
Logic Symbol Diagram
Preliminary Information AthlonProcessor Module Data Sheet
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Logic Symbol Diagram
Chapter
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AthlonProcessor Module Data Sheet
Power Management
Power Management States
Athlonprocessor uses multiple advanced power states place processor reduced power modes. These power states used enhance processor performance, minimize power dissipation, provide balance between performance power (see "Power Dissipation" page more information). addition, these power states conform industry-standard Advanced Configuration Power Interface (ACPI) requirements processor power states. (ACPI specification system hardware software support OS-oriented power management.) Each state specific mechanism that allows processor enter respective state. Figure shows power management states Athlon processor. figure includes ACPI power states processor, labeled
Execute Special Cycle SMI#, INTR, NMI, INIT#, RESET# Note
Auto Halt
Normal Full-On
sser
Read PLVL2 register
STPCLK# deasserted
STPCLK# asserted
Note: transition STPCLK# assertion/deassertion defined ACPI-compliant systems.
Figure AthlonProcessor Power Management States
Chapter
Incoming Probe
Probe State
Probe Serviced
Incoming Probe Probe Serviced
Stop Grant
Sleep
Legend: Hardware transitions Software transitions
Power Management
Preliminary Information AthlonProcessor Module Data Sheet
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following sections describe each low-power states. Note: power management states, system must disable system clock (SYSCLK/SYSCLK#) processor. Full-On Full-on normal state refers default power state means that functional units operating full processor clock speed. When Athlon processor executes instruction, processor issues Halt special cycle system bus. phase-lock loop (PLL) continues run, enabling processor monitor activity provide quick resume from Halt state. processor enter lower power state. Halt state exited when processor samples INIT#, INTR interrupts enabled), NMI, RESET#, SMI#. Stop Grant Sleep States After recognizing assertion STPCLK#, Athlon processor completes pending in-progress cycles acknowledges STPCLK# assertion issuing Stop Grant special cycle system bus. processor enter lower power state. From software standpoint, Sleep/Stop Grant state ACPI-compliant peripheral controller. difference between Stop Grant state Sleep state determined which PLVL register software reads from peripheral controller. software reads PLVL_2 register, processor enters Stop Grant state. this state, probes allowed, shown Figure page software reads PLVL_3 register, processor enters Sleep state, where probes allowed. This action accomplished disabling snoops within ACPI-compliant system controller. Sleep/Stop Grant state exited upon deassertion STPCLK# assertion RESET#. After processor enters Full-on state, resumes execution instruction boundary where STPCLK# initially recognized. processor latches INIT#, INTR interrupts enabled), NMI, SMI#, they asserted during Stop Grant Sleep state. However, processor does exit this state until deassertion STPCLK#. When STPCLK# deasserted, Power Management Chapter
Halt State
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AthlonProcessor Module Data Sheet
pending interrupts recognized after returning Normal state. RESET# sampled asserted during Stop Grant Sleep state, processor immediately returns Full-on state reset process begins. Probe State Probe state entered when system requires processor service probe. When Probe state, processor responds probe cycle same manner when Full-on state. When probe been serviced, processor returns same state when entered Probe state.
Connection Disconnection Protocol
Athlon processor enhances power savings each disconnects processor from system slows down internal clocks. Entering lowest power state accomplished with connection protocol between processor system logic. system initiate disconnection upon receipt Stop Grant special cycle. required system, processor disconnects from system slows down internal clocks before entering Stop Grant Sleep state. system requires processor service probe while Stop Grant state, must first request that processor increase clocks full speed reconnect system bus. Table page describes Athlon processor power states using connection protocol described page Athlon system connections disconnections controlled enable within system controller.
Chapter
Power Management
Preliminary Information AthlonProcessor Module Data Sheet Table AthlonProcessor Power Management States
Entered This full-on running state processor Execution Halt instruction. special cycle issued. processor enter lower power state. Exited Initiates either Halt instruction STPCLK# assertion. processor exits returns state upon occurrence INIT#, INTR, NMI, SMI# RESET#. processor transitions Stop Grant state STPCLK# asserted returns Halt state upon STPCLK# deassertion.
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State Name Full-On Normal
Halt
Stop Grant
processor transitions Stop Grant state with assertion STPCLK# processor transitions Full-on Halt state result read PLVL_2 register). upon STPCLK# deassertion. Stop Grant special cycle issued. processor enter lower power state. RESET# asserted initializes processor but, STPCLK# asserted, processor returns Note: While this state, interrupts Stop Grant state. latched serviced when processor transitions Full-on state. transition Probe state occurs when system asserts CONNECT. processor remains this state until probe serviced data transferred. processor returns Halt Stop Grant state when probe been serviced system deasserts CONNECT. processor disconnected from previous state, disconnection occurs internal frequency processor again slowed down.
Probe
Sleep
processor enter lowest power state, Sleep, from Full-on state with processor transitions state upon assertion STPCLK# result read STPCLK# deassertion. Asserting RESET# initializes PLVL_3 register). processor but, STPCLK# asserted, processor Note: While this state, interrupts returns Sleep state. latched serviced when processor transitions Full-on state.
Connection Protocol
addition legacy STPCLK# signal Halt Stop Grant special cycles, Athlon system connection protocol includes CONNECT, PROCRDY, CLKFWDRST signals Connect special cycle. Athlon system disconnects initiated system controller response receipt Stop Grant special cycle. Reconnections initiated processor response interrupt STPCLK# deassertion, system service probe. disconnect request implicit, enabled, processor Stop Grant special cycle request. expected that system controller provides BIOS-programmable register which
Power Management
Chapter
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AthlonProcessor Module Data Sheet
disconnect processor from Athlon system upon occurrence Stop Grant special cycle. system receives special cycle request from processor and, there outstanding probes data movements, system deasserts CONNECT processor. processor detects deassertion CONNECT rising edge SYSCLK, deasserts PROCRDY system. return, system asserts CLKFWDRST anticipation reestablishing connection some later point. Note: system must disconnect processor from Athlon system before issuing Stop Grant special cycle bus. processor receive interrupt STPCLK# deassertion after sends Stop Grant special cycle system before disconnection actually occurs. this case, processor sends Connect special cycle system, rather than continuing with disconnect sequence. system cancels disconnection. Figure shows sequence events from system perspective, which leads disconnecting processor from Athlon system placing processor Stop Grant state.
STPCLK# System CONNECT PROCRDY CLKFWDRST Stop Grant Stop Grant
Figure Example System Disconnection Sequence following sequence events describes processor placed Stop Grant state when disconnection enabled within system controller: peripheral controller asserts STPCLK# place processor Stop Grant state. When processor receives STPCLK#, acknowledges system sending Stop Grant special cycle Athlon system bus. Chapter Power Management
Preliminary Information AthlonProcessor Module Data Sheet
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When special cycle received system controller, system controller deasserts CONNECT, initiating disconnect processor. processor replies system controller deasserting PROCRDY, approving disconnect request. system controller asserts CLKFWDRST complete disconnection sequence. After processor disconnected from bus, system controller passes Stop Grant special cycle along peripheral controller bus, notifying that processor Stop Grant state. Figure shows signal sequence events that take processor Stop Grant state, reconnect processor Athlon system bus, processor into Full-on state.
STPCLK# PROCRDY CONNECT CLKFWDRST
Figure Exiting Stop Grant State/Bus Reconnection Sequence following sequence events removes processor from Stop Grant state reconnects Athlon system bus: peripheral controller deasserts STPCLK#, informing processor wake event. When processor receives STPCLK#, asserts PROCRDY, notifying system controller reconnect bus. system controller asserts CONNECT, telling processor that connected Athlon system bus. system controller finally deasserts CLKFWDRST, which synchronizes forwarded clocks between processor system controller. Power Management Chapter
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Connection State Machines
Figure Figure page describe system processor connection state machines, respectively.
Disconnect Pending Connect
Disconnect Requested
Disconnect 7/D,C
Reconnect Pending
Probe Pending
Probe Pending
Condition disconnect requested probes still pending disconnect requested probes pending CONNECT special cycle from processor probes pending PROCRDY deasserted probe needs service PROCRDY asserted SYSCLK periods after CLKFWDRST deasserted. Although reconnected system interface, system must issue non-NOP SysDC commands minimum four SYSCLK periods after deasserting CLKFWDRST.
Action Deassert CONNECT SYSCLK periods after last probe/command sent
Assert CLKFWDRST Assert CONNECT Deassert CLKFWDRST
Figure System Connection States Chapter Power Management
Preliminary Information AthlonProcessor Module Data Sheet
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Connect Connect Pending Connect Pending Disconnect
Disconnect Pending
Condition CONNECT deasserted system (for previously sent Halt Stop Grant special cycle). Processor receives wake-up event must cancel disconnect request. Processor wake-up event CONNECT asserted system. Forward clocks start SYSCLK periods after CLKFWDRST deasserted.
Action CLKFWDRST asserted system. Issue CONNECT special cycle. Assert PROCRDY return internal clocks full speed
Deassert PROCRDY slow down internal clocks.
CLKFWDRST deasserted system
Figure Processor Connection States
Power Management
Chapter
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Thermal Design
information about thermal design Athlonprocessor module, including layout airflow considerations, Thermal, Mechanical, Chassis Cooling Design www.amd.com.
Chapter
Thermal Design
Preliminary Information AthlonProcessor Module Data Sheet
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Thermal Design
Chapter
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AthlonProcessor Module Data Sheet
Electrical Data
AthlonSystem
Athlonsystem architecture designed liver unprecede oveme bandw idth next-generation platforms, well high performance required enterprise-class application software. system architecture consists three high-speed channels unidirectional processor request channel, unidirectional snoop channel, 72-bit bidirectional data channel, including 8-bit error code correction [ECC] protection), source-synchronous clocking, packet-based protocol. addition, system supports several control, clock, legacy signals. interface signals HSTL-like, low-voltage swing signaling technology contained within Slot mechanical connector, which mechanically compatible with industry-standard SC242 connector. more AthlonSystem Specification, order# 21902.
Signal Groupings
Athlon system processor connection memory controller shared multiprocessor controller. system interface categorized into four signal groups plus power ground connections. These groups listed Table page first group connects Athlon processor system controller uses source-synchronous, clock-forwarded clocking scheme. Using this technique, clocks data travel same direction down transmission line arrive together. second group connects Athlon processor peripheral controller, unlike system controller group, these signals source-synchronous scheme. third group control group, which contains signals that interface with power supply system. fourth group contains system clock. This input clock Athlon processor source other clocks generated Athlon processor module.
Chapter
Electrical Data
Preliminary Information AthlonProcessor Module Data Sheet
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Table
AthlonProcessor Interface Signal Groupings
Name Buffer Type Open-Drain Signals SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, SADDOUTCLK#, SFILLVAL#, SDATAINVAL#, SDATAOUTVAL#, SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, SCHECK[7:0]#, FID[3:0], CLKFWDRST, PROCRDY, CONNECT RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#, STPCLK#, PICD[1:0]#*, PICCLK* VID[3:0], VCC2SEL, COREFB+, COREFB-, PWROK SYSCLK, SYSCLK# VCC_CORE, VCC_SRAM,
System Controller (Northbridge) Peripheral Controller (Southbridge) Control Clock Power
Note:
industry-standard APIC signals, PICCLK PICD[1:0]#, available Model
Clock Forwarding
signals system controller group divided into source-synchronous groups, shown Table Groups that contain clocks bidirectional, source-synchronous groups. These groups different clock, based operation being performed. example, when data sent from Athlon processor system controller, SDATAOUTCLK# used, when data sent from system controller Athlon processor, SDATAINCLK# used. topology point-to-point active terminations.
Table
Group SData0 SData1 SData2 SData3 SAddIn SAddOut
Source-Synchronous Clock Signal Groups
Signals Group SDATA[15:0]#, SCHECK[0:1]# SDATA[31:16]#, SCHECK[2:3]# SDATA[47:32]#, SCHECK[4:5]# SDATA[63:48]#, SCHECK[6:7]# SADDIN[14:2]#, SFILLVAL#, SDATAINVAL#, SDATAOUTVAL# SADDOUT[14:2]# Clock SDATAINCLK[0]#, SDATAOUTCLK[0]# SDATAINCLK[1]#, SDATAOUTCLK[1]# SDATAINCLK[2]#, SDATAOUTCLK[2]# SDATAINCLK[3]#, SDATAOUTCLK[3]# SADDINCLK# SADDOUTCLK#
Electrical Data
Chapter
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Voltage Identification
Athlon processor provides four voltage lines back system proper configuration processor core voltage. processor either connects VSS, motherboard pulls these four signals levels. motherboard required pull VID[4] voltage regulator supply voltage appropriate range Athlon processor. These voltage values defined Table pullup resistors used motherboard must have value least Table Voltage Values
VID[3] VID[2] VID[1] VID[0] VCC_CORE 2.05 2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30
addition, Athlon processor provides VCC2SEL signal identify core voltage cache SRAMs. Like signals, Athlon processor either connects VCC2SEL open value, with pullup resistor motherboard. open value indicates that voltage 2.5V required VCC_SRAM, while indicates required voltage 3.3V.
Chapter
Electrical Data
Preliminary Information AthlonProcessor Module Data Sheet
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Frequency Identification
Athlon processor provides four frequency signals (FID[3:0]) system controller indicate SYSCLK multiplie which cesso core pera tes. This mechanism automatic, using system controller BIOS without jumpers motherboard operating frequency Athlon processor.
Decoupling
AthlonProcessor Voltage Regulation Design Application Note, order# 22651, contact your local office information about decoupling required motherboard with Athlon processor.
Termination
Table lists layout termination Slot signals clocks. additional information concerning termination design guidelines Athlon processor-based systems, contact your local representative obtain detailed documentation available under non-disclosure agreement.
Table
Signal Clock Layout Termination Requirements
Group/Name Termination Requirements Differential clock inputs system controller (Northbridge) Slot Point-to-point system clocks driven central system clock generator. "SYSCLK, SYSCLK#" page pullup resistors must kept with Northbridge. Termination" page These signals must pulled motherboard using 330-ohm resistor Vcc3 1.0-kohm resistor VSS. Route minimum length where possible. HSTL-like inputs. Point-to-point signals driven peripheral controller (Southbridge) Slot connector. These signals pulled VCC_CORE Slot card require termination motherboard.
SYSCLK, SYSCLK# SDATA0, SDATA1, SDATA2, SDATA3, SADDIN, SADDOUT1 CLKFWDRST, CONNECT, PROCRDY PICCLK2 PICD[1:0]2 NMI, INTR, SMI#, INIT#, A20M#, IGNNE#, STPCLK#, CPURESET#
Notes:
Table "Source-Synchronous Clock Signal Groups," page industry-standard APIC signals, PICCLK PICD[1:0]#, available Model
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AthlonProcessor Module Data Sheet
Termination
Both processor Northbridge HSTL-like open-drain outputs HSTL-like inputs. Therefore, signals must terminated both source destination with pullup resistors VCC_CORE. Pullups processor located processor module need considered terminations required motherboard pullup resistors Northbridge. These pullup termination resistors must located inch from Northbridge. systems that support ECC, SCHECK[7:0]# should tied VCC_CORE with 47-ohm pullup, with minimal routing where possible.
CLKFWD Signal Groups
termination scheme clock forward signals, both signal clock, involves having each terminated 47-ohm pullup resistor located inch from each device. Pullups processor located processor module need considered during motherboard layout. Note: data bus, SDATA[63:0], drives both directions and, therefore, must have unidirectional clock each data group travelling each way.
SYSCLK, SYSCLK#
Each SYSCLK pairs from clock generator processor, SYSCLK SYSCLK# (true complimentary), series terminated source with 47-ohm resistor located maximum distance inch from clock generator parallel terminated with 47-ohm resistor VCC_CORE. Parallel termination occurs processor module need cons idered motherboard layout.
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Electrical Data
Preliminary Information AthlonProcessor Module Data Sheet
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Operating Ranges
Athlon processor designed provide functional operation voltage temperature parameters within limits defined Table
Table
Operating Ranges
Description Athlonprocessor Model core supply 500-700 550-750 Athlon processor Model core supply 800-850 900-1000 Athlon processor Model core supply 650-850 900-1000 1.65 2.475 3.15 Nominal 1.75 1.85 2.625 3.45 Notes
Parameter
VCC_CORE
VCC_CORESLEEP Athlon processor core supply Sleep state VCC_SRAM TPLATE
Notes:
SRAM core supply SRAM core supply Temperature thermal plate
Normal operating conditions Sleep state operating conditions Value VCC_SRAM when VCC2SEL High Value VCC_SRAM when VCC2SEL
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AthlonProcessor Module Data Sheet
Absolute Ratings
Athlon processor should subjected conditions exceeding absolute ratings listed Table such conditions adversely affect long term reliability result functional damage.
Table
VCC_CORE VCC_SRAM VCC_SRAM VPIN TSTORAGE
Notes:
Absolute Ratings
Description Athlonprocessor core supply SRAM core supply SRAM core supply Voltage system Storage temperature processor -0.5 -0.5 -0.5 nominal Notes
Parameter
Value VCC_SRAM when VCC2SEL Value VCC_SRAM when VCC2SEL High
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Preliminary Information AthlonProcessor Module Data Sheet
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Power Dissipation
Table shows power current Athlon processor Model Model Model during normal reduced power states.
Table VCC_CORE Power Current Model Model Model
Frequency (MHz) Maximum Thermal Power Typical Thermal Power Model Model 1000
Notes:
Stop Grant (Maximum)4
Maximum (Power Supply Current)
Notes
Power measured 1.6V nominal Power measured 1.7V nominal Power measured 1.75V nominal Power measured 1.8V nominal Sleep state operating conditions measured 1.3V measured maximum VCC_CORE 1.7V-Power supply designs must take into account maximum power supply current. measured maximum VCC_CORE 1.8V-Power supply designs must take into account maximum power supply current. measured maximum VCC_CORE 1.85V-Power supply designs must take into account maximum power supply current. measured maximum VCC_CORE 1.9V-Power supply designs must take into account maximum power supply current.
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AthlonProcessor Module Data Sheet
Table VCC_CORE Power Current Model Model Model (continued)
Frequency (MHz) Maximum Thermal Power Typical Thermal Power Model 1000
Notes:
Stop Grant (Maximum)4
Maximum (Power Supply Current)
Notes
36.1 38.3 40.4 42.6 44.8 49.7 52.0 54.3
32.4 34.4 36.3 38.3 40.2 44.6 46.7 48.7
23.8 25.2 26.6 28.0 29.4 31.7 33.2 34.6
Power measured 1.6V nominal Power measured 1.7V nominal Power measured 1.75V nominal Power measured 1.8V nominal Sleep state operating conditions measured 1.3V measured maximum VCC_CORE 1.7V-Power supply designs must take into account maximum power supply current. measured maximum VCC_CORE 1.8V-Power supply designs must take into account maximum power supply current. measured maximum VCC_CORE 1.85V-Power supply designs must take into account maximum power supply current. measured maximum VCC_CORE 1.9V-Power supply designs must take into account maximum power supply current.
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Electrical Data
Preliminary Information AthlonProcessor Module Data Sheet
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6.10
Characteristics
characteristics Athlon processor shown Table These values defined card edge Athlon processor module.
Table Characteristics
Symbol VREF IVREF VIH-DC VIL-DC VIH-AC VIL-AC VOH-DC VOL-DC VOH-AC VOL-AC IOL-DC ILEAK
Notes:
Parameter Input Reference Voltage VREF Input Current Input High Voltage Input Voltage Input High Voltage Input Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output Current Tristate Leakage Input High Current Input Current Input Capacitance
Condition
Units Notes
(0.47*VCC_CORE) (0.47*VCC_CORE) VCC_CORE -250 VREF -300 VREF -500 VCC_CORE IOUT= IOL-DC-MAX -300 VCC_CORE -500 VOUT= VOL-DC-MAX VCC_CORE VIN=VIH-DC-MIN VIN=VIL-DC-MAX -100 +250 VCC_CORE VREF VCC_CORE VREF VCC_CORE +300 VCC_CORE +100
VREF: VREF nominally (1%) resistor divider from VCC_CORE. suggested divider resistor values 90.9 ohms over 80.6 ohms produce divisor 0.47. internal VREF (VREF-INT) external VREF scaled 0.80 (VREF-INT (VREF/0.80)). (Processor SysVrefMode High) Example: VCC_CORE 1.6V, VREF 752mV (1.6 0.47), VREF-INT 940mV (752mV/0.8). Peak-to-Peak noise VREF (AC) should exceed VREF (DC). IVREF should measured nominal VREF. VOL-DC-MAX, VOL-AC-MAX, VOH-DC-MIN VOH-AC-MIN specified 100°C VCC_CORE 1.4V. Does apply VREF. SYSCLK SYSCLK# signals have twice capacitance because they connect input pads. SYSCLK connects CLKIN/RSTCLK. SYSCLK# connects CLKIN#/RSTCLK#. following information pertains only Model Model SDATAINCLK[3:0]# signals have twice capacitance because they connect input pads. SDATAINCLK[3:0]# connects byte clocks form word sized clock.
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6.11
Characteristics
Table shows characteristics Athlon processor. parameters grouped based source destination signals involved. parameters defined card edge Athlon processor module.
Table Characteristics
Group Signals Symbol TRISE TFALL TSKEWSAMEEDGE Clock Forward TSKEWDIFFEDGE
Parameter Output Rise Slew Rate Output Fall Slew Rate Output skew with respect same clock edge Output skew with respect different clock edge Input Data Setup Time Input Data Hold Time Capacitance input Clocks Capacitance output Clocks RstClk Output Valid Setup RstClk Hold from RstClk
1000
2000
Units V/ns V/ns
Notes
COUT
Sync
Notes:
Test Circuit used-See Figure page Rise fall time ranges guidelines over which been characterized. TK7-SKEW-SAMEEDGE maximum skew within clock forwarded group between signals between signal forward clock, measured package, with respect same clock edge. TK7-SKEW-DIFFEDGE maximum skew within clock forwarded group between signals between signal forward clock, measured package, with respect different clock edges. Input times with respect appropriate Clock Forward Group input clock. synchronous signals include PROCRDY, CONNECT, CLKFWDRST. RstClk rising edge output valid PROCRDY. Test Load-25pf. setup CONNECT/CLKFWDRST rising edge RSTCLK. hold CONNECT/CLKFWDRST from rising edge RSTCLK.
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Preliminary Information AthlonProcessor Module Data Sheet
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VCC_CORE
Component
VCC_CORE
Component
Device Under Test Package
Package Device Under Test
Figure Test Circuit
Electrical Data
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AthlonProcessor Module Data Sheet
6.12
Southbridge Characteristics
racte isti Athlon processor Southbridge pins.
Table Southbridge Characteristics*
Symbol ILEAK TDELAY TBIT TRPT
Notes:
Parameter Description Input High Voltage Input Voltage
VCC_CORE -300 VCC_CORE -300 -100 -100 -100
Nominal
VCC_CORE VCC_CORE
Units
Notes
Delta Hysteresis change Output High Voltage Output Voltage Tristate Leakage Input High Current Input Current Output High Current Output Current Sync Input Setup Time Sync Input Hold Time Output Delay with respect RSTCLK Input Time Acquire Input Time Reacquire Input Voltage
10-14
20.0 40.0 -300 VCC_CORE
These parameters pertain Southbridge signals listed Table page Characterized across supply voltage range. Values specified nominal VCC_CORE. Scale parameters with VCC_CORE. Hysteresis values refer difference between initial return switching points. measured min, respectively. Synchronous inputs/outputs specified with respect RSTCLK RSTCK# pins. These aggregate numbers. specific pins vary widely within this window. Edge rates indicate range over which inputs were characterized. asynchronous operation, signal must persist this time guarantee capture. This value assumes RSTCLK frequency 10ns TBIT 2*fRST. approximate value standard case normal mode operation. This value dependent RSTCLK frequency, divisors, LowPower mode, core frequency. Reassertions signal within this time guaranteed seen core. This value assumes that skew between RSTCLK K7CLKOUT much less than phase. This value assumes RSTCLK K7CLKOUT running same frequency, though processor capable other configurations.
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Table Southbridge Characteristics* (continued)
Symbol TRISE TFALL CPIN
Notes:
Parameter Description Signal Rise Time Signal Fall Time Capacitance
Nominal
Units V/nS V/nS
Notes
These parameters pertain Southbridge signals listed Table page Characterized across supply voltage range. Values specified nominal VCC_CORE. Scale parameters with VCC_CORE. Hysteresis values refer difference between initial return switching points. measured min, respectively. Synchronous inputs/outputs specified with respect RSTCLK RSTCK# pins. These aggregate numbers. specific pins vary widely within this window. Edge rates indicate range over which inputs were characterized. asynchronous operation, signal must persist this time guarantee capture. This value assumes RSTCLK frequency 10ns TBIT 2*fRST. approximate value standard case normal mode operation. This value dependent RSTCLK frequency, divisors, LowPower mode, core frequency. Reassertions signal within this time guaranteed seen core. This value assumes that skew between RSTCLK K7CLKOUT much less than phase. This value assumes RSTCLK K7CLKOUT running same frequency, though processor capable other configurations.
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6.13
APIC Characteristics
racte isti Athlon processor APIC pins.
Table APIC Characteristics
Symbol ILEAK TRISE TFALL CPIN
Notes:
Parameter Description Input High Voltage Input Voltage Output High Voltage Output Voltage Tristate Leakage Input High Current Input Current Output Current Signal Rise Time Signal Fall Time Capacitance
-300
Nominal
2.625 2.625
Units
Notes
-300 -100 -100 -100
V/nS V/nS
Characterized across supply voltage range Values specified nominal (1.5V). Scale parameters with 2.625V 2.5V maximum measured Edge rates indicate range over which inputs were characterized
6.14
Signal Power-Up Requirements
information about signal power-up requirements Athlon processor module, AthlonProcessor Module Signal Power-Up Requirements Application Note, order#23811.
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Electrical Data
Preliminary Information AthlonProcessor Module Data Sheet
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Electrical Data
Chapter
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AthlonProcessor Module Data Sheet
Mechanical Data
Introduction
Athlonprocessor module comprised processor, cache, passive components, thermal plate, cover plate. Athlon processor connects motherboard through insertion into connector known Slot
Module Dimensions
Table shows dimensions Athlon processor module. Table AthlonProcessor Module Dimensions
Description Module Length Module Height Module Depth Thermal Plate Length Thermal Plate Height 5.505 inches 2.451 inches 0.637 inch 5.331 inches 1.917 inches 5.515 inches 2.483 inches 0.657 inch 5.351 inches 1.927 inches Figure page page
Figures through starting page show critical dimensions Athlon processor module. dimensions drawings inches scale. Table lists notes that pertain dimension drawings. Table Notes Dimension Drawings
Note Description Area part number traceability information Rivscrew attach hole. Maximum insertion depth: 0.269" Heatsink clip attach hole. Maximum insertion depth: 0.233" Thermal grease centered SRAM pedestal
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Mechanical Data
Preliminary Information AthlonProcessor Module Data Sheet
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Figure AthlonProcessor Module Dimensions-Front View
Mechanical Data
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AthlonProcessor Module Data Sheet
Figure AthlonProcessor Module Dimensions-Plate Side View
Chapter
Mechanical Data
Preliminary Information AthlonProcessor Module Data Sheet
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Figure AthlonProcessor Module Dimensions-Side View
This dimension daughtercard centerline
Figure AthlonProcessor Module Dimensions-Edge View Mechanical Data Chapter
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AthlonProcessor Module Data Sheet
Figure Card Edge Dimensions-Thermal Plate Side View
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Mechanical Data
Preliminary Information AthlonProcessor Module Data Sheet
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Figure Card Edge Dimensions (Detail)
Mechanical Data
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AthlonProcessor Module Data Sheet
AthlonProcessor Card-Edge Signal Listing
Tables through shows Slot signals pins ordered number, name, their physical position slot, respectively. High designation Name column Table refers staggered high/low arrangement pins slot. Three additional APIC-related signals have been designated (PICD[1:0]# PICCLK), which detailed Tables through Model these pins reserved.
Table AthlonProcessor Signals Ordered Number
VCC2SEL VCC_SRAM[7] PICCLK (Not present Model VCC_SRAM[6] PICD[0] (Not present Model VCC_SRAM[5] PICD[1] (Not present Model VCC_SRAM[4] SMI# VCC_SRAM[3] FERR INIT# VCC_SRAM[2] INTR VCC_SRAM[1] RESET# STPCLK# IGNNE# VCC_SRAM[8] A20M# VCC_CORE[41] SADDOUT[10]# VCC_CORE[1] SADDOUT[11]# VCC_CORE[19] SADDOUT[4]# VCC_CORE[44] SDATA[55]# VCC_CORE[10] SDATA[54]# VCC_CORE[11] Name Name SADDOUT[14]# GND[10] SADDOUT[13]# SADDOUT[7]# GND[51] SADDOUTCLK# GND[7] SADDOUT[12]# GND[21] SADDOUT[9]# SADDOUT[8]# GND[20] SADDOUT[5]# SADDOUT[6]# GND[30] SADDOUT[2]# GND[44] SADDOUT[3]# GND[19] SDATAOUTCLK[3]# GND[40] SCHECK[6]# SDATA[53]# GND[8] SDATA[49]# SDATA[63]# GND[32] SDATAINCLK[3]# GND[3] SDATA[62]# GND[1] SDATA[60]#
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Table AthlonProcessor Signals Ordered Number (continued)
Name SDATA[52]# VCC_CORE[35] SDATA[61]# VCC_CORE[25] SDATA[50]# VCC_CORE[4] SDATA[51]# VCC_CORE[26] SDATA[48]# VCC_CORE[34] SDATA[36]# VCC_CORE[16] SDATA[46]# VCC_CORE[38] SDATA[37]# VCC_CORE[20] SDATA[35]# VCC_CORE[30] SCHECK[4]# VCC_CORE[3] SDATA[34]# VCC_CORE[31] SDATA[33]# VCC_CORE[29] SDATA[32]# VCC_CORE[7] SDATAOUTCLK[2]# VCC_CORE[18] SDATA[30]# VCC_CORE[15] SDATA[31]# VCC_CORE[14] SCHECK[3]# VCC_CORE[33] SDATAINCLK[1]# VCC_CORE[32] SDATA[29]# SDATA[28]# VCC_CORE[9] SDATA[26]# SDATA[27]# VCC_CORE[42] SDATA[25]# VCC_CORE[13] SDATA[24]# GND[13] SCHECK[7]# SDATA[59]# GND[2] SDATA[58]# SDATA[57]# GND[16] SDATA[39]# GND[39] SDATA[56]# GND[38] SDATA[47]# SDATA[38]# GND[41] SDATA[45]# SDATA[44]# GND[37] SDATAINCLK[2]# GND[34] SCHECK[5]# GND[33] SDATA[43]# SDATA[42]# GND[22] SDATA[41]# SDATA[40]# GND[50] SDATAOUTCLK[1]# GND[31] SDATA[22]# GND[35] SDATA[23]# GND[36] SDATA[21]# GND[49] SDATA[20]# GND[14] SDATA[19]# SCHECK[2]# GND[9] SDATA[18]# SDATA[7]# GND[23] SDATA[17]# GND[15] Name
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Table AthlonProcessor Signals Ordered Number (continued)
A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 A111 A112 A113 A114 A115 A116 A117 A118 A119 A120 A121 Name VCC_CORE[27] SDATA[15]# VCC_CORE[24] SDATA[1]# VCC_CORE[2] SDATA[12]# VCC_CORE[23] SCHECK[1]# VCC_CORE[5] SDATA[8]# VCC_CORE[39] SDATA[10]# VCC_CORE[22] SDATAOUTCLK[0]# VCC_CORE[21] SADDIN[7]# VCC_CORE[40] SADDIN[6]# VCC_CORE[37] SADDIN[8]# VCC_CORE[6] SDATAOUTVAL# VCC_CORE[28] SDATAINVAL# VCC_CORE[36] CONNECT VCC_CORE[12] CLKFWDRST PROCRDY VCC_CORE[43] SYSCLK# SYSCLK VCC_CORE[17] PWROK VID[0] VID[1] VID[2] VID[3] FID[3] FID[2] FID[1] FID[0] COREFB+ COREFB- B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118 B119 B120 B121 Name SDATA[16]# GND[27] SDATA[6]# SDATA[5]# GND[28] SCHECK[0]# SDATA[4]# GND[29] SDATA[2]# GND[25] SDATAINCLK[0]# GND[26] SDATA[3]# GND[6] SDATA[0]# GND[5] SDATA[13]# SDATA[14]# GND[4] SDATA[11]# SDATA[9]# GND[17] SADDIN[5]# GND[18] SADDIN[11]# GND[45] SADDIN[2]# GND[48] SADDIN[3]# SADDIN[4]# GND[46] SADDIN[10]# SADDIN[9]# GND[43] SADDIN[13]# GND[42] SADDINCLK# GND[11] SADDIN[14]# GND[12] SFILLVAL# GND[47] SADDIN[12]# GND[24]
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Preliminary Information AthlonProcessor Module Data Sheet
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Table AthlonProcessor Signals Ordered Name
Name A20M# CLKFWDRST CONNECT COREFB+ COREFB- FERR FID[0] FID[1] FID[2] FID[3] GND[1] GND[2] GND[3] GND[4] GND[5] GND[6] GND[7] GND[8] GND[9] GND[10] GND[11] GND[12] GND[13] GND[14] GND[15] GND[16] GND[17] GND[18] GND[19] GND[20] GND[21] GND[22] GND[23] GND[24] PROCRDY PWROK RESET# SADDIN[2]# SADDIN[3]# SADDIN[4]# SADDIN[5]# SADDIN[6]# SADDIN[7]# SADDIN[8]# A105 A103 A120 A121 A119 A118 A117 A116 B115 B117 B101 B121 A106 A111 B104 B106 B107 B100 GND[25] GND[26] GND[27] GND[28] GND[29] GND[30] GND[31] GND[32] GND[33] GND[34] GND[35] GND[36] GND[37] GND[38] GND[39] GND[40] GND[41] GND[42] GND[43] GND[44] GND[45] GND[46] GND[47] GND[48] GND[49] GND[50] GND[51] IGNNE# INIT# INTR PICCLK (Not present Model PICD[0] (Not present Model PICD[1] (Not present Model SCHECK[3]# SCHECK[4]# SCHECK[5]# SCHECK[6]# SCHECK[7]# SDATA[0]# SDATA[1]# SDATA[2]# SDATA[3]# SDATA[4]# Name B113 B111 B103 B108 B119 B105
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Table AthlonProcessor Signals Ordered Name (continued)
Name SADDIN[9]# SADDIN[10]# SADDIN[11]# SADDIN[12]# SADDIN[13]# SADDIN[14]# SADDINCLK# SADDOUT[2]# SADDOUT[3]# SADDOUT[4]# SADDOUT[5]# SADDOUT[6]# SADDOUT[7]# SADDOUT[8]# SADDOUT[9]# SADDOUT[10]# SADDOUT[11]# SADDOUT[12]# SADDOUT[13]# SADDOUT[14]# SADDOUTCLK# SCHECK[0]# SCHECK[1]# SCHECK[2]# SDATA[29]# SDATA[30]# SDATA[31]# SDATA[32]# SDATA[33]# SDATA[34]# SDATA[35]# SDATA[36]# SDATA[37]# SDATA[38]# SDATA[39]# SDATA[40]# SDATA[41]# SDATA[42]# SDATA[43]# SDATA[44]# SDATA[45]# SDATA[46]# SDATA[47]# SDATA[48]# SDATA[49]# B110 B109 B102 B120 B112 B116 B114 SDATA[5]# SDATA[6]# SDATA[7]# SDATA[8]# SDATA[9]# SDATA[10]# SDATA[11]# SDATA[12]# SDATA[13]# SDATA[14]# SDATA[15]# SDATA[16]# SDATA[17]# SDATA[18]# SDATA[19]# SDATA[20]# SDATA[21]# SDATA[22]# SDATA[23]# SDATA[24]# SDATA[25]# SDATA[26]# SDATA[27]# SDATA[28]# SDATA[63]# SDATAINCLK[0]# SDATAINCLK[1]# SDATAINCLK[2]# SDATAINCLK[3]# SDATAINVAL# SDATAOUTCLK[0]# SDATAOUTCLK[1]# SDATAOUTCLK[2]# SDATAOUTCLK[3]# SDATAOUTVAL# SFILLVAL# SMI# STPCLK# SYSCLK SYSCLK# VCC2SEL VCC_CORE[1] VCC_CORE[2] VCC_CORE[3] VCC_CORE[4] Name A101 B118 A109 A108
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Table AthlonProcessor Signals Ordered Name (continued)
Name SDATA[50]# SDATA[51]# SDATA[52]# SDATA[53]# SDATA[54]# SDATA[55]# SDATA[56]# SDATA[57]# SDATA[58]# SDATA[59]# SDATA[60]# SDATA[61]# SDATA[62]# VCC_CORE[19] VCC_CORE[20] VCC_CORE[21] VCC_CORE[22] VCC_CORE[23] VCC_CORE[24] VCC_CORE[25] VCC_CORE[26] VCC_CORE[27] VCC_CORE[28] VCC_CORE[29] VCC_CORE[30] VCC_CORE[31] VCC_CORE[32] VCC_CORE[33] VCC_CORE[34] VCC_CORE[35] VCC_CORE[36] VCC_CORE[37] A100 A102 Name VCC_CORE[5] VCC_CORE[6] VCC_CORE[7] VCC_CORE[9] VCC_CORE[10] VCC_CORE[11] VCC_CORE[12] VCC_CORE[13] VCC_CORE[14] VCC_CORE[15] VCC_CORE[16] VCC_CORE[17] VCC_CORE[18] VCC_CORE[38] VCC_CORE[39] VCC_CORE[40] VCC_CORE[41] VCC_CORE[42] VCC_CORE[43] VCC_CORE[44] VCC_SRAM[1] VCC_SRAM[2] VCC_SRAM[3] VCC_SRAM[4] VCC_SRAM[5] VCC_SRAM[6] VCC_SRAM[7] VCC_SRAM[8] VID[0] VID[1] VID[2] VID[3] A104 A110 A107 A112 A113 A114 A115
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AthlonProcessor Module Data Sheet
Table AthlonProcessor Signals Ordered Physical Location
A121 A119 A117 A115 A113 A111 A109 A107 A105 A103 A101 Name-High COREFB- FID[0] FID[2] VID[3] VID[1] PWROK SYSCLK VCC_CORE[43] CLKFWDRST CONNECT SDATAINVAL# SDATAOUTVAL# SADDIN[8]# SADDIN[6]# SADDIN[7]# SDATAOUTCLK[0]# SDATA[10]# SDATA[8]# SCHECK[1]# SDATA[12]# SDATA[1]# SDATA[15]# SDATA[24]# SDATA[25]# SDATA[27]# VCC_CORE[9] SDATA[29]# SDATAINCLK[1]# SCHECK[3]# SDATA[31]# SDATA[30]# SDATAOUTCLK[2]# SDATA[32]# SDATA[33]# SDATA[34]# SCHECK[4]# SDATA[35]# SDATA[37]# SDATA[46]# SDATA[36]# SDATA[48]# SDATA[51]# SDATA[50]# SDATA[61]# SDATA[52]# SDATA[54]# SDATA[55]# SADDOUT[4]# SADDOUT[11]# SADDOUT[10]# A20M# IGNNE# RESET# INTR FERR# SMI# PICD[1] (Not present Model PICD[0] (Not present Model PICCLK (Not present Model VCC2SEL Name-Low COREFB+ FID[1] FID[3] VID[2] VID[0] VCC_CORE[17] SYSCLK# PROCRDY VCC_CORE[12] VCC_CORE[36] VCC_CORE[28] VCC_CORE[6] VCC_CORE[37] VCC_CORE[40] VCC_CORE[21] VCC_CORE[22] VCC_CORE[39] VCC_CORE[5] VCC_CORE[23] VCC_CORE[2] VCC_CORE[24] VCC_CORE[27] VCC_CORE[13] VCC_CORE[42] SDATA[26]# SDATA[28]# VCC_CORE[32] VCC_CORE[33] VCC_CORE[14] VCC_CORE[15] VCC_CORE[18] VCC_CORE[7] VCC_CORE[29] VCC_CORE[31] VCC_CORE[3] VCC_CORE[30] VCC_CORE[20] VCC_CORE[38] VCC_CORE[16] VCC_CORE[34] VCC_CORE[26] VCC_CORE[4] VCC_CORE[25] VCC_CORE[35] VCC_CORE[11] VCC_CORE[10] VCC_CORE[44] VCC_CORE[19] VCC_CORE[1] VCC_CORE[41] VCC_SRAM[8] STPCLK# VCC_SRAM[1] VCC_SRAM[2] INIT# VCC_SRAM[3] VCC_SRAM[4] VCC_SRAM[5] VCC_SRAM[6] VCC_SRAM[7] A120 A118 A116 A114 A112 A110 A108 A106 A104 A102 A100 B121 B119 B117 B115 B113 B111 B109 B107 B105 B103 B101 Name-High GND[24] GND[47] GND[12] GND[11] GND[42] GND[43] SADDIN[10]# SADDIN[4]# GND[48] GND[45] GND[18] GND[17] SDATA[11]# SDATA[14]# GND[5] GND[6] GND[26] GND[25] GND[29] SCHECK[0]# SDATA[5]# GND[27] GND[15] GND[23] SDATA[18]# SCHECK[2]# GND[14] GND[49] GND[36] GND[35] GND[31] GND[50] SDATA[41]# SDATA[42]# GND[33] GND[34] GND[37] SDATA[45]# SDATA[38]# GND[38] GND[39] GND[16] SDATA[58]# SDATA[59]# GND[13] GND[1] GND[3] GND[32] SDATA[49]# SDATA[53]# GND[40] GND[19] GND[44] GND[30] SADDOUT[5]# SADDOUT[8]# GND[21] GND[7] GND[51] SADDOUT[13]# SADDOUT[14]# Name-Low SADDIN[12]# SFILLVAL# SADDIN[14]# SADDINCLK# SADDIN[13]# SADDIN[9]# GND[46] SADDIN[3]# SADDIN[2]# SADDIN[11]# SADDIN[5]# SDATA[9]# GND[4] SDATA[13]# SDATA[0]# SDATA[3]# SDATAINCLK[0]# SDATA[2]# SDATA[4]# GND[28] SDATA[6]# SDATA[16]# SDATA[17]# SDATA[7]# GND[9] SDATA[19]# SDATA[20]# SDATA[21]# SDATA[23]# SDATA[22]# SDATAOUTCLK[1]# SDATA[40]# GND[22] SDATA[43]# SCHECK[5]# SDATAINCLK[2]# SDATA[44]# GND[41] SDATA[47]# SDATA[56]# SDATA[39]# SDATA[57]# GND[2] SCHECK[7]# SDATA[60]# SDATA[62]# SDATAINCLK[3]# SDATA[63]# GND[8] SCHECK[6]# SDATAOUTCLK[3]# SADDOUT[3]# SADDOUT[2]# SADDOUT[6]# GND[20] SADDOUT[9]# SADDOUT[12]# SADDOUTCLK# SADDOUT[7]# GND[10] B120 B118 B116 B114 B112 B110 B108 B106 B104 B102 B100
Chapter
Mechanical Data
Preliminary Information AthlonProcessor Module Data Sheet
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Mechanical Data
Chapter
21016M/0-June 2000
AthlonProcessor Module Data Sheet
Ordering Information
Standard AthlonProcessor Products
standard products available several operating ranges. ordering part numbers (OPN) Model shown Table page OPNs Model shown Table page These OPNs formed combination elements shown Figure OPNs Model shown Table page These OPNs formed combination elements shown Figure page
Product Naming
(Pad Printed)
Dynamic Marking Product
(Laser Marking)
AthlonProcessor
Copyright Info
AMD-K7750MTR52B
219927999994
Serial
(Laser Marking)
2000 (Pad Printed)
Code (44x44)
(Laser Marking)
AMD-K7
Reserved Characters blank spaces positioned before this character.) FSB: Cache Divisor: 2:1, 2.5:1, Size Ext. Cache: 512Kbytes Case Temperature: 70°C Operating Voltage: 1.6V, 1.7V, 1.8V Package Type: Card Module, Speed: 550MHz-950MHz, 1000 Family/Architecture: AMD-K7 Architecture
Note: Spaces added number illustrated above viewing clarity only.
Figure Example AthlonProcessor Model
Chapter
Ordering Information
Preliminary Information AthlonProcessor Module Data Sheet
21016M/0-June 2000
Product Naming
(Pad Printed)
Dynamic Marking Product
(Laser Marking)
AthlonProcessor
Copyright Info
AMD-A0850MPR24B
219927999994
Serial
(Laser Marking)
2000 (Pad Printed)
Code (44x44)
(Laser Marking)
AMD-A 0850
Reserved Characters blank spaces positioned before this character.) FSB: Cache Divisor: Size Cache: 256Kbytes Case Temperature: 70°C Operating Voltage: 1.6V, 1.7V, 1.75V, 1.8V Package Type: Card Module, Speed: 0850=850 MHz, 0900=900 MHz, 1000=1000 MHz, 1100=1100 MHz, etc. Family/Architecture: Athlon Architecture
Note: Spaces added number illustrated above viewing clarity only.
Figure Example AthlonProcessor Model
Ordering Information
Chapter
21016M/0-June 2000
AthlonProcessor Module Data Sheet
Table Valid Ordering Part Number Combinations Model
AMD-K7500MTR51B AMD-K7550MTR51B AMD-K7600MTR51B AMD-K7650MTR51B AMD-K7700MTR51B
Notes:
Package Type Card Module Card Module Card Module Card Module Card Module
Operating Voltage Plate Temperature 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C
This table lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly-released combinations.
Table Valid Ordering Part Number Combinations Model
AMD-K7550MTR51B AMD-K7600MTR51B AMD-K7650MTR51B AMD-K7700MTR51B AMD-K7750MTR52B AMD-K7800MPR52B AMD-K7850MPR52B AMD-K7900MNR53B AMD-K7950MNR53B AMD-K7100MNR53B
Notes:
Package Type Card Module Card Module Card Module Card Module Card Module Card Module Card Module Card Module Card Module Card Module
Operating Voltage Plate Temperature 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C
This table lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly-released combinations.
Chapter
Ordering Information
Preliminary Information AthlonProcessor Module Data Sheet
21016M/0-June 2000
Table Valid Ordering Part Number Combinations Model
AMD-A0650MPR24B AMD-A0700MPR24B AMD-A0750MPR24B AMD-A0800MPR24B AMD-A0850MPR24B AMD-A0900MMR24B AMD-A0950MMR24B AMD-A1000MMR24B
Notes:
Package Type Card Module Card Module Card Module Card Module Card Module Card Module Card Module Card Module
Operating Voltage Plate Temperature 1.75 1.75 1.75 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C 0°C-70°C
This table lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly-released combinations.
Ordering Information
Chapter
21016M/0-June 2000
AthlonProcessor Module Data Sheet
Appendix
Conventions, Abbreviations, References
This section contains information about conventions abbreviations used this document list related publications.
Signals Bits
Active-Low Signals-Signal names containing pound sign, such SFILL#, indicate active-Low signals. They asserted their Low-voltage state negated their High-voltage state. When used this context, High written with initial upper case letter. Signal Ranges-In range signals, highest lowest signal numbers contained brackets separated colon (for example, D[63:0]). Reserved Bits Signals-Signals bits marked reserved must driven inactive left unconnected, indicated signal descriptions. These bits signals reserved future implementations. When software reads registers with reserved bits, reserved bits must masked. When software writes such registers, must first read register change only non-reserved bits before writing back register. Three-State-In timing diagrams, signal ranges that high impedance shown straight horizontal line half-way between high levels.
Appendix
Preliminary Information AthlonProcessor Module Data Sheet
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Invalid Don't-Care-In timing diagrams, signal ranges that invalid don't-care filled with screen pattern.
Data Terminology
following list defines data terminology:
Quantities word bytes bits) doubleword four bytes bits) quadword eight bytes bits) Athlonprocessor cache line eight quadwords bytes) Addressing-Memory addressed series bytes eight-byte (64-bit) boundaries which each byte separately enabled. Abbreviations-The following notation used bits bytes: Kilo 4-Kbyte page) Mega Mbits/sec) Giga Gbytes memory space) Table more abbreviations. Little-Endian Convention-The byte with address xx.xx00 least-significant byte position (little end). byte diagrams, positions numbered from right left-the little right left. Data structure diagrams memory show addresses bottom high addresses top. When data items aligned, notation 64-bit data maps directly notation 64-bit-wide memory. Because byte addresses increase from right left, strings appear reverse order when illustrated. Ranges-In text, ranges shown with dash (for example, bits 9-1). When accompanied signal name, highest lowest numbers contained brackets separated colon (for example, AD[31:0]). Values-Bits either cleared
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AthlonProcessor Module Data Sheet
Hexadecimal Binary Numbers-Unless context makes interpretation clear, hexadecimal numbers followed binary numbers followed
Abbreviations Acronyms
Table contains definitions abbreviations used this document. Table Abbreviations
Abbreviation Gbit Gbyte Kbyte Mbit Mbyte Meaning Ampere Farad GigaGigabit Gigabyte Henry Hexadecimal KiloKilobyte MegaMegabit Megabyte Megahertz MilliMillisecond Milliwatt MicroMicroampere Microfarad Microhenry Microsecond Microvolt nanonanoampere nanofarad nanohenry nanosecond
Appendix
Preliminary Information AthlonProcessor Module Data Sheet
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Table
Abbreviation
Abbreviations (continued)
Meaning picopicoampere picofarad picohenry picosecond Second Volt Watt
Table contains definitions acronyms used this document. Table
Abbreviation ACPI APCI APIC BIOS BIST DIMM DRAM EIDE EISA EPROM FIFO GART
Acronyms
Meaning Advanced Configuration Power Interface Accelerated Graphics Port Peripheral Component Interconnect Application Programming Interface Advanced Programmable Interrupt Controller Basic Input/Output System Built-In Self-Test Interface Unit Double-Data Rate Dual Inline Memory Module Direct Memory Access Direct Random Access Memory Error Correcting Code Enhanced Integrated Device Electronics Extended Industry Standard Architecture Enhanced Programmable Read Only Memory DigitalAlphaBus First First Graphics Address Remapping Table
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AthlonProcessor Module Data Sheet
Table
Abbreviation HSTL JEDEC JTAG LVTTL MTRR PBGA PMSM POST SDRAM SMbus SRAM SROM
Acronyms (continued)
Meaning High-Speed Transistor Logic Integrated Device Electronics Industry Standard Architecture Joint Electron Device Engineering Council Joint Test Action Group Large Area Network Least-Recently Used Voltage Transistor Transistor Logic Most Significant Memory Type Range Registers Multiplexer Non-Maskable Interrupt Open Drain Plastic Ball Grid Array Physical Address Peripheral Component Interconnect Page Directory Entry Page Directory Table Phase Locked Loop Power Management State Machine Power-On Suspend Power-On Self-Test Random Access Memory Read Only Memory Read Acknowledge Queue System DRAM Interface Synchronous Direct Random Access Memory Serial Initialization Packet System Management Serial Presence Detect Synchronous Random Access Memory Serial Read Only Memory Translation Lookaside Buffer Memory
Appendix
Preliminary Information AthlonProcessor Module Data Sheet
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Table
Abbreviation
Acronyms (continued)
Meaning Transistor Transistor Logic Virtual Address Space Virtual Page Address Video Graphics Adapter Universal Serial Zero Delay Buffer
Appendix
21016M/0-June 2000
AthlonProcessor Module Data Sheet
Related Publications
following books discuss various aspects computer architecture that enhance your understanding products: Publications AthlonProcessor Technical Brief, order# 22054 AthlonProcessor Voltage Regulation Application Note, order# 22651 AthlonProcessor Thermal Application Note, order# 22439 AMD-751System Controller Data Sheet, order# 21910 AMD-756Peripheral Controller Data Sheet, order# 22548 Processor Recognition Application Note, order# 20734 Requirements Application Note, order#23811 Thermal, Mechanical, Chassis Cooling Design Guide, order# 23794 Websites Visit website documentation products. www.amd.com Other websites interest include following:
JEDEC home page-www.jedec.org IEEE home page-www.computer.org Forum-www.agpforum.org
Appendix
Preliminary Information AthlonProcessor Module Data Sheet
21016M/0-June 2000
Appendix

Processor Module Data Sheet Publication 21016 Rev: Issue Date: Ju

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