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Athlon Processor Model Data Sheet
Publication 24309 Rev: Issue Date: March 2002
2000-2002 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, Arrow logo, Athlon, Duron, combinations thereof, 3DNow!, QuantiSpeed trademarks Advanced Micro Devices, Inc. HyperTransport trademark HyperTransport Technology Consortium. trademark Intel Corporation. Windows trademark Microsoft Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
24309E-March 2002
AthlonXP Processor Model Data Sheet
Contents
Revision History Overview
QuantiSpeedArchitecture Summary Overview Signaling Technology Push-Pull (PP) Drivers AthlonSystem Signals
Interface Signals
Logic Symbol Diagram Power Management
Power Management States Working State. Halt State Stop Grant States. Probe State. Connect Disconnect Protocol Connect Protocol Connect State Diagram Clock Control
CPUID Support Thermal Design Electrical Data
7.10 7.11 7.12 7.13 7.14 7.15 Conventions Interface Signal Groupings Voltage Identification (VID[4:0]) Frequency Identification (FID[3:0]) VCCA Characteristics Decoupling VCC_CORE Characteristics Absolute Ratings VCC_CORE Voltage Current SYSCLK SYSCLK# Characteristics Athlon System Characteristics General Characteristics Open Drain Test Circuit Thermal Diode Characteristics APIC Pins Characteristics
Table Contents
Preliminary Information AthlonXP Processor Model Data Sheet
24309E-March 2002
Signal Power-Up Requirements
Power-Up Requirements Signal Sequence Timing Description Clock Multiplier Selection (FID[3:0]) Processor Warm Reset Requirements Northbridge Reset Pins. Introduction Loading OPGA Package Description Diagram Name Abbreviations List Detailed Descriptions A20M# Athlon System Pins Analog APIC Pins, PICCLK, PICD[1:0]# CLKFWDRST CLKIN, RSTCLK (SYSCLK) Pins. CONNECT COREFB COREFB# Pins CPU_PRESENCE# DBRDY DBREQ# Pins FERR FID[3:0] Pins FLUSH# IGNNE# INIT# INTR Pin. JTAG Pins K7CLKOUT K7CLKOUT# Pins Pins Pins Pin. Orientation Pins Bypass Test Pins PWROK SADDIN[1:0]# SADDOUT[1:0]# Pins Scan Pins SMI# STPCLK# SYSCLK SYSCLK#. THERMDA THERMDC Pins
Mechanical Data
Descriptions
10.1 10.2 10.3
Table Contents
24309E-March 2002
AthlonXP Processor Model Data Sheet
VCCA VID[4:0] Pins VREFSYS Pins
Ordering Information
Standard Athlon Processor Model Products
Appendix Conventions Abbreviations
Signals Bits Data Terminology Abbreviations Acronyms.
Table Contents
Preliminary Information AthlonXP Processor Model Data Sheet
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Table Contents
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AthlonXP Processor Model Data Sheet
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Typical AthlonXP Processor Model System Block Diagram Logic Symbol Diagram Athlon Processor Model Power Management States Athlon System Disconnect Sequence Stop Grant State Exiting Stop Grant State Connect Sequence Northbridge Connect State Diagram Processor Connect State Diagram VCC_CORE Voltage Waveform SYSCLK SYSCLK# Differential Clock Signals
Figure SYSCLK Waveform Figure General Open Drain Test Circuit. Figure Signal Relationship Requirements During Power-Up Sequence Figure Athlon Processor Model OPGA Package Figure Athlon Processor Model Diagram- Topside View Figure Athlon Processor Model Diagram- Bottomside View. Figure Example Athlon Processor Model
List Figures
Preliminary Information AthlonXP Processor Model Data Sheet
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viii
List Figures
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AthlonXP Processor Model Data Sheet
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Thermal Design Power. Interface Signal Groupings VID[4:0] Characteristics FID[3:0] Characteristics VCCA Characteristics VCC_CORE Characteristics Absolute Ratings VCC_CORE Voltage Current. SYSCLK SYSCLK# Characteristics SYSCLK SYSCLK# Characteristics AthlonSystem Characteristics Athlon System Characteristics General Characteristics Thermal Diode Electrical Characteristics Guidelines Platform Thermal Protection Processor APIC Characteristics. Mechanical Loading Dimensions Athlon Processor Model OPGA Package. Name Abbreviations Cross-Reference Location FID[3:0] Clock Multiplier Encodings VID[4:0] Code Voltage Definition Abbreviations Acronyms.
List Tables
Preliminary Information AthlonXP Processor Model Data Sheet
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List Tables
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AthlonXP Processor Model Data Sheet
Revision History
Date Description Revisions AthlonXP Processor Model Data Sheet since January 2002 include following:
March 2002
Chapter revised Table "Thermal Design Power," page Chapter revised Table "VCC_CORE Voltage Current," page Chapter revised Table "FID[3:0] Pins," page Chapter revised Figure "OPN Example AthlonXP Processor Model page
Revisions AthlonXP Processor Model Data Sheet since November 2001 include following: January 2002
Chapter revised Table "Thermal Design Power," page Chapter revised Table "VCC_CORE Voltage Current," page Chapter revised Figure "OPN Example AthlonXP Processor Model page
Revisions AthlonXP Processor Model Data Sheet since October 2001 include following:
November 2001
Chapter revised Table "Thermal Design Power," page Chapter revised Table "VCC_CORE Characteristics," page Table "VCC_CORE Voltage Current," page revised Table "General Characteristics," page added section, "Open Drain Test Circuit" page added Figure "General Open Drain Test Circuit' page added section, "Thermal Protection Characterization" page added Table "Guidelines Platform Thermal Protection Processor," page Chapter revised Figure "OPN Example AthlonXP Processor Model page
October 2001
Initial release AthlonXP Processor Model Data Sheet
Revision History
Preliminary Information AthlonXP Processor Model Data Sheet
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Revision History
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AthlonXP Processor Model Data Sheet
Overview
AthlonXP processor model with QuantiSpeedarchitecture powers next generation computing platforms, delivering extreme performance WindowsXP.
AthlonXP processor model latest member Athlon family processors designed meet computation-intensive requirements cutting-edge software applications running high-performance desktop systems. Delivered OPGA package, Athlon processor model delivers integer, floating-point, multimedia performance needed highly demanding applications running system platforms. Athlon processor model delivers compelling performance cutting-edge software applications that include high-speed Internet capability, digital content creation, digital photo editing, digital video, image compression, video encoding streaming over Internet, soft DVD, commercial modeling, workstation-class Computer-Aided Design (CAD), commercial desktop publishing, speech recognition. Athlon processor model also offers scalability reliability that managers business users require enterprise computing. Athlon processor model features seventh-generation microarchitecture with integrated, exclusive cache, which supports growing processor system bandwidth requirements emerging software, graphics, I/O, memory technologies. high-speed execution core Athlon processor model includes multiple instruction decoders, dual-ported 128-Kbyte split level-one (L1) cache, exclusive 256-Kbyte cache, three independent integer pipelines, three address calculation pipelines, superscalar, fully pipelined, out-of-order, three-way floating-point engine. floating-point engine capable delivering outstanding performance numerically complex applications. features Athlon processor model QuantiSpeedarchitecture, high-performance full-speed cache, 266-MHz, 2.1-Gigabyte second system bus, 3DNow!Professional technology. Athlon system combines latest technological advances, such point-to-point topology, source-synchronous packet-based transfers, low-voltage signaling provide extremely powerful, scalable processor.
Chapter
Overview
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Athlon processor model binary-compatible with existing software backwards compatible with applications optimized MMXTM, SSE, 3DNow! technology. Using data format Single-Instruction Multiple-Data (SIMD) operations based instruction model, Athlon processor model produce many four, 32-bit, single-precision floating-point results clock cycle. 3DNow! Professional technology implemented Athlon processor model includes integer multimedia instructions software-directed data movement instructions optimizing such applications digital content creation streaming video internet, well instructions Digital Signal Processing (DSP)/communications applications.
QuantiSpeedArchitecture Summary
following features summarize Athlon processor model QuantiSpeed architecture:
advanced nine-issue, superpipelined, superscalar processor microarchitecture designed increased Instructions Cycle (IPC) high clock frequencies Fully pipelined floating-point unit that executes (floating-point), MMX, 3DNow! instructions Hardware data pre-fetch that increases optimizes performance high-end software applications utilizing high-bandwidth system capabilities Advanced two-level Translation Look-aside Buffer (TLB) structures both enhanced data instruction address translation. Athlon processor model with QuantiSpeed architecture incorporates three optimizations: DTLB increases from entries, ITLB DTLB both exclusive architecture, entries speculatively loaded.
Athlon processor model delivers excellent system performance cost-effective, industry-standard form factor. Athlon processor model compatible with motherboards based Socket Figure page shows typical Athlon processor system block diagram.
Overview
Chapter
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Thermal Monitor
AthlonXP Processor Model
Athlon System System Controller (Northbridge) Memory SDRAM
Peripheral Controller (Southbridge)
SCSI
Modem Audio Dual EIDE BIOS
Figure Typical AthlonXP Processor Model System Block Diagram
Chapter
Overview
Preliminary Information AthlonXP Processor Model Data Sheet
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Overview
Chapter
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AthlonXP Processor Model Data Sheet
Interface Signals
Overview
Athlonsystem architecture designed delive excellent movement bandwidth nextgeneration platforms well high-performance required enterprise-class application software. system architecture consists three high-speed channels unidirectional processor request channel, unidirectional probe channel, 64-bit bidirectional data channel), source-synchronous clocking, packet-based protocol. addition, system supports several control, clock, legacy signals. interface signals impedance controlled push-pull, low-voltage, swing-signaling technology contained within Socket socket. more information, "AMD AthlonSystem Signals" page Chapter "Pin Descriptions" page Athlonand DuronSystem Specification, order# 21902.
Signaling Technology
Athlon system uses low-voltage, swing-signaling technology, that been enhanced provide larger noise margins, reduced ringing, variable voltage levels. signals push-pull impedance compensated. signal inputs differential receivers that require reference voltage (VREF). reference signal used receivers determine signal asserted deasserted source. Termination resistors needed because driver impedance-matched motherboard high impedance reflection used receiver bring signal past input threshold. more information about pins signals, Chapter "Pin Descriptions" page
Chapter
Interface Signals
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Push-Pull (PP) Drivers
Athlon processor model supports Push-Pull (PP) drivers. system logic configures processor with configuration parameter called SysPushPull (1=PP). impedance drivers match impedance motherboard external resistors connected pins. Pins" page more information.
AthlonSystem Signals
Athlon system clock-forwarded, point-topoint interface with following three point-to-point channels:
13-bit unidirectional output address/command channel 13-bit unidirectional input address/command channel 72-bit bidirectional data channel
more information, Chapter "Electrical Data" page Athlonand DuronSystem Specification, order# 21902.
Interface Signals
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AthlonXP Processor Model Data Sheet
Logic Symbol Diagram
Figure logic symbol diagram processor. This diagram shows logical grouping input output signals.
Clock
SYSCLK SDATA[63:0]# SDATAINCLK[3:0]# SDATAOUTCLK[3:0]# SDATAINVALID# SDATAOUTVALID# SFILLVALID#
SYSCLK# VID[4:0] COREFB COREFB# PWROK FID[3:0]
Voltage Control
Data
Frequency Control
Probe/SysCMD Request
SADDIN[14:2]# SADDINCLK# SADDOUT[14:2]# SADDOUTCLK# PROCRDY CLKFWDRST CONNECT STPCLK# RESET#
AthlonXP Processor Model
Power Management Initialization
FERR IGNNE# INIT# INTR A20M# SMI# FLUSH# THERMDA THERMDC PICCLK PICD[1:0]
Legacy
Thermal Diode APIC
Figure Logic Symbol Diagram
Chapter
Logic Symbol Diagram
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Logic Symbol Diagram
Chapter
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AthlonXP Processor Model Data Sheet
Power Management
This chapter describes power management control system AthlonXP processor model power management features processor compliant with ACPI 1.0b ACPI specifications.
Power Management States
Athlon processor model supports low-power Halt Stop Grant states. These states used Advanced Configuration Power Interface (ACPI) enabled operating systems processor power management. Figure shows power management states processor. figure includes ACPI "Cx" naming convention these states.
Halt
Execute SMI#, INTR, NMI, INIT#, RESET#
Working4
(Read PLVL2 register throttling)
STPCLK# deasserted
STPCLK# asserted
Incoming Probe
Probe State1
Note:
AthlonSystem connected during following states: Probe state During transitions between Halt state Stop Grant state During transitions between Stop Grant state Halt state Working state
Figure AthlonXP Processor Model Power Management States Chapter Power Management
Probe Serviced
Incoming Probe Probe Serviced
Stop Grant Cache Snoopable
Stop Grant Cache Snoopable Sleep
Legend Hardware transitions Software transitions
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following sections provide overview power Athlonand DuronSystem Specification, order# 21902. Note: power management states that processor powered, system must stop system clock (SYSCLK/SYSCLK#) processor. Working State Halt State Working state state which processor executing instructions. When processor executes instruction, processor enters Halt state issues Halt special cycle Athlon system bus. processor only enters power state dictated CLK_Ctl system controller (Northbridge) disconnects Athlon system response Halt special cycle. STPCLK# asserted, processor will exit Halt state enter Stop Grant state. processor will initiate system connect, disconnected, then issue Stop Grant special cycle. When STPCLK# deasserted, processor will exit Stop Grant state re-enter Halt state. processor will issue Halt special cycle when re-entering Halt state. Halt state exited when processor detects assertion INIT#, RESET#, SMI#, interrupt INTR pins, local APIC interrupt message. When Halt state exited, processor will initiate Athlon system connect disconnected.
Stop Grant States
processor enters Stop Grant state upon recognition assertion STPCLK# input. After entering Stop Grant state, processor issues Stop Grant special cycle Athlon system bus. processor low-power state this time, because Athlon system still connected. After Northbridge disconnects Athlon system response Stop Grant special cycle, processor enters low-power state dictated CLK_Ctl MSR. Northbridge needs probe processor during Stop Grant state while system disconnected, must first connect system bus. Connecting system Power Management Chapter
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AthlonXP Processor Model Data Sheet
places processor into higher power probe state. After Northbridge completed probes processor, Northbridge must disconnect Athlon system again that processor return low-power state. During Stop Grant states, processor latches INIT#, INTR, NMI, SMI#, local APIC interrupt message, they asserted. Stop Grant state exited upon deassertion STPCLK# assertion RESET#. When STPCLK# Athlon system disconnected. After processor enters Working state, pending interrupts recognized serviced processor resumes execution instruction boundary where STPCLK# initially recognized. RESET# sampled asserted during Stop Grant state, processor exits Stop Grant state reset process begins. There mechanisms asserting STPCLK#-hardware software. Southbridge force STPCLK# assertion throttling protect processor from exceeding maximum case temperature. This accomplished asserting THERM# input Southbridge. Throttling asserts STPCLK# percentage predefined throttling period: STPCLK# repetitively asserted deasserted until THERM# deasserted. Software force processor into Stop Grant state accessing ACPI-defined registers typically located Southbridge. operating system places processor into Stop Grant state reading P_LVL2 register Southbridge. ACPI Thermal Zone defined processor, operating system initiate throttling with STPCLK# using ACPI defined P_CNT register Southbridge. Northbridge connects Athlon system bus, processor enters Probe state service cache snoops during Stop Grant throttling. probes allowed, shown Figure page Chapter Power Management
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Stop Grant state also entered Powered Suspend, system sleep state based write SLP_TYP SLP_EN fields ACPI-defined Power Management control register Southbridge. During Sleep state, system software ensures master probe activity occurs. Southbridge deasserts STPCLK# brings processor Stop Grant state when enabled resume event occurs. Probe State Probe state entered when Northbridge connects Athlon system probe processor (for example, snoop processor caches) when processor Halt Stop Grant state. When Probe state, processor responds probe cycle same manner when Working state. When probe been serviced, processor returns same state when entered Probe state (Halt Stop Grant state). When probe activity completed processor only returns low-power state after Northbridge disconnects Athlon system again.
Power Management
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Connect Disconnect Protocol
Significant power savings processor only occur proc essor disconnected from system Northbridge while Halt Stop Grant state. Northbridge optionally initiate disconnect upon receipt Halt Stop Grant special cycle. option disconnecting controlled enable Northbridge. Northbridge requires processor service probe after system been disconnected, must first initiate system connect.
Connect Protocol
addition legacy STPCLK# signal Halt Stop Grant special cycles, Athlon system connect protocol includes CONNECT, PROCRDY, CLKFWDRST signals Connect special cycle. Athlon system disconnects initiated Northbridge response receipt Halt Stop Grant. Reconnect initiated processor response interrupt Halt STPCLK# deassertion. Reconnect initiated Northbridge probe processor. Northbridge contains BIOS programmable registers enable system disconnect response Halt Stop Grant special cycles. When Northbridge receives Halt Stop Grant special cycle from processor and, there outstanding probes data movements, Northbridge deasserts CONNECT minimum eight SYSCLK periods after last command sent processor. processor detects deassertion CONNECT rising edge SYSCLK deasserts PROCRDY Northbridge. return, Northbridge asserts CLKFWDRST anticipation reestablishing connection some later point. Note: Northbridge must disconnect processor from Athlon system before issuing Stop Grant special cycle passing Stop Grant special cycle Southbridge systems that connect Southbridge with HyperTransporttechnology. This note applies current chipset implementation- alternate chipset implementations that require this possible.
Chapter
Power Management
Preliminary Information AthlonXP Processor Model Data Sheet
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Note: response Halt special cycles, Northbridge passes Halt special cycle Southbridge immediately. processor receive interrupt after sends Halt special cycle, STPCLK# deassertion after sends Stop Grant special cycle Northbridge before disconnect actually occurs. this case, processor sends Connect special cycle Northbridge, rather than continuing with disconnect sequence. response Connect special cycle, Northbridge cancels disconnect request. system required assert CONNECT signal before returning C-bit connect special cycle (assuming CONNECT been deasserted). more information, Athlonand DuronSystem Specification, order# 21902 definition C-bit Connect special cycle.
Power Management
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AthlonXP Processor Model Data Sheet
Figure shows STPCLK# assertion resulting processor thlon syst disconnected.
STPCLK# Athlon
System
CONNECT PROCRDY CLKFWDRST
Stop Grant
Stop Grant
Figure AthlonSystem Disconnect Sequence Stop Grant State
example Athlon system disconnect sequence follows: peripheral controller (Southbridge) asserts STPCLK# place processor Stop Grant state. When processor recognizes STPCLK# asserted, enters Stop Grant state then issues Stop Grant special cycle. When special cycle received Northbridge, deasserts CONNECT, assuming probes pending, initiating disconnect processor. processor responds Northbridge deasserting PROCRDY. Northbridge asserts CLKFWDRST complete disconnect sequence. After processor disconnected from bus, processor enters low-power state. Northbridge passes Stop Grant special cycle along Southbridge.
Chapter
Power Management
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Figure shows signal sequence events that takes processor Stop Grant state, connects processor Athlon system bus, puts processor into Working state.
STPCLK# PROCRDY CONNECT CLKFWDRST
Figure Exiting Stop Grant State Connect Sequence following sequence events removes processor from Stop Grant state connects system bus: Southbridge deasserts processor wake event. STPCLK#, informing
When processor recognizes STPCLK# deassertion, exits low-power state asserts PROCRDY, notifying Northbridge connect bus. Northbridge asserts CONNECT. Northbridge deasserts CLKFWDRST, synchronizing forwarded clocks between processor Northbridge. processor issues Connect special cycle system resumes operating system application code execution.
Power Management
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AthlonXP Processor Model Data Sheet
Connect State Diagram
Figure below Figure page show Northbridge processor connect state diagrams, respectively.
Disconnect Pending Connect
Disconnect Requested
Disconnect 7/D,C
Reconnect Pending
Probe Pending
Probe Pending
Condition disconnect requested probes still pending. disconnect requested probes pending. Connect special cycle from processor. probes pending. PROCRDY deasserted. probe needs service. PROCRDY asserted. Three SYSCLK periods after CLKFWDRST deasserted. Although reconnected system interface, Northbridge must issue non-NOP SysDC commands minimum four SYSCLK periods after deasserting CLKFWDRST.
Action Deassert CONNECT eight SYSCLK periods after last SysDC sent.
Assert CLKFWDRST. Assert CONNECT. Deassert CLKFWDRST.
Figure Northbridge Connect State Diagram Chapter Power Management
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Connect Connect Pending Connect Pending Disconnect
Disconnect Pending
Condition CONNECT deasserted Northbridge (for previously sent Halt Stop Grant special cycle). Processor receives wake-up event must cancel disconnect request.
Action CLKFWDRST asserted Northbridge. Issue Connect special cycle.* Return internal clocks full speed assert PROCRDY.
Connect special cycle only issued after processor wake-up event (interrupt STPCLK# deassertion) occurs. Athlonsystem connected Northbridge probe processor, Connect special cycle issued that time only issued after subsequent processor wake-up event).
Deassert PROCRDY slow down internal clocks. Processor wake-up event CONNECT asserted Northbridge. CLKFWDRST deasserted Northbridge. Forward clocks start three SYSCLK periods after CLKFWDRST deasserted.
Note:
Figure Processor Connect State Diagram
Power Management
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AthlonXP Processor Model Data Sheet
Clock Control
processor implements Clock Control (CLK_Ctl) (address C001_001Bh) that determines internal clock divisor when Athlon system disconnected. Refer Athlonand DuronProcessors BIOS, Software, Debug Developers Guide, order# 21656, more details CLK_Ctl register.
Chapter
Power Management
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Power Management
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AthlonXP Processor Model Data Sheet
CPUID Support
AthlonXP processor model version feature recognition performed through CPUID instruction, that provides complete information about processor-vendor, type, name, etc., capabilities. Software make this information accurately tune system maximum performance benefit users. information CPUID instruction following documents:
Processor Recognition Application Note, order# 20734 Athlonand DuronProcessors Recognition Application Note Addendum, order# 21922 Athlonand DuronProcessors BIOS, Software, Debug Developers Guide, order# 21656
Chapter
CPUID Support
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CPUID Support
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AthlonXP Processor Model Data Sheet
Thermal Design
AthlonXP processor model provides diode that used conjunction with external temperature sensor determine temperature processor. diode anode (THERMDA) cathode (THERMDC) available pins processor. Refer "THERMDA THERMDC Pins" page more details. information about thermal design Athlon processor model including layout airflow considerations, AthlonProcessor Thermal, Mechanical, Chassis Cooling Design Guide, order# 23794, cooling guidelines http://www.amd.com. Table shows thermal design power specifications Athlon processor model
Table
Thermal Design Power
Frequency (MHz) 1333 1400 1467 1533 1600 1667 1733 1.75 Nominal Voltage Maximum Thermal Power* 60.0 62.8 64.0 66.0 68.0 70.0 72.0 Typical Thermal Power 53.8 56.3 57.4 59.2 60.7 62.5 64.3 90°C Maximum Temperature
Model Number 1500+ 1600+ 1700+ 1800+ 1900+ 2000+ 2100+
Note:
Thermal design power represents maximum sustained power dissipated while executing publicly-available software instruction sequences under normal system operation nominal VCC_CORE. Thermal solutions must monitor temperature processor prevent processor from exceeding maximum temperature.
Chapter
Thermal Design
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Thermal Design
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AthlonXP Processor Model Data Sheet
Electrical Data
Conventions
conventions used this chapter follows:
Current specified being sourced processor negative. Current specified being sunk processor positive.
Interface Signal Groupings
electrical data this chapter presented separately each signal group. Table defines each group signals contained each group.
Table
Interface Signal Groupings
Signals Notes "Absolute Ratings" page "Voltage Identification (VID[4:0])" page "VID[4:0] Pins" page page 27,"VCCA Pin" page "COREFB COREFB# Pins" page "Frequency Identification (FID[3:0])" page "FID[3:0] Pins" page Table "SYSCLK SYSCLK# Characteristics," page Table "SYSCLK SYSCLK# Characteristics," page "SYSCLK SYSCLK#" page "PLL Bypass Test Pins" page
Signal Group
Power
VID[4:0], VCCA, VCC_CORE, COREFB, COREFB#
Frequency
FID[3:0]
System Clocks
SYSCLK, SYSCLK# (Tied CLKIN/CLKIN# RSTCLK/RSTCLK#), PLLBYPASSCLK#, PLLBYPASSCLK
SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, SADDOUTCLK#, "AMD AthlonSystem AthlonSFILLVAL#, SDATAINVAL#, SDATAOUTVAL#, SDATA[63:0]#, Characteristics" page System SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, CLKFWDRST, PROCRDY, "CLKFWDRST Pin" page CONNECT
Chapter
Electrical Data
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Table
Interface Signal Groupings (continued)
Signals Notes "General Characteristics" page "INTR Pin" page "NMI Pin" page "SMI# Pin" page "INIT# Pin" page "A20M# Pin" page "FERR Pin" page 69,"IGNNE# Pin" page "SYSCLK SYSCLK#" page "FLUSH# Pin" page "General Characteristics" page "General Characteristics" page "PLL Bypass Test Pins" page "Scan Pins" page "Analog Pin" page "General Characteristics" page "DBRDY DBREQ# Pins" page "PWROK Pin" page "APIC Pins Characteristics" page "APIC Pins, PICCLK, PICD[1:0]#" page Table "Thermal Diode Electrical Characteristics," page "THERMDA THERMDC Pins" page
Signal Group
Southbridge
RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#, STPCLK#, FLUSH#
JTAG
TMS, TCK, TRST#, TDI,
Test
PLLBYPASS#, PLLTEST#, PLLMON1, PLLMON2, SCANCLK1, SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG
Miscellaneous DBREQ#, DBRDY, PWROK
APIC
PICD[1:0]#, PICCLK
Thermal
THERMDA, THERMDC
Voltage Identification (VID[4:0])
Table shows VID[4:0] characteristics. more information VID[4:0] characteristics, "VID[4:0] Pins" page Table
Parameter
Note:
VID[4:0] Characteristics
Description Output Current Output High Voltage 2.625
pins must pulled above this voltage external pullup resistor.
Electrical Data
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Frequency Identification (FID[3:0])
Table shows FID[3:0] characteristics. more information, "FID[3:0] Pins" page Table
Parameter
Note:
FID[3:0] Characteristics
Description Output Current Output High Voltage 2.625
pins must pulled above this voltage external pullup resistor.
VCCA Characteristics
Table shows characteristics VCCA. more information, "VCCA Pin" page
Table
Symbol VVCCA IVCCA
Notes:
VCCA Characteristics
Parameter VCCA Voltage VCCA Current 2.25 Nominal 2.75 Units mA/GHz Notes
Minimum Maximum voltages absolute. transients below minimum above maximum voltages permitted. Measured
Decoupling
AthlonProcessor-Based Motherboard Design Guide, order# 24363, contact your local office information about decoupling required motherboard with AthlonXP processor model
Chapter
Electrical Data
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VCC_CORE Characteristics
Table shows characteristics VCC_CORE. "VCC_CORE Voltage Current," page more information, Figure page
Table
VCC_CORE Characteristics
Parameter Limit Working State -100 Units
Symbol
VCC_CORE_DC_MAX Maximum static voltage above VCC_CORE_NOM* VCC_CORE_DC_MIN Maximum static voltage below VCC_CORE_NOM* VCC_CORE_AC_MAX Maximum excursion above VCC_CORE_NOM* VCC_CORE_AC_MIN Maximum excursion below VCC_CORE_NOM* tMAX_AC tMIN_AC
Note:
*All voltage measurements taken differentially
Maximum excursion time transients Negative excursion time transients
COREFB/COREFB# pins.
Electrical Data
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Figure shows processor core voltage (VCC_CORE) waveform response perturbation. tMIN_AC (negative transient excursion time) tMAX_AC (positive transient excursion time) represent maximum allowable time below above tolerance thresholds.
tmax_AC VCC_CORE_MAX_AC
VCC_CORE_MAX_DC
VCC_CORE_NOM
VCC_CORE_MIN_DC
VCC_CORE_MIN_AC tmin_AC
ICORE_MAX ICORE_MIN
Figure VCC_CORE Voltage Waveform
Chapter
Electrical Data
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Absolute Ratings
Athlon processor model should subjected conditions exceeding absolute ratings, such conditions adversely affect long-term reliability result functional damage. Table lists maximum absolute ratings operation Athlon processor model
Table
VCC_CORE VCCA VPIN TSTORAGE
Absolute Ratings
Description AthlonXP processor model core supply Athlon processor model supply Voltage signal Storage temperature processor -0.5 -0.5 -0.5 VCC_CORE VCCA VCC_CORE
Parameter
Electrical Data
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VCC_CORE Voltage Current
Table shows voltage current Athlon processor model during normal reduced power states.
Table
VCC_CORE Voltage Current
Frequency (MHz) Nominal Voltage Temperature 1333 1400 1467 1533 1600 1667 1733 1.30 50°C 1.75 90°C (Processor Current) Maximum Typical 30.8 32.2 32.8 33.8 34.7 35.7 36.7 0.66
Model Number 1500+ 1600+ 1700+ 1800+ 1900+ 2000+ 2100+
34.3 35.9 36.6 37.7 38.9 40.0 41.1 1.54
Stop Grant Sleep State1,
Notes:
cooling turned during Sleep state, customers should test their systems Sleep state ensure that system, when using typical parts, adequate cooling (without during Sleep state) meet temperature specification product. Figure "AMD AthlonXP Processor Model Power Management States" page maximum Stop Grant currents absolute worst case currents parts that yield from worst case corner process representative typical Stop Grant current that currently about one-third maximum specified current. These currents occur when Athlon system disconnected power ratio 1/64 applied core clock grid processor dictated value 6003_D22Fh programmed into Clock Control (CLK_Ctl) MSR. Stop Grant current consumption characterized tested.
Chapter
Electrical Data
Preliminary Information AthlonXP Processor Model Data Sheet
24309E-March 2002
7.10
SYSCLK SYSCLK# Characteristics
Table shows characteristics SYSCLK SYSCLK# differential clocks. SYSCLK signal represents CLKIN RSTCLK tied together while SYSCLK# signal represents CLKIN# RSTCLK# tied together.
Table
Symbol
SYSCLK SYSCLK# Characteristics
Description -250 VCC_CORE/2 ±100 Units
VThreshold-DC Crossing before transition detected (DC) VThreshold-AC Crossing before transition detected (AC) ILEAK_P ILEAK_N VCROSS CPIN
Note:
Leakage current through P-channel pullup VCC_CORE Leakage current through N-channel pulldown (Ground) Differential signal crossover Capacitance
following processor inputs have twice listed capacitance because they connect input pads-SYSCLK SYSCLK#. SYSCLK connects CLKIN/RSTCLK. SYSCLK# connects CLKIN#/RSTCLK#.
Figure shows characteristics SYSCLK SYSCLK# signals.
VCROSS
VThreshold-DC 400mV
VThreshold-AC 450mV
Figure SYSCLK SYSCLK# Differential Clock Signals
Electrical Data
Chapter
24309E-March 2002
AthlonXP Processor Model Data Sheet
Table shows SYSCLK/SYSCLK# differential clock characteristics Athlon processor model
Table SYSCLK SYSCLK# Characteristics
Symbol Parameter Description Clock Frequency Duty Cycle
Notes:
Minimum 1.05 1.05
Maximum
Units
Notes
Period High Time Time Fall Time Rise Time Period Stability
Circuitry driving Athlonsystem clock inputs must exhibit suitably closed-loop jitter bandwidth allow track jitter. -20dB attenuation point, measured into 20-pF load must less than kHz. Circuitry driving Athlon system clock inputs purposely alter Athlon system clock frequency (spread spectrum clock generators). cases Athlon system period violate minimum specification above. Athlon system clock inputs vary from 100% specified frequency specified frequency maximum rate kHz.
Figure shows sample waveform SYSCLK signal.
VCROSS
VThreshold-AC
Figure SYSCLK Waveform
Chapter
Electrical Data
Preliminary Information AthlonXP Processor Model Data Sheet
24309E-March 2002
7.11
AthlonSystem Characteristics
Table shows characteristics Athlon system used Athlon processor model
Table AthlonSystem Characteristics
Symbol VREF Parameter Input Reference Voltage VREF Nominal VREF Nominal VREF -500 IOUT -200 IOUT (Ground) VCC_CORE Nominal 0.85 VCC_CORE -500 Condition Units Notes (0.5*VCC_CORE) (0.5*VCC_CORE) -100 VCC_CORE VREF VCC_CORE+500
IVREF_LEAK_P VREF Tristate Leakage Pullup IVREF_LEAK_N VREF Tristate Leakage Pulldown ILEAK_P ILEAK_N
Notes:
Input High Voltage Input Voltage Output High Voltage Output Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Input Capacitance
VREF nominally VCC_CORE with actual values that specific motherboard design implementation. VREF must created with sufficiently accurate source sufficiently quiet response adhere specification listed above. Specified
Electrical Data
Chapter
24309E-March 2002
AthlonXP Processor Model Data Sheet
characteristics Athlon system shown Table parameters grouped based source destination signals involved. Table AthlonSystem Characteristics
Group Signals TRISE TFALL TSKEW-SAMEEDGE TSKEW-DIFFEDGE Forward Clocks COUT TVAL Sync
Notes:
Symbol
Parameter Output Rise Slew Rate Output Fall Slew Rate Output skew with respect same clock edge Output skew with respect different clock edge Input Data Setup Time Input Data Hold Time Capacitance input Clocks Capacitance output Clocks RSTCLK Output Valid Setup RSTCLK Hold from RSTCLK
1000
Units V/ns V/ns
Notes
2000
Rise fall time ranges guidelines over which been characterized. TSKEW-SAMEEDGE maximum skew within clock forwarded group between signals between signal forward clock, measured package, with respect same clock edge. TSKEW-DIFFEDGE maximum skew within clock forwarded group between signals between signal forward clock, measured package, with respect different clock edges. Input times with respect appropriate Clock Forward Group input clock. synchronous signals include PROCRDY, CONNECT, CLKFWDRST. RSTCLK rising edge output valid PROCRDY. Test Load setup CONNECT/CLKFWDRST rising edge RSTCLK. hold CONNECT/CLKFWDRST from rising edge RSTCLK.
Chapter
Electrical Data
Preliminary Information AthlonXP Processor Model Data Sheet
24309E-March 2002
7.12
General Characteristics
Table shows Athlon processor model characteristics Southbridge, JTAG, test, miscellaneous pins.
Table General Characteristics
Symbol ILEAK_P ILEAK_N TDELAY
Notes:
Parameter Description Input High Voltage Input Voltage Output High Voltage Output Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Output High Current Output Current Sync Input Setup Time Sync Input Hold Time Output Delay with respect RSTCLK
Condition
(VCC_CORE/2) -300 VCC_CORE -300
VCC_CORE VCC_CORE
Units
Notes
(Ground) VCC_CORE Nominal
Characterized across supply voltage range. Values specified nominal VCC_CORE. Scale parameters between VCC_CORE minimum VCC_CORE maximum. measured min, respectively. Synchronous inputs/outputs specified with respect RSTCLK RSTCK# pins. These aggregate numbers. Edge rates indicate range over which inputs were characterized. asynchronous operation, signal must persist this time enable capture. This value assumes RSTCLK period TBIT 2*fRST. approximate value standard case normal mode operation. This value dependent RSTCLK frequency, divisors, Power mode, core frequency. Reassertions signal within this time guaranteed seen core. This value assumes that skew between RSTCLK K7CLKOUT much less than phase. This value assumes RSTCLK K7CLKOUT running same frequency, though processor capable other configurations. Time valid open drain pins. requirements Chapter "Power-Up Timing Requirements," more information.
Electrical Data
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24309E-March 2002
AthlonXP Processor Model Data Sheet
Table General Characteristics (continued)
Symbol TBIT TRPT TRISE TFALL CPIN VALID
Notes:
Parameter Description Input Time Acquire Input Time Reacquire Signal Rise Time Signal Fall Time Capacitance Time data valid
Condition
20.0 40.0
Units
Notes 9-13
V/ns V/ns
Characterized across supply voltage range. Values specified nominal VCC_CORE. Scale parameters between VCC_CORE minimum VCC_CORE maximum. measured min, respectively. Synchronous inputs/outputs specified with respect RSTCLK RSTCK# pins. These aggregate numbers. Edge rates indicate range over which inputs were characterized. asynchronous operation, signal must persist this time enable capture. This value assumes RSTCLK period TBIT 2*fRST. approximate value standard case normal mode operation. This value dependent RSTCLK frequency, divisors, Power mode, core frequency. Reassertions signal within this time guaranteed seen core. This value assumes that skew between RSTCLK K7CLKOUT much less than phase. This value assumes RSTCLK K7CLKOUT running same frequency, though processor capable other configurations. Time valid open drain pins. requirements Chapter "Power-Up Timing Requirements," more information.
Chapter
Electrical Data
Preliminary Information AthlonXP Processor Model Data Sheet
24309E-March 2002
7.13
Open Drain Test Circuit
Figure test circuit that used Automated Test Equipment (ATE) test validity open drain pins. Refer Table "General Characteristics," page timing requirements.
VTermination1 Open Drain Output Current2
Notes: VTermination pins VTermination APIC pins pins APIC pins Figure General Open Drain Test Circuit
Electrical Data
Chapter
24309E-March 2002
AthlonXP Processor Model Data Sheet
7.14
Thermal Diode Characteristics
Thermal Diode Electrical Characteristics. Table shows Athlon processor model electrical characteristics on-die thermal diode. Table Thermal Diode Electrical Characteristics
Symbol
Notes:
Parameter Description Forward bias current Diode ideality factor
1.002
1.008
1.016
Units
Notes
sourcing current should always used forward bias only. Characterized 95°C with forward bias current pair 100% tested. Specified design limited characterization. diode ideality factor, correction factor ideal diode equation. following equations, following variables constants: Diode ideality factor Boltzmann constant Electron charge constant Diode temperature (Kelvin) Voltage from base emitter Collector current Saturation current Ratio collector currents equation
sourcing currents using above equation, difference base emitter voltage found that leads following equation temperature:
different sourcing current pair used other than following equation should used correct temperature. Subtract this offset from temperature measured temperature sensor. following equations, following variables constants: Ihigh High sourcing current Ilow sourcing current Toffset found using following equation:
high offset 2.34 high
Chapter
Electrical Data
Preliminary Information AthlonXP Processor Model Data Sheet
24309E-March 2002
Thermal Protection Characterization. following section describes parameters relating thermal protection. implementation thermal control circuitry control processor temperature left manufacturer determine implement. Thermal limits motherboard design necessary protect processor from thermal damage. temperature thermal protection circuitry initiate shutdown processor. SD_DELAY maximum time allowed from detection over-temperature condition processor shutdown prevent thermal damage processor. Systems that implement thermal protection circuitry that react within time specified TSD_DELAY cause thermal damage processor during unlikely events failure powering processor without heat-sink. processor relies thermal circuitry motherboard turn regulated core voltage processor response thermal shutdown event. Thermal protection circuitry reference designs thermal solution guidelines found following documents:
AthlonProcessor-Based Motherboard Design Guide, order# 24363 Thermal Diode Monitoring Circuits, order# 25658 Thermal, Mechanical, Chassis Cooling Design Guide, order# 23794
Table page shows SHUTDOWN SD_DELAY specifications circuitry motherboard design necessary thermal protection processor.
Electrical Data
Chapter
24309E-March 2002
AthlonXP Processor Model Data Sheet
Table Guidelines Platform Thermal Protection Processor
Symbol TSD_DELAY
Notes:
Parameter Description Maximum allowed time from TSHUTDOWN detection processor shutdown
Units
Notes
TSHUTDOWN Thermal diode shutdown temperature processor protection
thermal diode 100% tested, specified design limited characterization. thermal diode capable responding thermal events 40°C/s faster. AthlonXP processor model provides thermal diode measuring temperature processor. processor relies thermal circuitry motherboard turn regulated core voltage processor response thermal shutdown event. Refer Thermal Diode Monitoring Circuits, order# 25658, thermal protection circuitry designs.
7.15
APIC Pins Characteristics
Table shows Athlon processor model characteristics APIC pins.
Table APIC Characteristics
Symbol ILEAK_P ILEAK_N TRISE TFALL CPIN
Notes:
Parameter Description Input High Voltage Input Voltage Output High Voltage Output Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Output Current Signal Rise Time Signal Fall Time Capacitance
Condition
-300
2.625 2.625
Units
Notes
-300 (Ground)
V/ns V/ns
Characterized across supply voltage range. 2.625 value equal plus maximum five percent. Edge rates indicate range characterizing inputs.
Chapter
Electrical Data
Preliminary Information AthlonXP Processor Model Data Sheet
24309E-March 2002
Electrical Data
Chapter
24309E-March 2002
AthlonXP Processor Model Data Sheet
Signal Power-Up Requirements
AthlonXP processor model designed provide functional operation voltage temperature parameters within limits normal operating ranges.
Power-Up Requirements
Figure shows relationship between signals system during power-up sequence. This figure details requirements processor.
Signal Sequence Timing Description
Supply VCCA (2.5 (for PLL) VCC_CORE (Processor Core) RESET# Warm reset condition
NB_RESET#
PWROK FID[3:0] System Clock
Figure Signal Relationship Requirements During Power-Up Sequence Note: Figure represents several signals generically using names necessarily consistent with lists schematics.
Requirements Figure described "Power-Up Timing Requirements" page
Chapter
Signal Power-Up Requirements
Preliminary Information AthlonXP Processor Model Data Sheet
24309E-March 2002
Power-Up Timing Requirements. signal timing requirements follows: RESET# must asserted before PWROK asserted. Athlon processor model does correct clock multiplier PWROK asserted prior RESET# assertion. recommended that RESET# asserted least nanoseconds prior assertion PWROK. practice, Southbridge asserts RESET# milliseconds before PWROK asserted. motherboard voltage planes must within specification before PWROK asserted. PWROK output voltage regulation circuit motherboard. PWROK indicates that VCC_CORE other voltage planes system within specification. motherboard required delay PWROK assertion minimum three milliseconds from supply being within specification. This delay ensures that system clock (SYSCLK/SYSCLK#) operating within specification when PWROK asserted. processor core voltage, VCC_CORE, must within specification dictated VID[4:0] pins driven processor before PWROK asserted. Before PWROK assertion, Athlon processor clocked ring oscillator. processor powered VCCA. processor does lock VCCA high enough processor logic switch some period before PWROK asserted. VCCA must within specification least five microseconds before PWROK asserted. practice VCCA, VCC_CORE, other voltage planes must within specification several milliseconds before PWROK asserted. After PWROK asserted, processor locks operational frequency. system clock (SYSCLK/SYSCLK#) must running before PWROK asserted. When PWROK asserted, processor switches from driving internal processor clock grid from ring oscillator driving from PLL. reference system Signal Power-Up Requirements Chapter
24309E-March 2002
AthlonXP Processor Model Data Sheet
clock must valid this time. system clocks designed running after been within specification three milliseconds. PWROK assertion deassertion RESET# duration RESET# assertion during cold boots intended satisfy time takes lock with less than phase error. processor begins after PWROK asserted internal clock grid switched from ring oscillator PLL. lock time take from hundreds nanoseconds tens microseconds. recommended that minimum time between PWROK assertion deassertion RESET# least milliseconds. Southbridges enforce delay milliseconds between PWRGD (Southbridge version PWROK) assertion NB_RESET# deassertion. PWROK must monotonic meet timing requirements defined Table "General Characteristics," page processor should switch between ring oscillator after initial assertion PWROK. NB_RESET# must asserted (causing CONNECT also assert) before RESET# deasserted. practice Southbridges enforce this requirement. NB_RESET# does assert until after RESET# deasserted, processor misinterprets CONNECT assertion (due NB_RESET# being asserted) beginning transfer. There must sufficient overlap resets ensure that CONNECT sampled asserted processor before RESET# deasserted. FID[3:0] signals valid within after PWROK asserted. chipset must sample FID[3:0] signals until they become valid. Refer AthlonProcessor-Based Motherboard Design Guide, order# 24363, specific implementation additional circuitry required. FID[3:0] signals become valid within after RESET# asserted. Refer AthlonProcessorBased Motherboard Design Guide, order# 24363, specific implementation additional circuitry required.
Chapter
Signal Power-Up Requirements
Preliminary Information AthlonXP Processor Model Data Sheet
24309E-March 2002
Clock Multiplier Selection (FID[3:0])
chipset samples FID[3:0] signals chipset-specific manner from processor uses this information determine correct Serial Initialization Packet (SIP). chipset then sends information processor configuration Athlon system clock multiplier that determines processor frequency indicated FID[3:0] code. sent processor using protocol. This protocol uses PROCRDY, CONNECT, CLKFWDRST signals, that synchronous SYSCLK. more information about FID[3:0], "FID[3:0] Pins" page Serial Initialization Packet (SIP) Protocol. Refer Athlonand DuronSystem Specification, order# 21902 details protocol.
Processor Warm Reset Requirements
RESET# cannot asserted processor without also being asserted Northbridge. RESET# Northbridge same RESET#. minimum assertion RESET# millisecond. Southbridges enforce minimum assertion RESET# processor, Northbridge, milliseconds.
Northbridge Reset Pins
Signal Power-Up Requirements
Chapter
24309E-March 2002
AthlonXP Processor Model Data Sheet
Mechanical Data
Introduction
AthlonXP processor model connects motherboard through Grid Array (PGA) socket named Socket This processor utilizes Organic Grid Array Description" page more information, AthlonProcessor-Based Motherboard Design Guide, order# 24363.
Loading
processor OPGA package exposed package. This feature facilitates heat transfer from approved heat sink. critical that mechanical loading heat sink does exceed limits shown Table heat sink design should avoid loads corners edges die. OPGA package compliant pads that serve bring surfaces planar contact. Tool-assisted zero insertion force sockets should designed that load placed ceramic substrate package. Table shows mechanical loading specifications processor die. Table Mechanical Loading
Location Surface Edge
Notes:
Dynamic (MAX)
Static (MAX)
Units
Note
Load specified coplanar contact surface. Load defined surface more than degree angle inclination surface.
Chapter
Mechanical Data
Preliminary Information AthlonXP Processor Model Data Sheet
24309E-March 2002
OPGA Package Description
Figure page shows diagram notes Athlon processor model OPGA package. Table provides dimensions millimeters assigned letters symbols shown Figure diagram. Table Dimensions AthlonXP Processor Model OPGA Package
Letter Symbol D1/E1
Note:
Minimum Maximum Dimension* Dimension* 49.27 49.78 45.72 11.698 3.30 6.40 6.40 3.35 7.48 3.05 11.01 2.35 7.90 3.29 7.94 1.66 2.65 8.45 3.84 8.49 1.96 3.60 6.95 6.95 3.90 8.03 3.35
Letter Symbol
Minimum Maximum Dimension* Dimension* 1.942 1.00 0.80 0.116 0.43 1.40 1.435 3.05 1.27 2.54 2.375 3.31 1.20 0.88 1.90 6.60 0.50 4.50
*Dimensions given millimeters.
Mechanical Data
Chapter
24309E-March 2002
AthlonXP Processor Model Data Sheet
Figure AthlonXP Processor Model OPGA Package
Chapter
Mechanical Data
Preliminary Information AthlonXP Processor Model Data Sheet
24309E-March 2002
Mechanical Data
Chapter
24309E-March 2002
AthlonXP Processor Model Data Sheet
10.1
Descriptions
Diagram Name Abbreviations
Figure page shows staggered Grid Array (PGA) AthlonXP processor model Because some names long rid, they abbreviated. Figure page shows bottomside view array. Table page lists pins alphabetical order name, along with abbreviation where necessary.
Chapter
Descriptions
SAO#3 SAO#2 SAO#6 VID[4] VID[3] THDA THDC
SAO#12 SD#54 SD#52
SAO#5 SDOC#3 SD#50 SD#19 SD#26 SD#25 SD#24 SD#7 SD#5 SDIC#0 SD#8 SD#10 SAI#5 PLMN2 PLMN1
SD#55 SD#49 SDIC#1 SD#27 SD#17 SD#15 SD#4 SD#2 SD#3 SD#0 SD#14 SDOC#0 PLBYC# PLBYC
SD#61 SD#51 SDIC#3 SD#20 SD#23 SD#29 SD#28 SD#18 SD#16 SD#6 SD#1 SD#12 SD#13 SD#11 SD#9 CLKIN# CLKIN
SD#53 SD#60 SD#48 SD#58 SD#36 SD#46 SDIC#2 SD#33 SD#32 SD#31 SD#21 SD#22 SD#59 SD#56 SD#37 SD#47 SD#38 SD#45 SD#43 SD#42 SD#41 SDOC#1
SD#63
SD#62
SD#57
SD#39
SD#35
SD#34
SD#44
SDOC#2
SD#40
SD#30
SAO#7
SAO#9
SAO#8
SAO#11
SAOC#
SAO#4
SAO#10
SAO#14
SAO#13
SAO#0
SAO#1
VID[0]
VID[1]
VID[2]
PICCLK
PICD#0
PICD#1
SCNSN
AthlonXP Processor Model Data Sheet
SCNCK1
SCNINV
SCNCK2
TRST#
FID[0]
FID[1]
VREF_S
AthlonXP Processor Model Topside View
Descriptions
COREFB ANLOG COREFB# CLKFR RCLK# RCLK
FID[2]
FID[3]
DBRDY
DBREQ#
STPC#
PLTST#
A20M#
PWROK
VCCA K7CO K7CO#
PLBYP# CNNCT PRCRDY
SAI#0
SAI#2 SFILLV# SAI#1 SAI#12
SAI#11 SAIC# SDOV# SAI#14
SAI#7 SAI#6 SAI#8 SDINV#
FERR
RESET#
SAI#3 SAI#4 SAI#13
IGNNE#
INIT#
SAI#10 SAI#9
CPR#
INTR
FLUSH#
SMI#
24309E-March 2002
Chapter
Figure AthlonXP Processor Model Diagram-Topside View
SAO#10 SAO#14 SAO#13 SD#20 SD#23 SD#21
SAO#7 SAO#1 VID[4] COREFB COREFB# SD#19 SDIC#1 SD#29 SD#28 SD#18
SAO#11 VID[1] VID[2] VID[3] ANLOG CLKFR VCCA PLBYP# SAI#0 SD#7 SD#17 SD#16
SAO#0 PICD#0 PICD#1 PLMN2 PLBYC# CLKIN# RCLK# K7CO CNNCT SAI#1 SD#5 SD#15 SD#6
VID[0] SCNSN THDA THDC CPR# PLMN1 PLBYC CLKIN RCLK K7CO# PRCRDY SAI#12 SDIC#0 SD#4
PICCLK SCNINV SCNCK2 VREF_S SMI# TRST# FID[1] FID[3] DBREQ# PLTST# PWROK RESET# INIT# FLUSH#
SCNCK1
FID[0]
FID[2]
DBRDY
STPC#
A20M#
FERR
IGNNE#
INTR
Chapter
SAO#12
SAO#9
SAOC#
24309E-March 2002
SAO#5
SAO#8
SAO#4
SAO#3
SAO#2
SAO#6
SD#55
SD#54
SD#52
SD#61
SDOC#3
SD#50
SD#53
SD#49
SD#63
SD#51
SDIC#3
SD#62
SD#60
SD#48
SD#59
SD#58
SD#57
SD#56
SD#36
AthlonXP Processor Model Bottomside View
Descriptions
SD#26 SD#27 SD#25 SD#24 SD#2 SD#1
SD#39
SD#37
SD#46
SD#35
SD#47
SD#34
SD#38
SDIC#2
SD#44
SD#45
SD#33
SD#8 SD#3 SD#12
SD#10 SD#0 SD#13
SAI#5 SD#14 SD#11
SFILLV# SAI#2 SDOC#0 SD#9
SDOV# SAIC# SAI#11 SAI#7
SAI#14 SAI#8 SAI#6 SAI#3
SD#43
SD#32
SDINV# SAI#4 SAI#10
SDOC#2
SD#42
SAI#13 SAI#9
SD#40
SD#41
SD#31
SD#30
SDOC#1
SD#22
AthlonXP Processor Model Data Sheet
Figure AthlonXP Processor Model Diagram-Bottomside View
Preliminary Information AthlonXP Processor Model Data Sheet
24309E-March 2002
Table Name Abbreviations
Abbreviation Full Name A20M# ANALOG CLKFWDRST CLKIN CLKIN# CONNECT COREFB COREFB# CPU_PRESENCE# DBRDY DBREQ# FERR FID[0] FID[1] FID[2] FID[3] FLUSH# IGNNE# INIT# INTR K7CLKOUT K7CLKOUT# AJ13 AJ21 AN17 AL17 AL23 AG11 AG13 AL21 AN21 AG15 AG17 AG27 AG29
Table Name Abbreviations (continued)
Abbreviation Full Name AA31
ANLOG CLKFR
CNNCT
CPR#
K7CO K7CO#
Descriptions
Chapter
24309E-March 2002
AthlonXP Processor Model Data Sheet
Table Name Abbreviations (continued)
Abbreviation Full Name AC31 AD30 AE31 AF10 AF28 AF30 AF32 AG19 AG21 AG23 AG25 AG31 AH30 AJ11 AJ15 AJ17 AJ19 AJ27 AL11 AL25 AL27 AN11 AN25 AN27
Table Name Abbreviations (continued)
Abbreviation PICD#0 PICD#1 PLBYP# PLBYC PLBYC# PLMN1 PLMN2 PLTST# PRCRDY Full Name PICCLK PICD[0]# PICD[1]# PLLBYPASS# PLLBYPASSCLK PLLBYPASSCLK# PLLMON1 PLLMON2 PLLTEST# PROCREADY PWROK RESET# RSTCLK RSTCLK# SADDIN[0]# SADDIN[1]# SADDIN[2]# SADDIN[3]# SADDIN[4]# SADDIN[5]# SADDIN[6]# SADDIN[7]# SADDIN[8]# SADDIN[9]# SADDIN[10]# SADDIN[11]# SADDIN[12]# SADDIN[13]# SADDIN[14]# SADDINCLK# SADDOUT[0]# SADDOUT[1]# SADDOUT[2]# SADDOUT[3]# SADDOUT[4]# SADDOUT[5]# SADDOUT[6]# SADDOUT[7]# SADDOUT[8]# AJ25 AN15 AL15 AN13 AL13 AN23 AN19 AL19 AJ29 AL29 AG33 AJ37 AL35 AE33 AJ35 AG37 AL33 AN37 AL37 AG35 AN29 AN35 AN31 AJ33
RCLK RCLK# SAI#0 SAI#1 SAI#2 SAI#3 SAI#4 SAI#5 SAI#6 SAI#7 SAI#8 SAI#9 SAI#10 SAI#11 SAI#12 SAI#13 SAI#14 SAIC# SAO#0 SAO#1 SAO#2 SAO#3 SAO#4 SAO#5 SAO#6 SAO#7 SAO#8
Chapter
Descriptions
Preliminary Information AthlonXP Processor Model Data Sheet
24309E-March 2002
Table Name Abbreviations (continued)
Abbreviation SAO#9 SAO#10 SAO#11 SAO#12 SAO#13 SAO#14 SAOC# SCNCK1 SCNCK2 SCNINV SCNSN SD#0 SD#1 SD#2 SD#3 SD#4 SD#5 SD#6 SD#7 SD#8 SD#9 SD#10 SD#11 SD#12 SD#13 SD#14 SD#15 SD#16 SD#17 SD#18 SD#19 SD#20 SD#21 SD#22 SD#23 SD#24 SD#25 SD#26 SD#27 Full Name SADDOUT[9]# SADDOUT[10]# SADDOUT[11]# SADDOUT[12]# SADDOUT[13]# SADDOUT[14]# SADDOUTCLK# SCANCLK1 SCANCLK2 SCANINTEVAL SCANSHIFTEN SDATA[0]# SDATA[1]# SDATA[2]# SDATA[3]# SDATA[4]# SDATA[5]# SDATA[6]# SDATA[7]# SDATA[8]# SDATA[9]# SDATA[10]# SDATA[11]# SDATA[12]# SDATA[13]# SDATA[14]# SDATA[15]# SDATA[16]# SDATA[17]# SDATA[18]# SDATA[19]# SDATA[20]# SDATA[21]# SDATA[22]# SDATA[23]# SDATA[24]# SDATA[25]# SDATA[26]# SDATA[27]# AA35 AA33 AE37 AC33 AC37 AA37 AC35
Table Name Abbreviations (continued)
Abbreviation SD#28 SD#29 SD#30 SD#31 SD#32 SD#33 SD#34 SD#35 SD#36 SD#37 SD#38 SD#39 SD#40 SD#41 SD#42 SD#43 SD#44 SD#45 SD#46 SD#47 SD#48 SD#49 SD#50 SD#51 SD#52 SD#53 SD#54 SD#55 SD#56 SD#57 SD#58 SD#59 SD#60 SD#61 SD#62 SD#63 SDIC#0 SDIC#1 SDIC#2 Full Name SDATA[28]# SDATA[29]# SDATA[30]# SDATA[31]# SDATA[32]# SDATA[33]# SDATA[34]# SDATA[35]# SDATA[36]# SDATA[37]# SDATA[38]# SDATA[39]# SDATA[40]# SDATA[41]# SDATA[42]# SDATA[43]# SDATA[44]# SDATA[45]# SDATA[46]# SDATA[47]# SDATA[48]# SDATA[49]# SDATA[50]# SDATA[51]# SDATA[52]# SDATA[53]# SDATA[54]# SDATA[55]# SDATA[56]# SDATA[57]# SDATA[58]# SDATA[59]# SDATA[60]# SDATA[61]# SDATA[62]# SDATA[63]# SDATAINCLK[0]# SDATAINCLK[1]# SDATAINCLK[2]#
Descriptions
Chapter
24309E-March 2002
AthlonXP Processor Model Data Sheet
Table Name Abbreviations (continued)
Abbreviation SDIC#3 SDINV# SDOC#0 SDOC#1 SDOC#2 SDOC#3 SDOV# SFILLV# STPC# Full Name SDATAINCLK[3]# SDATAINVALID# SDATAOUTCLK[0]# SDATAOUTCLK[1]# SDATAOUTCLK[2]# SDATAOUTCLK[3]# SDATAOUTVALID# SFILLVALID# SMI# STPCLK# THERMDA THERMDC TRST# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE AN33 AE35 AL31 AJ31
Table Name Abbreviations (continued)
Abbreviation Full Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE
THDA THDC
Chapter
Descriptions
Preliminary Information AthlonXP Processor Model Data Sheet
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Table Name Abbreviations (continued)
Abbreviation Full Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE AB30 AB32 AB34 AB36 AF14 AF18 AF22 AF26 AF34 AF36 AH10 AH14 AH18 AH22 AH26 AK10 AK14 AK18 AK22 AK26 AK30 AK34 AK36 AM10 AM14 AM18 AM22 AM26 AM22
Table Name Abbreviations (continued)
Abbreviation Full Name VCC_CORE VCC_CORE VCC_CORE VCCA VID[0] VID[1] VID[2] VID[3] VID[4] VREF_SYS AM26 AM30 AM34 AJ23
VREF_S
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Table Name Abbreviations (continued)
Abbreviation Full Name AD32
Table Name Abbreviations (continued)
Abbreviation Full Name AD34 AD36 AF12 AF16 AH12 AH16 AH20 AH24 AH28 AH32 AH34 AH36 AK12 AK16 AK20 AK24 AK28 AK32 AM12 AM16 AM20 AM24 AM28 AM32 AM36
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10.2
List
Table cross-references Socket location signal name. (Level) column shows electrical specification this pin. indicates push-pull mode driven single source. indicates open-drain mode that allows devices share pin. Note: Athlon processor supports push-pull drivers. more information, "Push-Pull (PP) Drivers" page (Port) column indicates this signal input (I), output (O), bidirectional signal. (Reference) column indicates this signal should referenced VCC_CORE planes purpose signal routing with respect current return paths.
Table Cross-Reference Location
SADDOUT[12]# SADDOUT[5]# SADDOUT[3]# SDATA[55]# SDATA[61]# SDATA[53]# SDATA[63]# SDATA[62]# SDATA[57]# SDATA[39]# SDATA[35]# SDATA[34]# SDATA[44]# SDATAOUTCLK[2]# SDATA[40]# SDATA[30]# page page Name Description page
Table Cross-Reference Location
VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE SADDOUT[7]# Name Description
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Table Cross-Reference Location (continued) Table Cross-Reference Location
Name SADDOUT[9]# SADDOUT[8]# SADDOUT[2]# SDATA[54]# SDATAOUTCLK[3]# SDATA[51]# SDATA[60]# SDATA[59]# SDATA[56]# SDATA[37]# SDATA[47]# SDATA[38]# SDATA[45]# SDATA[43]# SDATA[42]# SDATA[41]# SDATAOUTCLK[1]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE page Description SADDOUT[11]# SADDOUTCLK# SADDOUT[4]# SADDOUT[6]# SDATA[52]# SDATA[50]# SDATA[49]# SDATAINCLK[3]# SDATA[48]# SDATA[58]# SDATA[36]# SDATA[46]# SDATAINCLK[2]# SDATA[33]# SDATA[32]# SDATA[31]# SDATA[22]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE page page page Name Description
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Table Cross-Reference Location (continued) Table Cross-Reference Location
VCC_CORE VCC_CORE VCC_CORE SADDOUT[10]# SADDOUT[14]# SADDOUT[13]# SDATA[20]# SDATA[23]# SDATA[21]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE page page page page page page page page page page page page page page page page Name VCC_CORE page Description VCC_CORE SADDOUT[0]# SADDOUT[1]# VID[4] SDATA[19]# SDATAINCLK[1]# SDATA[29]# VCC_CORE VCC_CORE VCC_CORE VID[0] VID[1] VID[2] VID[3] SDATA[26]# SDATA[28]# VCC_CORE VCC_CORE page page page page page page page page page page page page page page page page Name Description
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Table Cross-Reference Location (continued) Table Cross-Reference Location
Name VCC_CORE VCC_CORE PICCLK PICD#[0] PICD#[1] SDATA[25]# SDATA[27]# SDATA[18]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE SCANSHIFTEN SDATA[24]# SDATA[17]# SDATA[16]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE page page page page page page page page page page Description SCANCLK1 SCANINTEVAL SCANCLK2 THERMDA SDATA[7]# SDATA[15]# SDATA[6]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE TRST# THERMDC SDATA[5]# SDATA[4]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE page page page page page page page page page page page Name Description
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Table Cross-Reference Location (continued) Table Cross-Reference Location
FID[0] FID[1] VREFSYS SDATAINCLK[0]# SDATA[2]# SDATA[1]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE FID[2] FID[3] SDATA[3]# SDATA[12]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE page page page page page page page page page page page Name Description AA31 AA33 AA35 AA37 AB30 AB32 AB34 AB36 AC31 AC33 AC35 AC37 AD30 AD32 AD34 AD36 Name DBRDY DBREQ# SDATA[8]# SDATA[0]# SDATA[13]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE STPCLK# PLLTEST# SDATA[10]# SDATA[14]# SDATA[11]# VCC_CORE VCC_CORE VCC_CORE A20M# PWROK page page page page page page page page Description page page
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Table Cross-Reference Location (continued) Table Cross-Reference Location
AE31 AE33 AE35 AE37 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AF30 AF32 AF34 AF36 AG11 AG13 AG15 AG17 AG19 SADDIN[5]# SDATAOUTCLK[0]# SDATA[9]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE FERR RESET# COREFB COREFB# page page page page page page page page page page page page page page page page Name Description page AG21 AG23 AG25 AG27 AG29 AG31 AG33 AG35 AG37 AH10 AH12 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AH32 AH34 AH36 AJ11 AJ13 SADDIN[2]# SADDIN[11]# SADDIN[7]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE IGNNE# INIT# VCC_CORE Analog page page page page page page page page page Name Description page page page page page page
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Table Cross-Reference Location (continued) Table Cross-Reference Location
AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AJ33 AJ35 AJ37 AK10 AK12 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK30 AK32 AK34 AK36 CLKFWDRST VCCA PLLBYPASS# SADDIN[0]# SFILLVALID# SADDINCLK# SADDIN[6]# SADDIN[3]# CPU_PRESENCE# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE INTR FLUSH# VCC_CORE page page page page page Name Description page page page page page page page page AL11 AL13 AL15 AL17 AL19 AL21 AL23 AL25 AL27 AL29 AL31 AL33 AL35 AL37 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AM32 AM34 AM36 PLLMON2 PLLBYPASSCLK# CLKIN# RSTCLK# K7CLKOUT CONNECT SADDIN[1]# SDATAOUTVALID# SADDIN[8]# SADDIN[4]# SADDIN[10]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE page page Name Description page page page page page page page page page page page
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Table Cross-Reference Location (continued)
AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25 AN27 AN29 AN31 AN33 AN35 AN37 SMI# PLLMON1 PLLBYPASSCLK CLKIN RSTCLK K7CLKOUT# PROCRDY SADDIN[12]# SADDIN[14]# SDATAINVALID# SADDIN[13]# SADDIN[9]# page page page page page page page page page page Name Description
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10.3
Detailed Descriptions
information this section pertains Table page
A20M#
A20M# input from system used simulate address wrap-around 20-bit 8086. Socket processors implement location AH6. Socket designs must have plate cover that blocks this location. When cover plate blocks this location, non-AMD part (e.g., PGA370) does into socket. However, socket manufacturers allowed have contact loaded position. Therefore, motherboard socket design should account possibility that contact could loaded this position. Athlonand DuronSystem Specification, order# 21902 information about system pins PROCRDY, PWROK, RESET#, SADDIN[14:2]#, SADDINCLK#, SADDOUT[14:2]#, SADDOUTCLK#, SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAINVALID#, SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#. Treat this Advanced Programmable Interrupt Controller (APIC) feature that provides flexible expandable means delivering interrupts system using processor. pins, PICD[1:0], bi-directional message-passing signals used APIC driven Southbridge dedicated APIC. pin, PICCLK, must driven with valid clock input. more information, Table "APIC Characteristics," page
AthlonSystem Pins
Analog APIC Pins, PICCLK, PICD[1:0]#
CLKFWDRST CLKIN, RSTCLK (SYSCLK) Pins
CLKFWDRST resets clock-forward circuitry both system processor. Connect CLKIN with RSTCLK name SYSCLK. Connect CLKIN# with RSTCLK# name SYSCLK#. Length match clocks from clock generator Northbridge processor.
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"SYSCLK SYSCLK#" page more information. CONNECT COREFB COREFB# Pins CPU_PRESENCE# CONNECT input from system used power management clock-forward initialization reset. COREFB COREFB# outputs system that provide processor core voltage feedback system. CPU_PRESENCE# connected processor package. pulled-up motherboard, CPU_PRESENCE# used detect presence absence processor Socket A-style socket. DBRDY DBREQ# routed debug connector. DBREQ# tied VCC_CORE with pullup resistor. FERR output system that asserted unmasked numerical exception independent CR0. FERR push-pull active High signal that must inverted level shifted active signal. more information about FERR FERR#, "Required Circuits" chapter AthlonProcessor-Based Motherboard Design Guide, order# 24363.
DBRDY DBREQ# Pins FERR
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FID[3:0] Pins
FID[3] (Y3), FID[2] (Y1), FID[1] (W3), FID[0] (W1) 4-bit processor clock-to-SYSCLK ratio. Table describes encodings clock multipliers FID[3:0]. Table FID[3:0] Clock Multiplier Encodings
FID[3:0]2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Notes:
Processor Clock SYSCLK Frequency Ratio 11.5
12.51 10.5
ratios greater than equal 12.5x have same FID[3:0] code 0011, which causes configuration ratios 12.5x greater same. BIOS initializes CLK_Ctl 6003_D22Fh during POST routine. This CLK_Ctl setting used with combinations selects Halt disconnect divisor Stop Grant disconnect divisor more information, refer Athlonand DuronProcessors BIOS, Software, Debug Developers Guide, order# 21656.
FID[3:0] signals open drain processor outputs that pulled High motherboard sampled chipset determine (Serialization Initialization Packet) that sent processor. FID[3:0] signals valid after PWROK asserted. FID[3:0]signals must sampled DuronSystem Specification, order# 21902 more information about Serialization Initialization Packets protocol.
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processor FID[3:0] outputs open drain tolerant. prevent damage processor, these signals pulled High above they must electrically isolated from processor. information about FID[3:0] isolation circuit, AthlonProcessor-Based Motherboard Design Guide, order# 24363. "Frequency Identification (FID[3:0])" page characteristics FID[3:0]. FLUSH# FLUSH# must tied VCC_CORE with pullup resistor. debug connector implemented, FLUSH# routed debug connector. IGNNE# input from system that tells processor ignore numeric errors. INIT# input from system that resets integer registers without affecting floating-point registers internal caches. Execution starts 0_FFFF_FFF0h. INTR input from system that causes processor start interrupt acknowledge transaction that fetches 8-bit interrupt vector starts execution that location. TCK, TMS, TDI, TRST#, JTAG interface. Connect these pins directly motherboard debug connector. Pull TDI, TCK, TMS, TRST# VCC_CORE with pullup resistors. K7CLKOUT K7CLKOUT# each three inches then terminated with resistor pair: ohms VCC_CORE ohms VSS. effective termination resistance voltage ohms VCC_CORE/2. These locations processor type keying forwards backwards compatibility (G7, G15, G17, G23, G25, AA7, AG7, AG9, AG15, AG17, AG27, AG29). Motherboard designers should treat pins like Connect) pins. socket designer option creating mold piece that allows pins only where designated. However, sockets that populate pins must allowed, motherboard must always provide pins locations.
IGNNE# INIT#
INTR
JTAG Pins
K7CLKOUT K7CLKOUT# Pins
Pins
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Pins" more information. Pins Orientation Pins motherboard should provide plated hole pin. hole should electrically connected anything. input from system that causes non-maskable interrupt. present locations AN1. Motherboard designers should allow socket these locations. more information, AthlonProcessor-Based Motherboard Design Guide, order# 24363. Bypass Test Pins PLLBYPASSCLK, PLLBYPASSCLK# bypass test interface. This interface tied disabled motherboard. signals routed debug connector. four processor inputs (PLLTEST#, PLLBYPASS#, PLLMON1, PLLMON2) tied VCC_CORE with pullup resistors. PWROK input processor must asserted until voltage planes system within specification system clocks running within specification. more information, Chapter "Signal Power-Up Requirements" page SADDIN[1:0]# SADDOUT[1:0]# Pins Athlon processor model does support SADDIN[1:0]# SADDOUT[1:0]#. SADDIN[1]# tied with pullup resistors, this supported Northbridge (future models support SADDIN[1]#). SADDOUT[1:0]# tied with pullup resistors these pins supported Northbridge. more information, Athlonand DuronSystem Specification, order# 21902. SCANSHIFTEN, SCANCLK1, SCANINTEVAL, SCANCLK2 scan interface. This interface internal tied disabled with pulldown resistors ground motherboard.
PWROK
Scan Pins
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SMI# STPCLK# SYSCLK SYSCLK#
SMI# input that causes processor enter system management mode. STPCLK# input that causes processor enter lower power mode issue Stop Grant special cycle. SYSCLK SYSCLK# differential input clock signals provided processor from system-clock generator. "CLKIN, RSTCLK (SYSCLK) Pins" page more information.
THERMDA THERMDC Pins
Thermal Diode anode cathode pins used monitor actual temperature processor die, providing more accurate temperature control system. Table "Thermal Diode Electrical Characteristics," page more information.
VCCA
VCCA processor supply. information about VCCA pin, Table "VCCA Characteristics," page AthlonProcessor-Based Motherboard Design Guide, order# 24363. VID[4:0] (Voltage Identification) outputs used dictate VCC_CORE voltage level. VID[4:0] pins strapped ground left unconnected processor package. VID[4:0] pins pulled-up motherboard used VCC_CORE DC/DC converter. more information, Table "VID[4:0] Code Voltage Definition," page
VID[4:0] Pins
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Table VID[4:0] Code Voltage Definition
VID[4:0] 00000 00001 00010 00011 00100 00101 00111 01000 01001 01010 01011 01100 01101 01110 01111 VCC_CORE 1.850 1.825 1.800 1.775 1.750 1.725 1.675 1.650 1.625 1.600 1.575 1.550 1.525 1.500 1.475 VID[4:0] 10000 10001 10010 10011 10100 10101 10111 11000 11001 11010 11011 11100 11101 11110 11111 VCC_CORE 1.450 1.425 1.400 1.375 1.350 1.325 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100
more information, "Required Circuits" chapter AthlonProcessor-Based Motherboard Design Guide, order# 24363. VREFSYS VREFSYS (W5) drives threshold voltage system input receivers. value VREFSYS system specific. addition, minimize VCC_CORE noise rejection from information, AthlonProcessor-Based Motherboard Design Guide, order# 24363. (AC5) (AE5) push-pull compensation circuit pins. Push-Pull mode (selected parameter SysPushPull asserted), tied VCC_CORE with resistor that resistance matching impedance transmission line. tied with resistor that resistance matching impedance transmission line.
Pins
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Ordering Information
Standard AthlonXP Processor Model Products
standard products available several operating ranges. ordering part numbers (OPN) formed combination elements, shown Figure
2100
FSB: Size Cache: Kbytes Temperature: Operating Voltage: 1.75 Package Type: OPGA Model Number: 1500 operates 1333 MHz, 1600 1400 MHz, 1700 1467 MHz, 1800 1533 MHz, 1900 1600 MHz, 2000 1667 2100 1733 Generation: High-Performance Desktop Processor Family/Architecture: AthlonXP Processor Model Architecture
Note: Spaces added number shown above viewing clarity only.
Figure Example AthlonXP Processor Model
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Preliminary Information AthlonXP Processor Model Data Sheet
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Ordering Information
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Appendix
Conventions Abbreviations
This section contains information about conventions abbreviations used this document.
Signals Bits
Active-Low Signals-Signal names containing pound sign, such SFILL#, indicate active-Low signals. They asserted their Low-voltage state negated their High-voltage state. When used this context, High written with initial upper case letter. Signal Ranges-In range signals, highest lowest signal numbers contained brackets separated colon (for example, D[63:0]). Reserved Bits Signals-Signals bits marked reserved must driven inactive left unconnected, indicated signal descriptions. These bits signals reserved future implementations. When software reads registers with reserved bits, reserved bits must masked. When software writes such registers, must first read register change only non-reserved bits before writing back register. Three-State-In timing diagrams, signal ranges that high impedance shown straight horizontal line half-way between high levels.
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Preliminary Information AthlonXP Processor Model Data Sheet
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Invalid Don't-Care-In timing diagrams, signal ranges that invalid don't-care filled with screen pattern.
Data Terminology
following list defines data terminology:
Quantities word bytes bits) doubleword four bytes bits) quadword eight bytes bits) Addressing-Memory addressed series bytes eight-byte (64-bit) boundaries which each byte separately enabled. Abbreviations-The following notation used bits bytes: Kilo 4-Kbyte page) Mega Mbits/sec) Giga Gbytes memory space) Table page more abbreviations. Little-Endian Convention-The byte with address xx.xx00 least-significant byte position (little end). byte diagrams, positions numbered from right left-the little right left. Data structure diagrams memory show addresses bottom high addresses top. When data items aligned, notation 64-bit data maps directly notation 64-bit-wide memory. Because byte addresses increase from right left, strings appear reverse order when illustrated. Ranges-In text, ranges shown with dash (for example, bits 9-1). When accompanied signal name, highest lowest numbers contained brackets separated colon (for example, AD[31:0]). Values-Bits either cleared Hexadecimal Binary Numbers-Unless context makes interpretation clear, hexadecimal numbers followed binary numbers followed
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Abbreviations Acronyms
Table contains definitions abbreviations used this document. Table Abbreviations
Abbreviation Gbit Gbyte Kbyte Mbit Mbyte Meaning Ampere Farad Giga- Gigabit Gigabyte Henry Hexadecimal Kilo- Kilobyte Mega- Megabit Megabyte Megahertz Milli- Millisecond Milliwatt Micro- Microampere Microfarad Microhenry Microsecond Microvolt nano- nanoampere nanofarad nanohenry nanosecond pico- picoampere
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Table Abbreviations (continued)
Abbreviation Meaning picofarad picohenry picosecond Second Volt Watt
Table contains definitions acronyms used this document. Table Acronyms
Abbreviation ACPI APCI APIC BIOS BIST CPGA DIMM DRAM EIDE EISA EPROM FIFO GART HSTL JEDEC Meaning Advanced Configuration Power Interface Accelerated Graphics Port Peripheral Component Interconnect Application Programming Interface Advanced Programmable Interrupt Controller Basic Input/Output System Built-In Self-Test Interface Unit Ceramic Grid Array Double-Data Rate Dual Inline Memory Module Direct Memory Access Direct Random Access Memory Enhanced Integrated Device Electronics Extended Industry Standard Architecture Enhanced Programmable Read Only Memory First First Graphics Address Remapping Table High-Speed Transistor Logic Integrated Device Electronics Instructions Cycle Industry Standard Architecture Joint Electron Device Engineering Council
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Table Acronyms (continued)
Abbreviation JTAG LVTTL MTRR OPGA PBGA PMSM POST SCSI SDRAM SIMD SMbus SRAM SROM Meaning Joint Test Action Group Large Area Network Least-Recently Used Voltage Transistor Transistor Logic Most Significant Memory Type Range Registers Multiplexer Non-Maskable Interrupt Open-Drain Organic Grid Array Plastic Ball Grid Array Physical Address Peripheral Component Interconnect Page Directory Entry Page Directory Table Grid Array Phase Locked Loop Power Management State Machine Power-On Suspend Power-On Self-Test Random Access Memory Read Only Memory Read Acknowledge Queue Small Computer System Interface System DRAM Interface Synchronous Direct Random Access Memory Single Instruction Multiple Data Serial Initialization Packet System Management Serial Presence Detect Synchronous Random Access Memory Serial Read Only Memory Translation Lookaside Buffer Memory
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24309E-March 2002
Table Acronyms (continued)
Abbreviation Meaning Transistor Transistor Logic Virtual Address Space Virtual Page Address Video Graphics Adapter Universal Serial Zero Delay Buffer
Appendix

Publication 24309 Rev: Issue Date: March 2002 2000-2002 Advanced

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