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Athlon Processor Model
Multiprocessor-Capable Workstation Server Platforms
Publication 24685 Rev.: Issue Date: June 2001
2001 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right.
AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products
Trademarks AMD, logo, Athlon, Duron, combinations thereof, AMD-760, 3DNow!, HyperTransport trademarks Advanced Micro Devices, Inc. trademark Intel Corporation. Digital Alpha trademarks Digital Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
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ContentsRevision Historyxi
Revision History. Overview
AthlonMP Processor Model Microarchitecture Summary Overview Signaling Technology Push-Pull (PP) Drivers Athlon System Signals
Interface Signals
Logic Symbol Diagram Power Management
Power Management States Working State Halt State Stop Grant States. Probe State. Connect Disconnect Protocol Connect Protocol Clock Control
CPUID Support Thermal Design Electrical Data
7.10 7.11 7.12 7.13 7.14 Conventions Interface Signal Groupings Voltage Identification (VID[4:0]) Frequency Identification (FID[3:0]) VCCA Characteristics Decoupling VCC_CORE Characteristics Absolute Ratings VCC_CORE Voltage Current SYSCLK SYSCLK# Characteristics Athlon System Characteristics General Characteristics Thermal Diode Characteristics APIC Pins Characteristics
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Signal Power-Up Requirements
Power-Up Requirements Signal Sequence Timing Description Clock Multiplier Selection (FID[3:0]) Processor Warm Reset Requirements Northbridge Reset Pins Introduction Loading Package Description Diagram Name Abbreviations List Detailed Descriptions A20M# Athlon System Pins Analog APIC Pins, PICCLK, PICD[1:0]# CLKFWDRST CLKIN, RSTCLK (SYSCLK) Pins. CONNECT COREFB COREFB# Pins CPU_PRESENCE# DBRDY DBREQ# Pins FERR FID[3:0] Pins FLUSH# IGNNE# INIT# INTR Pin. JTAG Pins K7CLKOUT K7CLKOUT# Pins. Pins Pins Orientation Pins Bypass Test Pins PWROK SADDIN[1:0]# SADDOUT[1:0]# Pins Scan Pins SCHECK[7:0]# SMI# STPCLK# SYSCLK SYSCLK#.
Mechanical Data
Descriptions
10.1 10.2 10.3
Table Contents
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THDA THDC Pins VCCA VID[4:0] Pins VREFSYS Pins
Ordering Information
Standard Athlon Processor Model Products
Appendix Conventions Abbreviations
Signals Bits Data Terminology Abbreviations Acronyms.
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Table Contents
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List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Logic Symbol Diagram AthlonMP Processor Model Power Management States Example Athlon System Disconnect Sequence Stop Grant State Exiting Stop Grant State Connect Sequence Northbridge Connect State Diagram Processor Connect State Diagram VCC_CORE Voltage Waveform SYSCLK SYSCLK# Differential Clock Signals SYSCLK Waveform
Figure Signal Relationship Requirements During Power-Up Sequence Figure Athlon Processor Model Package View Figure Athlon Processor Model Diagram- Topside View Figure Athlon Processor Model Diagram- Bottomside View Figure Example Athlon Processor Model
List Figures
Preliminary Information AthlonMP Processor Model Multiprocessor Platforms
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viii
List Figures
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List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Thermal Design Power. Interface Signal Groupings VID[4:0] Characteristics FID[3:0] Characteristics VCCA Characteristics VCC_CORE Characteristics Absolute Ratings VCC_CORE Voltage Current. SYSCLK SYSCLK# Characteristics SYSCLK SYSCLK# Characteristics AthlonSystem Characteristics Athlon System Characteristics General Characteristics Thermal Diode Characteristics APIC Pins Characteristics CPGA Mechanical Loading Name Abbreviations Cross-Reference Location FID[3:0] Clock Multiplier Encodings VID[4:0] Code Voltage Definition Abbreviations Acronyms.
List Tables
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List Tables
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Revision History
Date June 2001 April 2001 Initial Public Release. Initial Release. Description
Revision History
Preliminary Information AthlonMP Processor Model Multiprocessor Platforms
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Revision History
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AthlonMP Processor Model Multiprocessor Platforms
Overview
AthlonM Processor Model powers next generation computing platforms, delivering compelling performance cutting-edge applications unprecedented computing experience.
Athlon processor model with performance-enhancing cache memory latest member Athlon family processors. Offering multiprocessor capability, these processors designed meet reliability computation-intensive requirements cutting-edge software applications running required workstations servers. Delivered socket package achieving frequencies (1200 MHz), Athlon processor model delivers integer, floating-point, multimedia performance enterprise applications running system platforms. Athlon processor model offers compelling performance productivity software, including workstation-class Digital Content Creation (DCC), Electronic Design Automation (EDA), Computer-Aided Design (CAD), well infrastructure collaborative server applications. also offers scalability `peace-of-mind' reliability that managers business users require mission-critical computing. seventh-generation microarchitecture, including high-speed execution core that includes multiple instruction decoders; dual-ported, 128-Kbyte, split level-one (L1) cache; 256-Kbyte on-chip cache; three independent integer pipelines, three address calculation pipelines; superscalar, fully pipelined, out-of-order, three-way floating-point engine. integrated cache supports growing processor system bandwidth requirements emerging software, graphics, I/O, memory technologies. processor also features advanced MOESI cache coherency protocol ensure efficient cache integrity multiprocessing environment. floating-point engine capable delivering superior performance numerically complex applications typical servers workstations.
Chapter
Overview
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Prototyping, modeling, high-end visualization applications take advantage exclusive Translation Lookaside rdwa Athlon processor model These full-speed cache features allow applications spend less time searching frequently used data more time computing tasks. Athlon processor model microarchitecture incorporates enhanced 3DNow!Professional technology, high-performance cache architecture, system that designed 266-MHz 2.1-Gigabyte second. This system combines latest technological advances, packet-based transfers, low-voltage signaling. Athlon processor model offers most powerful, scalable system architectures available microprocessors. Athlon processor model features point-topoint front-side architecture, providing more efficient, higher bandwidth that allows each processor, multiprocessor configuration, communicate system chipsets through two, full speed, independent buses rather than through common, shared bus. Combined with AMD-760MP chipset, processor system interface with double-data rate (DDR) memory subsystems, providing scalable headroom bandwidth-hungry applications such large databases, CAD/CAM modeling, simulation engines. front-side Athlon processor model also provides multiple-bit error detection single-bit error correction with 8-bit Error Correcting Code (ECC). frontside with 8-bit delivers high reliability consistency demanded mission-critical applications. Athlon processor model binary-compatible with existing software backwards compatible with applications optimized MMXand 3DNow!Professional technologies. Using data format Single-Instruction instruction model, Athlon processor model produce many four, 32-bit, single-precision floating-point results clock cycle. 3DNow! Professional technology implemented Athlon processor model includes integer multimedia instructions Overview Chapter
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software-directed data movement instructions optimizing such applications digital content creation streaming video internet, well instructions Digital Signal Processing (DSP)/communications applications. multimedia instructions incorporated Athlon processor model further extends capability 3DNow! more software than other processor world.
AthlonMP Processor Model Microarchitecture Summary
following features summarize Athlon processor model microarchitecture:
nine-issue, superpipelined, superscalar, processor microarchitecture designed high clock frequencies Multiple instruction decoders Three out-of-order, superscalar, fully pipelined floatingpoint execution units, which execute (floating-point), 3DNow! Professional instructions Three out-of-order, superscalar, pipelined integer units Three out-of-order, superscalar, pipelined address calculation units 72-entry instruction control unit Advanced dynamic branch prediction 3DNow! Professional technology with instructions enable improved integer-math calculations speech video encoding improved data movement internet plug-ins other streaming applications 266-MHz Athlon system (scalable beyond MHz) enabling leading-edge system bandwidth data movement-intensive applications Point-to-point front-side architecture allowing each processor multi-processor configuration communicate system chipsets through two, full speed, independent buses High-performance cache architecture featuring integrated 128-Kbyte cache 16-way, 256-Kbyte onchip cache total Kbytes on-chip cache
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Overview
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Exclusive Translation Lookaside Buffer (TLB) hardware pre-fetch Multiple-bit error detection single-bit error correction with 8-bit Error Correcting Code (ECC) Full featured Local APIC implementation Advanced MOESI cache coherency protocol ensure efficient cache integrity multiprocessing environment
Athlon processor model delivers superior scalability system performance cost-effective, industrystandard form factor. processor compatible with motherboards based AMD's Socket information about Athlon processor module, AthlonProcessor Module Data Sheet, order# 21016.
Overview
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Interface Signals
Overview
Athlonsystem architecture designed deliver superior data movement bandwidth next-generation platforms well high-performance required enterprise-class application software. system architecture consists three high-speed channels unidirectional processor request channel, unidirectional probe channel, 72-bit bidirectional data channel, including 8-bit Error Code Correction [ECC] protection), source-synchronous clocking, packet-based protocol. addition, system supports several control, clock, legacy signals. interface signals impedance controlled push-pull low-voltage swing signaling technology contained within Socket mechanical connector. more information, "AMD AthlonSystem Signals" page Chapter "Pin Descriptions" page Athlonand DuronSystem Specification, order# 21902.
Signaling Technology
Athlon system uses low-voltage, swing signaling technology, that been enhanced provide larger noise margins, reduced ringing, variable voltage levels. signals push-pull impedance compensated. signal inputs differential receivers, that require reference voltage (VREF). reference signal used receivers determine signal asserted deasserted source. Termination resistors needed because driver impedance-matched motherboard high impedance reflection used receiver bring signal past input threshold. more information about pins signals, Chapter "Pin Descriptions" page
Chapter
Interface Signals
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Push-Pull (PP) Drivers
Athlon processor model supports Push-Pull (PP) drivers. system logic configures processor with configuration parameter called SysPushPull (1=PP). impedance drivers match impedance motherboard external resistors connected pins. Pins" page more information.
AthlonSystem Signals
Athlon system clock-forwarded, point-topoint interface with following three point-to-point channels:
13-bit unidirectional output address/command channel 13-bit unidirectional input address/command channel 72-bit bidirectional data channel
more information, Chapter "Electrical Data" page Athlonand DuronSystem Specification, order# 21902.
Interface Signals
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Logic Symbol Diagram
Figure logic symbol diagram processor. This diagram shows logical grouping input output signals. Clock
SYSCLK SDATA[63:0]# SDATAINCLK[3:0]# SDATAOUTCLK[3:0]# SCHECK[7:0]# SDATAINVALID# SDATAOUTVALID# SFILLVALID# SADDIN[14:2]# SADDINCLK# SADDOUT[14:2]# SADDOUTCLK# PROCRDY CLKFWDRST CONNECT STPCLK# RESET#
SYSCLK# VID[4:0] COREFB COREFB# PWROK FID[3:0]
Voltage Control
Data
Frequency Control
Probe/SysCMD Request
AthlonMP Processor Model
Power Management Initialization
FERR IGNNE# INIT# INTR A20M# SMI# FLUSH# THERMDA THERMDC PICCLK PICD[1:0]
Legacy
Thermal Diode APIC
Figure Logic Symbol Diagram
Chapter
Logic Symbol Diagram
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Logic Symbol Diagram
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Power Management
This chapter describes power management control system AthlonMP processor model power management features processor compliant with ACPI 1.0b ACPI specifications.
Power Management States
Athlon processor model supports low-power Halt Stop Grant states. These states used Advanced Configuration Power Interface (ACPI) enabled operating systems processor power management. Figure shows power management states processor. figure includes ACPI "Cx" naming convention these states.
Write FidVidCtl Working44 Working Stream System Connect
dess aser setre aser setre
Halt Halt
Execute Execute SMI#, INTR, NMI, INIT#, RESET# SMI#, INTR, NMI, INIT#, RESET#
FID_Change
(Read PLVL2 register (Read PLVL2 register throttling) throttling)
STPCLK# deasserted STPCLK# deasserted
STPCLK# asserted STPCLK# asserted
Incoming Probe Incoming Probe
ease ssete ssete
Probe Probe State11 State
Note: Note:
AthlonProcessor System connected during following states: AthlonSystem connected during following states: Probe state Probe state During transitions between Halt state Stop Grant state During transitions between Halt state Stop Grant state During transitions between Stop Grant state Halt state During transitions between Stop Grant state Halt state Working state Working state
Figure AthlonMP Processor Model Power Management States Chapter Power Management
Probe Serviced Probe Serviced
Incoming Probe Incoming Probe Probe Serviced Probe Serviced
Stop Grant Stop Grant Cache Snoopable Cache Snoopable
C3/S1 Stop Grant Stop Grant Cache Snoopable Cache Snoopable Sleep Sleep Legend Legend Hardware transitions Hardware transitions Software transitions Software transitions
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following sections provide overview power Athlonand DuronSystem Specification, order# 21902. Note: power management states that processor powered, system must stop system clock (SYSCLK/SYSCLK#) processor. Working State Halt State Working state state which processor executing instructions. When processor executes instruction, processor enters Halt state issues Halt special cycle Athlon system bus. processor only enters power state dictated CLK_Ctl system controller (Northbridge) disconnects Athlon system response Halt special cycle. STPCLK# asserted, processor will exit Halt state enter Stop Grant state. processor will initiate system connect, disconnected, then issue Stop Grant special cycle. When STPCLK# deasserted, processor will exit Stop Grant state re-enter Halt state. processor will issue Halt special cycle when re-entering Halt state. Halt state exited when processor detects assertion INIT#, RESET#, SMI#, interrupt INTR pins, local APIC interrupt message. When Halt processor will initiate Athlon system connect disconnected. Stop Grant States processor enters Stop Grant state upon recognition assertion STPCLK# input. There mechanisms asserting STPCLK#-hardware software. Southbridge force STPCLK# assertion throttling protect processor from exceeding maximum case temperature. This accomplished asserting THERM# input Southbridge. Throttling asserts STPCLK# percentage predefined throttling period: STPCLK# repetitively asserted deasserted until THERM# deasserted. Software force processor into Stop Grant state accessing ACPI-defined registers typically located Power Management Chapter
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Southbridge. Software places processor reading PLVL_2 register Southbridge. probes allowed, shown Figure page Stop Grant state also entered Powered Suspend, system sleep state based write SLP_TYP SLP_EN fields ACPI-defined Power Management control register Southbridge. During sleep state, system software ensures master probe activity occurs. Southbridge deasserts STPCLK# brings processor Stop Grant state when enabled resume event occurs. Probe State Probe state entered when Northbridge connects Athlon system probe processor (for example, snoop processor caches) when processor Halt Stop Grant state. When Probe state, processor responds probe cycle same manner when Working state. When probe been serviced, processor returns same state when entered Probe state (Halt Stop Grant state). When probe activity completed processor only returns low-power state after Northbridge disconnects Athlon system again.
Chapter
Power Management
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Connect Disconnect Protocol
Significant power savings processor only occur processor disconnected system Northbridge while Halt Stop Grant state. Northbridge optionally initiate disconnect upon receipt Halt Stop Grant special cycle. option disconnecting controlled enable Northbridge. Northbridge requires processor service probe after system been disconnected, must first initiate system connect.
Connect Protocol
addition legacy STPCLK# signal Halt Stop Grant special cycles, Athlon system connect protocol includes CONNECT, PROCRDY, CLKFWDRST signals Connect special cycle. Athlon system disconnects initiated Northbridge response receipt Halt Stop Grant special cycle. Reconnect initiated processor response interrupt Halt, STPCLK# deassertion, Northbridge service probe. Northbridge contains BIOS programmable registers enable system disconnect response Halt Stop Grant special cycles. When Northbridge receives Halt Stop Grant special cycle from processor and, there outstanding probes data movements, Northbridge deasserts CONNECT minimum eight SYSCLK periods after last command sent processor. processor detects deassertion CONNECT rising edge SYSCLK deasserts PROCRDY Northbridge. return, Northbridge asserts CLKFWDRST anticipation reestablishing connection some later point. Note: Northbridge must disconnect processor from Athlon system before issuing Stop Grant special cycle bus, passing Stop Grant special cycle Southbridge systems that connect Southbridge with HyperTransporttechnology. This note applies current chipset implementation- alternate chipset implementations that require this possible.
Power Management
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Note: response Halt special cycles, Northbridge passes Halt special cycle Southbridge immediately. processor receive interrupt after sends Halt special cycle, STPCLK# deassertion after sends Stop Grant special cycle Northbridge before disconnect actually occurs. this case, processor sends Connect special cycle Northbridge, rather than continuing with disconnect sequence. response Connect special cycle, Northbridge cancels disconnect request. system required assert CONNECT signal before returning C-bit connect special cycle (assuming CONNECT been deasserted). more information, Athlonand DuronSystem Specification, order# 21902 definition C-bit Connect special cycle.
Figure shows STPCLK# assertion resulting processor Stop Grant state system disconnected.
STPCLK# AthlonSystem CONNECT PROCRDY CLKFWDRST Stop Grant
Stop Grant
Figure Example AthlonSystem Disconnect Sequence Stop Grant State Northbridge contains BIOS programmable registers enable system disconnect response Halt Stop Grant special cycles. When Northbridge receives Halt Stop Grant special cycle from processor and, there outstanding probes data movements, Northbridge deasserts CONNECT minimum eight SYSCLK periods after last command sent processor. processor detects deassertion CONNECT rising edge SYSCLK Chapter Power Management
Preliminary Information AthlonMP Processor Model Multiprocessor Platforms
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deasserts PROCRDY Northbridge. return, Northbridge asserts CLKFWDRST anticipation reestablishing connection some later point. Note: Northbridge must disconnect processor from Athlon system before issuing Stop Grant special cycle bus, passing Stop Grant special cycle Southbridge systems that connect Southbridge with HyperTransporttechnology. This note applies current chipset implementation- alternate chipset implementations that require this possible. Note: response Halt special cycles, Northbridge passes Halt special cycle Southbridge immediately. processor receive interrupt after sends Halt special cycle, STPCLK# deassertion after sends Stop Grant special cycle Northbridge before disconnect actually occurs. this case, processor sends Connect special cycle Northbridge, rather than continuing with disconnect sequence. response Connect special cycle, Northbridge cancels disconnect request. system required assert CONNECT signal before returning C-bit connect special cycle (assuming CONNECT been deasserted). more information, Athlonand DuronSystem Specification, order# 21902 definition C-bit Connect special cycle. Figure shows signal sequence events that takes processor Stop Grant state, connects processor Athlon system bus, puts processor into Working state.
Power Management
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STPCLK# PROCRDY CONNECT CLKFWDRST
Figure Exiting Stop Grant State Connect Sequence
following sequence events removes processor from Stop Grant state connects system bus: Southbridge deasserts processor wake event. STPCLK#, informing
When processor recognizes STPCLK# deassertion, exits low-power state asserts PROCRDY, notifying Northbridge connect bus. Northbridge asserts CONNECT. Northbridge deasserts CLKFWDRST, synchronizing forwarded clocks between processor Northbridge. processor issues Connect special cycle system resumes operating system application code execution. Figure Figure page describe Northbridge processor connect state diagrams, respectively.
Chapter
Power Management
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Disconnect Pending Connect
Disconnect Requested
Disconnect 7/D,C
Reconnect Pending
Probe Pending
Probe Pending
Condition disconnect requested probes still pending. disconnect requested probes pending. Connect special cycle from processor. probes pending. PROCRDY deasserted. probe needs service. PROCRDY asserted. Three SYSCLK periods after CLKFWDRST deasserted. Although reconnected system interface, Northbridge must issue non-NOP SysDC commands minimum four SYSCLK periods after deasserting CLKFWDRST.
Action Deassert CONNECT eight SYSCLK periods after last SysDC sent.
Assert CLKFWDRST. Assert CONNECT. Deassert CLKFWDRST.
Figure Northbridge Connect State Diagram
Power Management
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Connect Connect Pending Connect Pending Disconnect
Disconnect Pending
Condition CONNECT deasserted Northbridge (for previously sent Halt Stop Grant special cycle). Processor receives wake-up event must cancel disconnect request.
Action CLKFWDRST asserted Northbridge. Issue Connect special cycle.* Return internal clocks full speed assert PROCRDY
Connect special cycle only issued after
Deassert PROCRDY slow down internal clocks. Processor wake-up event CONNECT asserted Northbridge. CLKFWDRST deasserted Northbridge. Forward clocks start three SYSCLK periods after CLKFWDRST deasserted.
processor wake-up event (interrupt STPCLK# deassertion) occurs. Athlonsystem connected Northbridge probe processor Connect special cycle issued that time only issued after subsequent processor wake-up event).
Figure Processor Connect State Diagram
Chapter
Power Management
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Clock Control
processor implements Clock Control (CLK_Ctl) (address C001_001Bh) that determines internal clock divisor when Athlon system disconnected.
Power Management
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CPUID Support
AthlonMP processor model version feature recognition performed through CPUID instruction, that provides complete information about processor-vendor, type, name, etc., capabilities. Software make this information accurately tune system maximum performance benefit users. information CPUID instruction following documents:
Processor Recognition Application Note, order# 20734 AthlonProcessor Recognition Application Note Addendum, order# 21922 Athlonand DuronProcessors BIOS, Software, Debug Developers Guide, order# 21656
Chapter
CPUID Support
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CPUID Support
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Thermal Design
thermal design power represents maximum sustained power dissipated while executing publicly available software instruction sequences under normal system operation nominal VCC_CORE. Thermal solutions must monitor processor temperature prevent processor from exceeding maximum temperature. riza frequencies. information about thermal design AthlonM considerations, Processor Thermal, Mechanical, Chassis Cooling Design Guide, order# 23794, cooling guidelines http://www.amd.com. processor provides diode that used conjunction with external temperature sensor determine temperature processor. diode anode (THERMDA) cathode (THERMDC) available pins processor. Refer "THDA THDC Pins" page more details. Table shows thermal design power specifications. Table Thermal Design Power
Nominal Voltage 1.75 1.75 Maximum Thermal Typical Thermal Power Power Temperature 46.1 54.7 41.3 49.1
Frequency (MHz) 1000 1200
Chapter
Thermal Design
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Thermal Design
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Electrical Data
Conventions
conventions used this chapter follows:
Current specified being sourced processor negative. Current specified being sunk processor positive.
Interface Signal Groupings
electrical data this chapter presented separately each signal group. Table defines each group signals contained each group.
Table
Interface Signal Groupings
Signals Notes "Absolute Ratings" page "Voltage Identification (VID[4:0])" page "VID[4:0] Pins" page "VCCA Characteristics" page 25,"VCCA Pin" page "COREFB COREFB# Pins" page "Frequency Identification (FID[3:0])" page "FID[3:0] Pins" page Table "SYSCLK SYSCLK# Characteristics," page Table "SYSCLK SYSCLK# Characteristics," page "SYSCLK SYSCLK#" page "PLL Bypass Test Pins" page "AMD AthlonSystem Characteristics" page "CLKFWDRST Pin" page
Signal Group
Power
VID[4:0], VCCA, VCC_CORE, COREFB, COREFB#
Frequency
FID[3:0]
System Clocks
SYSCLK, SYSCLK# (Tied CLKIN/CLKIN# RSTCLK/RSTCLK#), PLLBYPASSCLK#, PLLBYPASSCLK
SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, SADDOUTCLK#, AthlonSFILLVAL#, SDATAINVAL#, SDATAOUTVAL#, SDATA[63:0]#, System SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, SCHECK[7:0]#, CLKFWDRST, PROCRDY, CONNECT
Chapter
Electrical Data
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Table
Interface Signal Groupings (Continued)
Signals Notes "General Characteristics" page "INTR Pin" page "NMI Pin" page "SMI# Pin" page "INIT# Pin" page "A20M# Pin" page "FERR Pin" page "IGNNE# Pin" page "STPCLK# Pin" page "FLUSH# Pin" page "General Characteristics" page "General Characteristics" page "PLL Bypass Test Pins" page "Scan Pins" page "Analog Pin" page "General Characteristics" page "DBRDY DBREQ# Pins" page "PWROK Pin" page "APIC Pins Characteristics" page "APIC Pins, PICCLK, PICD[1:0]#" page Table "Thermal Diode Characteristics," page "THDA THDC Pins" page
Signal Group
Southbridge
RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#, STPCLK#, FLUSH#
JTAG
TMS, TCK, TRST#, TDI,
Test
PLLBYPASS#, PLLTEST#, PLLMON1, PLLMON2, SCANCLK1, SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG
Miscellaneous DBREQ#, DBRDY, PWROK
APIC
PICD[1:0]#, PICCLK
Thermal
THERMDA, THERMDC
Voltage Identification (VID[4:0])
Table shows VID[4:0] Characteristics. more information VID[4:0] Characteristics, "VID[4:0] Pins" page Table
Parameter
Note:
VID[4:0] Characteristics
Description Output Current Output High Voltage 2.625
pins must pulled above this voltage external pullup resistor.
Electrical Data
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Frequency Identification (FID[3:0])
Table shows FID[3:0] characteristics. more information, "FID[3:0] Pins" page Table
Parameter
Note:
FID[3:0] Characteristics
Description Output Current Output High Voltage 2.625V
pins must pulled above this voltage external pullup resistor.
VCCA Characteristics
Table shows characteristics VCCA. more information, "VCCA Pin" page
Table
Symbol VVCCA IVCCA
Notes:
VCCA Characteristics
Parameter VCCA Voltage VCCA Current 2.25 Nominal 2.75 Units mA/GHz Notes
Minimum Maximum voltages absolute. transients below minimum above maximum voltages permitted. .Measured
Decoupling
AthlonProcessor Based Motherboard Design Guide, order# 24363, contact your local office information about decoupling required motherboard with Athlon processor model
Chapter
Electrical Data
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VCC_CORE Characteristics
Athlon processor model designed provide functional operation voltage temperature parameters within limits defined Table which also shows characteristics VCC_CORE. Figure page graphical representation VCC_CORE waveform.
Table
VCC_CORE Characteristics
Description 1.65 1.65 Min1 1.70 1.70 Nominal1 1.75 1.75 Max1 1.80 1.80 1.90 1.90 Units
Parameter
VCC_CORE@ 1.75 Processor core supply VCC_CORESLEEP2 tMAX_AC3 tMIN_AC3 TDIE
Notes:
Processor core supply sleep state Positive excursion time transients Negative excursion time transients Temperature processor
voltage measurements taken differentially COREFB/COREFB# pins. Sleep voltage used sleep state. Excursion time defined length time signal exceeds threshold level.
Electrical Data
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Figure shows processor core voltage (VCC_CORE) waveform response perturbation. tMIN_AC (negative transient excursion time) tMAX_AC (positive transient excursion time) represent maximum allowable time below above tolerance thresholds.
tmax_AC VCC_CORE_MAX_AC
VCC_CORE_MAX_DC
VCC_CORE_NOM
VCC_CORE_MIN_DC
VCC_CORE_MIN_AC tmin_AC
ICORE_MAX ICORE_MIN
Figure VCC_CORE Voltage Waveform
Chapter
Electrical Data
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Absolute Ratings
Athlon processor model should subjected conditions exceeding absolute ratings, such conditions adversely affect long-term reliability result functional damage. Table lists maximum absolute ratings operation Athlon processor.
Table
VCC_CORE VCCA VPIN TSTORAGE
Absolute Ratings
Description AthlonMP Processor Model core supply Athlon processor model supply Voltage signal Storage temperature processor -0.5 -0.5 -0.5 VCC_CORE VCCA VCC_CORE
Parameter
VCC_CORE Voltage Current
Table shows power current Athlon processor model during normal reduced power states.
Table
VCC_CORE Voltage Current
Nominal Voltage 1.75 1.75 Stop Grant (Maximum) Maximum (Power Supply Current)1 26.3 31.3 Temperature 95°C 95°C
Frequency (MHz) 1000 1200
Notes:
Measured Nominal voltage 1.75
Electrical Data
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7.10
SYSCLK SYSCLK# Characteristics
Table shows characteristics SYSCLK SYSCLK# differential clocks. SYSCLK signal represents CLKIN RSTCLK tied together while SYSCLK# signal represents CLKIN# RSTCLK# tied together.
Table
Symbol
SYSCLK SYSCLK# Characteristics
Description VCC_CORE/2 ±100 Units
VThreshold-DC Crossing before transition detected (DC) VThreshold-AC Crossing before transition detected (AC) ILEAK_P ILEAK_N VCROSS CPIN Leakage current through P-channel pullup VCC_CORE Leakage current through N-channel pulldown (Ground) Differential signal crossover Capacitance
Figure shows characteristics SYSCLK SYSCLK# signals.
VCROSS
VThreshold-DC 400mV
VThreshold-AC 450mV
Figure SYSCLK SYSCLK# Differential Clock Signals
Chapter
Electrical Data
Preliminary Information AthlonMP Processor Model Multiprocessor Platforms
24685B-June 2001
Table shows SYSCLK/SYSCLK# differential clock characteristics Athlon processor model Table SYSCLK SYSCLK# Characteristics
Symbol Parameter Description Clock Frequency Duty Cycle
Notes:
1.05 1.05
Units
Notes
Period High Time Time Fall Time Rise Time Period Stability
Circuitry driving Athlon system clock inputs must exhibit suitably closed-loop jitter bandwidth allow track jitter. -20dB attenuation point, measured into 20-pF load must less than kHz. Circuitry driving Athlon system clock inputs purposely alter Athlon system clock period (spread spectrum clock generators). cases Athlon system period violate minimum specification above. Athlon system clock inputs vary from 100% specified period specified period maximum rate kHz. Minimum Clock Frequency
Figure shows sample waveform SYSCLK signal.
VCROSS
VThreshold-AC
Figure SYSCLK Waveform
Electrical Data
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AthlonMP Processor Model Multiprocessor Platforms
7.11
AthlonSystem Characteristics
Table shows characteristics Athlon system used Athlon processor model Table "VCC_CORE Characteristics," page information VCC_CORE. information about SYSCLK SYSCLK#, "SYSCLK SYSCLK#" page Table "Pin Name Abbreviations," page
Table AthlonSystem Characteristics
Symbol VREF Parameter Input Reference Voltage VREF Nominal VREF Nominal VREF -500 IOUT -200 IOUT (Ground) VCC_CORE Nominal 0.85 VCC_CORE -500 Condition Units Notes (0.5*VCC_CORE) (0.5*VCC_CORE) -100 +100 VCC_CORE VREF VCC_CORE+500
IVREF_LEAK_P VREF Tristate Leakage Pullup IVREF_LEAK_N VREF Tristate Leakage Pulldown ILEAK_P ILEAK_N
Notes:
Input High Voltage Input Voltage Output High Voltage Output Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Input Capacitance
VREF nominally VCC_CORE with actual values that specific motherboard design implementation. VREF must created with sufficiently accurate source sufficiently quiet response adhere specification listed above. Specified following processor inputs have twice listed capacitance because they connect input pads-SYSCLK, SYSCLK#. SYSCLK connects CLKIN/RSTCLK. SYSCLK# connects CLKIN#/RSTCLK#.
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Electrical Data
Preliminary Information AthlonMP Processor Model Multiprocessor Platforms
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characteristics Athlon system shown Table page parameters grouped based source destination signals involved. Table AthlonSystem Characteristics
Group Signals TRISE TFALL TSKEW-SAMEEDGE TSKEW-DIFFEDGE Forward Clocks COUT TVAL Sync
Notes:
Symbol
Parameter Output Rise Slew Rate Output Fall Slew Rate Output skew with respect same clock edge Output skew with respect different clock edge Input Data Setup Time Input Data Hold Time Capacitance input Clocks Capacitance output Clocks RSTCLK Output Valid Setup RSTCLK Hold from RSTCLK
1000
Units V/ns V/ns
Notes
2000
Rise fall time ranges guidelines over which been characterized. TSKEW-SAMEEDGE maximum skew within clock forwarded group between signals between signal forward clock, measured package, with respect same clock edge. TSKEW-DIFFEDGE maximum skew within clock forwarded group between signals between signal forward clock, measured package, with respect different clock edges. Input times with respect appropriate Clock Forward Group input clock. synchronous signals include PROCRDY, CONNECT, CLKFWDRST. RSTCLK rising edge output valid PROCRDY. Test Load setup CONNECT/CLKFWDRST rising edge RSTCLK. hold CONNECT/CLKFWDRST from rising edge RSTCLK.
Electrical Data
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7.12
General Characteristics
Table shows Athlon processor model characteristics Southbridge, JTAG, test, miscellaneous pins.
Table General Characteristics
Symbol ILEAK_P ILEAK_N TDELAY TBIT TRPT
Notes:
Parameter Description Input High Voltage Input Voltage Output High Voltage Output Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Output High Current Output Current Sync Input Setup Time Sync Input Hold Time Output Delay with respect RSTCLK Input Time Acquire Input Time Reacquire
Condition
(VCC_CORE/2) -300 VCC_CORE -300
VCC_CORE VCC_CORE
Units
Notes
(Ground) VCC_CORE Nominal
20.0 40.0
9-13
Characterized across supply voltage range. Values specified nominal VCC_CORE. Scale parameters between VCC_CORE minimum VCC_CORE maximum. measured min, respectively. Synchronous inputs/outputs specified with respect RSTCLK RSTCK# pins. These aggregate numbers. Edge rates indicate range over which inputs were characterized. asynchronous operation, signal must persist this time guarantee capture. This value assumes RSTCLK frequency TBIT 2*fRST. approximate value standard case normal mode operation. This value dependent RSTCLK frequency, divisors, Power mode, core frequency. Reassertions signal within this time guaranteed seen core. This value assumes that skew between RSTCLK K7CLKOUT much less than phase. This value assumes RSTCLK K7CLKOUT running same frequency, though processor capable other configurations.
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Electrical Data
Preliminary Information AthlonMP Processor Model Multiprocessor Platforms
24685B-June 2001
Table General Characteristics (Continued)
Symbol TRISE TFALL CPIN
Notes:
Parameter Description Signal Rise Time Signal Fall Time Capacitance
Condition
Units V/ns V/ns
Notes
Characterized across supply voltage range. Values specified nominal VCC_CORE. Scale parameters between VCC_CORE minimum VCC_CORE maximum. measured min, respectively. Synchronous inputs/outputs specified with respect RSTCLK RSTCK# pins. These aggregate numbers. Edge rates indicate range over which inputs were characterized. asynchronous operation, signal must persist this time guarantee capture. This value assumes RSTCLK frequency TBIT 2*fRST. approximate value standard case normal mode operation. This value dependent RSTCLK frequency, divisors, Power mode, core frequency. Reassertions signal within this time guaranteed seen core. This value assumes that skew between RSTCLK K7CLKOUT much less than phase. This value assumes RSTCLK K7CLKOUT running same frequency, though processor capable other configurations.
Electrical Data
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7.13
Thermal Diode Characteristics
Table shows Athlon processor model characteristics on-board thermal diode Table Thermal Diode Characteristics
Symbol
Notes:
Parameter Description Forward bias current Diode ideality factor
1.002
1.008
1.016
Units
Notes
sourcing current should always used forward bias only. Characterized 95°C with forward bias current pair 100% tested. Specified design limited characterization. diode ideality factor, correction factor ideal diode equation. following equations, following variables constants: diode ideality factor Boltzmann constant electron charge constant diode temperature (Kelvin) Voltage from base emitter Collector current Saturation current Ratio collector currents equation
sourcing currents using above equation, difference base emitter voltage found which leads following equation temperature:
different sourcing current pair used other than following equation should used correct temperature. Subtract this offset from temperature measured temperature sensor. following equations, following variables constants: Ihigh High sourcing current Ilow sourcing current Toffset found using following equation:
high offset 2.34 high
Chapter
Electrical Data
Preliminary Information AthlonMP Processor Model Multiprocessor Platforms
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7.14
APIC Pins Characteristics
Table shows Athlon processor model characteristics APIC pins.
Table APIC Pins Characteristics
Symbol ILEAK_P ILEAK_N TRISE TFALL CPIN
Notes:
Parameter Description Input High Voltage Input Voltage Output High Voltage Output Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Output Current Signal Rise Time Signal Fall Time Capacitance
Condition
-300
2.625 2.625
Units
Notes
-300 (Ground)
V/ns V/ns
Characterized across supply voltage range Values specified nominal (1.5 Scale parameters with 2.625 maximum Edge rates indicate range over which inputs were characterized
Electrical Data
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Signal Power-Up Requirements
This chapter describes AthlonMP processor model power-up requirements during system power-up warm resets.
Power-Up Requirements
Figure shows relationship between signals system during power-up sequence. This figure details requirements processor.
Signal Sequence Timing Description
Supply VCCA (2.5 (for PLL) VCC_CORE (Processor Core) RESET# NB_RESET#
PWROK
System Clock
Figure Signal Relationship Requirements During Power-Up Sequence Notes:1. Figure represents several signals generically using names necessarily consistent with lists schematics. Requirements Figure described "Power-Up Requirements" page
Chapter
Signal Power-Up Requirements
Preliminary Information AthlonMP Processor Model Multiprocessor Platforms
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Power-Up Timing Requirements. signal timing requirements follows: RESET# must asserted before PWROK asserted Athlon processor model does correct clock multiplier PWROK asserted prior RESET# assertion. recommended that RESET# asserted least nanoseconds prior assertion PWROK. practice, Southbridges assert RESET# milliseconds before PWROK deasserted. motherboard voltage planes must specification before PWROK asserted. within
PWROK output voltage regulation circuit motherboard. PWROK indicates that VCC_CORE other voltage planes system within specification. motherboard required delay PWROK assertion minimum three milliseconds from supply being within specification. This ensures that system clock (SYSCLK/SYSCLK#) operating within specification when PWROK asserted. processor core voltage, VCC_CORE, must within specification dictated VID[4:0] pins driven processor before PWROK asserted. Before PWROK assertion, Athlon processor clocked ring oscillator. Athlon processor powered VCCA. processor does lock VCCA high enough processor logic switch some period before PWROK asserted. VCCA must within specification least five microseconds before PWROK asserted. practice VCCA, VCC_CORE, other voltage planes must within specification several milliseconds before PWROK asserted.
Signal Power-Up Requirements
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After PWROK asserted, processor locks operational frequency. system clock (SYSCLK/SYSCLK#) must running within specification before PWROK asserted. When PWROK asserted, processor switches from driving internal processor clock grid from ring oscillator driving from PLL. reference system clock should valid this time. system clocks guaranteed running after been within specification three milliseconds. PWROK assertion deassertion RESET#. duration RESET# assertion during cold boots intended satisfy time takes lock with less than 1-ns phase error. processor begins after PWROK asserted internal clock grid switched from ring oscillator PLL. lock time take from hundreds nanoseconds tens microseconds. recommended that minimum time between PWROK assertion deassertion RESET# least milliseconds. Southbridge enforces delay milliseconds between PWRGD (Southbridge version PWROK) assertion NB_RESET# deassertion. PWROK must monotonic. processor should switch between ring oscillator after initial assertion PWROK. NB_RESET# must asserted (causing CONNECT also assert) before RESET# deasserted. practice Southbridges enforce this requirement. NB_RESET# does assert until after RESET# deasserted, processor misinterprets CONNECT assertion (due NB_RESET# being asserted) beginning transfer (See "Serial Initialization Packet (SIP) Protocol" page 40). There must sufficient overlap resets ensure that CONNECT sampled asserted processor before RESET# deasserted. Clock Multiplier Selection (FID[3:0]) When RESET# deasserted, Northbridge samples FID[3:0] frequency from processor chipset-specific manner. more information, "FID[3:0] Pins" page Signal Power-Up Requirements
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Preliminary Information AthlonMP Processor Model Multiprocessor Platforms
24685B-June 2001
orthbridge uses this informat other information sampled deassertion RESET# determine correct Serial Initialization Packet (SIP) send processor configuration Athlon system clock multiplier processor frequency indicated FID[3:0] code. sent processor using protocol. This protocol uses PROCRDY, CONNECT, CLKFWDRST signals, which synchronous SYSCLK. Serial Initialization Packet (SIP) Protocol. Refer Athlonand DuronSystem Specification, order# 21902 details protocol.
Processor Warm Reset Requirements
RESET cannot asserted processor without also being asserted Northbridge. RESET# Northbridge same RESET#. minimum assertion RESET# millisecond. Southbridge enforces minimum assertion RESET# processor, Northbridge, milliseconds.
Northbridge Reset Pins
Signal Power-Up Requirements
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Mechanical Data
Introduction
AthlonMP processor model connects motherboard through socket named Socket more information, AthlonProcessor Based Motherboard Design Guide, order# 24363.
Loading
processor exposed package. This feature facilitates heat transfer from heat sink. critical that mechanical loading heat sink does exceed limits shown Table heat sink design should avoid loads corners edges die. CPGA package compliant pads that serve bring surfaces planar contact. Table CPGA Mechanical Loading
Location Surface Edge
Notes:
Dynamic (MAX)
Static (MAX)
Units
Note
Tool-assisted zero insertion force sockets should designed such that load placed ceramic substrate package. Load specified coplanar contact surface. Load defined surface more than degree angle inclination surface.
Package Description
Figure page shows mechanical drawing CPGA processor package. relevant dimensions locations processor shown reference purposes.
Chapter
Mechanical Data
Preliminary Information AthlonMP Processor Model Multiprocessor Platforms
24685B-June 2001
Figure AthlonMP Processor Model Package View
Mechanical Data
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10.1
Descriptions
Diagram Name Abbreviations
Figure page shows staggered Ceramic Grid Array (CPGA) AthlonMP Processor Model Because some names long grid, they abbreviated. Figure page show bottomside view array. Table page lists pins alphabetical order name, along with abbreviation where necessary.
Chapter
Descriptions
Descriptions Chapter
AthlonMP Processor Model Multiprocessor Platforms
SAO#12 SAO#7 SAO#11 SAO#10 SAO#0 VID[0] PICCLK SCNCK1 FID[0] FID[2] DBRDY STPC# A20M# FERR IGNNE# INTR
SAO#5 SAO#8 SAO#4 SAO#13 VID[2] PICD#1 SCNSN SCNCK2 VREF_S CPR# SMI#
SAO#3 SAO#2 SAO#6 VID[4] VID[3] THDA THDC
SD#55 SD#54 SD#52
SD#61 SDOC#3 SD#50
SD#53 SCK#6 SD#49
SD#63 SD#51 SDIC#3
SD#62 SD#60 SD#48
SCK#7 SD#59 SD#58
SD#57 SD#56 SD#36
SD#39 SD#37 SD#46
SD#35 SD#47 SCK#4
SD#34 SD#38 SDIC#2
SD#44 SD#45 SD#33
SCK#5 SD#43 SD#32
SDOC#2 SD#42 SCK#3 SD#20 SD#19 SD#26 SD#25 SD#24 SD#7 SD#5 SDIC#0 SCK#1 SD#8 SD#10 SAI#5 SAI#2 SAIC# SAI#8 SDINV#
SD#40 SD#41 SD#31 SD#23 SDIC#1 SCK#2 SD#27 SD#17 SD#15 SD#4 SD#2 SD#3 SD#0 SD#14 SDOC#0 SAI#11 SAI#6 SAI#4 SAI#13
SD#30
SAO#9
SDOC#1
SAOC#
SD#22
SAO#14
SD#21
SAO#1
SD#29
VID[1]
SD#28
PICD#0
SD#18
SD#16
SCNINV
TRST#
FID[1]
AthlonMP Processor Model Topside View
SD#6
SCK#0
SD#1
FID[3]
SD#12
DBREQ#
SD#13
PLTST#
SD#11
PWROK
SD#9
COREFB PLMN2
COREFB# ANLOG PLBYC# PLMN1
CLKIN# PLBYC
RCLK# CLKIN
K7CO RCLK
CLKFR CNNCT K7CO#
VCCA PRCRDY
PLBYP#
SAI#1
SAI#0 SDOV# SAI#12
RESET#
SAI#7
INIT#
SFILLV#
SAI#3
24685B-June 2001
FLUSH#
SAI#10
SAI#14
SAI#9
Figure AthlonMP Processor Model Diagram-Topside View
AthlonMP Processor Model Multiprocessor Platforms
SAO#7 SAO#12 SAO#5 SAO#3 SD#55 SD#61 SD#53 SD#63 SD#62 SCK#7 SD#57 SD#39 SD#35 SD#34 SD#44 SCK#5 SDOC#2 SD#40 SD#30
SAO#11 SAOC# SAO#4 SAO#6 SD#52 SD#50 SD#49 SDIC#3 SD#48 SD#58 SD#36 SD#46 SCK#4 SDIC#2 SD#33 SD#32 SCK#3 SD#31 SD#22
SAO#10 SAO#14 SAO#13 SD#20 SD#23 SD#21
SAO#0 SAO#1 VID[4]
VID[0] VID[1] VID[2] VID[3]
PICCLK PICD#0 PICD#1
SCNSN
SCNCK1 SCNINV SCNCK2 THDA
TRST# THDC
FID[0] FID[1] VREF_S
FID[2] FID[3]
DBRDY DBREQ#
STPC# PLTST#
A20M# PWROK
FERR RESET# COREFB COREFB#
IGNNE# INIT# CPR# ANLOG CLKFR VCCA PLBYP# SAI#0 SFILLV# SAIC# SAI#6 SAI#3
INTR FLUSH# PLMN2 PLBYC# CLKIN# RCLK# K7CO CNNCT SAI#1 SDOV# SAI#8 SAI#4 SAI#10
SAO#9
SAO#8
SMI#
SAO#2
SD#54
SDOC#3
SCK#6
PLMN1
SD#51
PLBYC
Descriptions Chapter
SD#60
CLKIN
SD#59
SD#56
AthlonMP Processor Model Bottomside View
RCLK
K7CO#
SD#37
PRCRDY
SD#47
SD#38
SD#45
SAI#12
SD#19 SDIC#1 SD#29
SD#26 SCK#2 SD#28
SD#25 SD#27 SD#18
SD#24 SD#17 SD#16
SD#7 SD#15 SD#6
SD#5 SD#4 SCK#0
SDIC#0 SD#2 SD#1
SCK#1 SD#3 SD#12
SD#8 SD#0 SD#13
SD#10 SD#14 SD#11
SAI#5 SDOC#0 SD#9
SD#43
SAI#14
SD#42
SAI#2
SDINV#
24685B-June 2001
SD#41
SAI#11
SAI#13
SDOC#1
SAI#7
SAI#9
Figure AthlonMP Processor Model Diagram-Bottomside View
24685B-June 2001
AthlonMP Processor Model Multiprocessor Platforms
Table Name Abbreviations
Abbreviation Full Name A20M# ANALOG CLKFWDRST CLKIN CLKIN# CONNECT COREFB COREFB# CPU_PRESENCE# DBRDY DBREQ# FERR FID[0] FID[1] FID[2] FID[3] FLUSH# IGNNE# INIT# INTR K7CLKOUT K7CLKOUT# AJ13 AJ21 AN17 AL17 AL23 AG11 AG13 AL21 AN21 AG15 AG17 AG27 AG29
Table Name Abbreviations (Continued)
Abbreviation Full Name AA31 AC31 AD30 AE31 AF10
ANLOG CLKFR
CNNCT
CPR#
K7CO K7CO#
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24685B-June 2001
Table Name Abbreviations (Continued)
Abbreviation Full Name PICCLK PICD[0]# PICD[1]# PLLBYPASS# PLLBYPASSCLK PLLBYPASSCLK# PLLMON1 PLLMON2 AF28 AF30 AF32 AG19 AG21 AG23 AG25 AG31 AH30 AJ11 AJ15 AJ17 AJ19 AJ27 AL11 AL25 AL27 AN11 AN25 AN27 AJ25 AN15 AL15 AN13 AL13
Table Name Abbreviations (Continued)
Abbreviation PLTST# PRCRDY Full Name PLLTEST# PROCREADY PWROK RESET# RSTCLK RSTCLK# SADDIN[0]# SADDIN[1]# SADDIN[2]# SADDIN[3]# SADDIN[4]# SADDIN[5]# SADDIN[6]# SADDIN[7]# SADDIN[8]# SADDIN[9]# SADDIN[10]# SADDIN[11]# SADDIN[12]# SADDIN[13]# SADDIN[14]# SADDINCLK# SADDOUT[0]# SADDOUT[1]# SADDOUT[2]# SADDOUT[3]# SADDOUT[4]# SADDOUT[5]# SADDOUT[6]# SADDOUT[7]# SADDOUT[8]# SADDOUT[9]# SADDOUT[10]# SADDOUT[11]# SADDOUT[12]# SADDOUT[13]# SADDOUT[14]# SADDOUTCLK# SCANCLK1 AN23 AN19 AL19 AJ29 AL29 AG33 AJ37 AL35 AE33 AJ35 AG37 AL33 AN37 AL37 AG35 AN29 AN35 AN31 AJ33
PICD#0 PICD#1 PLBYP# PLBYC PLBYC# PLMN1 PLMN2
RCLK RCLK# SAI#0 SAI#1 SAI#2 SAI#3 SAI#4 SAI#5 SAI#6 SAI#7 SAI#8 SAI#9 SAI#10 SAI#11 SAI#12 SAI#13 SAI#14 SAIC# SAO#0 SAO#1 SAO#2 SAO#3 SAO#4 SAO#5 SAO#6 SAO#7 SAO#8 SAO#9 SAO#10 SAO#11 SAO#12 SAO#13 SAO#14 SAOC# SCNCK1
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Table Name Abbreviations (Continued)
Abbreviation SCNCK2 SCNINV SCNSN SCK#0 SCK#1 SCK#2 SCK#3 SCK#4 SCK#5 SCK#6 SCK#7 SD#0 SD#1 SD#2 SD#3 SD#4 SD#5 SD#6 SD#7 SD#8 SD#9 SD#10 SD#11 SD#12 SD#13 SD#14 SD#15 SD#16 SD#17 SD#18 SD#19 SD#20 SD#21 SD#22 SD#23 SD#24 SD#25 SD#26 SD#27 Full Name SCANCLK2 SCANINTEVAL SCANSHIFTEN SCHECK[0]# SCHECK[1]# SCHECK[2]# SCHECK[3]# SCHECK[4]# SCHECK[5]# SCHECK[6]# SCHECK[7]# SDATA[0]# SDATA[1]# SDATA[2]# SDATA[3]# SDATA[4]# SDATA[5]# SDATA[6]# SDATA[7]# SDATA[8]# SDATA[9]# SDATA[10]# SDATA[11]# SDATA[12]# SDATA[13]# SDATA[14]# SDATA[15]# SDATA[16]# SDATA[17]# SDATA[18]# SDATA[19]# SDATA[20]# SDATA[21]# SDATA[22]# SDATA[23]# SDATA[24]# SDATA[25]# SDATA[26]# SDATA[27]# AA35 AA33 AE37 AC33 AC37 AA37 AC35
Table Name Abbreviations (Continued)
Abbreviation SD#28 SD#29 SD#30 SD#31 SD#32 SD#33 SD#34 SD#35 SD#36 SD#37 SD#38 SD#39 SD#40 SD#41 SD#42 SD#43 SD#44 SD#45 SD#46 SD#47 SD#48 SD#49 SD#50 SD#51 SD#52 SD#53 SD#54 SD#55 SD#56 SD#57 SD#58 SD#59 SD#60 SD#61 SD#62 SD#63 SDIC#0 SDIC#1 SDIC#2 Full Name SDATA[28]# SDATA[29]# SDATA[30]# SDATA[31]# SDATA[32]# SDATA[33]# SDATA[34]# SDATA[35]# SDATA[36]# SDATA[37]# SDATA[38]# SDATA[39]# SDATA[40]# SDATA[41]# SDATA[42]# SDATA[43]# SDATA[44]# SDATA[45]# SDATA[46]# SDATA[47]# SDATA[48]# SDATA[49]# SDATA[50]# SDATA[51]# SDATA[52]# SDATA[53]# SDATA[54]# SDATA[55]# SDATA[56]# SDATA[57]# SDATA[58]# SDATA[59]# SDATA[60]# SDATA[61]# SDATA[62]# SDATA[63]# SDATAINCLK[0]# SDATAINCLK[1]# SDATAINCLK[2]#
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Table Name Abbreviations (Continued)
Abbreviation SDIC#3 SDINV# SDOC#0 SDOC#1 SDOC#2 SDOC#3 SDOV# SFILLV# STPC# Full Name SDATAINCLK[3]# SDATAINVALID# SDATAOUTCLK[0]# SDATAOUTCLK[1]# SDATAOUTCLK[2]# SDATAOUTCLK[3]# SDATAOUTVALID# SFILLVALID# SMI# STPCLK# THERMDA THERMDC TRST# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE AN33 AE35 AL31 AJ31
Table Name Abbreviations (Continued)
Abbreviation Full Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE
THDA THDC
Descriptions
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Table Name Abbreviations (Continued)
Abbreviation Full Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE AB30 AB32 AB34 AB36 AF14 AF18 AF22 AF26 AF34 AF36 AH10 AH14 AH18 AH22 AH26 AK10 AK14 AK18 AK22 AK26 AK30 AK34 AK36 AM10 AM14 AM18 AM22 AM26 AM22
Table Name Abbreviations (Continued)
Abbreviation Full Name VCC_CORE VCC_CORE VCC_CORE VCCA VID[0] VID[1] VID[2] VID[3] VID[4] VREF_SYS AM26 AM30 AM34 AJ23
VREF_S
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Table Name Abbreviations (Continued)
Abbreviation Full Name AD32
Table Name Abbreviations (Continued)
Abbreviation Full Name AD34 AD36 AF12 AF16 AH12 AH16 AH20 AH24 AH28 AH32 AH34 AH36 AK12 AK16 AK20 AK24 AK28 AK32 AM12 AM16 AM20 AM24 AM28 AM32 AM36
Descriptions
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Preliminary Information AthlonMP Processor Model Multiprocessor Platforms
24685B-June 2001
10.2
List
Table cross-references Socket location signal name. (Level) column shows electrical specification this pin. indicates push-pull mode driven single source. indicates open-drain mode that allows devices share pin. Note: Socket Athlon processor supports push-pull drivers. more information, "Push-Pull (PP) Drivers" page (Port) column indicates this signal input (I), output (O), bidirectional signal. (Reference) column indicates this signal should referenced VCC_CORE planes purpose signal routing with respect current return paths. Table Cross-Reference Location
VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Name SDATA[30]# Description
Table Cross-Reference Location
SADDOUT[12]# SADDOUT[5]# SADDOUT[3]# SDATA[55]# SDATA[61]# SDATA[53]# SDATA[63]# SDATA[62]# SCHECK[7]# SDATA[57]# SDATA[39]# SDATA[35]# SDATA[34]# SDATA[44]# SCHECK[5]# SDATAOUTCLK[2]# SDATA[40]# page page Name Description page
Descriptions
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Table Cross-Reference Location (continued) Table Cross-Reference Location
Name VCC_CORE SADDOUT[7]# SADDOUT[9]# SADDOUT[8]# SADDOUT[2]# SDATA[54]# SDATAOUTCLK[3]# SCHECK[6]# SDATA[51]# SDATA[60]# SDATA[59]# SDATA[56]# SDATA[37]# SDATA[47]# SDATA[38]# SDATA[45]# SDATA[43]# SDATA[42]# SDATA[41]# SDATAOUTCLK[1]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE page Description VCC_CORE SADDOUT[11]# SADDOUTCLK# SADDOUT[4]# SADDOUT[6]# SDATA[52]# SDATA[50]# SDATA[49]# SDATAINCLK[3]# SDATA[48]# SDATA[58]# SDATA[36]# SDATA[46]# SCHECK[4]# SDATAINCLK[2]# SDATA[33]# SDATA[32]# SCHECK[3]# SDATA[31]# SDATA[22]# VCC_CORE VCC_CORE VCC_CORE page page page Name Description
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Table Cross-Reference Location (continued) Table Cross-Reference Location
VCC_CORE VCC_CORE VCC_CORE VCC_CORE SADDOUT[10]# SADDOUT[14]# SADDOUT[13]# SDATA[20]# SDATA[23]# SDATA[21]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE page page page page page page page page page page page page page page page page page Name VCC_CORE Description VCC_CORE VCC_CORE SADDOUT[0]# SADDOUT[1]# VID[4] SDATA[19]# SDATAINCLK[1]# SDATA[29]# VCC_CORE VCC_CORE VCC_CORE VID[0] VID[1] VID[2] VID[3] SDATA[26]# SCHECK[2]# SDATA[28]# page page page page page page page page page page page page page page page page Name Description
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Table Cross-Reference Location (continued) Table Cross-Reference Location
Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE PICCLK PICD#[0] PICD#[1] SDATA[25]# SDATA[27]# SDATA[18]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE SCANSHIFTEN SDATA[24]# SDATA[17]# SDATA[16]# VCC_CORE VCC_CORE page page page page page page page page page page Description Name VCC_CORE VCC_CORE SCANCLK1 SCANINTEVAL SCANCLK2 THERMDA SDATA[7]# SDATA[15]# SDATA[6]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE TRST# THERMDC SDATA[5]# SDATA[4]# SCHECK[0]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE page page page page page page page page page page page Description
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Table Cross-Reference Location (continued) Table Cross-Reference Location
FID[0] FID[1] VREFSYS SDATAINCLK[0]# SDATA[2]# SDATA[1]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE FID[2] FID[3] SCHECK[1]# SDATA[3]# SDATA[12]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE page page page page page page page page page page page Name Description AA31 AA33 AA35 AA37 AB30 AB32 AB34 AB36 AC31 AC33 AC35 AC37 AD30 AD32 AD34 AD36 DBRDY DBREQ# SDATA[8]# SDATA[0]# SDATA[13]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE STPCLK# PLLTEST# SDATA[10]# SDATA[14]# SDATA[11]# VCC_CORE VCC_CORE VCC_CORE page page page page page page page page page page Name Description
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Table Cross-Reference Location (continued) Table Cross-Reference Location
AE31 AE33 AE35 AE37 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AF30 AF32 AF34 AF36 AG11 AG13 AG15 Name A20M# PWROK SADDIN[5]# SDATAOUTCLK[0]# SDATA[9]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE FERR RESET# COREFB COREFB# page page page page page page page page page page page page page page page Description AG17 AG19 AG21 AG23 AG25 AG27 AG29 AG31 AG33 AG35 AG37 AH10 AH12 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AH32 AH34 AH36 SADDIN[2]# SADDIN[11]# SADDIN[7]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE IGNNE# INIT# VCC_CORE page page page page page page page Name Description page page page page page page page page
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Table Cross-Reference Location (continued) Table Cross-Reference Location
AJ11 AJ13 AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AJ33 AJ35 AJ37 AK10 AK12 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK30 AK32 AK34 AK36 Analog CLKFWDRST VCCA PLLBYPASS# SADDIN[0]# SFILLVALID# SADDINCLK# SADDIN[6]# SADDIN[3]# CPU_PRESENCE# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE INTR FLUSH# page page page page Name Description page page page page page page page page page page AL11 AL13 AL15 AL17 AL19 AL21 AL23 AL25 AL27 AL29 AL31 AL33 AL35 AL37 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AM32 AM34 PLLMON2 PLLBYPASSCLK# CLKIN# RSTCLK# K7CLKOUT CONNECT SADDIN[1]# SDATAOUTVALID# SADDIN[8]# SADDIN[4]# SADDIN[10]# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE page Name VCC_CORE page page page page page page page page page page page page Description
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Table Cross-Reference Location (continued)
AM36 AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25 AN27 AN29 AN31 AN33 AN35 AN37 SMI# PLLMON1 PLLBYPASSCLK CLKIN RSTCLK K7CLKOUT# PROCRDY SADDIN[12]# SADDIN[14]# SDATAINVALID# SADDIN[13]# SADDIN[9]# page page page page page page page page page page page Name Description
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10.3
Detailed Descriptions
information this section pertains Table page
A20M#
A20M# input from system used simulate address wrap-around 20-bit 8086. Socket processors implement location AH6. Socket designs must have plate cover that blocks this location. When cover plate blocks this location, non-AMD part (e.g., PGA370) does into socket. However, socket manufacturers allowed have contact loaded position. Therefore, motherboard socket design should account possibility that contact could loaded this position. Athlonand DuronSystem Specification, order# 21902 information about system pins PROCRDY, PWROK, RESET#, SADDIN[14:2]#, SADDINCLK#, SADDOUT[14:2]#, SADDOUTCLK#, DATA DATA SDATAINVALID#, SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#. Treat this Advanced Programmable Interrupt Controller (APIC) feature that provides flexible expandable means delivering interrupts system using processor. pins, PICD[1:0], bi-directional message-passing signals used APIC driven Southbridge, dedicated APIC, another multiprocessing-enabled Athlon processor model pin, PICCLK, must driven with valid clock input. more information, Table "APIC Pins Characteristics," page
AthlonSystem Pins
Analog APIC Pins, PICCLK, PICD[1:0]#
CLKFWDRST CLKIN, RSTCLK (SYSCLK) Pins
CLKFWDRST resets clock-forward circuitry both system processor. Connect CLKIN (AN17) with RSTCLK (AN19) name SYSCLK. Connect CLKIN# (AL17) with RSTCLK# (AL19) name SYSCLK#. Length match clocks from clock generator Northbridge processor. Descriptions Chapter
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"SYSCLK SYSCLK#" page more information. CONNECT COREFB COREFB# Pins CPU_PRESENCE# CONNECT input from system used power management clock-forward initialization reset. COREFB COREFB# outputs system that provide processor core voltage feedback system. CPU_PRESENCE# connected processor package. pulled-up motherboard, CPU_PRESENCE# used detect presence absence processor Socket A-style socket. DBRDY (AA1) DBREQ# (AA3) routed debug connector. DBREQ# tied VCC_CORE with pullup resistor. FERR output system that asserted unmasked numerical exception independent CR0. FERR push-pull active High signal that must inverted level shifted active signal. more information about FERR FERR#, "Required Circuits" chapter Socket Motherboard Design Guide, order# 24363. FID[3] (Y3), FID[2] (Y1), FID[1] (W3), FID[0] (W1) 4-bit processor clock-to-SYSCLK ratio. Table page describes encodings clock multipliers FID[3:0].
DBRDY DBREQ# Pins FERR
FID[3:0] Pins
Table FID[3:0] Clock Multiplier Encodings
FID[3] FID[2] FID[1] FID[0] Processor Clock SYSCLK Frequency Ratio 11.5 12.5*
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Table FID[3:0] Clock Multiplier Encodings (Continued)
FID[3]
Note:
FID[2]
FID[1]
FID[0]
Processor Clock SYSCLK Frequency Ratio 10.5
*All ratios greater than equal 12.5x have same FID[3:0] code 0011, which causes configuration ratios 12.5x greater same.
FID[3:0] signals open drain processor outputs that Northbridge deassertion RESET# determine (serialization initialization packet) that gets sent processor. Athlonand DuronSystem Specification, order#21902 more information about protocol. processor FID[3:0] outputs open drain 2.5V tolerant. prevent damage processor, these signals pulled High above they must electrically isolated from processor. information about FID[3:0] isolation circuit, AthlonProcessor Based Motherboard Design Guide, order# 24363. "Frequency Identification (FID[3:0])" page characteristics FID[3:0]. FLUSH# FLUSH# must tied VCC_CORE with pullup resistor. debug connector implemented, FLUSH# routed debug connector.
IGNNE#
IGNNE# input from system that tells processor ignore numeric errors.
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INIT#
INIT# input from system that resets integer registers without affecting floating-point registers internal caches. Execution starts 0FFFF FFF0h. INTR input from system that causes processor start interrupt acknowledge transaction that fetches 8-bit interrupt vector starts execution that location. (Q1), (Q3), (U1), TRST# (U3), (U5) JTAG interface. Connect these pins directly motherboard debug connector. Pullup TDI, TCK, TMS, TRST# VCC_CORE with pullup resistors. K7CLKOUT (AL21) K7CLKOUT# (AN21) each inches then terminated with resistor pair, ohms VCC_CORE ohms VSS. effective termination resistance voltage ohms VCC_CORE/2. These locations processor type keying forwards backwards compatibility (G7, G15, G17, G23, G25, AA7, AG7, AG9, AG15, AG17, AG27, AG29). Motherboard designers should treat pins like connect) pins. socket designer option creating mold piece that allows pins only where designated. However, sockets that populate pins must allowed, motherboard must always provide pins locations. motherboard should provide plated hole pin. hole should electrically connected anything. input from system that causes non-maskable interrupt. present locations AN1. Motherboard designers should allow socket these locations. more information, Socket Motherboard Design Guide Desktop Mobile Systems, order# 24363.
INTR
JTAG Pins
K7CLKOUT K7CLKOUT# Pins
Pins
Pins Orientation Pins
Bypass Test Pins
PLLTEST# (AC3), PLLBYPASS# (AJ25), PLLMON1 (AN13), PLLBYPASSCLK# (AL15) bypass test interface. This interface tied disabled motherboard. Descriptions
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Preliminary Information AthlonMP Processor Model Multiprocessor Platforms
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signals routed debug connector. four processor inputs (PLLTEST#, PLLBYPASS#, PLLMON1, PLLMON2) tied VCC_CORE with pullup resistors. PWROK PWROK input processor must asserted until voltage planes system within specification system clocks running within specification. Requirements" page SADDIN[1:0]# SADDOUT[1:0]# Pins Athlon processor model does support SADDIN[1:0]# SADDOUT[1:0]#. SADDIN[1]# tied with pullup resistors, this supported Northbridge (future models support SADDIN[1]#). SADDOUT[1:0]# tied with pullup resistors these pins supported Northbridge. more information, Athlonand DuronSystem Specification, order# 21902. SCANSHIFTEN (Q5), SCANCLK1 (S1), SCANINTEVAL (S3), SCANCLK2 (S5) scan interface. This interface internal tied disabled with pulldown resistors ground motherboard. systems that support ECC, SCHECK[7:0]# should treated pins. SMI# input that causes processor enter system management mode. STPCLK# input that causes processor enter lower power mode issue Stop Grant special cycle. SYSCLK SYSCLK# differential input clock signals provided processor's from system-clock generator.
Scan Pins
SCHECK[7:0]# SMI# STPCLK# SYSCLK SYSCLK#
"CLKIN, RSTCLK (SYSCLK) Pins" page more information. THDA THDC Pins Thermal Diode anode cathode pins used monitor actual temperature processor die, providing more accurate temperature control system.
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VCCA
VCCA processor supply. information about VCCA pin, Table "VCCA Characteristics," page AthlonProcessor Based Motherboard Design Guide, order# 24363. VID[4:0] (Voltage Identification) outputs used dictate VCC_CORE voltage level. VID[4:0] pins strapped ground left unconnected processor's package. VID[4:0] pins pulled-up motherboard used VCC_CORE DC/DC converter.
VID[4:0] Pins
Table VID[4:0] Code Voltage Definition
VID[4:0] 00000 00001 00010 00011 00100 00101 00111 01000 01001 01010 01011 01100 01101 01110 01111 VCC_CORE(V) 1.850 1.825 1.800 1.775 1.750 1.725 1.675 1.650 1.625 1.600 1.575 1.550 1.525 1.500 1.475 VID[4:0] 10000 10001 10010 10011 10100 10101 10111 11000 11001 11010 11011 11100 11101 11110 11111 VCC_CORE 1.450 1.425 1.400 1.375 1.350 1.325 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100
more information, "Required Circuits" chapter AthlonProcessor Based Motherboard Design Guide, order# 24363. VREFSYS VREFSYS (W5) drives threshold voltage system input receivers. value VREFSYS system specific. addition, minimize VCC_CORE noise rejection from information, Socket Motherboard Design Guide, order# 24363. Descriptions
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Pins
(AC5), (AE5), push-pull compensation circuit pins. Push-Pull mode (selected parameter SysPushPull asserted), tied VCC_CORE with resistor that resistance matching impedance transmission line. tied with resistor that resistance matching impedance transmission line.
Descriptions
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Ordering Information
Standard AthlonMP Processor Model Products
standard products available several operating ranges. ordering part numbers (OPN) formed combination elements, shown Figure
1200
FSB: C=266 Size Cache: =256Kbytes Case Temperature: Operating Voltage: 1.75V Package Type: Speed: 1000=1000 MHz, 1200=1200 MHz, etc. Generation: High-Performance Processor Multiprocessing Systems Family/Architecture: Athlon Processor Architecture
Note: Spaces added number shown above viewing clarity only.
Figure Example AthlonMP Processor Model
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Ordering Information
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Ordering Information
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Appendix
Conventions Abbreviations
This section contains information about conventions abbreviations used this document.
Signals Bits
Active-Low Signals-Signal names containing pound sign, such SFILL#, indicate active-Low signals. They asserted their Low-voltage state negated their High-voltage state. When used this context, High written with initial upper case letter. Signal Ranges-In range signals, highest lowest signal numbers contained brackets separated colon (for example, D[63:0]). Reserved Bits Signals-Signals bits marked reserved must driven inactive left unconnected, indicated signal descriptions. These bits signals reserved future implementations. When software reads registers with reserved bits, reserved bits must masked. When software writes such registers, must first read register change only non-reserved bits before writing back register. Three-State-In timing diagrams, signal ranges that high impedance shown straight horizontal line half-way between high levels.
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Preliminary Information AthlonMP Processor Model Multiprocessor Platforms
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Invalid Don't-Care-In timing diagrams, signal ranges that invalid don't-care filled with screen pattern.
Data Terminology
following list defines data terminology:
Quantities word bytes bits) doubleword four bytes bits) quadword eight bytes bits) Addressing-Memory addressed series bytes eight-byte (64-bit) boundaries which each byte separately enabled. Abbreviations-The following notation used bits bytes: Kilo 4-Kbyte page) Mega Mbits/sec) Giga Gbytes memory space) Table page more abbreviations. Little-Endian Convention-The byte with address xx.xx00 least-significant byte position (little end). byte diagrams, positions numbered from right left-the little right left. Data structure diagrams memory show addresses bottom high addresses top. When data items aligned, notation 64-bit data maps directly notation 64-bit-wide memory. Because byte addresses increase from right left, strings appear reverse order when illustrated. Ranges-In text, ranges shown with dash (for example, bits 9-1). When accompanied signal name, highest lowest numbers contained brackets separated colon (for example, AD[31:0]). Values-Bits either cleared Hexadecimal Binary Numbers-Unless context makes interpretation clear, hexadecimal numbers followed binary numbers followed
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Abbreviations Acronyms
Table contains definitions abbreviations used this document. Table Abbreviations
Abbreviation Gbit Gbyte Kbyte Mbit Mbyte Meaning Ampere Farad GigaGigabit Gigabyte Gigahertz Henry Hexadecimal KiloKilobyte Foot-pound MegaMegabit Megabyte Megahertz MilliMillisecond Milliwatt MicroMicroampere Microfarad Microhenry Microsecond Microvolt nanonanoampere nanofarad nanohenry nanosecond
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Table Abbreviations (Continued)
Abbreviation Meaning picopicoampere picofarad picohenry picosecond Second Volt Watt
Table contains definitions acronyms used this document. Table Acronyms
Abbreviation ACPI APCI APIC BIOS BIST DIMM DRAM EIDE EISA EPROM FIFO GART HSTL Meaning Advanced Configuration Power Interface Accelerated Graphics Port Peripheral Component Interconnect Application Programming Interface Advanced Programmable Interrupt Controller Basic Input/Output System Built-In Self-Test Interface Unit Double-Data Rate Dual Inline Memory Module Direct Memory Access Direct Random Access Memory Error Correcting Code Enhanced Integrated Device Electronics Extended Industry Standard Architecture Enhanced Programmable Read Only Memory DigitalAlphaBus First First Graphics Address Remapping Table High-Speed Transistor Logic
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Table Acronyms (Continued)
Abbreviation JEDEC JTAG LVTTL MTRR PBGA PMSM POST SCSI SDRAM SIMD SMbus SRAM SROM Meaning Integrated Device Electronics Industry Standard Architecture Joint Electron Device Engineering Council Joint Test Action Group Large Area Network Least-Recently Used Voltage Transistor Transistor Logic Most Significant Memory Type Range Registers Multiplexer Non-Maskable Interrupt Open-Drain Plastic Ball Grid Array Physical Address Peripheral Component Interconnect Page Directory Entry Page Directory Table Phase Locked Loop Power Management State Machine Power-On Suspend Power-On Self-Test Random Access Memory Read Only Memory Read Acknowledge Queue Small Computer System Interface System DRAM Interface Synchronous Direct Random Access Memory Single Instruction Multiple Data Serial Initialization Packet System Management Serial Presence Detect Synchronous Random Access Memory Serial Read Only Memory Translation Lookaside Buffer
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Table Acronyms (Continued)
Abbreviation Meaning Memory Transistor Transistor Logic Virtual Address Space Virtual Page Address Video Graphics Adapter Universal Serial Zero Delay Buffer
Appendix
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