FEATURES Single Supply Operation: Very Input Bias Current: Wide Input

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FEATURES Single Supply Operation: Very Input Bias Current: Wide Input

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Single Supply, Rail-to-Rail Power, FET-Input AD824
FEATURES Single Supply Operation: Very Input Bias Current: Wide Input Voltage Range Rail-to-Rail Output Swing Supply Current: A/Amp Wide Bandwidth: Slew Rate: Phase Reversal APPLICATIONS Photo Diode Preamplifier Battery Powered Instrumentation Power Supply Control Protection Medical Instrumentation Remote Sensors Voltage Strain Gage Amplifiers Output Amplifier CONFIGURATIONS 14-Lead Epoxy SOIC Suffix) 16-Lead Epoxy SOIC Suffix)
AD824
VIEW (Not Scale)
AD824
CONNECT
GENERAL DESCRIPTION
AD824 quad, input, single supply amplifier, featuring rail-to-rail outputs. combination inputs rail-to-rail outputs makes AD824 useful wide variety voltage applications where input current primary consideration. AD824 guaranteed operate from single supply dual supplies. AD824AR-3V Parametric Performance fully guaranteed. Fabricated ADI's complementary bipolar process, AD824 unique input stage that allows input voltage safely extend beyond negative supply positive supply without phase inversion latchup. output voltage swings within supplies. Capacitive loads handled without oscillation.
input combined with laser trimming provides input that extremely bias currents with guaranteed offsets below This enables high accuracy designs even with high source impedances. Precision combined with noise, making AD824 ideal battery powered medical equipment. Applications AD824 include portable medical equipment, photo diode preamplifiers high impedance transducer amplifiers. ability output swing rail-to-rail enables designers build multistage filters single supply systems maintain high signal-to-noise ratios. AD824 specified over extended industrial (-40C +85C) temperature range available narrow 14-lead 16-lead SOIC packages.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 2003 Analog Devices, Inc. rights reserved.
AD824-SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VOUT unless otherwise noted)
4000 1013 Unit V/mV V/mV V/mV V/mV mV/C V/ms Degrees nV/÷Hz fA/÷Hz
Parameter INPUT CHARACTERISTICS Offset Voltage AD824A Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio
Symbol
Conditions
TMIN TMAX TMIN TMAX TMIN TMAX CMRR TMIN TMAX TMIN TMAX, -0.2
Input Impedance Large Signal Voltage Gain
Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High
DVOS/DT
1000 4.988 4.985 4.85 4.82 -123 0.005
Output Voltage
Short Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion
ZOUT PSRR
ISOURCE TMIN TMAX ISOURCE TMIN TMAX ISINK TMIN TMAX ISINK TMIN TMAX Sink/Source TMIN TMAX MHz, TMIN TMAX TMIN TMAX Distortion, VOUT 0.01% Load kHz, kHz,
4.975 4.97 4.80 4.75
REV.
AD824 ELECTRICAL SPECIFICATIONS
15.0 VOUT unless otherwise noted)
Conditions 1013 2000 1000 14.988 14.985 14.85 14.82 -14.985 -14.98 -14.88 -14.86 4000 Unit V/mV V/mV V/mV V/mV mV/C V/ms Degrees nV/÷Hz fA/÷Hz
Parameter INPUT CHARACTERISTICS Offset Voltage AD824A Input Bias Current
Symbol CMRR
TMIN TMAX TMIN TMAX TMIN TMAX
Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Input Impedance Large Signal Voltage Gain
TMIN TMAX TMIN TMAX,
Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High
DVOS/DT
Output Voltage
Short Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion
ZOUT PSRR
ISOURCE TMIN TMAX ISOURCE TMIN TMAX ISINK TMIN TMAX ISINK TMIN TMAX Sink/Source, TMIN TMAX MHz, TMIN TMAX TMIN TMAX Distortion, VOUT 0.01% kHz, kHz, rms,
14.975 14.970 14.80 14.75
-14.975 -14.97 -14.85 -14.8
-123 0.005
REV.
AD824-SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
Parameter INPUT CHARACTERISTICS Offset Voltage AD824A Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Input Impedance Large Signal Voltage Gain TMIN TMAX TMIN TMAX TMIN TMAX CMRR TMIN TMAX TMIN TMAX, 1013 2.988 2.985 2.85 2.82
VOUT unless otherwise noted)
Conditions 4000 Unit V/mV V/mV V/mV V/mV mV/C V/ms Degrees nV/÷Hz fA/÷Hz
Symbol
Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High
DVOS/DT
Output Voltage
Short Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion
ZOUT PSRR
ISOURCE TMIN TMAX ISOURCE TMIN TMAX ISINK TMIN TMAX ISINK TMIN TMAX Sink/Source Sink/Source, TMIN TMAX MHz, TMIN TMAX TMIN TMAX Distortion, VOUT 0.01% kHz, kHz,
2.975 2.97 2.75
-123 0.01
REV.
AD824 WAFER TEST LIMITS
unless otherwise noted)
Conditions Limit -0.2 4.975 Unit mV/V V/mV
Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage High Output Voltage Supply Current/Amplifier
Symbol CMRR PSRR
ISOURCE ISINK
NOTE Electrical tests wafer probe limits shown. variations assembly methods normal yield loss, yield after packaging guaranteed standard product dice. Consult factory negotiate specifications based dice qualifications through sample assembly testing.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Input Voltage Differential Input Voltage Output Short Circuit Duration Indefinite Storage Temperature Range R-14, R-16 Packages -65C +150C Operating Temperature Range AD824A -40C +85C Junction Temperature Range R-14, R-16 Packages -65C +150C Lead Temperature Range (Soldering sec) 300C Package Type 14-Lead SOIC 16-Lead SOIC qJA2 Unit
VOUT
NOTES Absolute maximum ratings apply packaged parts unless otherwise noted. specified worst case conditions, i.e., specified device socket P-DIP packages; specified device soldered circuit board SOIC package.
ORDERING GUIDE
Model AD824AR-14 AD824AR-14-3V AD824AR-16 Temperature Range Package Description Package Option R-14 R-14 R-16
Figure Simplified Schematic AD824
-40C +85C 14-Pin SOIC -40C +85C 14-Pin SOIC -40C +85C 16-Pin SOIC
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD824 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD824 -Typical Performance Characteristics
LOAD
LOAD
GAIN GAIN
PHASE Degrees 100k
PHASE Degrees
PHASE Degrees
100k
50mV
50mV
Open-Loop Gain/Phase Small Signal Response, Load
Open-Loop Gain/Phase Small Signal Response, Load
100pF
220pF
GAIN
GAIN
100k
PHASE Degrees
100k
50mV
50mV
Open-Loop Gain/Phase Small Signal Response,
Open-Loop Gain/Phase Small Signal Response,
REV.
AD824
LOAD
PHASE Degrees GAIN
9.950µs
100k
10.810µs
50mV
Open-Loop Gain/Phase Small Signal Response, Load
Slew Rate,
220pF
PHASE Degrees GAIN
VOUT
100µs
100k
Phase Reversal with Inputs Exceeding Supply
OUTPUT RAIL Volts
SINK
SOURCE
50mV
LOAD CURRENT
Open-Loop Gain/Phase Small Signal Response,
Output Voltage Supply Rail Sink Source Load Currents
REV.
AD824
COUNT
NOISE DENSITY
NUMBER UNITS
FREQUENCY
-2.5 -2.0 -1.5 -1.0 -0.5 OFFSET VOLTAGE DRIFT
Voltage Noise Density
Distribution, -55C +125C,
INPUT OFFSET CURRENT
0.010
THD+N
0.001
0.0001 FREQUENCY
TEMPERATURE
Total Harmonic Distortion
Input Offset Current Temperature
COUNT -0.5 -0.4 -0.3 -0.2 -0.1 OFFSET VOLTAGE
100k
INPUT BIAS CURRENT
NUMBER UNITS
TEMPERATURE
Input Offset Distribution,
Input Bias Current Temperature
REV.
AD824
COMMON-MODE REJECTION
INPUT VOLTAGE NOISE nV/÷Hz
100k FREQUENCY
FREQUENCY
100k
Common-Mode Rejection Frequency
Input Voltage Noise Spectral Density Frequency
POWER SUPPLY REJECTION
FREQUENCY 100k
-100
-120
100k FREQUENCY
Frequency,
Power Supply Rejection Frequency
OPEN-LOOP GAIN
PHASE MARGIN Degrees
OUTPUT VOLTAGE Volts
100k FREQUENCY
100k INPUT FREQUENCY
300k
Open-Loop Gain Phase Frequency
Large Signal Frequency Response
REV.
AD824
CROSSTALK
-100
-110 -120 -130
-140
FREQUENCY
100k
Crosstalk Frequency
Large Signal Response
2750 2500
SUPPLY CURRENT
OUTPUT IMPEDANCE
2250 2000 1750 1500 1250 1000
100k FREQUENCY
TEMPERATURE
Output Impedance Frequency, Gain
Supply Current Temperature
1000
OUTPUT SATURATION VOLTAGE
20mV
500ns
0.01
0.10 LOAD CURRENT
10.0
Small Signal Response, Unity Gain Follower, Load
Output Saturation Voltage
-10-
REV.
AD824
APPLICATION NOTES
INPUT CHARACTERISTICS
AD824, n-channel JFETs used provide offset, noise, high impedance input stage. Minimum input common-mode voltage extends from below less than +VS. Driving input voltage closer positive rail will cause loss amplifier bandwidth. AD824 does exhibit phase reversal input voltages including +VS. Figure shows response AD824 voltage follower (+VS) square wave input. input output superimposed. output tracks input without phase reversal. reduced bandwidth above input causes rounding output wave form. input voltages greater than +VS, resistor series with AD824's noninverting input will prevent phase reversal expense greater input voltage noise. This illustrated Figure
current-limiting resistor should used series with input AD824 there possibility input voltage exceeding positive supply more than input voltage will applied AD824 when amplifier will damaged left that condition more than seconds. resistor allows amplifier withstand continuous overvoltage increases input voltage noise negligible amount. Input voltages less than completely different story. amplifier safely withstand input voltages below minus supply voltage long total voltage from positive supply input terminal less than addition, input stage typically maintains picoamp level input currents across that input voltage range.
OUTPUT CHARACTERISTICS
AD824's unique bipolar rail-to-rail output stage swings within positive negative supply voltages. AD824's approximate output saturation resistance both sourcing sinking. This used estimate output saturation voltage when driving heavier current loads. instance, saturation voltage will from either supply with current load. load resistances over AD824's input error voltage virtually unchanged until output voltage driven either supply.
AD824's output overdriven saturate either output devices, amplifier will recover within input returning amplifier's linear operating region.
10µs
Direct capacitive loads will interact with amplifier's effective output impedance form additional pole amplifier's feedback loop, which cause excessive peaking pulse response loss stability. Worst case when amplifier used unity gain follower. show AD824's pulse response unity gain follower driving Configurations with less loop gain, result less loop bandwidth, will much less sensitive capacitance load effects. Noise gain inverse feedback attenuation factor provided feedback network use. Figure shows method extending capacitance load drive capability unity gain follower. With these component values, circuit will drive 5,000 with overshoot.
VOUT 0.01 0.01 20pF VOUT
Figure Response with from VOUT 49.9
AD824
Since input stage uses n-channel JFETs, input current during normal operation positive; current flows from input terminals. input voltage driven more positive than input current will reverse direction internal device junctions become forward biased. This illustrated
Figure Extending Unity Gain Follower Capacitive Load Capability Beyond
REV.
-11-
AD824
APPLICATIONS Single Supply Voltage-to-Frequency Converter Table AD824 Performance
circuit shown Figure uses AD824 drive power timer, which produces stable pulse width positive going output pulse integrated R1-C1 used input AD824, which connected differential integrator. other input (nonloading) unknown voltage, VIN. AD824 output drives timer trigger input, closing overall feedback loop.
REF02 VREF RSCALE** CMOS 74HCO4 CMOS 116k 390pF (NPO) OUT2 OUT1
Parameters CMRR Common-Mode Voltage Range tSETTLING Step Noise kHz,
-0.2 -5.2 nV/÷Hz mV/÷Hz nV/÷Hz mV/÷Hz
0.01 499k 499k 2.5V FULL SCALE 0.01
AD824
Figure Pulse Response Input Signal; Gain
VREF
NOTES fOUT IN/(VREF t1), 25kHz SHOWN.
OHMTEK PART 1043
METAL FILM, <50ppm/ 10%, FILM, <100ppm/
fOUT 20kHz 2.0V
Figure Single Supply Voltage-to-Frequency Converter
Typical AD824 bias currents allow megaohm-range source impedances with negligible errors. Linearity errors order 0.01% full scale achieved with this circuit. This performance obtained with single supply, which delivers less than entire circuit.
Single Supply Programmable Gain Instrumentation Amplifier
VIN1 VIN2 (VIN1 IN2)
AD824
AD824
VOUT
AD824 configured single supply instrumentation amplifier that able operate from single supplies down dual supplies AD824 inputs' bias currents minimize offset errors caused high unbalanced source impedances. array precision thin-film resistors sets gain either 100. These resistors laser-trimmed ratio match 0.01% have maximum differential ppm/C.
100) (VIN1 IN2)
Figure Single Supply Programmable Instrumentation Amplifier
-12-
REV.
AD824
Volt, Single Supply Stereo Headphone Driver
AD824 exhibits good current drive THD+N performance, even single supplies. kHz, total harmonic distortion plus noise (THD+N) equals (0.079%) output signal. This comparable other single supply amps that consume more power cannot power supplies. Figure each channel's input signal coupled Mylar capacitor. Resistor dividers voltage noninverting inputs that output voltage midway between power supplies (1.5 gain 1.5. Each half AD824 then used drive headphone channel. high-pass filter realized capacitors headphones, which modeled load resistors ground. This ensures that signals audio frequency range Hz-20 kHz) delivered headphones.
used drive converter front end. other half AD824 configured unity-gain inverter generates other bridge input -4.5 Resistors provide constant current bridge excitation. AD620 power instrumentation amplifier used condition differential output voltage bridge. gain AD620 programmed using external resistor determined
49.4
Precision Sample-and-Hold Amplifier
CHANNEL MYLAR
95.3k 47.5k AD824 AD824
HEADPHONES IMPEDANCE
95.3k
4.99k
battery-powered applications, supply voltage operational amplifiers required power consumption. Also, supply voltage applications limit signal range precision analog circuitry. Circuits like sample-and-hold circuit shown Figure illustrate techniques designing precision analog circuitry supply voltage applications. maintain high signal-to-noise ratios (SNRs) supply voltage application requires rail-to-rail, input/output operational amplifiers. This design highlights ability AD824 operate rail-to-rail from single supply, with advantages high input impedance. AD824, quad JFET-input amp, well suited circuits input bias currents typical) high input impedances 1013 typical). AD824 also exhibits very supply currents total supply current this circuit less than
3.3/5V 3.3/5V
4.99k CHANNEL MYLAR 47.5k AD824 AD824
AD824A
FALSE GROUND (FG) 3.3/5V 500pF ADG513
Figure Volt Single Supply Stereo Headphone Driver
Dropout Bipolar Bridge Driver
AD824 used driving Wheatstone bridge. Figure shows half AD824 being used buffer AD589-a 1.235 power reference. output
49.9k
AD824B
AD824 AD824
+1.235V
AD589
CONVERTER REFERENCE INPUT
AD824C
500pF
26.4k
AD824D
AD824 AD620
SAMPLE/ HOLD
Figure V/5.5 Precision Sample Hold
VREF
-4.5V
AD824 AD824
many single supply applications, false ground generator required. this circuit, divide supply voltage symmetrically, creating false ground voltage one-half supply. Amplifier then buffers this voltage creating impedance output drive. circuit configured inverting topology centered around this false ground level.
Figure Dropout Bipolar Bridge Driver
REV.
-13-
AD824
design consideration sample-and-hold circuits voltage droop output caused bias switch leakage currents. choosing JFET leakage CMOS switch, this design minimizes droop rate error better than mV/ms this circuit. Higher values will yield lower droop rate. best performance, should polystyrene, polypropylene Teflon capacitors. These types capacitors exhibit leakage dielectric absorption. Additionally, metal film resistors were used throughout design. sample mode, closed, output VOUT -VIN. purpose SW4, which operates parallel with SW1, reduce pedestal, hold step, error injecting same amount charge into noninverting input that injects into inverting input This creates common-mode voltage across inputs then rejected otherwise, charge injection from would create differential voltage step error that would appear VOUT. pedestal error this circuit less than over entire signal range. Another method reducing pedestal error reduce pulse amplitude applied control pins. order control ADG513, only required "ON" state "OFF" state. possible, input control signal whose amplitude ranges from instead full range minimum pedestal error. Other circuit features include acquisition time less than reducing will speed acquisition time further, increased pedestal error will result. Settling time less than sample-mode signal kHz. ADG513 chosen ability work with supplies having normallyopen normallyclosed precision CMOS switches dielectrically isolated process. required this circuit; however, used parallel with provide lower analog switch.
-14-
REV.
AD824
AD824 SPICE Macro-model 9/94, Rev. ARG/ADI Copyright 1994 Analog Devices, Inc. Refer "README.DOC" file License Statement. this model indicates your acceptance with terms provisions License Statement. Node assignments noninverting input inverting input positive supply negative supply output .SUBCKT AD824 INPUT STAGE POLE 1.193E3 1.193E3 4E-12 19.229E-12 108E-6 1E-12 POLY(1) (12,98) 100E-6 GAIN STAGE DOMINANT POLE EREF (30,0) 2.205E6 54E-12 (6,5) 0.838E-3 COMMON-MODE GAIN NETWORK WITH ZERO 159E-12 POLY(2) (2,98) (1,98) POLE 15.9E-15 (9,98) 1E-6 OUTPUT STAGE (18,98) 2.404E-3 2.404E-3 2E-12 2E-12 (99,0) (50,0) FSY1 FSY2 50VN MODELS USED .MODEL NJF(BETA=3.2526E-3 VTO=-2.000 IS=2E-12) .MODEL NPN(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=550 IS=1E-16) .MODEL PNP(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=750 IS=1E-16) .MODEL D(IS=1E-15) .MODEL .MODEL D(IS=1E-16) .ENDS AD824
REV.
-15-
AD824
OUTLINE DIMENSIONS
Dimensions shown millimeters (inches)
Dimensions shown millimeters (inches)
8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 3.80 (0.1496)
10.50 (0.4134) 10.10 (0.3976)
6.20 (0.2441) 5.80 (0.2283)
7.60 (0.2992) 7.40 (0.2913)
0.50 (0.0197) 0.25 (0.0098)
0.25 (0.0098) 0.10 (0.0039)
1.27 (0.0500)
1.75 (0.0689) 1.35 (0.0531)
10.65 (0.4193) 10.00 (0.3937)
COPLANARITY 0.10
0.51 (0.0201) 0.33 (0.0130)
SEATING PLANE
0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.19 (0.0075)
1.27 (0.0500) 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
COMPLIANT JEDEC STANDARDS MS-012AB CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS PARENTHESES) ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
COPLANARITY 0.10
SEATING PLANE
0.32 (0.0126) 0.23 (0.0091)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS PARENTHESES) ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
Revision History
Location 2/03-Data Sheet changed from REV. REV. Page
Deleted Package .Universal Edits GENERAL DESCRIPTION Edits ABSOLUTE MAXIMUM RATINGS Edits ORDERING GUIDE Edits Figure Edits Figure Updated OUTLINE DIMENSIONS
1/02-Data Sheet changed from REV. REV.
Edits ABSOLUTE MAXIMUM RATINGS Edits ORDERING GUIDE Deleted DICE CHARACTERISTICS
-16-
REV.
PRINTED U.S.A.
Edits ELECTRICAL SPECIFICATIONS
C00875-0-2/03(C)
14-Lead Standard Small Outline Package [SOIC] Narrow Body (R-14)
16-Lead Standard Small Outline Package [SOIC] Wide Body (R-16)

FEATURES Single Supply Operation: Very Input Bias Current: Wide Input

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