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Hitachi SuperH RISC engine
SH7144 Series
sH7144,SH7144F-ZTAT sH7145,SH7145F-ZTAT
Hardware Manual
ADE-602-254A Rev. 09/19/02 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Rev. 2.0, 09/02, page xxxviii
General Precautions Handling Products
Treatment Pins Note: connect anything pins. (not connected) pins connected internal circuitry; they used test pins reduce noise. something connected pins, operation guaranteed. Treatment Unused Input Pins Note: unused input pins high level. Generally, input pins CMOS products high-impedance input pins. unused pins their open states, intermediate levels induced noise vicinity, passthrough current flows internally, malfunction occur. Processing before Initialization Note: When power first supplied, product's state undefined. states internal circuits undefined until full power supplied throughout chip level input reset pin. During period where states undefined, register settings output state each also undefined. Design your system that does malfunction because processing while this undefined state. those products which have reset function, reset immediately after power supply been turned Prohibition access undefined reserved addresses Note: Access undefined reserved addresses prohibited. undefined reserved addresses used expand functions, test registers have been allocated these addresses. access these registers; system's operation guaranteed they accessed.
Rev. 2.0, 09/02, page xxxviii
Configuration This Manual
This manual comprises following items: General Precautions Handling Product Configuration This Manual Preface Contents Overview Description Functional Modules System-Control Modules On-Chip Peripheral Modules configuration functional description each module differs according module. However, generic style includes following items: Feature Input/Output iii) Register Description Operation Usage Note When designing application system that includes this LSI, take notes into account. Each section includes notes relation descriptions given, usage notes given, required, final part each section. List Registers Electrical Characteristics Appendix Main Revisions Additions this Edition (only revised versions) list revisions summary points that have been revised added earlier versions. This does include revised contents. details, actual locations this manual. Index
Rev. 2.0, 09/02, page xxxviii
Preface
SH7144 Series single-chip RISC (Reduced Instruction Computer) microprocessor includes Hitachi-original RISC core, peripheral functions required configure system. Target users: This manual written users will using this design application systems. Users this manual expected understand fundamentals electrical circuits, logical circuits, microcomputers. Objective: This manual written explain hardware functions electrical characteristics this above users. Refer SH-1, SH-2, SH-DSP Programming Manual detailed description instruction set.
Notes reading this manual: Product names following products covered this manual.
Product Classifications Abbreviations Basic Classification SH7144 (112-pin version) On-Chip Classification SH7144F SH7144M SH7145 (144-pin version) SH7145F SH7145M Note: Under development Flash memory version (ROM: kbytes) Mask version (ROM: kbytes) Flash memory version (ROM: kbytes) Mask version (ROM: kbytes) Product Code HD64F7144 HD6437144* HD64F7145 HD6437145*
this manual, product abbreviations used distinguish products. example, 112pin products collectively referred SH7144, abbreviation basic type's classification code, while 144-pin products collectively referred SH7145. There versions each: flash memory version mask version. When description limited flash memory version alone, character added abbreviation, such SH7144F. When description limited mask version alone, abbreviation that determined adding abbreviation.
Rev. 2.0, 09/02, page xxxviii
typical product HD64F7144 taken typical product descriptions this manual. Accordingly, when using HD6437144, HD64F7145, HD6437145, simply replace HD64F7144 those references where differences between products pointed with HD6437144, HD64F7145, HD6437145. Where differences indicated, aware that each specification apply products indicated. order understand overall functions chip Read manual according contents. This manual roughly categorized into parts CPU, system control functions, peripheral functions electrical characteristics. order understand details CPU's functions Read SH-1, SH-2, SH-DSP Programming Manual. order understand details register when user knows name Read index that final part manual find page number entry register. addresses, names, initial values registers summarized section List Registers. Rules: Register name: following notation used cases when same similar function, e.g. serial communication, implemented more than channel: XXX_N (XXX register name channel number) left right. active signals expressed xxxx.
order: Signal expression: Related Manuals:
Numerical expression: Binary Bxxxx, Hexadecimal Hxxxx, decimal xxxx.
latest versions related manuals available from site. Please ensure have latest versions documents require.
SH7144 Series manuals:
Manual Title SH7144 Series Hardware Manual SH-1, SH-2, SH-DSP Programming Manual This manual ADE-602-063
Rev. 2.0, 09/02, page xxxviii
Users manuals development tools:
Manual Title C/C++ Compiler, Assembler, Optimized Linkage Editor Users Manual Simulator Debugger (for Windows) Users Manual Simulator Debugger (for UNIX) Users Manual Hitachi Embedded Workshop Users Manual ADE-702-246 ADE-702-186 ADE-702-203 ADE-702-201
Application Notes:
Manual Title C/C++ Compiler Edition F-ZTAT Technical ADE-702-179 ADE-502-046
Rev. 2.0, 09/02, page xxxviii
Rev. 2.0, 09/02, page viii xxxviii
Contents
Section Overview.
Features Internal Block Diagram.3 Arrangement Functions
Section CPU.
Features Register Configuration 2.2.1 General Registers (Rn).13 2.2.2 Control Registers 2.2.3 System Registers 2.2.4 Initial Values Registers.17 Data Formats 2.3.1 Data Format Registers.17 2.3.2 Data Formats Memory 2.3.3 Immediate Data Format Instruction Features.18 2.4.1 RISC-Type Instruction Set.18 2.4.2 Addressing Modes 2.4.3 Instruction Format.25 Instruction 2.5.1 Instruction Classification Processing States.41 2.6.1 State Transitions.41
Section Operating Modes.
Selection Operating Modes.43 Input/Output Pin.44 Explanation Operating Modes 3.3.1 Mode (MCU extension mode 3.3.2 Mode (MCU extension mode 3.3.3 Mode (MCU extension mode 3.3.4 Mode (Single chip mode).45 3.3.5 Clock mode Address Initial State This
Rev. 2.0, 09/02, page xxxviii
Section Clock Pulse Generator
Oscillator. 4.1.1 Connecting Crystal Oscillator 4.1.2 External Clock Input Method. Function Detecting Oscillator Halt. Usage Notes 4.3.1 Note Crystal Resonator 4.3.2 Notes Board Design
Section Exception Processing.53
Overview. 5.1.1 Types Exception Processing Priority 5.1.2 Exception Processing Operations. 5.1.3 Exception Processing Vector Table Resets 5.2.1 Types Reset 5.2.2 Power-On Reset 5.2.3 Manual Reset Address Errors 5.3.1 Cause Address Error Exception. 5.3.2 Address Error Exception Processing. Interrupts. 5.4.1 Interrupt Sources. 5.4.2 Interrupt Priority Level 5.4.3 Interrupt Exception Processing Exceptions Triggered Instructions 5.5.1 Types Exceptions Triggered Instructions 5.5.2 Trap Instructions 5.5.3 Illegal Slot Instructions 5.5.4 General Illegal Instructions. Cases when Exception Sources Accepted 5.6.1 Immediately after Delayed Branch Instruction 5.6.2 Immediately after Interrupt-Disabled Instruction. Stack Status after Exception Processing Ends Usage Notes 5.8.1 Value Stack Pointer (SP) 5.8.2 Value Vector Base Register (VBR) 5.8.3 Address Errors Caused Stacking Address Error Exception Processing.
Section Interrupt Controller (INTC).67
Features. Input/Output Pins Register Descriptions
Rev. 2.0, 09/02, page xxxviii
6.3.1 Interrupt Control Register (ICR1).70 6.3.2 Interrupt Control Register (ICR2).72 6.3.3 Status Register (ISR).74 6.3.4 Interrupt Priority Registers (IPRA IPRJ).75 Interrupt Sources 6.4.1 External Interrupts 6.4.2 On-Chip Peripheral Module Interrupts 6.4.3 User Break Interrupt 6.4.4 H-UDI Interrupt Interrupt Exception Processing Vectors Table.79 Interrupt Operation.82 6.6.1 Interrupt Sequence 6.6.2 Stack after Interrupt Exception Processing Interrupt Response Time Data Transfer with Interrupt Request Signals 6.8.1 Handling Interrupt Request Signals Sources Activating Interrupt, DMAC Activating.88 6.8.2 Handling Interrupt Request Signals Sources Activating DMAC, Interrupt Activating 6.8.3 Handling Interrupt Request Signals Source Activating, Interrupt DMAC Activating.88 6.8.4 Handling Interrupt Request Signals Source Interrupt DMAC Activating
Section User Break Controller (UBC)
Overview.91 Register Descriptions 7.2.1 User Break Address Register (UBAR).93 7.2.2 User Break Address Mask Register (UBAMR) 7.2.3 User Break Cycle Register (UBBR) 7.2.4 User Break Control Register (UBCR).95 Operation.96 7.3.1 Flow User Break Operation 7.3.2 Break On-Chip Memory Instruction Fetch Cycle 7.3.3 Program Counter (PC) Values Saved.98 Examples Usage Notes .101 7.5.1 Simultaneous Fetching Instructions.101 7.5.2 Instruction Fetches Branches .101 7.5.3 Contention between User Break Exception Processing .102 7.5.4 Break Non-Delay Branch Instruction Jump Destination.102 7.5.5 Module Standby Mode Setting .102
Rev. 2.0, 09/02, page xxxviii
Section Data Transfer Controller (DTC) .103
Features. Register Descriptions 8.2.1 Mode Register (DTMR). 8.2.2 Source Address Register (DTSAR) 8.2.3 Destination Address Register (DTDAR). 8.2.4 Initial Address Register (DTIAR) 8.2.5 Transfer Count Register (DTCRA) 8.2.6 Transfer Count Register (DTCRB) 8.2.7 Enable Registers (DTER). 8.2.8 Control/Status Register (DTCSR). 8.2.9 Information Base Register (DTBR) Operation 8.3.1 Activation Sources. 8.3.2 Location Register Information Vector Table 8.3.3 Operation 8.3.4 Interrupt Source 8.3.5 Operation Timing. 8.3.6 Execution State Counts Procedures Using DTC. 8.4.1 Activation Interrupt. 8.4.2 Activation Software 8.4.3 Example Cautions 8.5.1 Prohibition against DMAC/DTC Register Access DTC. 8.5.2 Module Standby Mode Setting 8.5.3 On-Chip
Section State Controller (BSC) .125
Features. Configuration. Register Descriptions Address Description Registers. 9.5.1 Control Register (BCR1) 9.5.2 Control Register (BCR2) 9.5.3 Wait Control Register (WCR1). 9.5.4 Wait Control Register (WCR2). 9.5.5 Emulation Register (RAMER). Accessing External Space 9.6.1 Basic Timing. 9.6.2 Wait State Control 9.6.3 Assert Period Extension
Rev. 2.0, 09/02, page xxxviii
Waits between Access Cycles .142 9.7.1 Prevention Data Conflicts.142 9.7.2 Simplification Cycle Start Detection .143 Arbitration.144 Memory Connection Example .145 9.10 Access On-chip Peripheral Registers.148 9.11 Cycles No-Bus Mastership Release .148 9.12 Operation When Program Located External Memory.148
Section Direct Memory Access Controller (DMAC)
10.1 Features .149 10.2 Input/Output Pins .151 10.3 Register Descriptions .151 10.3.1 Source Address Registers_0 (SAR_0 SAR_3) .152 10.3.2 Destination Address Registers_0 (DAR_0 DAR_3).152 10.3.3 Transfer Count Registers_0 (DMATCR_0 DMATCR_3).153 10.3.4 Channel Control Registers_0 (CHCR_0 CHCR_3).153 10.3.5 DMAC Operation Register (DMAOR) .159 10.4 Operation.161 10.4.1 Transfer Flow .161 10.4.2 Transfer Requests .163 10.4.3 Channel Priority .165 10.4.4 Transfer Types.168 10.4.5 Number Cycle States DREQ Sample Timing.177 10.4.6 Source Address Reload Function .182 10.4.7 Transfer Ending Conditions.184 10.4.8 DMAC Access from CPU.185 10.5 Examples .185 10.5.1 Example Transfer between On-Chip External Memory .185 10.5.2 Example Transfer between External External Device with DACK .186 10.5.3 Example Transfer between Converter On-chip Memory (Address Reload On).186 10.5.4 Example Transfer between External Memory SCI1 Transmit Side (Indirect Address On).188 10.6 Cautions .190
Section Multi-Function Timer Pulse Unit (MTU)
11.1 Features .191 11.2 Input/Output Pins .195 11.3 Register Descriptions .196 11.3.1 Timer Control Register (TCR) .198 11.3.2 Timer Mode Register (TMDR) .202
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11.4
11.5
11.6
11.7
11.3.3 Timer Control Register (TIOR) 11.3.4 Timer Interrupt Enable Register (TIER) 11.3.5 Timer Status Register (TSR). 11.3.6 Timer Counter (TCNT). 11.3.7 Timer General Register (TGR) 11.3.8 Timer Start Register (TSTR). 11.3.9 Timer Synchronous Register (TSYR). 11.3.10 Timer Output Master Enable Register (TOER) 11.3.11 Timer Output Control Register (TOCR) 11.3.12 Timer Gate Control Register (TGCR). 11.3.13 Timer Subcounter (TCNTS) 11.3.14 Timer Dead Time Data Register (TDDR). 11.3.15 Timer Period Data Register (TCDR) 11.3.16 Timer Period Buffer Register (TCBR). 11.3.17 Master Interface Operation 11.4.1 Basic Functions. 11.4.2 Synchronous Operation. 11.4.3 Buffer Operation 11.4.4 Cascaded Operation 11.4.5 Modes 11.4.6 Phase Counting Mode. 11.4.7 Reset-Synchronized Mode. 11.4.8 Complementary Mode. Interrupt Sources. 11.5.1 Interrupt Sources Priorities. 11.5.2 DTC/DMAC Activation. 11.5.3 Converter Activation. Operation Timing. 11.6.1 Input/Output Timing 11.6.2 Interrupt Signal Timing Usage Notes 11.7.1 Module Standby Mode Setting 11.7.2 Input Clock Restrictions 11.7.3 Caution Period Setting 11.7.4 Contention between TCNT Write Clear Operations. 11.7.5 Contention between TCNT Write Increment Operations. 11.7.6 Contention between Write Compare Match 11.7.7 Contention between Buffer Register Write Compare Match 11.7.8 Contention between Read Input Capture. 11.7.9 Contention between Write Input Capture. 11.7.10 Contention between Buffer Register Write Input Capture 11.7.11 TCNT2 Write Overflow/Underflow Contention Cascade Connection
Rev. 2.0, 09/02, page xxxviii
11.7.12 Counter Value during Complementary Mode Stop .301 11.7.13 Buffer Operation Setting Complementary Mode .302 11.7.14 Reset Sync Mode Buffer Operation Compare Match Flag .302 11.7.15 Overflow Flags Reset Synchronous Mode .303 11.7.16 Contention between Overflow/Underflow Counter Clearing.304 11.7.17 Contention between TCNT Write Overflow/Underflow.305 11.7.18 Cautions Transition from Normal Operation Mode Reset-Synchronous Mode.305 11.7.19 Output Level Complementary Mode Reset-Synchronous Mode .306 11.7.20 Interrupts Module Standby Mode .306 11.7.21 Simultaneous Capture TCNT_1 TCNT_2 Cascade Connection.306 11.8 Output Initialization .306 11.8.1 Operating Modes.306 11.8.2 Reset Start Operation .307 11.8.3 Operation Case Re-Setting Error During Operation, Etc. .307 11.8.4 Overview Initialization Procedures Mode Transitions Case Error during Operation, Etc.308 11.9 Port Output Enable (POE).338 11.9.1 Features.338 11.9.2 Configuration.340 11.9.3 Register Descriptions .340 11.9.4 Operation .345 11.9.5 Usage Note.347
Section Watchdog Timer
12.1 Features .349 12.2 Input/Output Pin.350 12.3 Register Descriptions .350 12.3.1 Timer Counter (TCNT).351 12.3.2 Timer Control/Status Register (TCSR) .351 12.3.3 Reset Control/Status Register (RSTCSR) .353 12.4 Operation.354 12.4.1 Watchdog Timer Mode .354 12.4.2 Interval Timer Mode .355 12.4.3 Clearing Software Standby Mode .356 12.4.4 Timing Setting Overflow Flag (OVF) .356 12.4.5 Timing Setting Watchdog Timer Overflow Flag (WOVF).357 12.5 Interrupt Sources .357 12.6 Usage Notes .357 12.6.1 Notes Register Access.357 12.6.2 TCNT Write Increment Contention .359 12.6.3 Changing CKS2 CKS0 Values.359
Rev. 2.0, 09/02, page xxxviii
12.6.4 12.6.5 12.6.6 12.6.7
Changing between Watchdog Timer/Interval Timer Modes. System Reset WDTOVF Signal. Internal Reset Watchdog Timer Mode. Manual Reset Watchdog Timer Mode
Section Serial Communication Interface (SCI) .361
13.1 Features. 13.2 Input/Output Pins 13.3 Register Descriptions 13.3.1 Receive Shift Register (RSR) 13.3.2 Receive Data Register (RDR) 13.3.3 Transmit Shift Register (TSR) 13.3.4 Transmit Data Register (TDR). 13.3.5 Serial Mode Register (SMR). 13.3.6 Serial Control Register (SCR). 13.3.7 Serial Status Register (SSR) 13.3.8 Serial Direction Control Register (SDCR). 13.3.9 Rate Register (BRR) 13.4 Operation Asynchronous Mode 13.4.1 Data Transfer Format. 13.4.2 Receive Data Sampling Timing Reception Margin Asynchronous Mode 13.4.3 Clock. 13.4.4 initialization (Asynchronous mode). 13.4.5 Data transmission (Asynchronous mode) 13.4.6 Serial data reception (Asynchronous mode) 13.5 Multiprocessor Communication Function. 13.5.1 Multiprocessor Serial Data Transmission 13.5.2 Multiprocessor Serial Data Reception 13.6 Operation Clocked Synchronous Mode 13.6.1 Clock. 13.6.2 initialization (Clocked Synchronous mode). 13.6.3 Serial data transmission (Clocked Synchronous mode) 13.6.4 Serial data reception (Clocked Synchronous mode) 13.6.5 Simultaneous Serial Data Transmission Reception (Clocked Synchronous mode) 13.7 Interrupt Sources. 13.7.1 Interrupts Normal Serial Communication Interface Mode 13.8 Usage Notes 13.8.1 Write TDRE Flag 13.8.2 Module Standby Mode Setting 13.8.3 Break Detection Processing (Asynchronous Mode Only). 13.8.4 Sending Break Signal (Asynchronous Mode Only)
Rev. 2.0, 09/02, page xxxviii
13.8.5 Receive Error Flags Transmit Operations (Clocked Synchronous Mode Only).409 13.8.6 Constraints DMAC Use.409 13.8.7 Cautions Clocked Synchronous External Clock Mode .409 13.8.8 Caution Clocked Synchronous Internal Clock Mode.409
Section Interface (IIC) Option
14.1 Features .411 14.2 Input/Output Pins .413 14.3 Description Registers.414 14.3.1 Data Register (ICDR) .414 14.3.2 Slave-Address Register (SAR).416 14.3.3 Second Slave-Address Register (SARX) .417 14.3.4 Mode Register (ICMR) .418 14.3.5 Control Register (ICCR) .421 14.3.6 Status Register (ICSR).429 14.3.7 Serial Control Register (SCRX) .434 14.4 Operation.435 14.4.1 Data Formats.435 14.4.2 Operations Master Transmission .437 14.4.3 Operations Master Reception.440 14.4.4 Operations Slave Reception .442 14.4.5 Operations Slave Transmission.445 14.4.6 Timing Setting IRIC Control SCL.447 14.4.7 Noise Canceller .448 14.4.8 Operation.449 14.4.9 Using Interface: Some Examples .450 14.5 Usage Notes .453
Section Converter.
15.1 Features .463 15.2 Input/Output Pins .465 15.3 Register Description.466 15.3.1 Data Registers (ADDR0 ADDR7) .466 15.3.2 Control/Status Register_0 (ADCSR_0 ADCSR_1) .467 15.3.3 Control Register_0 (ADCR_0 ADCR_1) .468 15.3.4 Trigger Select Register (ADTSR) .470 15.4 Operation.471 15.4.1 Single Mode.471 15.4.2 Continuous Scan Mode .471 15.4.3 Single-Cycle Scan Mode.472 15.4.4 Input Signal Sampling Conversion Time .472 15.4.5 Converter Activation .474
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15.4.6 External Trigger Input Timing. 15.5 Interrupt Sources DTC, DMAC Transfer Requests. 15.6 Definitions Conversion Accuracy. 15.7 Usage Notes 15.7.1 Module Standby Mode Setting 15.7.2 Permissible Signal Source Impedance 15.7.3 Influences Absolute Accuracy 15.7.4 Range Analog Power Supply Other Settings. 15.7.5 Notes Board Design 15.7.6 Notes Noise Countermeasures
Section Compare Match Timer (CMT) .481
16.1 Features. 16.2 Register Descriptions 16.2.1 Compare Match Timer Start Register (CMSTR) 16.2.2 Compare Match Timer Control/Status Register 1(CMCSR0, 16.2.3 Compare Match Timer Counter_0 (CMCNT_0, 16.2.4 Compare Match Timer Constant Register_0 (CMCOR_0, 16.3 Operation 16.3.1 Compare Match Counter Operation. 16.3.2 CMCNT Count Timing. 16.4 Interrupts. 16.4.1 Interrupt Sources Activation 16.4.2 Compare Match Flag Timing. 16.4.3 Compare Match Flag Clear Timing 16.5 Usage Notes 16.5.1 Contention between CMCNT Write Compare Match. 16.5.2 Contention between CMCNT Word Write Counter Incrementation. 16.5.3 Contention between CMCNT Byte Write Counter Incrementation
Section Function Controller (PFC) .489
17.1 Register Descriptions 17.1.1 Port Register (PAIORL, 17.1.2 Port Control Registers (PACRL2, PACRL1, PACRH) 17.1.3 Port Register (PBIOR) 17.1.4 Port Control Registers (PBCR1 PBCR2). 17.1.5 Port Register (PCIOR) 17.1.6 Port Control Register (PCCR) 17.1.7 Port Registers (PDIORL, 17.1.8 Port Control Registers (PDCRL1, PDCRL2, PDCRH1, PDCRH2) 17.1.9 Port Register (PEIORL). 17.1.10 Port Control Registers (PECRL1 PECRL2).
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17.1.11 High-Current Port Control Register (PPCR).550 17.2 Precautions .550
Section Ports
18.1 Port .553 18.1.1 Register Descriptions .555 18.1.2 Port Data Registers (PADRH PADRL).555 18.2 Port .557 18.2.1 Register Descriptions .557 18.2.2 Port Data Register (PBDR) .557 18.3 Port .559 18.3.1 Register Descriptions .559 18.3.2 Port Data Register (PCDR) .559 18.4 Port .561 18.4.1 Register Descriptions .563 18.4.2 Port Data Registers (PDDRH PDDRL).563 18.5 Port .566 18.5.1 Register Descriptions .567 18.5.2 Port Data Register (PEDRL) .567 18.6 Port F.569 18.6.1 Register Descriptions .569 18.6.2 Port Data Register (PFDR) .569
Section Flash Memory (F-ZTAT Version)
19.1 19.2 19.3 19.4 19.5 Features .571 Mode Transitions .572 Block Configuration.576 Input/Output Pins .577 Register Descriptions .577 19.5.1 Flash Memory Control Register (FLMCR1).577 19.5.2 Flash Memory Control Register (FLMCR2).579 19.5.3 Erase Block Register (EBR1).579 19.5.4 Erase Block Register (EBR2).580 19.5.5 Emulation Register (RAMER).580 On-Board Programming Modes.581 19.6.1 Boot Mode .582 19.6.2 Programming/Erasing User Program Mode.584 Flash Memory Emulation RAM.585 Flash Memory Programming/Erasing .587 19.8.1 Program/Program-Verify Mode.587 19.8.2 Erase/Erase-Verify Mode.589 19.8.3 Interrupt Handling when Programming/Erasing Flash Memory.589 Program/Erase Protection .591
Rev. 2.0, 09/02, page xxxviii
19.6
19.7 19.8
19.9
19.9.1 Hardware Protection 19.9.2 Software Protection. 19.9.3 Error Protection. 19.10 PROM Programmer Mode 19.11 Usage Note. 19.12 Notes when Converting F-ZTAT Versions Mask-ROM Versions.
Section Mask .595
20.1 Usage Note.
Section .597
21.1 Usage Note.
Section Hitachi User Debug Interface (H-UDI) .599
22.1 Overview. 22.1.1 Features. 22.1.2 Block Diagram. 22.2 Input/Output Pins 22.3 Register Description. 22.3.1 Instruction Register (SDIR) 22.3.2 Status Register (SDSR). 22.3.3 Data Register (SDDR) 22.3.4 Bypass Register (SDBPR) 22.4 Operation 22.4.1 H-UDI Interrupt 22.4.2 Bypass Mode. 22.4.3 H-UDI Reset 22.5 Usage Notes
Section Advanced User Debugger (AUD) .611
23.1 Overview. 23.1.1 Features. 23.1.2 Block Diagram. 23.2 Input/Output Pins 23.2.1 Descriptions. 23.3 Branch Trace Mode. 23.3.1 Overview. 23.3.2 Operation 23.4 Monitor Mode 23.4.1 Overview. 23.4.2 Communication Protocol 23.4.3 Operation 23.5 Usage Notes
Rev. 2.0, 09/02, page xxxviii
23.5.1 23.5.2 23.5.3 23.5.4 23.5.5
Initialization .619 Operation Software Standby Mode.619 Setting PA15/CK pin.619 States.619 Start-up Sequence.620
Section Power-Down Modes
24.1 Input/Output Pins .623 24.2 Register Descriptions .623 24.2.1 Standby Control Register (SBYCR) .623 24.2.2 System Control Register (SYSCR) .625 24.2.3 Module Standby Control Register (MSTCR1 MSTCR2).626 24.3 Operation.628 24.3.1 Sleep Mode .628 24.3.2 Software Standby Mode.629 24.3.3 Module Standby Mode.631 24.4 Usage Notes .632 24.4.1 Port Status.632 24.4.2 Current Consumption during Oscillation Stabilization Wait Period .632 24.4.3 On-Chip Peripheral Module Interrupt.632 24.4.4 Writing MSTCR1 MSTCR2 .632 24.4.5 DMAC, DTC, Operation Sleep Mode.632
Section List Registers
25.1 Register Address Table Order from Lower Addresses).633 25.2 Register List .645 25.3 Register States Each Operating Mode.658
Section Electrical Characteristics
26.1 Absolute Maximum Ratings .665 26.2 Characteristics .666 26.3 Characteristics .669 26.3.1 Test conditions characteristics .669 26.3.2 Clock timing .670 26.3.3 Control Signal Timing .672 26.3.4 Timing .675 26.3.5 Direct Memory Access Controller (DMAC) Timing .679 26.3.6 Multi-Function Timer Pulse Unit (MTU)Timing.681 26.3.7 Port Timing.682 26.3.8 Watchdog Timer (WDT)Timing .683 26.3.9 Serial Communication Interface (SCI)Timing.684 26.3.10 Interface Timing .686 26.3.11 Output Enable (POE) Timing .687
Rev. 2.0, 09/02, page xxxviii
26.3.12 Converter Timing. 26.3.13 H-UDI Timing 26.3.14 Timing 26.4 Converter Characteristics 26.5 Flash Memory Characteristics.
Appendix States.697
State
Appendix States Related Signals .707
States Related Signals
Appendix Product Code Lineup.710 Appendix Package Dimensions .711 Main Revisions Additions this Edition.713 Index .729
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Figures
Section Figure Figure Figure Figure Section Figure Figure Figure Figure Overview Internal Block Diagram SH7144.3 Block Diagram SH7145 SH7144 Arrangement.5 SH7145 Arrangement.6 Internal Registers Data Format Registers Data Formats Memory.18 Transitions between Processing States
Section Operating Modes Figure Address Each Operating Mode.46 Section Figure Figure Figure Figure Figure Figure Section Figure Figure Figure Figure Figure Figure Clock Pulse Generator Block Diagram Clock Pulse Generator Connection Crystal Oscillator (Example).49 Crystal Resonator Equivalent Circuit Example External Clock Connection Cautions Oscillator Circuit System Board Design.51 Recommended External Circuitry around Interrupt Controller (INTC) INTC Block Diagram Block Diagram IRQ7 IRQ0 Interrupts Control Interrupt Sequence Flowchart.83 Stack after Interrupt Exception Processing.84 Example Pipeline Operation when Interrupt Accepted Interrupt Control Block Diagram.87
Section User Break Controller (UBC) Figure User Break Controller Block Diagram Figure Break Condition Determination Method Section Figure Figure Figure Figure Figure Figure Figure Data Transfer Controller (DTC) Block Diagram .104 Activating Source Control Block Diagram.112 Register Information Allocation Memory Space.112 Correspondence between Vector Address Transfer Information .113 Operation Flowchart .116 Memory Mapping Normal Mode .117 Memory Mapping Repeat Mode.118
Rev. 2.0, 09/02, page xxiii xxxviii
Figure Memory Mapping Block Transfer Mode. Figure Chain Transfer. Figure 8.10 Operation Timing Example (Normal Mode) Section Figure Figure Figure Figure Figure State Controller (BSC) Block Diagram. Address Format Basic Timing External Space Access. Wait State Timing External Space Access (Software Wait Only) Wait State Timing External Space Access (Two Software Wait States WAIT Signal Wait State). Figure Assert Period Extension Function Figure Example Idle Cycle Insertion. Figure Example Idle Cycle Insertion Same Space Consecutive Access. Figure Mastership Release Procedure. Figure 9.10 Example 8-bit Data Width Connection Figure 9.11 Example 16-bit Data Width Connection Figure 9.12 Example 32-bit Data Width Connection (only SH7145). Figure 9.13 Example 8-bit Data Width SRAM Connection. Figure 9.14 Example 16-bit Data Width SRAM Connection. Figure 9.15 Example 32-bit Data Width SRAM Connection (only SH7145) Figure 9.16 Cycle. Section Direct Memory Access Controller (DMAC) Figure 10.1 DMAC Block Diagram. Figure 10.2 DMAC Transfer Flowchart Figure 10.3 Round Robin Mode. Figure 10.3 Example Changes Priority Round Robin Mode Figure 10.4 Data Flow Single Address Mode. Figure 10.5 Example Transfer Timing Single Address Mode. Figure 10.6 Direct Address Operation during Dual Address Mode. Figure 10.7 Example Direct Address Transfer Timing Dual Address Mode Figure 10.8 Dual Address Mode Indirect Address Operation (When External Memory Space bits) Figure 10.9 Dual Address Mode Indirect Address Transfer Timing Example (External Memory Space External Memory Space, 16-bit width) Figure 10.10 Dual Address Mode Indirect Address Transfer Timing Example (On-chip Memory Space On-chip Memory Space) Figure 10.11 Transfer Example Cycle-Steal Mode Figure 10.12 Transfer Example Burst Mode Figure 10.13 Handling when Multiple Channels Operating Figure 10.14 Cycle Steal, Dual Address Level Detection (Fastest Operation) Figure 10.15 Cycle Steal, Dual Address Level Detection (Normal Operation) Figure 10.16 Cycle Steal, Single Address Level Detection (Fastest Operation).
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Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 10.21 Figure 10.22 Figure 10.23 Figure 10.24 Figure 10.25
Cycle Steal, Single Address Level Detection (Normal Operation).180 Burst Mode, Dual Address Level Detection (Fastest Operation).181 Burst Mode, Dual Address Level Detection (Normal Operation).181 Burst Mode, Single Address Level Detection (Fastest Operation) .181 Burst Mode, Single Address Level Detection (Normal Operation) .181 Burst Mode, Dual Address Edge Detection .182 Burst Mode, Single Address Edge Detection.182 Source Address Reload Function.182 Source Address Reload Function Timing Chart .183
Section Multi-Function Timer Pulse Unit (MTU) Figure 11.1 Block Diagram .194 Figure 11.2 Complementary Mode Output Level Example .231 Figure 11.3 Example Counter Operation Setting Procedure .235 Figure 11.4 Free-Running Counter Operation .236 Figure 11.5 Periodic Counter Operation .237 Figure 11.6 Example Setting Procedure Waveform Output Compare Match .237 Figure 11.7 Example Output/1 Output Operation.238 Figure 11.8 Example Toggle Output Operation .238 Figure 11.9 Example Input Capture Operation Setting Procedure .239 Figure 11.10 Example Input Capture Operation.240 Figure 11.11 Example Synchronous Operation Setting Procedure.241 Figure 11.12 Example Synchronous Operation .242 Figure 11.13 Compare Match Buffer Operation .243 Figure 11.14 Input Capture Buffer Operation.243 Figure 11.15 Example Buffer Operation Setting Procedure .243 Figure 11.16 Example Buffer Operation (1).244 Figure 11.17 Example Buffer Operation (2).245 Figure 11.18 Cascaded Operation Setting Procedure .246 Figure 11.19 Example Cascaded Operation .246 Figure 11.20 Example Mode Setting Procedure .249 Figure 11.21 Example Mode Operation .249 Figure 11.22 Example Mode Operation .250 Figure 11.23 Example Mode Operation .251 Figure 11.24 Example Phase Counting Mode Setting Procedure.252 Figure 11.25 Example Phase Counting Mode Operation .253 Figure 11.26 Example Phase Counting Mode Operation .254 Figure 11.27 Example Phase Counting Mode Operation .255 Figure 11.28 Example Phase Counting Mode Operation .256 Figure 11.29 Phase Counting Mode Application Example.257 Figure 11.30 Procedure Selecting Reset-Synchronized Mode.259 Figure 11.31 Reset-Synchronized Mode Operation Example (When TOCR's OLSN OLSP 1).260
Rev. 2.0, 09/02, page xxxviii
Figure 11.32 Figure 11.33 Figure 11.34 Figure 11.35 Figure 11.36 Figure 11.37 Figure 11.38 Figure 11.39 Figure 11.40 Figure 11.41 Figure 11.42 Figure 11.43 Figure 11.44 Figure 11.45 Figure 11.46 Figure 11.47 Figure 11.48 Figure 11.49 Figure 11.50 Figure 11.51 Figure 11.52 Figure 11.53 Figure 11.54 Figure 11.55 Figure 11.56 Figure 11.57 Figure 11.58 Figure 11.59 Figure 11.60 Figure 11.61 Figure 11.62 Figure 11.63 Figure 11.64 Figure 11.65 Figure 11.66 Figure 11.67 Figure 11.68 Figure 11.69 Figure 11.70 Figure 11.71 Figure 11.72 Figure 11.73
Block Diagram Channels Complementary Mode Example Complementary Mode Setting Procedure. Complementary Mode Counter Operation. Example Complementary Mode Operation Example Cycle Updating Example Data Update Complementary Mode Example Initial Output Complementary Mode (1). Example Initial Output Complementary Mode (2). Example Complementary Mode Waveform Output (1). Example Complementary Mode Waveform Output (2). Example Complementary Mode Waveform Output (3). Example Complementary Mode 100% Waveform Output Example Complementary Mode 100% Waveform Output Example Complementary Mode 100% Waveform Output Example Complementary Mode 100% Waveform Output Example Complementary Mode 100% Waveform Output Example Toggle Output Waveform Synchronized with Output. Counter Clearing Synchronized with Another Channel Example Output Phase Switching External Input (1). Example Output Phase Switching External Input (2). Example Output Phase Switching Means Settings Example Output Phase Switching Means Settings Count Timing Internal Clock Operation. Count Timing External Clock Operation. Count Timing External Clock Operation (Phase Counting Mode). Output Compare Output Timing (Normal Mode/PWM Mode). Output Compare Output Timing (Complementary Mode/Reset Synchronous Mode). Input Capture Input Signal Timing. Counter Clear Timing (Compare Match) Counter Clear Timing (Input Capture) Buffer Operation Timing (Compare Match). Buffer Operation Timing (Input Capture) Interrupt Timing (Compare Match) Interrupt Timing (Input Capture) TCIV Interrupt Setting Timing. TCIU Interrupt Setting Timing. Timing Status Flag Clearing CPU. Timing Status Flag Clearing DTC/DMAC Activation Phase Difference, Overlap, Pulse Width Phase Counting Mode Contention between TCNT Write Clear Operations. Contention between TCNT Write Increment Operations Contention between Write Compare Match.
Rev. 2.0, 09/02, page xxvi xxxviii
Figure 11.74 Contention between Buffer Register Write Compare Match (Channel .297 Figure 11.75 Contention between Buffer Register Write Compare Match (Channels .298 Figure 11.76 Contention between Read Input Capture .298 Figure 11.77 Contention between Write Input Capture .299 Figure 11.78 Contention between Buffer Register Write Input Capture.300 Figure 11.79 TCNT_2 Write Overflow/Underflow Contention with Cascade Connection .301 Figure 11.80 Counter Value during Complementary Mode Stop.302 Figure 11.81 Buffer Operation Compare-Match Flags Reset Sync Mode.303 Figure 11.82 Reset Synchronous Mode Overflow Flag .304 Figure 11.83 Contention between Overflow Counter Clearing.304 Figure 11.84 Contention between TCNT Write Overflow.305 Figure 11.85 Error Occurrence Normal Mode, Recovery Normal Mode .309 Figure 11.86 Error Occurrence Normal Mode, Recovery Mode 1.310 Figure 11.87 Error Occurrence Normal Mode, Recovery Mode 2.311 Figure 11.88 Error Occurrence Normal Mode, Recovery Phase Counting Mode .312 Figure 11.89 Error Occurrence Normal Mode, Recovery Complementary Mode.313 Figure 11.90 Error Occurrence Normal Mode, Recovery Reset-Synchronous Mode .314 Figure 11.91 Error Occurrence Mode Recovery Normal Mode.315 Figure 11.92 Error Occurrence Mode Recovery Mode .316 Figure 11.93 Error Occurrence Mode Recovery Mode .317 Figure 11.94 Error Occurrence Mode Recovery Phase Counting Mode .318 Figure 11.95 Error Occurrence Mode Recovery Complementary Mode.319 Figure 11.96 Error Occurrence Mode Recovery Reset-Synchronous Mode .320 Figure 11.97 Error Occurrence Mode Recovery Normal Mode.321 Figure 11.98 Error Occurrence Mode Recovery Mode .322 Figure 11.99 Error Occurrence Mode Recovery Mode .323 Figure 11.100 Error Occurrence Mode Recovery Phase Counting Mode .324 Figure 11.101 Error Occurrence Phase Counting Mode, Recovery Normal Mode .325 Figure 11.102 Error Occurrence Phase Counting Mode, Recovery Mode .326 Figure 11.103 Error Occurrence Phase Counting Mode, Recovery Mode .327 Figure 11.104 Error Occurrence Phase Counting Mode, Recovery Phase Counting Mode.328 Figure 11.105 Error Occurrence Complementary Mode, Recovery Normal Mode.329 Figure 11.106 Error Occurrence Complementary Mode, Recovery Mode .330 Figure 11.107 Error Occurrence Complementary Mode, Recovery Complementary Mode.331
Rev. 2.0, 09/02, page xxvii xxxviii
Figure 11.108 Error Occurrence Complementary Mode, Recovery Complementary Mode. Figure 11.109 Error Occurrence Complementary Mode, Recovery Reset-Synchronous Mode Figure 11.110 Error Occurrence Reset-Synchronous Mode, Recovery Normal Mode. Figure 11.111 Error Occurrence Reset-Synchronous Mode, Recovery Mode Figure 11.112 Error Occurrence Reset-Synchronous Mode, Recovery Complementary Mode. Figure 11.113 Error Occurrence Reset-Synchronous Mode, Recovery Reset-Synchronous Mode Figure 11.114 Block Diagram Figure 11.115 Low-Level Detection Operation Figure 11.116 Output-Level Detection Operation Figure 11.117 Falling Edge Detection Operation Section Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 12.8 Figure 12.9 Watchdog Timer Block Diagram Operation Watchdog Timer Mode. Operation Interval Timer Mode. Timing Setting OVF. Timing Setting WOVF. Writing TCNT TCSR Writing RSTCSR. Contention between TCNT Write Increment. Example System Reset Circuit Using WDTOVF Signal
Section Serial Communication Interface (SCI) Figure 13.1 Block Diagram Figure 13.2 Data Format Asynchronous Communication (Example with 8-Bit Data, Parity, Stop Bits) Figure 13.3 Receive Data Sampling Timing Asynchronous Mode Figure 13.4 Relation between Output Clock Transmit Data Phase (Asynchronous Mode) Figure 13.5 Sample Initialization Flowchart Figure 13.6 Example Operation Transmission Asynchronous Mode (Example with 8-Bit Data, Parity, Stop Bit). Figure 13.7 Sample Serial Transmission Flowchart Figure 13.8 Example Operation Reception (Example with 8-Bit Data, Parity, Stop Bit). Figure 13.9 Sample Serial Reception Data Flowchart Figure 13.9 Sample Serial Reception Data Flowchart Figure 13.10 Example Communication Using Multiprocessor Format (Transmission Data H'AA Receiving Station
Rev. 2.0, 09/02, page xxviii xxxviii
Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart .394 Figure 13.12 Example Operation Reception (Example with 8-Bit Data, Multiprocessor Bit, Stop Bit) .395 Figure 13.13 Sample Multiprocessor Serial Reception Flowchart .396 Figure 13.13 Sample Multiprocessor Serial Reception Flowchart .397 Figure 13.14 Data Format Clocked Synchronous Communication (For LSB-First) .398 Figure 13.15 Sample Initialization Flowchart.399 Figure 13.16 Sample Transmission Operation Clocked Synchronous Mode .400 Figure 13.17 Sample Serial Transmission Flowchart .401 Figure 13.18 Example Operation Reception .402 Figure 13.19 Sample Serial Reception Flowchart.403 Figure 13.20 Sample Flowchart Simultaneous Serial Transmit Receive Operations.405 Figure 13.21 Example Clocked Synchronous Transmission with DMAC/DTC .409 Section Interface (IIC) Option Figure 14.1 Block Diagram Interface .412 Figure 14.2 Example Connection Interfaces (This Master Device) .413 Figure 14.3 Data Format (I2C Format) .436 Figure 14.4 Data Format (Serial Format) .436 Figure 14.5 Timing.436 Figure 14.6 Example Timing Operations Master-Transmission Mode (MLS WAIT 0).438 Figure 14.7 Example Continuous Transmission Timing Master-Transmission Mode (MLS WAIT 0).439 Figure 14.8 Example Timing Operations Master-Reception Mode (MLS WAIT ACKB .441 Figure 14.9 Example Timing Operations Slave-Reception Mode (MLS ACKB .443 Figure 14.10 Example Timing Operations Slave-Reception Mode (MLS ACKB .444 Figure 14.11 Example Timing Operations Slave-Transmission Mode (MLS .446 Figure 14.12 IRIC-Set Timing Control SCL.447 Figure 14.13 Block Diagram Noise Canceller .448 Figure 14.14 Example: Flowchart Operations Master-Transmission Mode .450 Figure 14.15 Example: Flowchart Operations Master-Reception Mode .451 Figure 14.16 Example: Flowchart Operations Slave-Reception Mode.452 Figure 14.17 Example: Flowchart Operations Slave-Transmission Mode .453 Figure 14.18 Points Caution Reading Data Received Master Reception .458 Figure 14.19 Flowchart Timing Execution Instruction that Sets Start Condition Re-Transmission.459 Figure 14.20 Timing Setting Stop Condition .460
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Figure 14.21 Scheme Slave Transmit Operation Figure 14.22 Scheme Setting Slave Mode Section Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Figure 15.7 Section Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Figure 16.7 Figure 16.8 Section Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Figure 18.8 Figure 18.9 Converter Block Diagram Converter (For Module) Conversion Timing External Trigger Input Timing Definitions Conversion Accuracy Definitions Conversion Accuracy Example Analog Input Circuit Example Analog Input Protection Circuit Compare Match Timer (CMT) Block Diagram. Counter Operation Count Timing Timing. Timing Clear CMCNT Write Compare Match Contention. CMCNT Word Write Increment Contention CMCNT Byte Write Increment Contention. Ports Port (SH7144). Port (SH7145). Port Port Port (SH7144). Port (SH7145). Port (SH7144) Port (SH7145) Port
Section Flash Memory (F-ZTAT Version) Figure 19.1 Block Diagram Flash Memory. Figure 19.2 Flash Memory State Transitions. Figure 19.3 Boot Mode. Figure 19.4 User Program Mode Figure 19.5 Flash Memory Block Configuration. Figure 19.6 Programming/Erasing Flowchart Example User Program Mode Figure 19.7 Flowchart Flash Memory Emulation Figure 19.8 Example Overlap Operation (RAM[2:0] B'000). Figure 19.9 Program/Program-Verify Flowchart. Figure 19.10 Erase/Erase-Verify Flowchart Section Mask
Rev. 2.0, 09/02, page xxxviii
Figure 20.1 Mask Block Diagram.595 Section Figure 22.1 Figure 22.2 Figure 22.3 Figure 22.4 Figure 22.5 Section Figure 23.1 Figure 23.2 Figure 23.3 Figure 23.4 Figure 23.5 Figure 23.6 Figure 23.7 Hitachi User Debug Interface (H-UDI) H-UDI Block Diagram .600 Data Input/Output Timing Chart (1).606 Data Input/Output Timing Chart (2).607 Data Input/Output Timing Chart (3).607 Serial Data Input/Output.609 Advanced User Debugger (AUD) Block Diagram .612 Example Data Output (32-Bit Output) .616 Example Output Case Successive Branches .616 AUDATA Input Format .617 Example Read Operation (Byte Read) .618 Example Write Operation (Longword Write) .618 Example Error Occurrence (Longword Read).618
Section Power-Down Modes Figure 24.1 Timing Software Standby Mode (Application Example) .631 Section Electrical Characteristics Figure 26.1 Output Load Circuit.669 Figure 26.2 System Clock Timing .670 Figure 26.3 EXTAL Clock Input Timing .671 Figure 26.4 Oscillation Settling Time.671 Figure 26.5 Reset Input Timing .673 Figure 26.6 Interrupt Signal Input Timing.673 Figure 26.7 Interrupt Signal Output Timing .674 Figure 26.8 Release Timing.674 Figure 26.9 Basic Cycle Waits) .676 Figure 26.10 Basic Cycle (One Software Wait).677 Figure 26.11 Basic Cycle (Two Software Waits Waits WAIT Signal) .678 Figure 26.12 DREQ0, DREQ1 Input Timing (1).679 Figure 26.13 DREQ0, DREQ1 Input Timing (2).680 Figure 26.14 DRAK Output Delay Time.680 Figure 26.15 Input/Output timing .681 Figure 26.16 Clock Input Timing.681 Figure 26.17 Port Input/Output timing .682 Figure 26.18 Timing .683 Figure 26.19 Input Timing.684 Figure 26.20 Input/Output Timing.685 Figure 26.21 Interface Timing.687 Figure 26.22 Input/Output Timing .687 Figure 26.23 External Trigger Input Timing.688
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Figure 26.24 Figure 26.25 Figure 26.26 Figure 26.27 Figure 26.28 Figure 26.29
H-UDI Clock Timing H-UDI TRST Timing H-UDI Input/Output Timing Reset Timing. Branch Trace Timing. Monitor Timing
Appendix Package Dimensions Figure FP-112B Figure FP-144F
Rev. 2.0, 09/02, page xxxii xxxviii
Tables
Section Table Initial Values Registers.17 Table Sign Extension Word Data Table Delayed Branch Instructions.19 Table Bit.20 Table Immediate Data Accessing Table Absolute Address Accessing.21 Table Displacement Accessing Table Addressing Modes Effective Addresses.22 Table Instruction Formats Table 2.10 Classification Instructions Section Table Table Table Section Table Table Table Operating Modes Selection Operating Modes Clock Mode Setting Operating Mode Configuration.44 Clock Pulse Generator Operating clock each module Damping Resistance Values Crystal Resonator Characteristics
Section Exception Processing Table Types Exception Processing Priority Order.53 Table Timing Exception Source Detection Start Exception Processing.54 Table Exception Processing Vector Table Table Calculating Exception Processing Vector Table Addresses.56 Table Reset Status.57 Table Cycles Address Errors.59 Table Interrupt Sources.60 Table Interrupt Priority Order Table Types Exceptions Triggered Instructions Table 5.10 Generation Exception Sources Immediately after Delayed Branch Instruction Interrupt-Disabled Instruction.63 Table 5.11 Stack Status after Exception Processing Ends Section Table Table Table Interrupt Controller (INTC) Configuration.69 Interrupt Exception Processing Vectors Priorities Interrupt Response Time.85
Section Data Transfer Controller (DTC) Table Interrupt Sources, Vector Addresses, Corresponding DTEs .113
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Table Table Table Table Table Section Table Table Table Section Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 10.6
Normal Mode Register Functions. Repeat Mode Register Functions Block Transfer Mode Register Functions Execution State DTC. State Counts Needed Execution State State Controller (BSC) Configuration. Address Map. Access On-chip Peripheral Registers
Direct Memory Access Controller (DMAC) DMAC Configuration. Selecting External Request Modes with Bits Selecting On-Chip Peripheral Module Request Modes with Bits Supported Transfers. Relationship Request Modes Modes Transfer Category Transfer Conditions Register Values Transfer between On-chip External Memory Table 10.7 Transfer Conditions Register Values Transfer between External External Device with DACK. Table 10.8 Transfer Conditions Register Values Transfer between Converter (A/D1) On-chip Memory. Table 10.9 DMAC Internal Status Table 10.10 Transfer Conditions Register Values Transfer between External Memory SCI1 Transmit Side. Section Multi-Function Timer Pulse Unit (MTU) Table 11.1 Functions. Table 11.2 Pins Table 11.3 CCLR0 CCLR2 (channels Table 11.4 CCLR0 CCLR2 (channels Table 11.5 TPSC0 TPSC2 (channel Table 11.6 TPSC0 TPSC2 (channel Table 11.7 TPSC0 TPSC2 (channel Table 11.8 TPSC0 TPSC2 (channels Table 11.9 Table 11.10 TIORH_0 (channel Table 11.11 TIORL_0 (channel Table 11.12 TIOR_1 (channel Table 11.13 TIOR_2 (channel Table 11.14 TIORH_3 (channel Table 11.15 TIORL_3 (channel Table 11.16 TIORH_4 (channel
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Table 11.17 Table 11.18 Table 11.19 Table 11.20 Table 11.21 Table 11.22 Table 11.23 Table 11.24 Table 11.25 Table 11.26 Table 11.27 Table 11.28 Table 11.29 Table 11.30 Table 11.31 Table 11.32 Table 11.33 Table 11.34 Table 11.35 Table 11.36 Table 11.37 Table 11.38 Table 11.39 Table 11.40 Table 11.41 Table 11.42 Table 11.43 Table 11.44 Table 11.45
TIORL_4 (channel 4).212 TIORH_0 (channel .213 TIORL_0 (channel 0).214 TIOR_1 (channel .215 TIOR_2 (channel .216 TIORH_3 (channel .217 TIORL_3 (channel 3).218 TIORH_4 (channel .219 TIORL_4 (channel 4).220 Output Level Select Function .230 Output Level Select Function .231 Output level Select Function.233 Register Combinations Buffer Operation .242 Cascaded Combinations.245 Output Registers Output Pins .248 Phase Counting Mode Clock Input Pins .252 Up/Down-Count Conditions Phase Counting Mode 1.253 Up/Down-Count Conditions Phase Counting Mode 2.254 Up/Down-Count Conditions Phase Counting Mode 3.255 Up/Down-Count Conditions Phase Counting Mode 4.256 Output Pins Reset-Synchronized Mode .258 Register Settings Reset-Synchronized Mode.258 Output Pins Complementary Mode .261 Register Settings Complementary Mode .262 Registers Counters Requiring Initialization .268 Interrupts .285 Mode Transition Combinations .307 Configuration.340 Combinations.340
Section Watchdog Timer Table 12.1 Configuration.350 Table 12.2 Interrupt Source Interval Timer Mode) .357 Section Table 13.1 Table 13.2 Table 13.3 Table 13.3 Table 13.3 Table 13.3 Table 13.4 Serial Communication Interface (SCI) Configuration.363 Relationships between Setting Effective Rate .373 Settings Various Rates (Asynchronous Mode) .374 Settings Various Rates (Asynchronous Mode) .374 Settings Various Rates (Asynchronous Mode) .375 Settings Various Rates (Asynchronous Mode) .375 Maximum Rate Each Frequency when Using Baud Rate Generator (Asynchronous Mode) .376 Table 13.5 Maximum Rate with External Clock Input (Asynchronous Mode) .377
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Table 13.6 Settings Various Rates (Clocked Synchronous Mode) Table 13.6 Settings Various Rates (Clocked Synchronous Mode) Table 13.6 Settings Various Rates (Clocked Synchronous Mode) Table 13.6 Settings Various Rates (Clocked Synchronous Mode) Table 13.7 Maximum Rate with External Clock Input (Clocked Synchronous Mode) Table 13.8 Serial Transfer Formats (Asynchronous Mode). Table 13.9 Status Flags Receive Data Handling Table 13.10 Interrupt Sources. Section Interface (IIC) Option Table 14.1 Configuration. Table 14.2 Transfer Format Table 14.3 Setting Transfer Clock. Table 14.4 Setting Counter Table 14.5 Description IRIC Table 14.6 Relationship between Flags Transfer States Table 14.7 Data Format: Description Symbols Table 14.8 Examples Operations which Used Table 14.9 Timing (output SDA) Table 14.10 Tolerance Rise Time (tSr) Table 14.11 Timing (when effect tSr/tSf maximum) Section Table 15.1 Table 15.2 Table 15.3 Table 15.4 Table 15.5 Table 15.6 Converter Configuration. Channel Select List Conversion Time (Single Mode). Conversion Time (Scan Mode) Converter Interrupt Source. Analog Specifications.
Section Function Controller (PFC) Table 17.1 SH7144 Multiplexed Pins (Port Table 17.2 SH7144 Multiplexed Pins (Port Table 17.3 SH7144 Multiplexed Pins (Port Table 17.4 SH7144 Multiplexed Pins (Port Table 17.5 SH7144 Multiplexed Pins (Port Table 17.6 SH7144 Multiplexed Pins (Port Table 17.7 SH7145 Multiplexed Pins (Port Table 17.8 SH7145 Multiplexed Pins (Port Table 17.9 SH7145 Multiplexed Pins (Port Table 17.10 SH7145 Multiplexed Pins (Port Table 17.11 SH7145 Multiplexed Pins (Port Table 17.12 SH7145 Multiplexed Pins (Port Table 17.13 SH7144 Functions Each Mode
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Table 17.13 SH7144 Functions Each Mode .501 Table 17.14 SH7145 Functions Each Mode .505 Table 17.14 SH7145 Functions Each Mode .510 Section Table 18.1 Table 18.2 Table 18.3 Table 18.4 Table 18.5 Table 18.6 Section Table 19.1 Table 19.2 Table 19.3 Table 19.4 Table 19.5 Ports Port Data Register (PADR) Read/Write Operations .556 Port Data Register (PBDR) Read/Write Operations.558 Port Data Register (PCDR) Read/Write Operations.560 Port Data Register (PDDR) Read/Write Operations .565 Port Data Register (PEDRL) Read/Write Operations .568 Port Data Register (PFDR) Read/Write Operations .570 Flash Memory (F-ZTAT Version) Differences between Boot Mode User Program Mode .573 Configuration.577 Setting On-Board Programming Modes.581 Boot Mode Operation .583 Peripheral Clock Frequencies which Automatic Adjustment Rate Possible .583
Section Hitachi User Debug Interface (H-UDI) Table 22.1 H-UDI Pins .601 Table 22.2 Serial Transfer Characteristics H-UDI Registers.602 Section Advanced User Debugger (AUD) Table 23.1 Configuration .612 Table 23.2 Ready Flag Format.618 Section Power-Down Modes Table 24.1 Internal Operation States Each Mode .622 Table 24.2 Configuration.623 Section Electrical Characteristics Table 26.1 Absolute Maximum Ratings .665 Table 26.2 Characteristics .666 Table 26.3 Permitted Output Current Values.668 Table 26.4 Clock Timing .670 Table 26.5 Control Signal Timing .672 Table 26.6 Timing .675 Table 26.7 Direct Memory Access Controller Timing .679 Table 26.8 Multi-Function Timer Pulse Unit Timing .681 Table 26.9 Port Timing.682 Table 26.10 Watchdog Timer Timing.683 Table 26.11 Serial Communication Interface Timing.684 Table 26.12 Interface Timing .686 Table 26.13 Output Enable Timing.687
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Table 26.14 Table 26.15 Table 26.16 Table 26.17 Table 26.18
Converter Timing. H-UDI Timing Timing. Converter Characteristics. Flash Memory Characteristics
Appendix States Table States (SH7144). Table States (SH7145). Table States Table States Table States Appendix States Related Signals Table States Related Signals (1). Table States Related Signals (2). Table States Related Signals (3).
Rev. 2.0, 09/02, page xxxviii xxxviii
Section Overview
SH7144 Series single-chip RISC (Reduced Instruction Computer) microcomputers integrate Hitachi-original RISC core with peripheral functions required system configuration. SH7144 series RISC-type instruction set. Most instructions executed state (one system clock cycle), which greatly improves instruction execution speed. addition, 32-bit internal-bus architecture enhances data processing power. With this CPU, become possible assemble cost, high performance/high-functioning systems, even applications that were previously impossible with microcomputers, such real-time control, which demands high speeds. addition, SH7144 series includes on-chip peripheral functions necessary system configuration, such direct memory access controller (DMAC), large-capacity RAM, timers, serial communication interface (SCI), converter, interrupt controller (INTC), ports. option, interface also incorporated. SRAM directly connected SH7144 means external memory access support function. This greatly reduces system cost. There versions on-chip ROM: F-ZTAT (Flexible Zero Turn Around Time) that includes flash memory, mask ROM. flash memory programmed with programmer that supports SH7144 series programming, also programmed erased software. This enables chip re-programmed user-site while mounted board. Note: F-ZTAT
registered trademark Hitachi, Ltd.
Features
Central processing unit with internal 32-bit RISC (Reduced Instruction Computer) architecture Instruction length: 16-bit fixed length improved code efficiency Load-store architecture (basic operations executed between registers) Sixteen 32-bit general registers Five-stage pipeline On-chip multiplier: multiplication operations bits bits bits) executed four cycles language-oriented basic instructions Various peripheral functions Direct memory access controller (DMAC) Data transfer controller (DTC)
Rev. 2.0, 09/02, page
Multifunction timer/pulse unit (MTU) Compare match timer (CMT) Watchdog timer (WDT) Asynchronous clocked synchronous serial communication interface (SCI) interface (IIC)*
10-bit converter Clock pulse generator User break controller (UBC) Hitachi user debug interface (H-UDI)* Advanced user debugger (AUD)* Notes: Option Supported only flash memory version. On-chip memory
Flash memory Version Mask Version Model HD64F7144F50 HD64F7145F50 HD6437144F50* HD6437145F50* kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes Remarks
Note: Under development
ports
Model HD64F7144F50/ HD6437144F50* HD64F7145F50/ HD6437145F50* Note: Under development Pins Input-only Pins
Supports various power-down states Compact package
Model HD64F7144F50/ HD6437144F50* HD64F7145F50/ HD6437145F50* Note: Under development Package QFP-112 LQFP-144 (Code) FP-112B FP-144F Body Size 20.0 20.0 Pitch 0.65
20.0 20.0
Rev. 2.0, 09/02, page
Internal Block Diagram
/SDA0 /A21/ /A20/ /A19/ PA0/RXD0 /A18/ PA1/TXD0 /SCL0 PB1/A17
EXTAL XTAL PLLVcc PLLCAP PLLVss FWP* AVcc AVss DBGMD
Note: Modules F-ZTAT reision only
;;;; ;;;; ;;;; ;;;; ;;;; ;;;; ;;;; ;;;;
PA9/TCLKD/ PA8/TCLKC/ PA7/TCLKB/ PA6/TCLKA/ PA5/SCK1/ PA2/SCK0/ PA3/RXD1 PA4/TXD1 PA14/ PA13/ PA12/ PA11/ PA10/ PB0/A16 PB9/ PB8/ PB7/ PB6/ PB5/ PB4/ PB3/ PB2/
PA15/CK
PC15/A15 PC14/A14 PC13/A13 PC12/A12 PC11/A11 PC10/A10 PC9/A9 PC8/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD15/D15/ PD14/D14/AUDCK PD13/D13/AUDMD PD12/D12/ PD11/D11/AUDATA3 PD10/D10/AUDATA2 PD9/D9/AUDATA1 PD8/D8/AUDATA0 PD7/D7 PD6/D6 PD5/D5 PD4/D4 PD3/D3 PD2/D2 PD1/D1 PD0/D0
AUD*
Flash ROM/ mask 256kB
Data transfer Controller
Direct memory access controller
Interrupt controller
User break controller
state controller
Serial communication interface channels)
Multifunction timer pulse unit
Compare match timer channels)
converter
Watchdog timer
interface
H-UDI*
PE15/TIOC4D/DACK1/ PE14/TIOC4C/DACK0 PE13/TIOC4B/ PE12/TIOC4A/TXD3 PE11/TIOC3D/RXD3 PE10/TIOC3C/TXD2 PE9/TIOC3B/SCK3 PE8/TIOC3A/SCK2 PE7/TIOC2B/RXD2 PE6/TIOC2A/SCK3 PE5/TIOC1B/TXD3 PE4/TIOC1A/RXD3/TCK PE3/TIOC0D/DRAK1/TDO /TDI PE2/TIOC0C/ PE1/TIOC0B/DRAK0/ PE0/TIOC0A/ /TMS
PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0
Peripheral address (12bits) Peripheral data (16bits) Internal address (32bits) Internal upper data (16bits) Internal lower data (16bits)
Figure Internal Block Diagram SH7144
Rev. 2.0, 09/02, page
/SDA0
/SCL0
PC15/A15 PC14/A14 PC13/A13 PC12/A12 PC11/A11 PC10/A10 PC9/A9 PC8/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD31/D31/ PD30/D30/ PD29/D29/ PD28/D28/ PD27/D27/DACK1 PD26/D26/DACK0 PD25/D25/ PD24/D24/ PD23/D23/ PD22/D22/ PD21/D21/ PD20/D20/ PD19/D19/ PD18/D18/ PD17/D17/ PD16/D16/ PD15/D15 PD14/D14 PD13/D13 PD12/D12 PD11/D11 PD10/D10 PD9/D9 PD8/D8 PD7/D7 PD6/D6 PD5/D5 PD4/D4 PD3/D3 PD2/D2 PD1/D1 PD0/D0 /AUDCK /AUDMD /AUDATA3 /AUDATA2 /AUDATA1 /AUDATA0
/DRAK1
/DRAK0
EXTAL XTAL PLLVcc PLLCAP PLLVss FWP* AVcc AVref AVss DBGMD
Note: Modules F-ZTAT reision only
;;;; ;;;; ;;;; ;;;; ;;;; ;;;;
/A21/ /A20/ /A19/ PA9/TCLKD/ PA8/TCLKC/ PA7/TCLKB/ PA6/TCLKA/ PA5/SCK1/ PA2/SCK0/ PA3/RXD1 PA0/RXD0 /A18/ PA4/TXD1 PA1/TXD0 PB1/A17 PA13/ PA12/ PA11/ PA10/
PA15/CK
PA23/
PA22/
PA19/
PA16/
PA18/
PA17/
PA14/
PA21
PA20
AUD*
Flash ROM/ mask 256kB
Data transfer Controller
Direct memory access controller
Interrupt controller
User break controller
state controller
Serial communication interface channels)
Multifunction timer pulse unit
Compare match timer channels)
converter
Watchdog timer
interface
H-UDI*
PE15/TIOC4D/DACK1/ PE14/TIOC4C/DACK0 PE13/TIOC4B/ PE12/TIOC4A/TXD3/TCK PE11/TIOC3D/RXD3/TDO PE10/TIOC3C/TXD2/TDI PE9/TIOC3B/SCK3/ PE8/TIOC3A/SCK2/TMS PE7/TIOC2B/RXD2 PE6/TIOC2A/SCK3/AUDATA0 PE5/TIOC1B/TXD3/AUDATA1 PE4/TIOC1A/RXD3/AUDATA2 PE3/TIOC0D/DRAK1/AUDATA3 PE2/TIOC0C/ PE1/TIOC0B/DRAK0/AUDMD /AUDCK PE0/TIOC0A/
PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0
PB0/A16
PB9/
PB8/
PB7/
PB6/
PB5/
PB4/
PB3/
PB2/
Peripheral address (12bits) Peripheral data (16bits) Internal address (32bits) Internal upper data (16bits) Internal lower data (16bits)
Figure Block Diagram SH7145
Rev. 2.0, 09/02, page
Arrangement
PD10/D10/AUDATA2*4 PD8/D8/AUDATA0*4 PD11/D11/AUDATA3*4 PD9/D9/AUDATA1*4
Vcc(FWP*1)
PA15/CK
PLLCAP
PD0/D0
PD1/D1
PD2/D2
PD3/D3
PD4/D4
PD5/D5
PD6/D6
PD7/D7
PLLVss
PLLVcc
EXTAL
XTAL
PE0/TIOC0A/ PE1/TIOC0B/DRAK0/ /TMS*4
PE14/TIOC4C/DACK0
PD12/D12/
PE2/TIOC0C/ /TDI* PE3/TIOC0D/DRAK1/TDO* PE4/TIOC1A/RXD3/TCK* PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 AVss PF6/AN6 PF7/AN7 AVcc PE5/TIOC1B/TXD3 PE6/TIOC2A/SCK3 PE7/TIOC2B/RXD2 PE8/TIOC3A/SCK2 PE9/TIOC3B/SCK3
PD13/D13/AUDMD*4 PD14/D14/AUDCK*4 PD15/D15/ PA0/RXD0 PA1/TXD0 PA2/SCK0/ PA3/RXD1 PA4/TXD1 PA5/SCK1/ PA6/TCLKA/ PA7/TCLKB/ PA8/TCLKC/ PA9/TCLKD/ PA10/ PA11/ PA12/ PA13/ PA14/ Vss(DBGMD*3) PB9/ PB8/ PB7/ PB6/ /A21/ /A20/ /A19/ /A18/
QFP-112 (Top view)
PE10/TIOC3C/TXD2 PE11/TIOC3D/RXD3 PE12/TIOC4A/TXD3 PE13/TIOC4B/
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
PC5/A5
/SDA0 /SCL0 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 PC15/A15 PB0/A16 PB1/A17 PB4/ PB5/
PE15/TIOC4D/DACK1/
PB2/
Notes
Fixed Mask version, Used F-ZTAT version (Used write made). Used E10A debugging mode. Used processing pin. F-ZTAT version. Refer table below
Used E10A debugging mode. Fixed mask version, used DBGMD F-ZTAT version. Valid only F-ZTAT version (invalid only mask version). Processing Product type Mask version F-ZTAT version (when using E10A) F-ZTAT version (Not when using E10A) Fixed Fixed Processing Pull-up
PB3/
Pull-down
Figure SH7144 Arrangement
Rev. 2.0, 09/02, page
Vcc(FWP*1)
PD10/D10
PD11/D11
PD12/D12
PD13/D13
PD14/D14
107106 103102 PE0/TIOC0A/ PE2/TIOC0C/ /AUDCK*4
PD15/D15
PA15/CK
PLLCAP
PD0/D0
PD1/D1
PD2/D2
PD3/D3
PD4/D4
PD5/D5
PD6/D6
PD7/D7
PD8/D8
PD9/D9
PLLVss
PLLVcc
EXTAL
PA17/
PA16/
XTAL
PD16/D16/ PD17/D17/ PD18/D18/ PD19/D19/ PD20/D20/ PD21/D21/ PD22/D22/ PD23/D23/ PD24/D24/ PD25/D25/
/AUDATA0*4 /AUDATA1*4 /AUDATA2*4 /AUDATA3*4 /AUDCK*
PE1/TIOC0B/DRAK0/AUDMD*
PE3/TIOC0D/DRAK1/AUDATA3*4 PE4/TIOC1A/RXD3/AUDATA2* PE6/TIOC2A/SCK3/AUDATA0*
PE5/TIOC1B/TXD3/AUDATA1*4
/AUDMD*4
PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 AVss PF6/AN6 PF7/AN7 AVref AVcc PA0/RXD0 PA1/TXD0 PA2/SCK0/ PA3/RXD1 PA4/TXD1 PA5/SCK1/ PE7/TIOC2B/RXD2 PE8/TIOC3A/SCK2/TMS*4 PE9/TIOC3B/ *4/SCK3 PE11/TIOC3D/TDO*4/RXD3 PE12/TIOC4A/TCK*4/TXD3 PE13/TIOC4B/ PE10/TIOC3C/TXD2/TDI*4
PD26/D26/DACK0 PD27/D27/DACK1 PD28/D28/ PD29/D29/ PA6/TCLKA/ PA7/TCLKB/ PA8/TCLKC/ PA9/TCLKD/ PA10/ PA11/ PA12/ PA13/ PD30/D30/ PD31/D31/ PA14/ Vss(DBGMD*3 PB9/ PB8/ PB7/ PB6/ /A20/ /A19/ /A18/ /A21/
LQFP-144 (Top view)
/SDA0
/SCL0
/DRAK0
PE14/TIOC4C/DACK0
PC10/A10
PC11/A11
PC12/A12
PC13/A13
PC14/A14
PC15/A15
PB0/A16
PB1/A17
/DRAK1
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
PC5/A5
PC6/A6
PC7/A7
PC8/A8
PC9/A9
PA21
PA20
PB4/
PB5/
PA23/
PA22/
PE15/TIOC4D/DACK1/
PA19/
PB2/
Notes
Fixed Mask version, Used F-ZTAT version (Used write made). Used E10A debugging mode. Used processing pin. F-ZTAT version. Refer table below
Used E10A debugging mode. Fixed mask version, DBGMD F-ZTAT version. Valid only F-ZTAT version (invalid only mask version). Processing Product type Mask version F-ZTAT version (when using E10A) F-ZTAT version (Not when using E10A) Fixed Fixed Processing Pull-up Pull-down
Figure SH7145 Arrangement
Rev. 2.0, 09/02, page
PB3/
PA18/
Type Power Supply
Functions
Symbol Input Name Power supply Function Power supply pins. Connect these pins system power supply. chip does operate when some these pins opened. Ground pins. Connect these pins system power supply chip does operate when some these pins opened. Power supply supplying power on-chip PLL. On-chip oscillator ground pin. External capacitance on-chip oscillator.
Input
Ground
Clock
PLLVCC PLLVSS PLLCAP EXTAL
Input Input Input Input
Power supply Ground Capacitance
External clock connection crystal resonator. external clock supplied from EXTAL pin.) examples crystal resonator connection external clock input, section Clock Pulse Generator. Crystal connection crystal resonator. examples crystal resonator connection external clock input, section Clock Pulse Generator. Supplies system clock external devices. operating mode. Inputs these pins should changed during operation. flash memory. This only used F-ZTAT version. Programming erasing flash memory protected. This used mask version.
XTAL
Input
Operating mode control
Output Input
System clock output mode
Input
Protection against write operation into Flash memory
Rev. 2.0, 09/02, page
Type System control
Symbol MRES WDTOVF*
Input Input Output
Name Power reset Manual reset
Function When this driven low, chip becomes power reset state. When this driven low, chip becomes manual reset state.
Watchdog Output signal watchdog timer timer overflow overflow. this needs pulled-down, resistance value must higher. request acknowledge External device request release mastership setting this low. Shows that mastership been released external device. device that issued BREQ signal know that mastership been released itself receiving BACK signal.
BREQ BACK
Input Output
Interrupts
IRQ7 IRQ3 IRQ6 IRQ2 IRQ5 IRQ1 IRQ4 IRQ0 IRQOUT
Input Input
Non-maskable Non-maskable interrupt pin. this interrupt used, should fixed high. Interrupt request These pins request maskable interrupt. level input edge input selected case edge input, rising edge, falling edge, both selected.
Output
Interrupt Shows that interrupt cause request output occurred. interrupt cause recognized even release state. Address Data Output address. SH7144: Bi-directional 16-bit SH7145: Bi-directional 32-bit
Address Data
SH7144: SH7145:
Output Input/ Output
control
WRHH (SH7145 only) WRHL (SH7145 only)
Output Output Output
Chip select Read Write
Chip select signal external memory devices. Shows reading from external devices. Shows writing into bits (bits external data. Shows writing into bits (bits external data.
Output
Write
Rev. 2.0, 09/02, page
Type control
Symbol WAIT
Output Output Input Input Output
Name Write upper half Write lower half Wait transfer request
Function Shows writing into upper bits (bits external data. Shows writing into lower bits (bit7 bit0) external data. Inserts wait cycles into cycle when accessing external spaces. request input pins from external device.
Direct memory access controller (DMAC)
DREQ0 DREQ1 DRAK0 DRAK1 DACK0 DACK1
DREQ request Outputs acknowledge signal acknowledge external device that input transfer request signal. transfer strobe Outputs strobe external device that input transfer request signal.
Output
Multi function TCLKA timer-pulse TCLKB unit (MTU) TCLKC TCLKD TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B
Input
External clock These pins input external clock. input timer input TGRA_0 TGRD_0 input capture capture/output input/output compare output/PWM output compare pins. (channel input TGRA_1 TGRB_1 input capture capture/output input/output compare output/PWM output compare pins. (channel input TGRA_2 TGRB_2 input capture capture/output input/output compare output/PWM output compare pins. (channel input TGRA_3 TGRD_3 input capture capture/output input/output compare output/PWM output compare pins. (channel input TGRA_4 TGRB_4 input capture capture/output input/output compare output/PWM output compare pins. (channel
Input/ Output
Input/ Output
TIOC2A TIOC2B
Input/ Output
TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D
Input/ Output
Input/ Output
Rev. 2.0, 09/02, page
Type
Symbol
Output Input Input/ Output Input/ Output
Name Transmitted data
Function Data output pins.
Serial TXD3 communication TXD0 interface (SCI) RXD3 RXD0 SCK3 SCK0 interface (option)
Received data Data input pins. Serial clock clock input/ output
Clock input/output pins. clock input/output pins, which drive bus. Output clock NMOS open-drain method. data input/output pins, which drive bus. Output data NMOS open-drain method. Input pins signal request output pins waveforms become high impedance state. Analog input pins.
SCL0
SDA0
Input/ Output
data input/ output
Output control POE3 POE0 converter
Input
Port output control Analog input pins
Input ADTRG Input
Input trigger input external trigger start conversion conversion Analog reference power supply Analog power supply Analog reference power supply pin, SH7144, this internally connected AVcc pin). Power supply converter. When converter used, connect this system power supply (+3.3
AVref (SH7145 only) AVCC
Input
Input
AVSS
Input
Analog ground ground converter. Connect this system power supply General purpose port SH7144: 16-bit general purpose input/output pins. SH7145: 24-bit general purpose input/output pins. General purpose port General purpose port 10-bit general purpose input/output pins. 16-bit general purpose input/output pins.
port
SH7144 Input/ PA15 Output SH7145 PA23 Input/ Output PC15 Input/ Output
Rev. 2.0, 09/02, page
Type port
Symbol SH7144: PD15 SH7145: PD31
Input/ Output
Name General purpose port
Function SH7144: 16-bit general purpose input/output pins. SH7145: 32-bit general purpose input/output pins.
PE15 Input/ Output Hitachi user debug interface (H-UDI) (flash version only) TRST Input Input Input Input Output Input
General purpose port General purpose port Test clock Test mode select Test data input Test data output Test reset data
16-bit general purpose input/output pins. 8-bit general purpose input pins. Test clock input pin. Test mode select signal input pin. Instruction/data serial input pin. Instruction/data serial output pin. Initialization signal input pin. Branch trace mode: Branch destination address output pins. monitor mode: Monitor address input/data input/output pins.
Advanced user AUDATA3 Input/ debugger AUDATA0 Output (AUD) (flash version only) AUDRST Input AUDMD Input
reset mode
Reset signal input pin. Mode select signal input pin. Branch trace mode: monitor mode: High
AUDCK
Input/ Output
clock
Branch trace mode: Synchronous clock output pin. monitor mode: Synchronous clock input pin.
AUDSYNC
Input/ Output
synchronization signal
Branch trace mode: Data start position identification signal output pin. monitor mode: Data start position identification signal input pin.
Rev. 2.0, 09/02, page
Type interface (flash version only)
Symbol
Name Break mode acknowledge
Function Shows that E10A entered break mode. Refer "E10A emulator user's manual SH7144 (provisional name)" detail connection E10A. Enables functions E10A emulator. Input normal operation (other than debug mode). debug mode, input high user board. Refer "E10A emulator user's manual SH7144 (provisional name)" detail connection E10A.
ASEBRKAK Output
DBGMD
Input
Debug mode
Note: pull-down WDTOVF pin. this needs pulled-down, however, resistance value must higher.
Rev. 2.0, 09/02, page
Section
Features
General-register architecture Sixteen 32-bit general registers Sixty-two basic instructions Eleven addressing modes Register direct [Rn] Register indirect [@Rn] Register indirect with post-increment [@Rn+] Register indirect with pre-decrement [@-Rn] Register indirect with displacement [@disp:4,Rn] Register indirect with index [@R0, indirect with displacement [@disp:8,GBR] indirect with index [@R0,GBR] Program-counter relative with displacement [@disp:8,PC] Program-counter relative [disp:8/disp:12/Rn] Immediate [#imm:8]
Register Configuration
register consists sixteen 32-bit general registers, three 32-bit control registers, four 32-bit system registers. 2.2.1 General Registers (Rn)
sixteen 32-bit general registers (Rn) numbered R15. General registers used data processing address calculation. also used index register. Several instructions have fixed their only usable register. used hardware stack pointer (SP). Saving recovering status register (SR) program counter (PC) exception processing accomplished referencing stack using R15.
CPUS201A_010020020700
Rev. 2.0, 09/02, page
General registers (Rn)
R0*1 R15, (hardware stack pointer)*2
Status register (SR)
Global base register (GBR)
Vector base register (VBR)
Multiply-accumulate register (MAC)
MACH MACL
Procedure register
Program counter (PC)
Notes: functions index register indirect indexed register addressing mode indirect indexed addressing mode. some instructions, functions fixed source register destination register. functions hardware stack pointer (SP) during exception processing.
Figure Internal Registers
Rev. 2.0, 09/02, page
2.2.2
Control Registers
control registers consist three 32-bit registers: status register (SR), global base register (GBR), vector base register (VBR). status register indicates processing states. global base register functions base address indirect addressing mode transfer data registers on-chip peripheral modules. vector base register functions base address exception processing vector area (including interrupts). Status Register (SR):
Name Initial Value Undefined Undefined Used DIV0U, DIV0S, DIV1 instructions. Used DIV0U, DIV0S, DIV1 instructions. Description Reserved bits. This always read write value should always
Rev. 2.0, 09/02, page
Name
Initial Value Undefined Undefined
Description Interrupt mask bits.
Reserved bits. This always read write value should always Used instruction. MOVT, CMP/cond, TAS, TST, (BT/S), (BF/S), SETT, CLRT instructions indicate true false (0). ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S, DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, ROTCL instructions also indicate carry/borrow overflow/underflow.
Global Base Register (GBR): Indicates base address indirect addressing mode. indirect addressing mode used data transfer on-chip peripheral modules register areas logic operations. Vector Base Register (VBR): Indicates base address exception processing vector area. 2.2.3 System Registers
System registers consist four 32-bit registers: high multiply accumulate registers (MACH MACL), procedure register (PR), program counter (PC). Multiply-and-Accumulate Registers (MAC): Registers store results multiply-andaccumulate operations. Procedure Register (PR): Registers store return address from subroutine procedure. Program Counter (PC): Registers indicate current instruction addresses four, that address second instruction after current instruction.
Rev. 2.0, 09/02, page
2.2.4
Initial Values Registers
Table lists values registers after reset. Table Initial Values Registers
Classification General registers Register (SP) Control registers System registers MACH, MACL, Initial Value Undefined Value stack pointer vector address table Bits 1111 (H'F), reserved bits other bits undefined Undefined H'00000000 Undefined Value program counter vector address table
2.3.1
Data Formats
Data Format Registers
Register operands always longwords bits). size memory operand byte bits) word bits), changed into longword expanding sign-part when loaded into register.
Longword
Figure Data Format Registers 2.3.2 Data Formats Memory
Memory data formats classified into bytes, words, longwords. Byte data accessed from address. Locate, however, word data address longword data Otherwise, address error will occur attempt made access word data starting from address other than longword data starting from address other than such cases, data accessed cannot guaranteed. hardware stack area, pointed hardware stack pointer (SP, R15), uses only longword data starting from address because this area holds program counter status register.
Rev. 2.0, 09/02, page
Address Address Byte Address Address Word Longword Byte
Address
Address Byte Word Byte
Figure Data Formats Memory 2.3.3 Immediate Data Format
Byte bit) immediate data resides instruction code. Immediate data accessed MOV, ADD, CMP/EQ instructions sign-extended handled registers longword data. Immediate data accessed TST, AND, instructions zero-extended handled longword data. Consequently, instructions with immediate data always clear upper bits destination register. Word longword immediate data located instruction code, instead stored memory table. immediate data transfer instruction (MOV) accesses memory table using relative addressing mode with displacement.
2.4.1
Instruction Features
RISC-Type Instruction
instructions RISC type. This section details their functions. 16-Bit Fixed Length: instructions bits long, increasing program code efficiency. Instruction State: microcomputer execute basic instructions state using pipeline system. state MHz. Data Length: Longword standard data length operations. Memory accessed bytes, words, longwords. Byte word data accessed from memory sign-extended handled longword data. Immediate data sign-extended arithmetic operations zeroextended logic operations. also handled longword data.
Rev. 2.0, 09/02, page
Table Sign Extension Word Data
This MOV.W Description Example Conventional ADD.W #H'1234,R0
.DATA.W
@(disp,PC),R1 Data sign-extended bits, becomes R1,R0 H'00001234. next operated upon instruction. H'1234
Note: @(disp, accesses immediate data.
Load-Store Architecture: Basic operations executed between registers. operations that involve memory access, data loaded registers executed (load-store architecture). Instructions such that manipulate bits, however, executed directly memory. Delayed Branch Instructions: Unconditional branch instructions delayed branch instructions. With delayed branch instruction, branch taken after execution instruction following delayed branch instruction. This reduces disturbance pipeline control case branch instructions. There types conditional branch instructions: delayed branch instructions ordinary branch instructions. Table Delayed Branch Instructions
This TRGET R1,R0 Description Executes before branching TRGET. Example Conventional ADD.W R1,R0 TRGET
Operations: 16-bit 16-bit 32-bit multiply operations executed states. 16-bit 16-bit 64-bit 64-bit multiply-and-accumulate operations executed three states. 32-bit 32-bit 64-bit multiply 32-bit 32-bit 64-bit 64-bit multiply-and-accumulate operations executed four states. Bit: status register changes according result comparison. Whether conditional branch taken taken depends upon condition (true/false). number instructions that change kept minimum improve processing speed.
Rev. 2.0, 09/02, page
Table
This CMP/GE CMP/EQ R1,R0 TRGET0 TRGET1 #-1,R0 #0,R0 TRGET Description when program branches TRGET0 when TRGET1 when changed ADD. when program branches Example Conventional CMP.W SUB.W R1,R0 TRGET0 TRGET1 #1,R0 TRGET
Immediate Data: Byte (8-bit) immediate data located instruction code. Word longword immediate data located instruction codes memory table. immediate data transfer instruction (MOV) accesses memory table using relative addressing mode with displacement. Table Immediate Data Accessing
Classification 8-bit immediate 16-bit immediate This MOV.W #H'12,R0 @(disp,PC),R0 .DATA.W 32-bit immediate MOV.L H'1234 @(disp,PC),R0 .DATA.L H'12345678 Note: @(disp, accesses immediate data. MOV.L #H'12345678,R0 Example Conventional MOV.B MOV.W #H'12,R0 #H'1234,R0
Absolute Address: When data accessed absolute address, value absolute address placed memory table advance. That value transferred register loading immediate data during execution instruction, data accessed indirect register addressing mode.
Rev. 2.0, 09/02, page
Table Absolute Address Accessing
Classification Absolute address This MOV.L MOV.B @(disp,PC),R1 @R1,R0 .DATA.L H'12345678 Note: @(disp,PC) accesses immediate data. Example Conventional MOV.B @H'12345678,R0
16-Bit/32-Bit Displacement: When data accessed 16-bit 32-bit displacement, displacement value placed memory table advance. That value transferred register loading immediate data during execution instruction, data accessed indirect indexed register addressing mode. Table Displacement Accessing
Classification 16-bit displacement This MOV.W MOV.W @(disp,PC),R0 @(R0,R1),R2 .DATA.W H'1234 Note: @(disp,PC) accesses immediate data. Example Conventional MOV.W @(H'1234,R1),R2
Rev. 2.0, 09/02, page
2.4.2
Addressing Modes
Table describes addressing modes effective address calculation. Table Addressing Modes Effective Addresses
Addressing Mode Direct register addressing Indirect register addressing Post-increment indirect register addressing Instruction Format Effective Address Calculation effective address register (The operand contents register Rn.) Equation
effective address contents register
@Rn+
effective address contents register constant added content after instruction executed. added byte operation, word operation, longword operation.
1/2/4 1/2/4
(After instruction executes) Byte: Word: Longword:
Pre-decrement indirect register addressing
@-Rn
effective address value obtained subtracting constant from subtracted byte operation, word operation, longword operation.
1/2/4 1/2/4 1/2/4
Byte: Word: Longword: (Instruction executed with after this calculation) Byte: disp Word: disp Longword: disp
Indirect register addressing with displacement
@(disp:4, effective address 4-bit displacement (disp). value disp zeroRn) extended, remains unchanged byte operation, doubled word operation, quadrupled longword operation.
disp (zero-extended) 1/2/4 disp 1/2/4
Rev. 2.0, 09/02, page
Addressing Mode
Instruction Format Effective Address Calculation
Equation
Indirect indexed @(R0, effective address register addressing
Indirect addressing with displacement
@(disp:8, effective address value 8-bit displacement (disp). value disp GBR) zero-extended, remains unchanged byte operation, doubled word operation, quadrupled longword operation.
disp (zero-extended) 1/2/4 disp 1/2/4
Byte: disp Word: disp Longword: disp
Indirect indexed @(R0, addressing GBR)
effective address value
Indirect addressing with displacement
@(disp:8, effective address value 8-bit displacement (disp). value disp zero-extended, doubled word operation, quadrupled longword operation. longword operation, lowest bits value masked.
H'FFFFFFFC disp (zero-extended) (for longword) disp H'FFFFFFFC disp
Word: disp Longword: H'FFFFFFFC disp
Rev. 2.0, 09/02, page
Addressing Mode relative addressing
Instruction Format Effective Address Calculation disp:8 effective address value value that obtained doubling signextended 8-bit displacement (disp).
disp (sign-extended) disp
Equation disp
disp:12
effective address value value that obtained doubling signextended 12-bit displacement (disp).
disp (sign-extended) disp
disp
effective address register
Immediate addressing
#imm:8 #imm:8 #imm:8
8-bit immediate data (imm) TST, AND, instructions zero-extended. 8-bit immediate data (imm) MOV, ADD, CMP/EQ instructions sign-extended. 8-bit immediate data (imm) TRAPA instruction zero-extended then quadrupled.
Rev. 2.0, 09/02, page
2.4.3
Instruction Format
instruction formats meaning source destination operand described below. meaning operand depends instruction code. symbols used follows: xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement Table Instruction Formats
Instruction Formats format
xxxx xxxx xxxx xxxx
Source Operand
Destination Operand
Example
format
xxxx nnnn xxxx xxxx
Control register system register Control register system register
nnnn: Direct register nnnn: Direct register nnnn: Indirect predecrement register Control register system register Control register system register
MOVT
MACH,Rn
STC.L SR,@-Rn Rm,SR
format
xxxx mmmm xxxx xxxx
mmmm: Direct register mmmm: Indirect post-increment register mmmm: Indirect register
LDC.L @Rm+,SR
BRAF
mmmm: relative using
Rev. 2.0, 09/02, page
Instruction Formats format
xxxx nnnn mmmm xxxx
Source Operand mmmm: Direct register mmmm: Direct register mmmm: Indirect post-increment register (multiplyand-accumulate) nnnn*: Indirect post-increment register (multiplyand-accumulate) mmmm: Indirect post-increment register mmmm: Direct register mmmm: Direct register
Destination Operand nnnn: Direct register nnnn: Indirect register MACH, MACL
Example Rm,Rn
MOV.L Rm,@Rn MAC.W @Rm+,@Rn+
nnnn: Direct register nnnn: Indirect predecrement register nnnn: Indirect indexed register
MOV.L
@Rm+,Rn
MOV.L
Rm,@-Rn
MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rn),R0
format
xxxx xxxx mmmm dddd
mmmmdddd: (Direct Indirect register with register) displacement
format
xxxx xxxx nnnn dddd
(Direct register) nnnndddd: MOV.B Indirect register with R0,@(disp,Rn) displacement mmmm: Direct register nnnndddd: Indirect register with displacement MOV.L Rm,@(disp,Rn) MOV.L @(disp,Rm),Rn
format
xxxx nnnn mmmm dddd
mmmmdddd: nnnn: Direct Indirect register with register displacement
Rev. 2.0, 09/02, page
Instruction Formats format
xxxx xxxx dddd dddd
Source Operand dddddddd: Indirect with displacement
Destination Operand
Example
(Direct register) MOV.L @(disp,GBR),R0 MOV.L R0,@(disp,GBR)
(Direct register) dddddddd: Indirect with displacement dddddddd: relative with displacement format
xxxx dddd dddd dddd
(Direct register) MOVA @(disp,PC),R0 dddddddd: relative label
dddddddddddd: label relative (label disp nnnn: Direct register Indirect indexed MOV.L @(disp,PC),Rn AND.B #imm,@(R0,GBR) #imm,R0 #imm #imm,Rn
format
xxxx nnnn dddd dddd
dddddddd: relative with displacement iiiiiiii: Immediate
format
xxxx xxxx iiii iiii
iiiiiiii: Immediate iiiiiiii: Immediate
(Direct register) nnnn: Direct register TRAPA
format
xxxx nnnn iiii iiii
iiiiiiii: Immediate
Note: multiply-and-accumulate instructions, nnnn source register.
Rev. 2.0, 09/02, page
2.5.1
Instruction
Instruction Classification
Table 2.10 lists instructions according their classification. Table 2.10 Classification Instructions
Operation Classification Types Code Function Data transfer Data transfer, immediate data transfer, peripheral module data transfer, structure data transfer Effective address transfer transfer Swap upper lower bytes Extraction middle registers connected Binary addition Binary addition with carry Binary addition with overflow check Instructions
MOVA MOVT SWAP XTRCT Arithmetic operations ADDC ADDV
CMP/cond Comparison DIV1 DIV0S DIV0U DMULS DMULU EXTS EXTU MULS MULU NEGC Division Initialization signed division Initialization unsigned division Signed double-length multiplication Unsigned double-length multiplication Decrement test Sign extension Zero extension Multiply-and-accumulate, double-length multiply-and-accumulate operation Double-length multiply operation Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction
Rev. 2.0, 09/02, page
Operation Classification Types Code Function Arithmetic operations Logic operations SUBC SUBV Shift ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch BRAF BSRF Binary subtraction with borrow Binary subtraction with underflow Logical inversion Logical Memory test Logical Exclusive One-bit left rotation One-bit right rotation One-bit left rotation with One-bit right rotation with One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Conditional branch, conditional branch with delay (Branch when Conditional branch, conditional branch with delay (Branch when Unconditional branch Unconditional branch Branch subroutine procedure Branch subroutine procedure Unconditional branch Branch subroutine procedure Return from subroutine procedure
Instructions
Rev. 2.0, 09/02, page
Operation Classification Types Code Function System control CLRT CLRMAC SETT SLEEP TRAPA Total: clear register clear Load control register Load system register operation Return from exception processing Transition power-down mode Store control register data Store system register data Trap exception handling
Instructions
Rev. 2.0, 09/02, page
table below shows format instruction codes, operation, execution states. They described using this format according their classification. Instruction Code Format
Item Instruction Format Described mnemonic. OP.Sz SRC,DEST Explanation Operation code Size SRC: Source DEST: Destination Source register Destination register imm: Immediate data disp: Displacement*2 mmmm: Source register nnnn: Destination register 0000: 0001: 1111: iiii: Immediate data dddd: Displacement Direction transfer Memory operand Flag bits Logical each Logical each Exclusive each Logical each n-bit left shift n-bit right shift Value when wait states inserted*1 Value after instruction executed. em-dash column means change.
Instruction code
Described order
Outline Operation
(xx) M/Q/T
Execution states
Notes: Instruction execution states: execution states shown table minimums. actual number states increased when contention occurs between instruction fetches data access, when destination register load instruction (memory register) equals register used next instruction. Depending operand size, displacement scaled details, refer SH-1/SH-2/SH-DSP Programming Manual.
Rev. 2.0, 09/02, page
Data Transfer Instructions
Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L #imm,Rn @(disp,PC),Rn @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0 @(disp,Rm),R0 @(disp,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100 0000nnnnmmmm0101 0000nnnnmmmm0110 Operation Execution States
#imm Sign extension (disp Sign extension (disp (Rn) (Rn) (Rn)
(Rm) Sign extension (Rm) Sign extension (Rm) Rn-1 (Rn) Rn-2 (Rn) Rn-4 (Rn)
(Rm) Sign extension Rn,Rm (Rm) Sign extension Rn,Rm (Rm) Rn,Rm (disp (disp (disp (disp Sign extension (disp Sign extension (disp
Rev. 2.0, 09/02, page
Instruction MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn
Instruction Code 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110
Operation Sign extension Sign extension (disp GBR) (disp GBR) (disp GBR) (disp GBR) Sign extension (disp GBR) Sign extension (disp GBR) disp Swap bottom bytes Swap consecutive words Middle bits
Execution States
R0,@(disp,GBR) 11000000dddddddd R0,@(disp,GBR) 11000001dddddddd R0,@(disp,GBR) 11000010dddddddd @(disp,GBR),R0 11000100dddddddd @(disp,GBR),R0 11000101dddddddd @(disp,GBR),R0 11000110dddddddd @(disp,PC),R0 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101
SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn
Rev. 2.0, 09/02, page
Arithmetic Operation Instructions
Instruction ADDC ADDV CMP/EQ CMP/EQ CMP/HS CMP/GE CMP/HI CMP/GT CMP/PL CMP/PZ Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010101 0100nnnn00010001 0010nnnnmmmm1100 0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 0011nnnnmmmm1101 Operation Carry Overflow imm, Execution States Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result
RnRm with unsigned data, with signed data, with unsigned data,
with signed data, have equivalent byte, Single-step division
CMP/STR Rm,Rn DIV1 DIV0S DIV0U DMULS.L Rm,Rn Rm,Rn Rm,Rn
M/Q/T Signed operation MACH, MACL bits Unsigned operation MACH, MACL bits
DMULU.L Rm,Rn
0011nnnnmmmm0101
Rev. 2.0, 09/02, page
Instruction
Instruction Code 0100nnnn00010000
Operation
Execution States Comparison result
when When nonzero, Byte signextended Word signextended Byte zeroextended Word zeroextended Signed operation (Rn) (Rm) bits Signed operation (Rn) (Rm) bits MACL, bits
EXTS.B EXTS.W EXTU.B EXTU.W MAC.L
Rm,Rn Rm,Rn Rm,Rn Rm,Rn
0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101
@Rm+,@Rn+ 0000nnnnmmmm1111
3/(2
MAC.W
@Rm+,@Rn+ 0100nnnnmmmm1111
3/(2)*
MUL.L MULS.W
Rm,Rn Rm,Rn
0000nnnnmmmm0111 0010nnnnmmmm1111
Signed operation MACL bits Unsigned operation MACL bits Borrow Borrow Underflow
MULU.W
Rm,Rn
0010nnnnmmmm1110
NEGC SUBC SUBV
Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn
0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011
Borrow Borrow Overflow
Note: normal number execution states shown. (The number parentheses number states when there contention with preceding following instructions.)
Rev. 2.0, 09/02, page
Logic Operation Instructions
Instruction AND.B OR.B TAS.B TST.B XOR.B Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn #imm,R0 #imm,@(R0,GBR) Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 0010nnnnmmmm1000 11001000iiiiiiii 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii Operation GBR) GBR) GBR) GBR) Execution States Test result Test result Test result Test result
(Rn) (Rn) result imm; result GBR) imm; result GBR) GBR)
Rev. 2.0, 09/02, page
Shift Instructions
Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 Operation Rn<<2 Rn>>2 Rn<<8 Rn>>8 Rn<<16 Rn>>16 Execution States
SHLL16 SHLR16
Rev. 2.0, 09/02, page
Branch Instructions
Instruction label Instruction Code 10001011dddddddd 10001111dddddddd 10001001dddddddd 10001101dddddddd 1010dddddddddddd 0000mmmm00100011 1011dddddddddddd 0000mmmm00000011 0100mmmm00101011 0100mmmm00001011 0000000000001011 Operation disp Delayed branch, disp disp Delayed branch, disp Delayed branch, disp Delayed branch, Delayed branch, disp Delayed branch, Delayed branch, Delayed branch, Delayed branch, Execution States 3/1* 2/1* 3/1* 2/1*
BF/S label label
BT/S label label
BRAF label
BSRF
Note: state when program does branch.
Rev. 2.0, 09/02, page
System Control Instructions
Instruction CLRT CLRMAC LDC.L LDC.L LDC.L LDS.L LDS.L LDS.L SETT SLEEP STC.L STC.L STC.L STS.L STS.L SR,Rn GBR,Rn VBR,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn Rm,SR Rm,GBR Rm,VBR @Rm+,SR @Rm+,GBR @Rm+,VBR Rm,MACH Rm,MACL Rm,PR Instruction Code 0000000000001000 0000000000101000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 Operation MACH, MACL (Rm) (Rm) GBR, (Rm) VBR, MACH MACL (Rm) MACH, (Rm) MACL, (Rm) operation Delayed branch, stack area PC/SR Sleep (Rn) (Rn) (Rn) MACH MACL MACH (Rn) MACL (Rn) Execution States
@Rm+,MACH 0100mmmm00000110 @Rm+,MACL 0100mmmm00010110 @Rm+,PR 0100mmmm00100110 0000000000001001 0000000000101011 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010
MACH,@-Rn 0100nnnn00000010 MACL,@-Rn 0100nnnn00010010
Rev. 2.0, 09/02, page
Instruction STS.L TRAPA PR,@-Rn #imm
Instruction Code 0100nnnn00100010 11000011iiiiiiii
Operation (Rn)
Execution States
PC/SR stack area, (imm VBR)
Note: number execution states before chip enters sleep mode: execution states shown table minimums. actual number states increased when contention occurs between instruction fetches data access, when destination register load instruction (memory register) equals register used next instruction.
Rev. 2.0, 09/02, page
2.6.1
Processing States
State Transitions
five processing states: reset, exception processing, release, program execution power-down. Figure shows transitions between states.
From state when From state when
Power-on reset state
Manual reset state
When internal power-on reset internal manual reset occurs request cleared
Reset state
Exception processing state request generated Exception processing source occurs Exception processing ends interrupt source occurs
release state request generated request generated request cleared
request cleared Program execution state SSBY SLEEP instruction
SSBY cleared SLEEP instruction
Sleep mode
Software standby mode Power-down state
Figure Transitions between Processing States
Rev. 2.0, 09/02, page
Reset State: resets reset state. When level goes low, power-on reset state entered. When high MRES low, manual reset state entered. Exception Processing State: exception processing state transient state that occurs when exception processing sources such resets interrupts alter CPU's processing state flow. reset, initial values program counter (PC) (execution start address) stack pointer (SP) fetched from exception processing vector table stored; then branches execution start address execution program begins. interrupt, stack pointer (SP) accessed program counter (PC) status register (SR) saved stack area. exception service routine start address fetched from exception processing vector table; then branches that address program starts executing, thereby entering program execution state. Program Execution State: program execution state, sequentially executes program. Power-Down State: power-down state, operation halts power consumption declines. SLEEP instruction places sleep mode software standby mode. Release State: release state, releases mastership device that requested them.
Rev. 2.0, 09/02, page
Section Operating Modes
Selection Operating Modes
This four operating modes four clock modes. operating mode determined setting MD0, pins. change these pins during operation (while power on). these pins other than combination shown table 3.1. When power applied system, sure conduct power-on reset. Table Selection Operating Modes
Setting MD3*
Mode
Width Area Mode Name extension mode extension mode extension mode Single chip mode Boot mode*
MD2*
On-Chip SH7144 SH7145 Active bits bits
Mode
Mode
Active
bits
bits
Mode
Active
BCR1 BCR1
Mode
Active Active
User programming mode*
Active
BCR1
Notes: symbol means "Don't care." pins used select clock mode. User programming mode flash memory. Supported only F-ZTAT version.
There modes operating modes: extension mode single chip mode. There modes program flash memory (on-board programming mode): boot mode user programming mode.
Rev. 2.0, 09/02, page
clock mode selected input pins. Table Clock Mode Setting
Setting Clock Mode Clock Ratio (when input clock System clock Peripheral clock System clock output (CK)
Note: maximum clock input frequency 10MHz because specified 40MHz less.
Input/Output
Table describes configuration operating mode related pin. Table Operating Mode Configuration
Name Input/Output Input Input Input Input Input Function Designates operating mode through level applied this Designates operating mode through level applied this Designates clock mode through level applied this Designates clock mode through level applied this hardware protection against programming/erasing on-chip flash memory
Rev. 2.0, 09/02, page
3.3.1
Explanation Operating Modes
Mode (MCU extension mode
area becomes external memory space with 8-bit width SH7144 16-bit width SH7145. 3.3.2 Mode (MCU extension mode
area becomes external memory space with 16-bit width SH7144 32-bit width SH7145. 3.3.3 Mode (MCU extension mode
on-chip active area used this mode. 3.3.4 Mode (Single chip mode)
ports used this mode, however external address cannot used. 3.3.5 Clock mode
input waveform frequency used doubled quadrupled system clock frequency mode mode
Rev. 2.0, 09/02, page
Address
address operating modes shown figure 3.1.
Modes On-chip disabled mode H'00000000 area H'003FFFFF H'00400000 area H'007FFFFF H'00800000 area H'00BFFFFF H'00C00000 area H'00FFFFFF H'01000000 H'00FFFFFF H'01000000 H'00BFFFFF H'00C00000 area H'007FFFFF H'00800000 area Modes On-chip enabled mode H'00000000 H'0003FFFF H'00040000 H'00200000 H'003FFFFF H'00400000 On-chip Reserved area area (256kB) H'00000000 H'0003FFFF H'00040000 Modes Single-chip mode On-chip (256kB)
area
Reserved area
Reserved area
Reserved area
H'FFFF7FFF H'FFFF8000 H'FFFFBFFF H'FFFFC000 H'FFFFDFFF H'FFFFE000 H'FFFFFFFF
On-chip peripheral registers Reserved area On-chip RAM(8kB)
H'FFFF7FFF H'FFFF8000 H'FFFFBFFF H'FFFFC000 H'FFFFDFFF H'FFFFE000 H'FFFFFFFF
On-chip peripheral registers Reserved area On-chip RAM(8kB)
H'FFFF7FFF H'FFFF8000 H'FFFFBFFF H'FFFFC000 H'FFFFDFFF H'FFFFE000 H'FFFFFFFF
On-chip peripheral registers Reserved area On-chip RAM(8kB)
Figure Address Each Operating Mode
Initial State This
initial state this LSI, some on-chip modules module standby state saving power. When operating these modules, clear module standby state according procedure section Power-Down Modes.
Rev. 2.0, 09/02, page
Section Clock Pulse Generator
This on-chip clock pulse generator (CPG) that generates system clock ()and peripheral clock(P), then makes internal clock /8192 P/1024) this generated clock. consists oscillator, circuit, pre-scaler. block diagram clock pulse generator shown figure 4.1. frequency from oscillator modified circuit.
PLLCAP EXTAL Oscillator XTAL circuit
Clock divider 1/2)
Clock mode control circuitry
Pre-scaler Pre-scaler
/8192
P/1024
internal circuit
Figure Block Diagram Clock Pulse Generator
CPG0111A_010020020700
Rev. 2.0, 09/02, page
Table shows operating clock each module. Table Operating clock each module
Operating clock System clock Operating Module DMAC Peripheral clock H-UDI
Oscillator
Clock pulses supplied from connected crystal resonator external clock. 4.1.1 Connecting Crystal Oscillator
Circuit Configuration: crystal oscillator connected shown figure 4.2. damping resistance (Rd) listed table 4.2. AT-cut parallel-resonance type crystal oscillator that resonance frequency 12.5 MHz. recommended consult crystal dealer concerning compatibility crystal oscillator LSI.
Rev. 2.0, 09/02, page
EXTAL XTAL 18-22 (Recommended value)
Figure Connection Crystal Oscillator (Example) Table Damping Resistance Values
Frequency (MHz) 12.5
Crystal Resonator: Figure shows equivalent circuit crystal resonator. crystal resonator with characteristics listed table 4.3.
XTAL EXTAL
Figure Crystal Resonator Equivalent Circuit Table Crystal Resonator Characteristics
Frequency (MHz) (pF) 12.5
4.1.2
External Clock Input Method
Figure shows example external clock input connection. this case, make external clock high level stop when software standby mode. During operation, make external input clock frequency 12.5 MHz. When leaving XTAL open, make sure parasitic capacitance less than Even when inputting external clock, sure wait least oscillation stabilization time power-on sequence releasing software standby mode, order ensure stabilization time.
Rev. 2.0, 09/02, page
EXTAL XTAL Open state
External clock input
Figure Example External Clock Connection
Function Detecting Oscillator Halt
This detect clock halt automatically cause timer pins become highimpedance when system abnormality causes oscillator halt. That when change EXTAL been detected, high-current pins (PE9/TIOC3B/
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