Presettable Synchronous 4-Bit Binary Up/Down Counter CD74AC191 CD

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Presettable Synchronous 4-Bit Binary Up/Down Counter CD74AC191 CD

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CD74AC191, CD74ACT191
Presettable Synchronous 4-Bit Binary Up/Down Counter
CD74AC191 CD74ACT191 asynchronously presettable binary up/down synchronous counters that utilize Harris Advanced CMOS Logic technology. Presetting counter number preset data inputs (P0-P3) accomplished setting asynchronous parallel load input (PL). Counting occurs when HIGH, Count Enable (CE) LOW, Up/Down (U/D) input either up-counting HIGH down-counting. counter incremented decremented synchronously with LOW-to-HIGH transition clock. When overflow underflow counter occurs, Terminal Count (TC) output, which during counting, goes HIGH remains HIGH clock cycle. This output used look-ahead carry high-speed cascading (see Figure 12). output also initiates Ripple Clock (RC) output which, normally HIGH, goes remains low-level cascaded using Ripple Count output.
October 1998
Features
Buffered Inputs
PRReplacem mende
Typical Propagation Delay 12.8ns 25oC, 50pF Exceeds Protection MIL-STD-883, Method 3015 SCR-Latchup-Resistant CMOS Process Circuit Design Speed Bipolar FASTTM/AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays Types Feature 1.5V 5.5V Operation Balanced Noise Immunity Supply ±24mA Output Drive Current Fanout FASTICs Drives Transmission Lines
Ordering Information
PART NUMBER CD74AC191E CD74ACT191E CD74AC191M CD74ACT191M NOTES: When ordering, entire part number. suffix obtain variant tape reel. Wafer this part number available which meets electrical specifications. Please contact your local sales office Harris customer service ordering information. TEMP. RANGE (oC) PACKAGE PKG. E16.3 E16.3 M16.15 M16.15
Pinout
CD74AC191, CD74ACT191 (PDIP, SOIC) VIEW
70oC, PDIP 70oC, PDIP 70oC, SOIC 70oC, SOIC
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. FASTis Trademark Fairchild Semiconductor. Copyright Harris Corporation 1998
File Number
1911.1
CD74AC191, CD74ACT191 Functional Diagram
BINARY PRESET ASYN. PARALLEL LOAD ENABLE CLOCK UP/DOWN BINARY OUTPUTS
TERMINAL COUNT COUNT ENABLE RIPPLE CLOCK
TRUTH TABLE INPUTS FUNCTION Count Count Down Asynchronous Preset Change
should changed only when clock high. Don't Care Low-to-High clock transition.
CD74AC191, CD74ACT191
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±50mA Output Source Sink Current Output Pin, -0.5V 0.5V .±50mA Ground Current, IGND (Note .±100mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) PDIP Package SOIC Package Maximum Junction Temperature (Hermetic Package Die) 175oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, (Note Types. .1.5V 5.5V Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Slew Rate, dt/dv Types, 1.5V 50ns (Max) Types, 3.6V 5.5V 20ns (Max) Types, 4.5V 5.5V. 10ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: outputs device, ±25mA each additional output. Unless otherwise specified, voltages referenced ground. measured with component mounted evaluation board free air.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 -0.05 -0.05 (Note (Note 3.85 2.58 3.94 1.65 3.85 2.48 3.85 1.65 3.85 3.85 1.65 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD74AC191, CD74ACT191
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Level Output Voltage SYMBOL (mA) 0.05 0.05 0.05 (Note (Note Input Leakage Current Quiescent Supply Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 (Note (Note Level Output Voltage 0.05 (Note (Note Input Leakage Current Quiescent Supply Current Additional Supply Current Input Inputs High Unit Load NOTES: Test output time 1-second maximum duration. Measurement made forcing current measuring voltage minimize power dissipation. Test verifies minimum transmission-line-drive capability 85oC, 125oC. -2.1 3.94 0.36 ±0.1 3.85 0.44 1.65 3.85 1.65 25oC 0.36 0.36 ±0.1 -40oC 85oC 0.44 0.44 1.65 -55oC 125oC 1.65 UNITS
Input Load Table
INPUT P0-P3, U/D, UNIT LOAD 0.75 0.85
NOTE: Unit load limit specified Electrical Specifications Table, e.g., 2.4mA 25oC.
CD74AC191, CD74ACT191
Prerequisite Switching Function
-40oC 85oC PARAMETER TYPES Max. Frequency fMAX (Note (Note (Note Pulse Width Pulse Width Recovery Time tREC Set-Up Time, Set-Up Time, Set-Up Time, Hold Time, Hold Time, Hold Time, TYPES Max. Frequency Pulse Width Pulse Width Recovery Time Set-Up Time, fMAX (Note tREC (Note 10.5 12.9 14.7 10.5 11.6 14.7 10.5 16.8 SYMBOL -55oC 125oC UNITS
CD74AC191, CD74ACT191
Prerequisite Switching Function
(Continued) -40oC 85oC PARAMETER Set-Up Time, Set-Up Time, Hold Time, Hold Time, Hold Time, NOTES: 3.3V 4.5V. Applies non-cascaded operation only. With cascaded counters clock-to-terminal count propagation delays, count enable (CE)-to-clock set-up times, count enable (CE)-to-clock hold times determine clock frequency. example, with these devices 85oC 5V:. 36MHz CP-to-TC prop. delay CE-to-CP setup CE-to-CP Hold 18.2 SYMBOL 10.5 -55oC 125oC 10.5 UNITS
Switching Specifications Input 3ns, 50pF (Worst Case)
-40oC 85oC PARAMETER TYPES Propagation Delay tPLH, tPHL (Note (Note Propagation Delay tPLH, tPHL Propagation Delay tPLH, tPHL Propagation Delay tPLH, tPHL Propagation Delay tPLH, tPHL Propagation Delay tPLH, tPHL Propagation Delay tPLH, tPHL 19.1 13.6 19.4 13.8 20.4 14.5 15.3 25.5 18.2 27.6 19.7 17.9 12.8 21.3 15.2 22.4 16.8 30.4 21.7 19.7 14.1 SYMBOL -55oC 125oC UNITS
CD74AC191, CD74ACT191
Switching Specifications Input 3ns, 50pF (Worst Case)
PARAMETER Propagation Delay SYMBOL tPLH, tPHL Input Capacitance Power Dissipation Capacitance TYPES Propagation Delay Propagation Delay Propagation Delay Propagation Delay Propagation Delay Propagation Delay Propagation Delay Propagation Delay Input Capacitance Power Dissipation Capacitance NOTES: Limits tested 100%. 3.3V 3.6V, 5.5V, 4.5V used determine dynamic power consumption package. CPDVCC2 VCC2 where input frequency, output frequency, output load capacitance, supply voltage. tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL (Note (Note 14.8 13.8 14.5 10.9 18.2 19.7 13.5 11.5 16.3 15.2 21.7 14.9 12.7 (Note (Continued) -55oC 125oC 15.4 16.9 12.1 UNITS
-40oC 85oC
1/fMAX tPHL tPLH INPUT LEVEL tPHL
INPUT LEVEL tPLH
FIGURE
FIGURE
CD74AC191, CD74ACT191
INPUT LEVEL tPHL INPUT LEVEL tPLH tPLH INPUT LEVEL tPHL
FIGURE
FIGURE
INPUT LEVEL INPUT LEVEL tREC INPUT LEVEL tSU(H) tH(H) tSU(L) tH(L) INPUT LEVEL
FIGURE
shaded areas indicate when input permitted change predictable output performance. FIGURE
tPLH tPHL
INPUT LEVEL tPHL tPLH CHANGE (H-L) ONLY tSU(L) tH(L) CHANGE tSU(H)
INPUT LEVEL INPUT LEVEL
FIGURE
FIGURE
OUTPUT (NOTE) OUTPUT LOAD 50pF
NOTE: Series Only: When 1.5V, CD74AC Input Level Input Switching Voltage, Output Switching Voltage, CD74ACT 1.5V
FIGURE PROPAGATION DELAY TIMES
CD74AC191, CD74ACT191
LOAD PRESET INPUTS CLOCK DOWN/UP ENABLE TERMINAL COUNT RIPPLE CLOCK LOAD INHIBIT
COUNT
COUNT DOWN
Sequence: Load (preset) binary thirteen. Count fourteen, fifteen, zero, one, two. Inhibit. Count down one, zero, fifteen, fourteen, thirteen. FIGURE CD74AC191 DECODE COUNTERS TYPICAL LOAD, COUNT, INHIBIT SEQUENCES
DIRECTION CONTROL ENABLE
CLOCK
FIGURE SYNCHRONOUS N-STAGE COUNTER WITH PARALLEL GATED TC/RC
DIRECTION CONTROL ENABLE CLOCK
FIGURE SYNCHRONOUS N-STAGE COUNTER USING RIPPLE TC/RC
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated

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